1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/types.h> 29 #include <linux/mm.h> 30 #include <linux/kthread.h> 31 #include <linux/workqueue.h> 32 #include <kgd_kfd_interface.h> 33 #include <drm/ttm/ttm_execbuf_util.h> 34 #include "amdgpu_sync.h" 35 #include "amdgpu_vm.h" 36 37 extern uint64_t amdgpu_amdkfd_total_mem_size; 38 39 enum TLB_FLUSH_TYPE { 40 TLB_FLUSH_LEGACY = 0, 41 TLB_FLUSH_LIGHTWEIGHT, 42 TLB_FLUSH_HEAVYWEIGHT 43 }; 44 45 struct amdgpu_device; 46 47 enum kfd_mem_attachment_type { 48 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ 49 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ 50 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ 51 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */ 52 }; 53 54 struct kfd_mem_attachment { 55 struct list_head list; 56 enum kfd_mem_attachment_type type; 57 bool is_mapped; 58 struct amdgpu_bo_va *bo_va; 59 struct amdgpu_device *adev; 60 uint64_t va; 61 uint64_t pte_flags; 62 }; 63 64 struct kgd_mem { 65 struct rwlock lock; 66 struct amdgpu_bo *bo; 67 struct dma_buf *dmabuf; 68 struct list_head attachments; 69 /* protected by amdkfd_process_info.lock */ 70 struct ttm_validate_buffer validate_list; 71 struct ttm_validate_buffer resv_list; 72 uint32_t domain; 73 unsigned int mapped_to_gpu_memory; 74 uint64_t va; 75 76 uint32_t alloc_flags; 77 78 atomic_t invalid; 79 struct amdkfd_process_info *process_info; 80 81 struct amdgpu_sync sync; 82 83 bool aql_queue; 84 bool is_imported; 85 }; 86 87 /* KFD Memory Eviction */ 88 struct amdgpu_amdkfd_fence { 89 struct dma_fence base; 90 struct mm_struct *mm; 91 spinlock_t lock; 92 char timeline_name[TASK_COMM_LEN]; 93 struct svm_range_bo *svm_bo; 94 }; 95 96 struct amdgpu_kfd_dev { 97 struct kfd_dev *dev; 98 int64_t vram_used; 99 uint64_t vram_used_aligned; 100 bool init_complete; 101 struct work_struct reset_work; 102 }; 103 104 enum kgd_engine_type { 105 KGD_ENGINE_PFP = 1, 106 KGD_ENGINE_ME, 107 KGD_ENGINE_CE, 108 KGD_ENGINE_MEC1, 109 KGD_ENGINE_MEC2, 110 KGD_ENGINE_RLC, 111 KGD_ENGINE_SDMA1, 112 KGD_ENGINE_SDMA2, 113 KGD_ENGINE_MAX 114 }; 115 116 117 struct amdkfd_process_info { 118 /* List head of all VMs that belong to a KFD process */ 119 struct list_head vm_list_head; 120 /* List head for all KFD BOs that belong to a KFD process. */ 121 struct list_head kfd_bo_list; 122 /* List of userptr BOs that are valid or invalid */ 123 struct list_head userptr_valid_list; 124 struct list_head userptr_inval_list; 125 /* Lock to protect kfd_bo_list */ 126 struct rwlock lock; 127 128 /* Number of VMs */ 129 unsigned int n_vms; 130 /* Eviction Fence */ 131 struct amdgpu_amdkfd_fence *eviction_fence; 132 133 /* MMU-notifier related fields */ 134 atomic_t evicted_bos; 135 struct delayed_work restore_userptr_work; 136 struct pid *pid; 137 bool block_mmu_notifications; 138 }; 139 140 int amdgpu_amdkfd_init(void); 141 void amdgpu_amdkfd_fini(void); 142 143 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 144 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev); 145 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); 146 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 147 const void *ih_ring_entry); 148 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 149 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 150 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); 151 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 152 enum kgd_engine_type engine, 153 uint32_t vmid, uint64_t gpu_addr, 154 uint32_t *ib_cmd, uint32_t ib_len); 155 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); 156 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); 157 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 158 uint16_t vmid); 159 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 160 uint16_t pasid, enum TLB_FLUSH_TYPE flush_type); 161 162 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 163 164 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev); 165 166 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 167 168 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev); 169 170 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 171 int queue_bit); 172 173 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 174 struct mm_struct *mm, 175 struct svm_range_bo *svm_bo); 176 #if defined(CONFIG_DEBUG_FS) 177 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); 178 #endif 179 #if IS_ENABLED(CONFIG_HSA_AMD) 180 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 181 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 182 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); 183 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); 184 #else 185 static inline 186 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 187 { 188 return false; 189 } 190 191 static inline 192 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 193 { 194 return NULL; 195 } 196 197 static inline 198 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 199 { 200 return 0; 201 } 202 203 static inline 204 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 205 { 206 return 0; 207 } 208 #endif 209 /* Shared API */ 210 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 211 void **mem_obj, uint64_t *gpu_addr, 212 void **cpu_ptr, bool mqd_gfx9); 213 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj); 214 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 215 void **mem_obj); 216 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); 217 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 218 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 219 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 220 enum kgd_engine_type type); 221 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 222 struct kfd_local_mem_info *mem_info); 223 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev); 224 225 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev); 226 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, 227 struct kfd_cu_info *cu_info); 228 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 229 struct amdgpu_device **dmabuf_adev, 230 uint64_t *bo_size, void *metadata_buffer, 231 size_t buffer_size, uint32_t *metadata_size, 232 uint32_t *flags); 233 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 234 struct amdgpu_device *src); 235 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 236 struct amdgpu_device *src, 237 bool is_min); 238 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); 239 240 /* Read user wptr from a specified user address space with page fault 241 * disabled. The memory must be pinned and mapped to the hardware when 242 * this is called in hqd_load functions, so it should never fault in 243 * the first place. This resolves a circular lock dependency involving 244 * four locks, including the DQM lock and mmap_lock. 245 */ 246 #define read_user_wptr(mmptr, wptr, dst) \ 247 ({ \ 248 bool valid = false; \ 249 if ((mmptr) && (wptr)) { \ 250 pagefault_disable(); \ 251 if ((mmptr) == current->mm) { \ 252 valid = !get_user((dst), (wptr)); \ 253 } else if (current->flags & PF_KTHREAD) { \ 254 kthread_use_mm(mmptr); \ 255 valid = !get_user((dst), (wptr)); \ 256 kthread_unuse_mm(mmptr); \ 257 } \ 258 pagefault_enable(); \ 259 } \ 260 valid; \ 261 }) 262 263 /* GPUVM API */ 264 #define drm_priv_to_vm(drm_priv) \ 265 (&((struct amdgpu_fpriv *) \ 266 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 267 268 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev, 269 struct file *filp, u32 pasid); 270 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 271 struct file *filp, 272 void **process_info, 273 struct dma_fence **ef); 274 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev, 275 void *drm_priv); 276 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 277 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev); 278 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 279 struct amdgpu_device *adev, uint64_t va, uint64_t size, 280 void *drm_priv, struct kgd_mem **mem, 281 uint64_t *offset, uint32_t flags, bool criu_resume); 282 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 283 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 284 uint64_t *size); 285 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev, 286 struct kgd_mem *mem, void *drm_priv); 287 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 288 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); 289 int amdgpu_amdkfd_gpuvm_sync_memory( 290 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); 291 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 292 void **kptr, uint64_t *size); 293 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); 294 295 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo); 296 297 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 298 struct dma_fence **ef); 299 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 300 struct kfd_vm_fault_info *info); 301 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, 302 struct dma_buf *dmabuf, 303 uint64_t va, void *drm_priv, 304 struct kgd_mem **mem, uint64_t *size, 305 uint64_t *mmap_offset); 306 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 307 struct tile_config *config); 308 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 309 bool reset); 310 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem); 311 void amdgpu_amdkfd_block_mmu_notifications(void *p); 312 int amdgpu_amdkfd_criu_resume(void *p); 313 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev); 314 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 315 uint64_t size, u32 alloc_flag); 316 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 317 uint64_t size, u32 alloc_flag); 318 319 #if IS_ENABLED(CONFIG_HSA_AMD) 320 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 321 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 322 struct amdgpu_vm *vm); 323 324 /** 325 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released 326 * 327 * Allows KFD to release its resources associated with the GEM object. 328 */ 329 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo); 330 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 331 #else 332 static inline 333 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 334 { 335 } 336 337 static inline 338 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 339 struct amdgpu_vm *vm) 340 { 341 } 342 343 static inline 344 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 345 { 346 } 347 #endif 348 /* KGD2KFD callbacks */ 349 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); 350 int kgd2kfd_resume_mm(struct mm_struct *mm); 351 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 352 struct dma_fence *fence); 353 #if IS_ENABLED(CONFIG_HSA_AMD) 354 int kgd2kfd_init(void); 355 void kgd2kfd_exit(void); 356 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); 357 bool kgd2kfd_device_init(struct kfd_dev *kfd, 358 struct drm_device *ddev, 359 const struct kgd2kfd_shared_resources *gpu_resources); 360 void kgd2kfd_device_exit(struct kfd_dev *kfd); 361 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); 362 int kgd2kfd_resume_iommu(struct kfd_dev *kfd); 363 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); 364 int kgd2kfd_pre_reset(struct kfd_dev *kfd); 365 int kgd2kfd_post_reset(struct kfd_dev *kfd); 366 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 367 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 368 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); 369 #else 370 static inline int kgd2kfd_init(void) 371 { 372 return -ENOENT; 373 } 374 375 static inline void kgd2kfd_exit(void) 376 { 377 } 378 379 static inline 380 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 381 { 382 return NULL; 383 } 384 385 static inline 386 bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev, 387 const struct kgd2kfd_shared_resources *gpu_resources) 388 { 389 return false; 390 } 391 392 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 393 { 394 } 395 396 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 397 { 398 } 399 400 static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd) 401 { 402 return 0; 403 } 404 405 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 406 { 407 return 0; 408 } 409 410 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd) 411 { 412 return 0; 413 } 414 415 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 416 { 417 return 0; 418 } 419 420 static inline 421 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 422 { 423 } 424 425 static inline 426 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 427 { 428 } 429 430 static inline 431 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 432 { 433 } 434 #endif 435 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 436