1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_amdkfd.h" 24 #include "amd_shared.h" 25 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "amdgpu_dma_buf.h" 29 #include <linux/module.h> 30 #include <linux/dma-buf.h> 31 #include "amdgpu_xgmi.h" 32 #include <uapi/linux/kfd_ioctl.h> 33 34 static const unsigned int compute_vmid_bitmap = 0xFF00; 35 36 /* Total memory size in system memory and all GPU VRAM. Used to 37 * estimate worst case amount of memory to reserve for page tables 38 */ 39 uint64_t amdgpu_amdkfd_total_mem_size; 40 41 int amdgpu_amdkfd_init(void) 42 { 43 #ifdef __linux__ 44 struct sysinfo si; 45 int ret; 46 47 si_meminfo(&si); 48 amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh; 49 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 50 #else 51 int ret; 52 53 amdgpu_amdkfd_total_mem_size = ptoa(physmem); 54 #endif 55 56 #ifdef CONFIG_HSA_AMD 57 ret = kgd2kfd_init(); 58 amdgpu_amdkfd_gpuvm_init_mem_limits(); 59 #else 60 ret = -ENOENT; 61 #endif 62 63 return ret; 64 } 65 66 void amdgpu_amdkfd_fini(void) 67 { 68 kgd2kfd_exit(); 69 } 70 71 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 72 { 73 bool vf = amdgpu_sriov_vf(adev); 74 75 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, 76 adev->pdev, adev->asic_type, vf); 77 78 if (adev->kfd.dev) 79 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 80 } 81 82 /** 83 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 84 * setup amdkfd 85 * 86 * @adev: amdgpu_device pointer 87 * @aperture_base: output returning doorbell aperture base physical address 88 * @aperture_size: output returning doorbell aperture size in bytes 89 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 90 * 91 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 92 * takes doorbells required for its own rings and reports the setup to amdkfd. 93 * amdgpu reserved doorbells are at the start of the doorbell aperture. 94 */ 95 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 96 phys_addr_t *aperture_base, 97 size_t *aperture_size, 98 size_t *start_offset) 99 { 100 /* 101 * The first num_doorbells are used by amdgpu. 102 * amdkfd takes whatever's left in the aperture. 103 */ 104 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { 105 *aperture_base = adev->doorbell.base; 106 *aperture_size = adev->doorbell.size; 107 *start_offset = adev->doorbell.num_doorbells * sizeof(u32); 108 } else { 109 *aperture_base = 0; 110 *aperture_size = 0; 111 *start_offset = 0; 112 } 113 } 114 115 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 116 { 117 int i; 118 int last_valid_bit; 119 120 if (adev->kfd.dev) { 121 struct kgd2kfd_shared_resources gpu_resources = { 122 .compute_vmid_bitmap = compute_vmid_bitmap, 123 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 124 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 125 .gpuvm_size = min(adev->vm_manager.max_pfn 126 << AMDGPU_GPU_PAGE_SHIFT, 127 AMDGPU_GMC_HOLE_START), 128 .drm_render_minor = adev->ddev->render->index, 129 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 130 131 }; 132 133 /* this is going to have a few of the MSBs set that we need to 134 * clear 135 */ 136 bitmap_complement(gpu_resources.cp_queue_bitmap, 137 adev->gfx.mec.queue_bitmap, 138 KGD_MAX_QUEUES); 139 140 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 141 * nbits is not compile time constant 142 */ 143 last_valid_bit = 1 /* only first MEC can have compute queues */ 144 * adev->gfx.mec.num_pipe_per_mec 145 * adev->gfx.mec.num_queue_per_pipe; 146 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 147 clear_bit(i, gpu_resources.cp_queue_bitmap); 148 149 amdgpu_doorbell_get_kfd_info(adev, 150 &gpu_resources.doorbell_physical_address, 151 &gpu_resources.doorbell_aperture_size, 152 &gpu_resources.doorbell_start_offset); 153 154 /* Since SOC15, BIF starts to statically use the 155 * lower 12 bits of doorbell addresses for routing 156 * based on settings in registers like 157 * SDMA0_DOORBELL_RANGE etc.. 158 * In order to route a doorbell to CP engine, the lower 159 * 12 bits of its address has to be outside the range 160 * set for SDMA, VCN, and IH blocks. 161 */ 162 if (adev->asic_type >= CHIP_VEGA10) { 163 gpu_resources.non_cp_doorbells_start = 164 adev->doorbell_index.first_non_cp; 165 gpu_resources.non_cp_doorbells_end = 166 adev->doorbell_index.last_non_cp; 167 } 168 169 kgd2kfd_device_init(adev->kfd.dev, adev->ddev, &gpu_resources); 170 } 171 } 172 173 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev) 174 { 175 if (adev->kfd.dev) { 176 kgd2kfd_device_exit(adev->kfd.dev); 177 adev->kfd.dev = NULL; 178 } 179 } 180 181 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 182 const void *ih_ring_entry) 183 { 184 if (adev->kfd.dev) 185 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 186 } 187 188 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 189 { 190 if (adev->kfd.dev) 191 kgd2kfd_suspend(adev->kfd.dev, run_pm); 192 } 193 194 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 195 { 196 int r = 0; 197 198 if (adev->kfd.dev) 199 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 200 201 return r; 202 } 203 204 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 205 { 206 int r = 0; 207 208 if (adev->kfd.dev) 209 r = kgd2kfd_pre_reset(adev->kfd.dev); 210 211 return r; 212 } 213 214 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 215 { 216 int r = 0; 217 218 if (adev->kfd.dev) 219 r = kgd2kfd_post_reset(adev->kfd.dev); 220 221 return r; 222 } 223 224 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd) 225 { 226 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 227 228 if (amdgpu_device_should_recover_gpu(adev)) 229 amdgpu_device_gpu_recover(adev, NULL); 230 } 231 232 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 233 void **mem_obj, uint64_t *gpu_addr, 234 void **cpu_ptr, bool cp_mqd_gfx9) 235 { 236 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 237 struct amdgpu_bo *bo = NULL; 238 struct amdgpu_bo_param bp; 239 int r; 240 void *cpu_ptr_tmp = NULL; 241 242 memset(&bp, 0, sizeof(bp)); 243 bp.size = size; 244 bp.byte_align = PAGE_SIZE; 245 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 246 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 247 bp.type = ttm_bo_type_kernel; 248 bp.resv = NULL; 249 250 if (cp_mqd_gfx9) 251 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 252 253 r = amdgpu_bo_create(adev, &bp, &bo); 254 if (r) { 255 dev_err(adev->dev, 256 "failed to allocate BO for amdkfd (%d)\n", r); 257 return r; 258 } 259 260 /* map the buffer */ 261 r = amdgpu_bo_reserve(bo, true); 262 if (r) { 263 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 264 goto allocate_mem_reserve_bo_failed; 265 } 266 267 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 268 if (r) { 269 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 270 goto allocate_mem_pin_bo_failed; 271 } 272 273 r = amdgpu_ttm_alloc_gart(&bo->tbo); 274 if (r) { 275 dev_err(adev->dev, "%p bind failed\n", bo); 276 goto allocate_mem_kmap_bo_failed; 277 } 278 279 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 280 if (r) { 281 dev_err(adev->dev, 282 "(%d) failed to map bo to kernel for amdkfd\n", r); 283 goto allocate_mem_kmap_bo_failed; 284 } 285 286 *mem_obj = bo; 287 *gpu_addr = amdgpu_bo_gpu_offset(bo); 288 *cpu_ptr = cpu_ptr_tmp; 289 290 amdgpu_bo_unreserve(bo); 291 292 return 0; 293 294 allocate_mem_kmap_bo_failed: 295 amdgpu_bo_unpin(bo); 296 allocate_mem_pin_bo_failed: 297 amdgpu_bo_unreserve(bo); 298 allocate_mem_reserve_bo_failed: 299 amdgpu_bo_unref(&bo); 300 301 return r; 302 } 303 304 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) 305 { 306 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 307 308 amdgpu_bo_reserve(bo, true); 309 amdgpu_bo_kunmap(bo); 310 amdgpu_bo_unpin(bo); 311 amdgpu_bo_unreserve(bo); 312 amdgpu_bo_unref(&(bo)); 313 } 314 315 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, 316 void **mem_obj) 317 { 318 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 319 struct amdgpu_bo *bo = NULL; 320 struct amdgpu_bo_param bp; 321 int r; 322 323 memset(&bp, 0, sizeof(bp)); 324 bp.size = size; 325 bp.byte_align = 1; 326 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 327 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 328 bp.type = ttm_bo_type_device; 329 bp.resv = NULL; 330 331 r = amdgpu_bo_create(adev, &bp, &bo); 332 if (r) { 333 dev_err(adev->dev, 334 "failed to allocate gws BO for amdkfd (%d)\n", r); 335 return r; 336 } 337 338 *mem_obj = bo; 339 return 0; 340 } 341 342 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj) 343 { 344 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 345 346 amdgpu_bo_unref(&bo); 347 } 348 349 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 350 enum kgd_engine_type type) 351 { 352 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 353 354 switch (type) { 355 case KGD_ENGINE_PFP: 356 return adev->gfx.pfp_fw_version; 357 358 case KGD_ENGINE_ME: 359 return adev->gfx.me_fw_version; 360 361 case KGD_ENGINE_CE: 362 return adev->gfx.ce_fw_version; 363 364 case KGD_ENGINE_MEC1: 365 return adev->gfx.mec_fw_version; 366 367 case KGD_ENGINE_MEC2: 368 return adev->gfx.mec2_fw_version; 369 370 case KGD_ENGINE_RLC: 371 return adev->gfx.rlc_fw_version; 372 373 case KGD_ENGINE_SDMA1: 374 return adev->sdma.instance[0].fw_version; 375 376 case KGD_ENGINE_SDMA2: 377 return adev->sdma.instance[1].fw_version; 378 379 default: 380 return 0; 381 } 382 383 return 0; 384 } 385 386 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 387 struct kfd_local_mem_info *mem_info) 388 { 389 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 390 #ifdef __linux__ 391 uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask : 392 ~((1ULL << 32) - 1); 393 #else 394 uint64_t address_mask = ~((1ULL << 32) - 1); 395 #endif 396 resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size; 397 398 memset(mem_info, 0, sizeof(*mem_info)); 399 if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) { 400 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 401 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 402 adev->gmc.visible_vram_size; 403 } else { 404 mem_info->local_mem_size_public = 0; 405 mem_info->local_mem_size_private = adev->gmc.real_vram_size; 406 } 407 mem_info->vram_width = adev->gmc.vram_width; 408 409 pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n", 410 &adev->gmc.aper_base, &aper_limit, 411 mem_info->local_mem_size_public, 412 mem_info->local_mem_size_private); 413 414 if (amdgpu_sriov_vf(adev)) 415 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 416 else if (adev->pm.dpm_enabled) { 417 if (amdgpu_emu_mode == 1) 418 mem_info->mem_clk_max = 0; 419 else 420 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 421 } else 422 mem_info->mem_clk_max = 100; 423 } 424 425 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd) 426 { 427 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 428 429 if (adev->gfx.funcs->get_gpu_clock_counter) 430 return adev->gfx.funcs->get_gpu_clock_counter(adev); 431 return 0; 432 } 433 434 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd) 435 { 436 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 437 438 /* the sclk is in quantas of 10kHz */ 439 if (amdgpu_sriov_vf(adev)) 440 return adev->clock.default_sclk / 100; 441 else if (adev->pm.dpm_enabled) 442 return amdgpu_dpm_get_sclk(adev, false) / 100; 443 else 444 return 100; 445 } 446 447 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) 448 { 449 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 450 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 451 452 memset(cu_info, 0, sizeof(*cu_info)); 453 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 454 return; 455 456 cu_info->cu_active_number = acu_info.number; 457 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 458 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 459 sizeof(acu_info.bitmap)); 460 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 461 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 462 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 463 cu_info->simd_per_cu = acu_info.simd_per_cu; 464 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 465 cu_info->wave_front_size = acu_info.wave_front_size; 466 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 467 cu_info->lds_size = acu_info.lds_size; 468 } 469 470 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 471 struct kgd_dev **dma_buf_kgd, 472 uint64_t *bo_size, void *metadata_buffer, 473 size_t buffer_size, uint32_t *metadata_size, 474 uint32_t *flags) 475 { 476 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 477 struct dma_buf *dma_buf; 478 struct drm_gem_object *obj; 479 struct amdgpu_bo *bo; 480 uint64_t metadata_flags; 481 int r = -EINVAL; 482 483 dma_buf = dma_buf_get(dma_buf_fd); 484 if (IS_ERR(dma_buf)) 485 return PTR_ERR(dma_buf); 486 487 if (dma_buf->ops != &amdgpu_dmabuf_ops) 488 /* Can't handle non-graphics buffers */ 489 goto out_put; 490 491 obj = dma_buf->priv; 492 if (obj->dev->driver != adev->ddev->driver) 493 /* Can't handle buffers from different drivers */ 494 goto out_put; 495 496 adev = obj->dev->dev_private; 497 bo = gem_to_amdgpu_bo(obj); 498 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 499 AMDGPU_GEM_DOMAIN_GTT))) 500 /* Only VRAM and GTT BOs are supported */ 501 goto out_put; 502 503 r = 0; 504 if (dma_buf_kgd) 505 *dma_buf_kgd = (struct kgd_dev *)adev; 506 if (bo_size) 507 *bo_size = amdgpu_bo_size(bo); 508 if (metadata_size) 509 *metadata_size = bo->metadata_size; 510 if (metadata_buffer) 511 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 512 metadata_size, &metadata_flags); 513 if (flags) { 514 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 515 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 516 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 517 518 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 519 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 520 } 521 522 out_put: 523 dma_buf_put(dma_buf); 524 return r; 525 } 526 527 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd) 528 { 529 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 530 531 return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 532 } 533 534 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd) 535 { 536 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 537 538 return adev->gmc.xgmi.hive_id; 539 } 540 541 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd) 542 { 543 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 544 545 return adev->unique_id; 546 } 547 548 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src) 549 { 550 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src; 551 struct amdgpu_device *adev = (struct amdgpu_device *)dst; 552 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 553 554 if (ret < 0) { 555 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 556 adev->gmc.xgmi.physical_node_id, 557 peer_adev->gmc.xgmi.physical_node_id, ret); 558 ret = 0; 559 } 560 return (uint8_t)ret; 561 } 562 563 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd) 564 { 565 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 566 567 return adev->rmmio_remap.bus_addr; 568 } 569 570 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd) 571 { 572 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 573 574 return adev->gds.gws_size; 575 } 576 577 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 578 uint32_t vmid, uint64_t gpu_addr, 579 uint32_t *ib_cmd, uint32_t ib_len) 580 { 581 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 582 struct amdgpu_job *job; 583 struct amdgpu_ib *ib; 584 struct amdgpu_ring *ring; 585 struct dma_fence *f = NULL; 586 int ret; 587 588 switch (engine) { 589 case KGD_ENGINE_MEC1: 590 ring = &adev->gfx.compute_ring[0]; 591 break; 592 case KGD_ENGINE_SDMA1: 593 ring = &adev->sdma.instance[0].ring; 594 break; 595 case KGD_ENGINE_SDMA2: 596 ring = &adev->sdma.instance[1].ring; 597 break; 598 default: 599 pr_err("Invalid engine in IB submission: %d\n", engine); 600 ret = -EINVAL; 601 goto err; 602 } 603 604 ret = amdgpu_job_alloc(adev, 1, &job, NULL); 605 if (ret) 606 goto err; 607 608 ib = &job->ibs[0]; 609 memset(ib, 0, sizeof(struct amdgpu_ib)); 610 611 ib->gpu_addr = gpu_addr; 612 ib->ptr = ib_cmd; 613 ib->length_dw = ib_len; 614 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 615 job->vmid = vmid; 616 617 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 618 if (ret) { 619 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 620 goto err_ib_sched; 621 } 622 623 ret = dma_fence_wait(f, false); 624 625 err_ib_sched: 626 dma_fence_put(f); 627 amdgpu_job_free(job); 628 err: 629 return ret; 630 } 631 632 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 633 { 634 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 635 636 amdgpu_dpm_switch_power_profile(adev, 637 PP_SMC_POWER_PROFILE_COMPUTE, 638 !idle); 639 } 640 641 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 642 { 643 if (adev->kfd.dev) { 644 if ((1 << vmid) & compute_vmid_bitmap) 645 return true; 646 } 647 648 return false; 649 } 650 651 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid) 652 { 653 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 654 655 if (adev->family == AMDGPU_FAMILY_AI) { 656 int i; 657 658 for (i = 0; i < adev->num_vmhubs; i++) 659 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 660 } else { 661 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); 662 } 663 664 return 0; 665 } 666 667 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid) 668 { 669 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 670 const uint32_t flush_type = 0; 671 bool all_hub = false; 672 673 if (adev->family == AMDGPU_FAMILY_AI) 674 all_hub = true; 675 676 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub); 677 } 678 679 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd) 680 { 681 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 682 683 return adev->have_atomics_support; 684 } 685 686 #ifndef CONFIG_HSA_AMD 687 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 688 { 689 return false; 690 } 691 692 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) 693 { 694 } 695 696 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 697 { 698 return 0; 699 } 700 701 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 702 struct amdgpu_vm *vm) 703 { 704 } 705 706 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 707 { 708 return NULL; 709 } 710 711 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 712 { 713 return 0; 714 } 715 716 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, 717 unsigned int asic_type, bool vf) 718 { 719 return NULL; 720 } 721 722 bool kgd2kfd_device_init(struct kfd_dev *kfd, 723 struct drm_device *ddev, 724 const struct kgd2kfd_shared_resources *gpu_resources) 725 { 726 return false; 727 } 728 729 void kgd2kfd_device_exit(struct kfd_dev *kfd) 730 { 731 } 732 733 void kgd2kfd_exit(void) 734 { 735 } 736 737 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 738 { 739 } 740 741 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 742 { 743 return 0; 744 } 745 746 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 747 { 748 return 0; 749 } 750 751 int kgd2kfd_post_reset(struct kfd_dev *kfd) 752 { 753 return 0; 754 } 755 756 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 757 { 758 } 759 760 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 761 { 762 } 763 #endif 764