xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd.c (revision 4e1ee0786f11cc571bd0be17d38e46f635c719fc) 
1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "amdgpu_amdkfd.h"
24 #include "amd_shared.h"
25 
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include "amdgpu_dma_buf.h"
29 #include <linux/module.h>
30 #include <linux/dma-buf.h>
31 #include "amdgpu_xgmi.h"
32 #include <uapi/linux/kfd_ioctl.h>
33 
34 /* Total memory size in system memory and all GPU VRAM. Used to
35  * estimate worst case amount of memory to reserve for page tables
36  */
37 uint64_t amdgpu_amdkfd_total_mem_size;
38 
39 static bool kfd_initialized;
40 
41 int amdgpu_amdkfd_init(void)
42 {
43 #ifdef __linux__
44 	struct sysinfo si;
45 	int ret;
46 
47 	si_meminfo(&si);
48 	amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
49 	amdgpu_amdkfd_total_mem_size *= si.mem_unit;
50 #else
51 	int ret;
52 
53 	amdgpu_amdkfd_total_mem_size = ptoa(physmem);
54 #endif
55 
56 #ifdef CONFIG_HSA_AMD
57 	ret = kgd2kfd_init();
58 	amdgpu_amdkfd_gpuvm_init_mem_limits();
59 #else
60 	ret = -ENOENT;
61 #endif
62 	kfd_initialized = !ret;
63 
64 	return ret;
65 }
66 
67 void amdgpu_amdkfd_fini(void)
68 {
69 	if (kfd_initialized) {
70 		kgd2kfd_exit();
71 		kfd_initialized = false;
72 	}
73 }
74 
75 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
76 {
77 	bool vf = amdgpu_sriov_vf(adev);
78 
79 	if (!kfd_initialized)
80 		return;
81 
82 	adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
83 				      adev->pdev, adev->asic_type, vf);
84 
85 	if (adev->kfd.dev)
86 		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
87 }
88 
89 /**
90  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
91  *                                setup amdkfd
92  *
93  * @adev: amdgpu_device pointer
94  * @aperture_base: output returning doorbell aperture base physical address
95  * @aperture_size: output returning doorbell aperture size in bytes
96  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
97  *
98  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
99  * takes doorbells required for its own rings and reports the setup to amdkfd.
100  * amdgpu reserved doorbells are at the start of the doorbell aperture.
101  */
102 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
103 					 phys_addr_t *aperture_base,
104 					 size_t *aperture_size,
105 					 size_t *start_offset)
106 {
107 	/*
108 	 * The first num_doorbells are used by amdgpu.
109 	 * amdkfd takes whatever's left in the aperture.
110 	 */
111 	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
112 		*aperture_base = adev->doorbell.base;
113 		*aperture_size = adev->doorbell.size;
114 		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
115 	} else {
116 		*aperture_base = 0;
117 		*aperture_size = 0;
118 		*start_offset = 0;
119 	}
120 }
121 
122 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
123 {
124 	int i;
125 	int last_valid_bit;
126 
127 	if (adev->kfd.dev) {
128 		struct kgd2kfd_shared_resources gpu_resources = {
129 			.compute_vmid_bitmap =
130 				((1 << AMDGPU_NUM_VMID) - 1) -
131 				((1 << adev->vm_manager.first_kfd_vmid) - 1),
132 			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
133 			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
134 			.gpuvm_size = min(adev->vm_manager.max_pfn
135 					  << AMDGPU_GPU_PAGE_SHIFT,
136 					  AMDGPU_GMC_HOLE_START),
137 			.drm_render_minor = adev_to_drm(adev)->render->index,
138 			.sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
139 
140 		};
141 
142 		/* this is going to have a few of the MSBs set that we need to
143 		 * clear
144 		 */
145 		bitmap_complement(gpu_resources.cp_queue_bitmap,
146 				  adev->gfx.mec.queue_bitmap,
147 				  KGD_MAX_QUEUES);
148 
149 		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
150 		 * nbits is not compile time constant
151 		 */
152 		last_valid_bit = 1 /* only first MEC can have compute queues */
153 				* adev->gfx.mec.num_pipe_per_mec
154 				* adev->gfx.mec.num_queue_per_pipe;
155 		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
156 			clear_bit(i, gpu_resources.cp_queue_bitmap);
157 
158 		amdgpu_doorbell_get_kfd_info(adev,
159 				&gpu_resources.doorbell_physical_address,
160 				&gpu_resources.doorbell_aperture_size,
161 				&gpu_resources.doorbell_start_offset);
162 
163 		/* Since SOC15, BIF starts to statically use the
164 		 * lower 12 bits of doorbell addresses for routing
165 		 * based on settings in registers like
166 		 * SDMA0_DOORBELL_RANGE etc..
167 		 * In order to route a doorbell to CP engine, the lower
168 		 * 12 bits of its address has to be outside the range
169 		 * set for SDMA, VCN, and IH blocks.
170 		 */
171 		if (adev->asic_type >= CHIP_VEGA10) {
172 			gpu_resources.non_cp_doorbells_start =
173 					adev->doorbell_index.first_non_cp;
174 			gpu_resources.non_cp_doorbells_end =
175 					adev->doorbell_index.last_non_cp;
176 		}
177 
178 		kgd2kfd_device_init(adev->kfd.dev, adev_to_drm(adev), &gpu_resources);
179 	}
180 }
181 
182 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
183 {
184 	if (adev->kfd.dev) {
185 		kgd2kfd_device_exit(adev->kfd.dev);
186 		adev->kfd.dev = NULL;
187 	}
188 }
189 
190 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
191 		const void *ih_ring_entry)
192 {
193 	if (adev->kfd.dev)
194 		kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
195 }
196 
197 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
198 {
199 	if (adev->kfd.dev)
200 		kgd2kfd_suspend(adev->kfd.dev, run_pm);
201 }
202 
203 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
204 {
205 	int r = 0;
206 
207 	if (adev->kfd.dev)
208 		r = kgd2kfd_resume(adev->kfd.dev, run_pm);
209 
210 	return r;
211 }
212 
213 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
214 {
215 	int r = 0;
216 
217 	if (adev->kfd.dev)
218 		r = kgd2kfd_pre_reset(adev->kfd.dev);
219 
220 	return r;
221 }
222 
223 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
224 {
225 	int r = 0;
226 
227 	if (adev->kfd.dev)
228 		r = kgd2kfd_post_reset(adev->kfd.dev);
229 
230 	return r;
231 }
232 
233 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
234 {
235 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
236 
237 	if (amdgpu_device_should_recover_gpu(adev))
238 		amdgpu_device_gpu_recover(adev, NULL);
239 }
240 
241 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
242 				void **mem_obj, uint64_t *gpu_addr,
243 				void **cpu_ptr, bool cp_mqd_gfx9)
244 {
245 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
246 	struct amdgpu_bo *bo = NULL;
247 	struct amdgpu_bo_param bp;
248 	int r;
249 	void *cpu_ptr_tmp = NULL;
250 
251 	memset(&bp, 0, sizeof(bp));
252 	bp.size = size;
253 	bp.byte_align = PAGE_SIZE;
254 	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
255 	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
256 	bp.type = ttm_bo_type_kernel;
257 	bp.resv = NULL;
258 
259 	if (cp_mqd_gfx9)
260 		bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
261 
262 	r = amdgpu_bo_create(adev, &bp, &bo);
263 	if (r) {
264 		dev_err(adev->dev,
265 			"failed to allocate BO for amdkfd (%d)\n", r);
266 		return r;
267 	}
268 
269 	/* map the buffer */
270 	r = amdgpu_bo_reserve(bo, true);
271 	if (r) {
272 		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
273 		goto allocate_mem_reserve_bo_failed;
274 	}
275 
276 	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
277 	if (r) {
278 		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
279 		goto allocate_mem_pin_bo_failed;
280 	}
281 
282 	r = amdgpu_ttm_alloc_gart(&bo->tbo);
283 	if (r) {
284 		dev_err(adev->dev, "%p bind failed\n", bo);
285 		goto allocate_mem_kmap_bo_failed;
286 	}
287 
288 	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
289 	if (r) {
290 		dev_err(adev->dev,
291 			"(%d) failed to map bo to kernel for amdkfd\n", r);
292 		goto allocate_mem_kmap_bo_failed;
293 	}
294 
295 	*mem_obj = bo;
296 	*gpu_addr = amdgpu_bo_gpu_offset(bo);
297 	*cpu_ptr = cpu_ptr_tmp;
298 
299 	amdgpu_bo_unreserve(bo);
300 
301 	return 0;
302 
303 allocate_mem_kmap_bo_failed:
304 	amdgpu_bo_unpin(bo);
305 allocate_mem_pin_bo_failed:
306 	amdgpu_bo_unreserve(bo);
307 allocate_mem_reserve_bo_failed:
308 	amdgpu_bo_unref(&bo);
309 
310 	return r;
311 }
312 
313 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
314 {
315 	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
316 
317 	amdgpu_bo_reserve(bo, true);
318 	amdgpu_bo_kunmap(bo);
319 	amdgpu_bo_unpin(bo);
320 	amdgpu_bo_unreserve(bo);
321 	amdgpu_bo_unref(&(bo));
322 }
323 
324 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
325 				void **mem_obj)
326 {
327 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
328 	struct amdgpu_bo *bo = NULL;
329 	struct amdgpu_bo_param bp;
330 	int r;
331 
332 	memset(&bp, 0, sizeof(bp));
333 	bp.size = size;
334 	bp.byte_align = 1;
335 	bp.domain = AMDGPU_GEM_DOMAIN_GWS;
336 	bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
337 	bp.type = ttm_bo_type_device;
338 	bp.resv = NULL;
339 
340 	r = amdgpu_bo_create(adev, &bp, &bo);
341 	if (r) {
342 		dev_err(adev->dev,
343 			"failed to allocate gws BO for amdkfd (%d)\n", r);
344 		return r;
345 	}
346 
347 	*mem_obj = bo;
348 	return 0;
349 }
350 
351 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
352 {
353 	struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
354 
355 	amdgpu_bo_unref(&bo);
356 }
357 
358 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
359 				      enum kgd_engine_type type)
360 {
361 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
362 
363 	switch (type) {
364 	case KGD_ENGINE_PFP:
365 		return adev->gfx.pfp_fw_version;
366 
367 	case KGD_ENGINE_ME:
368 		return adev->gfx.me_fw_version;
369 
370 	case KGD_ENGINE_CE:
371 		return adev->gfx.ce_fw_version;
372 
373 	case KGD_ENGINE_MEC1:
374 		return adev->gfx.mec_fw_version;
375 
376 	case KGD_ENGINE_MEC2:
377 		return adev->gfx.mec2_fw_version;
378 
379 	case KGD_ENGINE_RLC:
380 		return adev->gfx.rlc_fw_version;
381 
382 	case KGD_ENGINE_SDMA1:
383 		return adev->sdma.instance[0].fw_version;
384 
385 	case KGD_ENGINE_SDMA2:
386 		return adev->sdma.instance[1].fw_version;
387 
388 	default:
389 		return 0;
390 	}
391 
392 	return 0;
393 }
394 
395 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
396 				      struct kfd_local_mem_info *mem_info)
397 {
398 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
399 #ifdef __linux__
400 	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
401 					     ~((1ULL << 32) - 1);
402 #else
403 	uint64_t address_mask = ~((1ULL << 32) - 1);
404 #endif
405 	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
406 
407 	memset(mem_info, 0, sizeof(*mem_info));
408 	if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
409 		mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
410 		mem_info->local_mem_size_private = adev->gmc.real_vram_size -
411 				adev->gmc.visible_vram_size;
412 	} else {
413 		mem_info->local_mem_size_public = 0;
414 		mem_info->local_mem_size_private = adev->gmc.real_vram_size;
415 	}
416 	mem_info->vram_width = adev->gmc.vram_width;
417 
418 	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
419 			&adev->gmc.aper_base, &aper_limit,
420 			mem_info->local_mem_size_public,
421 			mem_info->local_mem_size_private);
422 
423 	if (amdgpu_sriov_vf(adev))
424 		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
425 	else if (adev->pm.dpm_enabled) {
426 		if (amdgpu_emu_mode == 1)
427 			mem_info->mem_clk_max = 0;
428 		else
429 			mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
430 	} else
431 		mem_info->mem_clk_max = 100;
432 }
433 
434 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
435 {
436 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
437 
438 	if (adev->gfx.funcs->get_gpu_clock_counter)
439 		return adev->gfx.funcs->get_gpu_clock_counter(adev);
440 	return 0;
441 }
442 
443 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
444 {
445 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
446 
447 	/* the sclk is in quantas of 10kHz */
448 	if (amdgpu_sriov_vf(adev))
449 		return adev->clock.default_sclk / 100;
450 	else if (adev->pm.dpm_enabled)
451 		return amdgpu_dpm_get_sclk(adev, false) / 100;
452 	else
453 		return 100;
454 }
455 
456 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
457 {
458 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
459 	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
460 
461 	memset(cu_info, 0, sizeof(*cu_info));
462 	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
463 		return;
464 
465 	cu_info->cu_active_number = acu_info.number;
466 	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
467 	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
468 	       sizeof(acu_info.bitmap));
469 	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
470 	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
471 	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
472 	cu_info->simd_per_cu = acu_info.simd_per_cu;
473 	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
474 	cu_info->wave_front_size = acu_info.wave_front_size;
475 	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
476 	cu_info->lds_size = acu_info.lds_size;
477 }
478 
479 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
480 				  struct kgd_dev **dma_buf_kgd,
481 				  uint64_t *bo_size, void *metadata_buffer,
482 				  size_t buffer_size, uint32_t *metadata_size,
483 				  uint32_t *flags)
484 {
485 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
486 	struct dma_buf *dma_buf;
487 	struct drm_gem_object *obj;
488 	struct amdgpu_bo *bo;
489 	uint64_t metadata_flags;
490 	int r = -EINVAL;
491 
492 	dma_buf = dma_buf_get(dma_buf_fd);
493 	if (IS_ERR(dma_buf))
494 		return PTR_ERR(dma_buf);
495 
496 	if (dma_buf->ops != &amdgpu_dmabuf_ops)
497 		/* Can't handle non-graphics buffers */
498 		goto out_put;
499 
500 	obj = dma_buf->priv;
501 	if (obj->dev->driver != adev_to_drm(adev)->driver)
502 		/* Can't handle buffers from different drivers */
503 		goto out_put;
504 
505 	adev = drm_to_adev(obj->dev);
506 	bo = gem_to_amdgpu_bo(obj);
507 	if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
508 				    AMDGPU_GEM_DOMAIN_GTT)))
509 		/* Only VRAM and GTT BOs are supported */
510 		goto out_put;
511 
512 	r = 0;
513 	if (dma_buf_kgd)
514 		*dma_buf_kgd = (struct kgd_dev *)adev;
515 	if (bo_size)
516 		*bo_size = amdgpu_bo_size(bo);
517 	if (metadata_size)
518 		*metadata_size = bo->metadata_size;
519 	if (metadata_buffer)
520 		r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
521 					   metadata_size, &metadata_flags);
522 	if (flags) {
523 		*flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
524 				KFD_IOC_ALLOC_MEM_FLAGS_VRAM
525 				: KFD_IOC_ALLOC_MEM_FLAGS_GTT;
526 
527 		if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
528 			*flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
529 	}
530 
531 out_put:
532 	dma_buf_put(dma_buf);
533 	return r;
534 }
535 
536 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
537 {
538 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
539 	struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
540 
541 	return amdgpu_vram_mgr_usage(vram_man);
542 }
543 
544 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
545 {
546 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
547 
548 	return adev->gmc.xgmi.hive_id;
549 }
550 
551 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd)
552 {
553 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
554 
555 	return adev->unique_id;
556 }
557 
558 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
559 {
560 	struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
561 	struct amdgpu_device *adev = (struct amdgpu_device *)dst;
562 	int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
563 
564 	if (ret < 0) {
565 		DRM_ERROR("amdgpu: failed to get  xgmi hops count between node %d and %d. ret = %d\n",
566 			adev->gmc.xgmi.physical_node_id,
567 			peer_adev->gmc.xgmi.physical_node_id, ret);
568 		ret = 0;
569 	}
570 	return  (uint8_t)ret;
571 }
572 
573 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
574 {
575 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
576 
577 	return adev->rmmio_remap.bus_addr;
578 }
579 
580 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
581 {
582 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
583 
584 	return adev->gds.gws_size;
585 }
586 
587 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
588 {
589 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
590 
591 	return adev->rev_id;
592 }
593 
594 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd)
595 {
596 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
597 
598 	return adev->gmc.noretry;
599 }
600 
601 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
602 				uint32_t vmid, uint64_t gpu_addr,
603 				uint32_t *ib_cmd, uint32_t ib_len)
604 {
605 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
606 	struct amdgpu_job *job;
607 	struct amdgpu_ib *ib;
608 	struct amdgpu_ring *ring;
609 	struct dma_fence *f = NULL;
610 	int ret;
611 
612 	switch (engine) {
613 	case KGD_ENGINE_MEC1:
614 		ring = &adev->gfx.compute_ring[0];
615 		break;
616 	case KGD_ENGINE_SDMA1:
617 		ring = &adev->sdma.instance[0].ring;
618 		break;
619 	case KGD_ENGINE_SDMA2:
620 		ring = &adev->sdma.instance[1].ring;
621 		break;
622 	default:
623 		pr_err("Invalid engine in IB submission: %d\n", engine);
624 		ret = -EINVAL;
625 		goto err;
626 	}
627 
628 	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
629 	if (ret)
630 		goto err;
631 
632 	ib = &job->ibs[0];
633 	memset(ib, 0, sizeof(struct amdgpu_ib));
634 
635 	ib->gpu_addr = gpu_addr;
636 	ib->ptr = ib_cmd;
637 	ib->length_dw = ib_len;
638 	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
639 	job->vmid = vmid;
640 
641 	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
642 
643 	if (ret) {
644 		DRM_ERROR("amdgpu: failed to schedule IB.\n");
645 		goto err_ib_sched;
646 	}
647 
648 	ret = dma_fence_wait(f, false);
649 
650 err_ib_sched:
651 	dma_fence_put(f);
652 	amdgpu_job_free(job);
653 err:
654 	return ret;
655 }
656 
657 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
658 {
659 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
660 
661 	amdgpu_dpm_switch_power_profile(adev,
662 					PP_SMC_POWER_PROFILE_COMPUTE,
663 					!idle);
664 }
665 
666 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
667 {
668 	if (adev->kfd.dev)
669 		return vmid >= adev->vm_manager.first_kfd_vmid;
670 
671 	return false;
672 }
673 
674 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
675 {
676 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
677 
678 	if (adev->family == AMDGPU_FAMILY_AI) {
679 		int i;
680 
681 		for (i = 0; i < adev->num_vmhubs; i++)
682 			amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
683 	} else {
684 		amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
685 	}
686 
687 	return 0;
688 }
689 
690 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid)
691 {
692 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
693 	const uint32_t flush_type = 0;
694 	bool all_hub = false;
695 
696 	if (adev->family == AMDGPU_FAMILY_AI)
697 		all_hub = true;
698 
699 	return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
700 }
701 
702 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
703 {
704 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
705 
706 	return adev->have_atomics_support;
707 }
708 
709 #ifndef CONFIG_HSA_AMD
710 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
711 {
712 	return false;
713 }
714 
715 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
716 {
717 }
718 
719 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
720 {
721 	return 0;
722 }
723 
724 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
725 					struct amdgpu_vm *vm)
726 {
727 }
728 
729 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
730 {
731 	return NULL;
732 }
733 
734 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
735 {
736 	return 0;
737 }
738 
739 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
740 			      unsigned int asic_type, bool vf)
741 {
742 	return NULL;
743 }
744 
745 bool kgd2kfd_device_init(struct kfd_dev *kfd,
746 			 struct drm_device *ddev,
747 			 const struct kgd2kfd_shared_resources *gpu_resources)
748 {
749 	return false;
750 }
751 
752 void kgd2kfd_device_exit(struct kfd_dev *kfd)
753 {
754 }
755 
756 void kgd2kfd_exit(void)
757 {
758 }
759 
760 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
761 {
762 }
763 
764 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
765 {
766 	return 0;
767 }
768 
769 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
770 {
771 	return 0;
772 }
773 
774 int kgd2kfd_post_reset(struct kfd_dev *kfd)
775 {
776 	return 0;
777 }
778 
779 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
780 {
781 }
782 
783 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
784 {
785 }
786 
787 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask)
788 {
789 }
790 #endif
791