1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_amdkfd.h" 24 #include "amd_pcie.h" 25 #include "amd_shared.h" 26 27 #include "amdgpu.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_dma_buf.h" 30 #include <linux/module.h> 31 #include <linux/dma-buf.h> 32 #include "amdgpu_xgmi.h" 33 #include <uapi/linux/kfd_ioctl.h> 34 35 /* Total memory size in system memory and all GPU VRAM. Used to 36 * estimate worst case amount of memory to reserve for page tables 37 */ 38 uint64_t amdgpu_amdkfd_total_mem_size; 39 40 static bool kfd_initialized; 41 42 int amdgpu_amdkfd_init(void) 43 { 44 #ifdef __linux__ 45 struct sysinfo si; 46 int ret; 47 48 si_meminfo(&si); 49 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 50 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 51 #else 52 int ret; 53 54 amdgpu_amdkfd_total_mem_size = ptoa(physmem); 55 #endif 56 ret = kgd2kfd_init(); 57 amdgpu_amdkfd_gpuvm_init_mem_limits(); 58 kfd_initialized = !ret; 59 60 return ret; 61 } 62 63 void amdgpu_amdkfd_fini(void) 64 { 65 if (kfd_initialized) { 66 kgd2kfd_exit(); 67 kfd_initialized = false; 68 } 69 } 70 71 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 72 { 73 bool vf = amdgpu_sriov_vf(adev); 74 75 if (!kfd_initialized) 76 return; 77 78 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, 79 adev->pdev, adev->asic_type, vf); 80 81 if (adev->kfd.dev) 82 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 83 } 84 85 /** 86 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 87 * setup amdkfd 88 * 89 * @adev: amdgpu_device pointer 90 * @aperture_base: output returning doorbell aperture base physical address 91 * @aperture_size: output returning doorbell aperture size in bytes 92 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 93 * 94 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 95 * takes doorbells required for its own rings and reports the setup to amdkfd. 96 * amdgpu reserved doorbells are at the start of the doorbell aperture. 97 */ 98 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 99 phys_addr_t *aperture_base, 100 size_t *aperture_size, 101 size_t *start_offset) 102 { 103 /* 104 * The first num_doorbells are used by amdgpu. 105 * amdkfd takes whatever's left in the aperture. 106 */ 107 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { 108 *aperture_base = adev->doorbell.base; 109 *aperture_size = adev->doorbell.size; 110 *start_offset = adev->doorbell.num_doorbells * sizeof(u32); 111 } else { 112 *aperture_base = 0; 113 *aperture_size = 0; 114 *start_offset = 0; 115 } 116 } 117 118 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 119 { 120 int i; 121 int last_valid_bit; 122 123 if (adev->kfd.dev) { 124 struct kgd2kfd_shared_resources gpu_resources = { 125 .compute_vmid_bitmap = 126 ((1 << AMDGPU_NUM_VMID) - 1) - 127 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 128 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 129 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 130 .gpuvm_size = min(adev->vm_manager.max_pfn 131 << AMDGPU_GPU_PAGE_SHIFT, 132 AMDGPU_GMC_HOLE_START), 133 .drm_render_minor = adev_to_drm(adev)->render->index, 134 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 135 136 }; 137 138 /* this is going to have a few of the MSBs set that we need to 139 * clear 140 */ 141 bitmap_complement(gpu_resources.cp_queue_bitmap, 142 adev->gfx.mec.queue_bitmap, 143 KGD_MAX_QUEUES); 144 145 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 146 * nbits is not compile time constant 147 */ 148 last_valid_bit = 1 /* only first MEC can have compute queues */ 149 * adev->gfx.mec.num_pipe_per_mec 150 * adev->gfx.mec.num_queue_per_pipe; 151 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 152 clear_bit(i, gpu_resources.cp_queue_bitmap); 153 154 amdgpu_doorbell_get_kfd_info(adev, 155 &gpu_resources.doorbell_physical_address, 156 &gpu_resources.doorbell_aperture_size, 157 &gpu_resources.doorbell_start_offset); 158 159 /* Since SOC15, BIF starts to statically use the 160 * lower 12 bits of doorbell addresses for routing 161 * based on settings in registers like 162 * SDMA0_DOORBELL_RANGE etc.. 163 * In order to route a doorbell to CP engine, the lower 164 * 12 bits of its address has to be outside the range 165 * set for SDMA, VCN, and IH blocks. 166 */ 167 if (adev->asic_type >= CHIP_VEGA10) { 168 gpu_resources.non_cp_doorbells_start = 169 adev->doorbell_index.first_non_cp; 170 gpu_resources.non_cp_doorbells_end = 171 adev->doorbell_index.last_non_cp; 172 } 173 174 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 175 adev_to_drm(adev), &gpu_resources); 176 } 177 } 178 179 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 180 { 181 if (adev->kfd.dev) { 182 kgd2kfd_device_exit(adev->kfd.dev); 183 adev->kfd.dev = NULL; 184 } 185 } 186 187 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 188 const void *ih_ring_entry) 189 { 190 if (adev->kfd.dev) 191 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 192 } 193 194 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 195 { 196 if (adev->kfd.dev) 197 kgd2kfd_suspend(adev->kfd.dev, run_pm); 198 } 199 200 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev) 201 { 202 int r = 0; 203 204 if (adev->kfd.dev) 205 r = kgd2kfd_resume_iommu(adev->kfd.dev); 206 207 return r; 208 } 209 210 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 211 { 212 int r = 0; 213 214 if (adev->kfd.dev) 215 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 216 217 return r; 218 } 219 220 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 221 { 222 int r = 0; 223 224 if (adev->kfd.dev) 225 r = kgd2kfd_pre_reset(adev->kfd.dev); 226 227 return r; 228 } 229 230 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 231 { 232 int r = 0; 233 234 if (adev->kfd.dev) 235 r = kgd2kfd_post_reset(adev->kfd.dev); 236 237 return r; 238 } 239 240 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd) 241 { 242 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 243 244 if (amdgpu_device_should_recover_gpu(adev)) 245 amdgpu_device_gpu_recover(adev, NULL); 246 } 247 248 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 249 void **mem_obj, uint64_t *gpu_addr, 250 void **cpu_ptr, bool cp_mqd_gfx9) 251 { 252 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 253 struct amdgpu_bo *bo = NULL; 254 struct amdgpu_bo_param bp; 255 int r; 256 void *cpu_ptr_tmp = NULL; 257 258 memset(&bp, 0, sizeof(bp)); 259 bp.size = size; 260 bp.byte_align = PAGE_SIZE; 261 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 262 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 263 bp.type = ttm_bo_type_kernel; 264 bp.resv = NULL; 265 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 266 267 if (cp_mqd_gfx9) 268 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 269 270 r = amdgpu_bo_create(adev, &bp, &bo); 271 if (r) { 272 dev_err(adev->dev, 273 "failed to allocate BO for amdkfd (%d)\n", r); 274 return r; 275 } 276 277 /* map the buffer */ 278 r = amdgpu_bo_reserve(bo, true); 279 if (r) { 280 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 281 goto allocate_mem_reserve_bo_failed; 282 } 283 284 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 285 if (r) { 286 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 287 goto allocate_mem_pin_bo_failed; 288 } 289 290 r = amdgpu_ttm_alloc_gart(&bo->tbo); 291 if (r) { 292 dev_err(adev->dev, "%p bind failed\n", bo); 293 goto allocate_mem_kmap_bo_failed; 294 } 295 296 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 297 if (r) { 298 dev_err(adev->dev, 299 "(%d) failed to map bo to kernel for amdkfd\n", r); 300 goto allocate_mem_kmap_bo_failed; 301 } 302 303 *mem_obj = bo; 304 *gpu_addr = amdgpu_bo_gpu_offset(bo); 305 *cpu_ptr = cpu_ptr_tmp; 306 307 amdgpu_bo_unreserve(bo); 308 309 return 0; 310 311 allocate_mem_kmap_bo_failed: 312 amdgpu_bo_unpin(bo); 313 allocate_mem_pin_bo_failed: 314 amdgpu_bo_unreserve(bo); 315 allocate_mem_reserve_bo_failed: 316 amdgpu_bo_unref(&bo); 317 318 return r; 319 } 320 321 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) 322 { 323 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 324 325 amdgpu_bo_reserve(bo, true); 326 amdgpu_bo_kunmap(bo); 327 amdgpu_bo_unpin(bo); 328 amdgpu_bo_unreserve(bo); 329 amdgpu_bo_unref(&(bo)); 330 } 331 332 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, 333 void **mem_obj) 334 { 335 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 336 struct amdgpu_bo *bo = NULL; 337 struct amdgpu_bo_user *ubo; 338 struct amdgpu_bo_param bp; 339 int r; 340 341 memset(&bp, 0, sizeof(bp)); 342 bp.size = size; 343 bp.byte_align = 1; 344 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 345 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 346 bp.type = ttm_bo_type_device; 347 bp.resv = NULL; 348 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 349 350 r = amdgpu_bo_create_user(adev, &bp, &ubo); 351 if (r) { 352 dev_err(adev->dev, 353 "failed to allocate gws BO for amdkfd (%d)\n", r); 354 return r; 355 } 356 357 bo = &ubo->bo; 358 *mem_obj = bo; 359 return 0; 360 } 361 362 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj) 363 { 364 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 365 366 amdgpu_bo_unref(&bo); 367 } 368 369 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 370 enum kgd_engine_type type) 371 { 372 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 373 374 switch (type) { 375 case KGD_ENGINE_PFP: 376 return adev->gfx.pfp_fw_version; 377 378 case KGD_ENGINE_ME: 379 return adev->gfx.me_fw_version; 380 381 case KGD_ENGINE_CE: 382 return adev->gfx.ce_fw_version; 383 384 case KGD_ENGINE_MEC1: 385 return adev->gfx.mec_fw_version; 386 387 case KGD_ENGINE_MEC2: 388 return adev->gfx.mec2_fw_version; 389 390 case KGD_ENGINE_RLC: 391 return adev->gfx.rlc_fw_version; 392 393 case KGD_ENGINE_SDMA1: 394 return adev->sdma.instance[0].fw_version; 395 396 case KGD_ENGINE_SDMA2: 397 return adev->sdma.instance[1].fw_version; 398 399 default: 400 return 0; 401 } 402 403 return 0; 404 } 405 406 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 407 struct kfd_local_mem_info *mem_info) 408 { 409 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 410 411 memset(mem_info, 0, sizeof(*mem_info)); 412 413 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 414 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 415 adev->gmc.visible_vram_size; 416 417 mem_info->vram_width = adev->gmc.vram_width; 418 419 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 420 &adev->gmc.aper_base, 421 mem_info->local_mem_size_public, 422 mem_info->local_mem_size_private); 423 424 if (amdgpu_sriov_vf(adev)) 425 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 426 else if (adev->pm.dpm_enabled) { 427 if (amdgpu_emu_mode == 1) 428 mem_info->mem_clk_max = 0; 429 else 430 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 431 } else 432 mem_info->mem_clk_max = 100; 433 } 434 435 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd) 436 { 437 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 438 439 if (adev->gfx.funcs->get_gpu_clock_counter) 440 return adev->gfx.funcs->get_gpu_clock_counter(adev); 441 return 0; 442 } 443 444 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd) 445 { 446 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 447 448 /* the sclk is in quantas of 10kHz */ 449 if (amdgpu_sriov_vf(adev)) 450 return adev->clock.default_sclk / 100; 451 else if (adev->pm.dpm_enabled) 452 return amdgpu_dpm_get_sclk(adev, false) / 100; 453 else 454 return 100; 455 } 456 457 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) 458 { 459 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 460 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 461 462 memset(cu_info, 0, sizeof(*cu_info)); 463 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 464 return; 465 466 cu_info->cu_active_number = acu_info.number; 467 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 468 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 469 sizeof(acu_info.bitmap)); 470 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 471 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 472 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 473 cu_info->simd_per_cu = acu_info.simd_per_cu; 474 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 475 cu_info->wave_front_size = acu_info.wave_front_size; 476 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 477 cu_info->lds_size = acu_info.lds_size; 478 } 479 480 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 481 struct kgd_dev **dma_buf_kgd, 482 uint64_t *bo_size, void *metadata_buffer, 483 size_t buffer_size, uint32_t *metadata_size, 484 uint32_t *flags) 485 { 486 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 487 struct dma_buf *dma_buf; 488 struct drm_gem_object *obj; 489 struct amdgpu_bo *bo; 490 uint64_t metadata_flags; 491 int r = -EINVAL; 492 493 dma_buf = dma_buf_get(dma_buf_fd); 494 if (IS_ERR(dma_buf)) 495 return PTR_ERR(dma_buf); 496 497 if (dma_buf->ops != &amdgpu_dmabuf_ops) 498 /* Can't handle non-graphics buffers */ 499 goto out_put; 500 501 obj = dma_buf->priv; 502 if (obj->dev->driver != adev_to_drm(adev)->driver) 503 /* Can't handle buffers from different drivers */ 504 goto out_put; 505 506 adev = drm_to_adev(obj->dev); 507 bo = gem_to_amdgpu_bo(obj); 508 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 509 AMDGPU_GEM_DOMAIN_GTT))) 510 /* Only VRAM and GTT BOs are supported */ 511 goto out_put; 512 513 r = 0; 514 if (dma_buf_kgd) 515 *dma_buf_kgd = (struct kgd_dev *)adev; 516 if (bo_size) 517 *bo_size = amdgpu_bo_size(bo); 518 if (metadata_buffer) 519 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 520 metadata_size, &metadata_flags); 521 if (flags) { 522 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 523 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 524 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 525 526 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 527 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 528 } 529 530 out_put: 531 dma_buf_put(dma_buf); 532 return r; 533 } 534 535 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd) 536 { 537 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 538 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 539 540 return amdgpu_vram_mgr_usage(vram_man); 541 } 542 543 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd) 544 { 545 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 546 547 return adev->gmc.xgmi.hive_id; 548 } 549 550 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd) 551 { 552 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 553 554 return adev->unique_id; 555 } 556 557 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src) 558 { 559 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src; 560 struct amdgpu_device *adev = (struct amdgpu_device *)dst; 561 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 562 563 if (ret < 0) { 564 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 565 adev->gmc.xgmi.physical_node_id, 566 peer_adev->gmc.xgmi.physical_node_id, ret); 567 ret = 0; 568 } 569 return (uint8_t)ret; 570 } 571 572 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev *src, bool is_min) 573 { 574 struct amdgpu_device *adev = (struct amdgpu_device *)dst, *peer_adev; 575 int num_links; 576 577 if (adev->asic_type != CHIP_ALDEBARAN) 578 return 0; 579 580 if (src) 581 peer_adev = (struct amdgpu_device *)src; 582 583 /* num links returns 0 for indirect peers since indirect route is unknown. */ 584 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 585 if (num_links < 0) { 586 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 587 adev->gmc.xgmi.physical_node_id, 588 peer_adev->gmc.xgmi.physical_node_id, num_links); 589 num_links = 0; 590 } 591 592 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 593 return (num_links * 16 * 25000)/BITS_PER_BYTE; 594 } 595 596 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct kgd_dev *dev, bool is_min) 597 { 598 struct amdgpu_device *adev = (struct amdgpu_device *)dev; 599 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 600 fls(adev->pm.pcie_mlw_mask)) - 1; 601 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 602 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 603 fls(adev->pm.pcie_gen_mask & 604 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 605 uint32_t num_lanes_mask = 1 << num_lanes_shift; 606 uint32_t gen_speed_mask = 1 << gen_speed_shift; 607 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 608 609 switch (num_lanes_mask) { 610 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 611 num_lanes_factor = 1; 612 break; 613 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 614 num_lanes_factor = 2; 615 break; 616 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 617 num_lanes_factor = 4; 618 break; 619 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 620 num_lanes_factor = 8; 621 break; 622 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 623 num_lanes_factor = 12; 624 break; 625 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 626 num_lanes_factor = 16; 627 break; 628 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 629 num_lanes_factor = 32; 630 break; 631 } 632 633 switch (gen_speed_mask) { 634 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 635 gen_speed_mbits_factor = 2500; 636 break; 637 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 638 gen_speed_mbits_factor = 5000; 639 break; 640 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 641 gen_speed_mbits_factor = 8000; 642 break; 643 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 644 gen_speed_mbits_factor = 16000; 645 break; 646 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 647 gen_speed_mbits_factor = 32000; 648 break; 649 } 650 651 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 652 } 653 654 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd) 655 { 656 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 657 658 return adev->rmmio_remap.bus_addr; 659 } 660 661 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd) 662 { 663 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 664 665 return adev->gds.gws_size; 666 } 667 668 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd) 669 { 670 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 671 672 return adev->rev_id; 673 } 674 675 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd) 676 { 677 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 678 679 return adev->gmc.noretry; 680 } 681 682 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 683 uint32_t vmid, uint64_t gpu_addr, 684 uint32_t *ib_cmd, uint32_t ib_len) 685 { 686 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 687 struct amdgpu_job *job; 688 struct amdgpu_ib *ib; 689 struct amdgpu_ring *ring; 690 struct dma_fence *f = NULL; 691 int ret; 692 693 switch (engine) { 694 case KGD_ENGINE_MEC1: 695 ring = &adev->gfx.compute_ring[0]; 696 break; 697 case KGD_ENGINE_SDMA1: 698 ring = &adev->sdma.instance[0].ring; 699 break; 700 case KGD_ENGINE_SDMA2: 701 ring = &adev->sdma.instance[1].ring; 702 break; 703 default: 704 pr_err("Invalid engine in IB submission: %d\n", engine); 705 ret = -EINVAL; 706 goto err; 707 } 708 709 ret = amdgpu_job_alloc(adev, 1, &job, NULL); 710 if (ret) 711 goto err; 712 713 ib = &job->ibs[0]; 714 memset(ib, 0, sizeof(struct amdgpu_ib)); 715 716 ib->gpu_addr = gpu_addr; 717 ib->ptr = ib_cmd; 718 ib->length_dw = ib_len; 719 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 720 job->vmid = vmid; 721 722 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 723 724 if (ret) { 725 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 726 goto err_ib_sched; 727 } 728 729 ret = dma_fence_wait(f, false); 730 731 err_ib_sched: 732 amdgpu_job_free(job); 733 err: 734 return ret; 735 } 736 737 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 738 { 739 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 740 741 amdgpu_dpm_switch_power_profile(adev, 742 PP_SMC_POWER_PROFILE_COMPUTE, 743 !idle); 744 } 745 746 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 747 { 748 if (adev->kfd.dev) 749 return vmid >= adev->vm_manager.first_kfd_vmid; 750 751 return false; 752 } 753 754 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid) 755 { 756 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 757 758 if (adev->family == AMDGPU_FAMILY_AI) { 759 int i; 760 761 for (i = 0; i < adev->num_vmhubs; i++) 762 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 763 } else { 764 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); 765 } 766 767 return 0; 768 } 769 770 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid, 771 enum TLB_FLUSH_TYPE flush_type) 772 { 773 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 774 bool all_hub = false; 775 776 if (adev->family == AMDGPU_FAMILY_AI || 777 adev->family == AMDGPU_FAMILY_RV) 778 all_hub = true; 779 780 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub); 781 } 782 783 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd) 784 { 785 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 786 787 return adev->have_atomics_support; 788 } 789