1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 64 #include <dev/wscons/wsconsio.h> 65 #include <dev/wscons/wsdisplayvar.h> 66 #include <dev/rasops/rasops.h> 67 68 #include <kgd_kfd_interface.h> 69 #include "dm_pp_interface.h" 70 #include "kgd_pp_interface.h" 71 72 #include "amd_shared.h" 73 #include "amdgpu_mode.h" 74 #include "amdgpu_ih.h" 75 #include "amdgpu_irq.h" 76 #include "amdgpu_ucode.h" 77 #include "amdgpu_ttm.h" 78 #include "amdgpu_psp.h" 79 #include "amdgpu_gds.h" 80 #include "amdgpu_sync.h" 81 #include "amdgpu_ring.h" 82 #include "amdgpu_vm.h" 83 #include "amdgpu_dpm.h" 84 #include "amdgpu_acp.h" 85 #include "amdgpu_uvd.h" 86 #include "amdgpu_vce.h" 87 #include "amdgpu_vcn.h" 88 #include "amdgpu_jpeg.h" 89 #include "amdgpu_mn.h" 90 #include "amdgpu_gmc.h" 91 #include "amdgpu_gfx.h" 92 #include "amdgpu_sdma.h" 93 #include "amdgpu_lsdma.h" 94 #include "amdgpu_nbio.h" 95 #include "amdgpu_hdp.h" 96 #include "amdgpu_dm.h" 97 #include "amdgpu_virt.h" 98 #include "amdgpu_csa.h" 99 #include "amdgpu_mes_ctx.h" 100 #include "amdgpu_gart.h" 101 #include "amdgpu_debugfs.h" 102 #include "amdgpu_job.h" 103 #include "amdgpu_bo_list.h" 104 #include "amdgpu_gem.h" 105 #include "amdgpu_doorbell.h" 106 #include "amdgpu_amdkfd.h" 107 #include "amdgpu_discovery.h" 108 #include "amdgpu_mes.h" 109 #include "amdgpu_umc.h" 110 #include "amdgpu_mmhub.h" 111 #include "amdgpu_gfxhub.h" 112 #include "amdgpu_df.h" 113 #include "amdgpu_smuio.h" 114 #include "amdgpu_fdinfo.h" 115 #include "amdgpu_mca.h" 116 #include "amdgpu_ras.h" 117 118 #define MAX_GPU_INSTANCE 16 119 120 struct amdgpu_gpu_instance 121 { 122 struct amdgpu_device *adev; 123 int mgpu_fan_enabled; 124 }; 125 126 struct amdgpu_mgpu_info 127 { 128 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 129 struct rwlock mutex; 130 uint32_t num_gpu; 131 uint32_t num_dgpu; 132 uint32_t num_apu; 133 134 /* delayed reset_func for XGMI configuration if necessary */ 135 struct delayed_work delayed_reset_work; 136 bool pending_reset; 137 }; 138 139 enum amdgpu_ss { 140 AMDGPU_SS_DRV_LOAD, 141 AMDGPU_SS_DEV_D0, 142 AMDGPU_SS_DEV_D3, 143 AMDGPU_SS_DRV_UNLOAD 144 }; 145 146 struct amdgpu_watchdog_timer 147 { 148 bool timeout_fatal_disable; 149 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 150 }; 151 152 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 153 154 /* 155 * Modules parameters. 156 */ 157 extern int amdgpu_modeset; 158 extern int amdgpu_vram_limit; 159 extern int amdgpu_vis_vram_limit; 160 extern int amdgpu_gart_size; 161 extern int amdgpu_gtt_size; 162 extern int amdgpu_moverate; 163 extern int amdgpu_audio; 164 extern int amdgpu_disp_priority; 165 extern int amdgpu_hw_i2c; 166 extern int amdgpu_pcie_gen2; 167 extern int amdgpu_msi; 168 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 169 extern int amdgpu_dpm; 170 extern int amdgpu_fw_load_type; 171 extern int amdgpu_aspm; 172 extern int amdgpu_runtime_pm; 173 extern uint amdgpu_ip_block_mask; 174 extern int amdgpu_bapm; 175 extern int amdgpu_deep_color; 176 extern int amdgpu_vm_size; 177 extern int amdgpu_vm_block_size; 178 extern int amdgpu_vm_fragment_size; 179 extern int amdgpu_vm_fault_stop; 180 extern int amdgpu_vm_debug; 181 extern int amdgpu_vm_update_mode; 182 extern int amdgpu_exp_hw_support; 183 extern int amdgpu_dc; 184 extern int amdgpu_sched_jobs; 185 extern int amdgpu_sched_hw_submission; 186 extern uint amdgpu_pcie_gen_cap; 187 extern uint amdgpu_pcie_lane_cap; 188 extern u64 amdgpu_cg_mask; 189 extern uint amdgpu_pg_mask; 190 extern uint amdgpu_sdma_phase_quantum; 191 extern char *amdgpu_disable_cu; 192 extern char *amdgpu_virtual_display; 193 extern uint amdgpu_pp_feature_mask; 194 extern uint amdgpu_force_long_training; 195 extern int amdgpu_job_hang_limit; 196 extern int amdgpu_lbpw; 197 extern int amdgpu_compute_multipipe; 198 extern int amdgpu_gpu_recovery; 199 extern int amdgpu_emu_mode; 200 extern uint amdgpu_smu_memory_pool_size; 201 extern int amdgpu_smu_pptable_id; 202 extern uint amdgpu_dc_feature_mask; 203 extern uint amdgpu_freesync_vid_mode; 204 extern uint amdgpu_dc_debug_mask; 205 extern uint amdgpu_dc_visual_confirm; 206 extern uint amdgpu_dm_abm_level; 207 extern int amdgpu_backlight; 208 extern struct amdgpu_mgpu_info mgpu_info; 209 extern int amdgpu_ras_enable; 210 extern uint amdgpu_ras_mask; 211 extern int amdgpu_bad_page_threshold; 212 extern bool amdgpu_ignore_bad_page_threshold; 213 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 214 extern int amdgpu_async_gfx_ring; 215 extern int amdgpu_mcbp; 216 extern int amdgpu_discovery; 217 extern int amdgpu_mes; 218 extern int amdgpu_mes_kiq; 219 extern int amdgpu_noretry; 220 extern int amdgpu_force_asic_type; 221 extern int amdgpu_smartshift_bias; 222 extern int amdgpu_use_xgmi_p2p; 223 #ifdef CONFIG_HSA_AMD 224 extern int sched_policy; 225 extern bool debug_evictions; 226 extern bool no_system_mem_limit; 227 #else 228 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 229 static const bool __maybe_unused debug_evictions; /* = false */ 230 static const bool __maybe_unused no_system_mem_limit; 231 #endif 232 #ifdef CONFIG_HSA_AMD_P2P 233 extern bool pcie_p2p; 234 #endif 235 236 extern int amdgpu_tmz; 237 extern int amdgpu_reset_method; 238 239 #ifdef CONFIG_DRM_AMDGPU_SI 240 extern int amdgpu_si_support; 241 #endif 242 #ifdef CONFIG_DRM_AMDGPU_CIK 243 extern int amdgpu_cik_support; 244 #endif 245 extern int amdgpu_num_kcq; 246 247 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 248 extern int amdgpu_vcnfw_log; 249 250 #define AMDGPU_VM_MAX_NUM_CTX 4096 251 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 252 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 253 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 254 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 255 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 256 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 257 #define AMDGPUFB_CONN_LIMIT 4 258 #define AMDGPU_BIOS_NUM_SCRATCH 16 259 260 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 261 262 /* hard reset data */ 263 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 264 265 /* reset flags */ 266 #define AMDGPU_RESET_GFX (1 << 0) 267 #define AMDGPU_RESET_COMPUTE (1 << 1) 268 #define AMDGPU_RESET_DMA (1 << 2) 269 #define AMDGPU_RESET_CP (1 << 3) 270 #define AMDGPU_RESET_GRBM (1 << 4) 271 #define AMDGPU_RESET_DMA1 (1 << 5) 272 #define AMDGPU_RESET_RLC (1 << 6) 273 #define AMDGPU_RESET_SEM (1 << 7) 274 #define AMDGPU_RESET_IH (1 << 8) 275 #define AMDGPU_RESET_VMC (1 << 9) 276 #define AMDGPU_RESET_MC (1 << 10) 277 #define AMDGPU_RESET_DISPLAY (1 << 11) 278 #define AMDGPU_RESET_UVD (1 << 12) 279 #define AMDGPU_RESET_VCE (1 << 13) 280 #define AMDGPU_RESET_VCE1 (1 << 14) 281 282 /* max cursor sizes (in pixels) */ 283 #define CIK_CURSOR_WIDTH 128 284 #define CIK_CURSOR_HEIGHT 128 285 286 /* smart shift bias level limits */ 287 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 288 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 289 290 struct amdgpu_device; 291 struct amdgpu_irq_src; 292 struct amdgpu_fpriv; 293 struct amdgpu_bo_va_mapping; 294 struct kfd_vm_fault_info; 295 struct amdgpu_hive_info; 296 struct amdgpu_reset_context; 297 struct amdgpu_reset_control; 298 299 enum amdgpu_cp_irq { 300 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 301 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 302 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 303 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 304 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 305 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 306 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 307 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 308 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 309 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 310 311 AMDGPU_CP_IRQ_LAST 312 }; 313 314 enum amdgpu_thermal_irq { 315 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 316 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 317 318 AMDGPU_THERMAL_IRQ_LAST 319 }; 320 321 enum amdgpu_kiq_irq { 322 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 323 AMDGPU_CP_KIQ_IRQ_LAST 324 }; 325 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 326 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 327 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 328 #define MAX_KIQ_REG_TRY 1000 329 330 int amdgpu_device_ip_set_clockgating_state(void *dev, 331 enum amd_ip_block_type block_type, 332 enum amd_clockgating_state state); 333 int amdgpu_device_ip_set_powergating_state(void *dev, 334 enum amd_ip_block_type block_type, 335 enum amd_powergating_state state); 336 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 337 u64 *flags); 338 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 339 enum amd_ip_block_type block_type); 340 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 341 enum amd_ip_block_type block_type); 342 343 #define AMDGPU_MAX_IP_NUM 16 344 345 struct amdgpu_ip_block_status { 346 bool valid; 347 bool sw; 348 bool hw; 349 bool late_initialized; 350 bool hang; 351 }; 352 353 struct amdgpu_ip_block_version { 354 const enum amd_ip_block_type type; 355 const u32 major; 356 const u32 minor; 357 const u32 rev; 358 const struct amd_ip_funcs *funcs; 359 }; 360 361 #define HW_REV(_Major, _Minor, _Rev) \ 362 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 363 364 struct amdgpu_ip_block { 365 struct amdgpu_ip_block_status status; 366 const struct amdgpu_ip_block_version *version; 367 }; 368 369 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 370 enum amd_ip_block_type type, 371 u32 major, u32 minor); 372 373 struct amdgpu_ip_block * 374 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 375 enum amd_ip_block_type type); 376 377 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 378 const struct amdgpu_ip_block_version *ip_block_version); 379 380 /* 381 * BIOS. 382 */ 383 bool amdgpu_get_bios(struct amdgpu_device *adev); 384 bool amdgpu_read_bios(struct amdgpu_device *adev); 385 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 386 u8 *bios, u32 length_bytes); 387 /* 388 * Clocks 389 */ 390 391 #define AMDGPU_MAX_PPLL 3 392 393 struct amdgpu_clock { 394 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 395 struct amdgpu_pll spll; 396 struct amdgpu_pll mpll; 397 /* 10 Khz units */ 398 uint32_t default_mclk; 399 uint32_t default_sclk; 400 uint32_t default_dispclk; 401 uint32_t current_dispclk; 402 uint32_t dp_extclk; 403 uint32_t max_pixel_clock; 404 }; 405 406 /* sub-allocation manager, it has to be protected by another lock. 407 * By conception this is an helper for other part of the driver 408 * like the indirect buffer or semaphore, which both have their 409 * locking. 410 * 411 * Principe is simple, we keep a list of sub allocation in offset 412 * order (first entry has offset == 0, last entry has the highest 413 * offset). 414 * 415 * When allocating new object we first check if there is room at 416 * the end total_size - (last_object_offset + last_object_size) >= 417 * alloc_size. If so we allocate new object there. 418 * 419 * When there is not enough room at the end, we start waiting for 420 * each sub object until we reach object_offset+object_size >= 421 * alloc_size, this object then become the sub object we return. 422 * 423 * Alignment can't be bigger than page size. 424 * 425 * Hole are not considered for allocation to keep things simple. 426 * Assumption is that there won't be hole (all object on same 427 * alignment). 428 */ 429 430 #define AMDGPU_SA_NUM_FENCE_LISTS 32 431 432 struct amdgpu_sa_manager { 433 wait_queue_head_t wq; 434 struct amdgpu_bo *bo; 435 struct list_head *hole; 436 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 437 struct list_head olist; 438 unsigned size; 439 uint64_t gpu_addr; 440 void *cpu_ptr; 441 uint32_t domain; 442 uint32_t align; 443 }; 444 445 /* sub-allocation buffer */ 446 struct amdgpu_sa_bo { 447 struct list_head olist; 448 struct list_head flist; 449 struct amdgpu_sa_manager *manager; 450 unsigned soffset; 451 unsigned eoffset; 452 struct dma_fence *fence; 453 }; 454 455 int amdgpu_fence_slab_init(void); 456 void amdgpu_fence_slab_fini(void); 457 458 /* 459 * IRQS. 460 */ 461 462 struct amdgpu_flip_work { 463 struct delayed_work flip_work; 464 struct work_struct unpin_work; 465 struct amdgpu_device *adev; 466 int crtc_id; 467 u32 target_vblank; 468 uint64_t base; 469 struct drm_pending_vblank_event *event; 470 struct amdgpu_bo *old_abo; 471 unsigned shared_count; 472 struct dma_fence **shared; 473 struct dma_fence_cb cb; 474 bool async; 475 }; 476 477 478 /* 479 * file private structure 480 */ 481 482 struct amdgpu_fpriv { 483 struct amdgpu_vm vm; 484 struct amdgpu_bo_va *prt_va; 485 struct amdgpu_bo_va *csa_va; 486 struct rwlock bo_list_lock; 487 struct idr bo_list_handles; 488 struct amdgpu_ctx_mgr ctx_mgr; 489 }; 490 491 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 492 493 /* 494 * Writeback 495 */ 496 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 497 498 struct amdgpu_wb { 499 struct amdgpu_bo *wb_obj; 500 volatile uint32_t *wb; 501 uint64_t gpu_addr; 502 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 503 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 504 }; 505 506 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 507 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 508 509 /* 510 * Benchmarking 511 */ 512 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 513 514 /* 515 * ASIC specific register table accessible by UMD 516 */ 517 struct amdgpu_allowed_register_entry { 518 uint32_t reg_offset; 519 bool grbm_indexed; 520 }; 521 522 enum amd_reset_method { 523 AMD_RESET_METHOD_NONE = -1, 524 AMD_RESET_METHOD_LEGACY = 0, 525 AMD_RESET_METHOD_MODE0, 526 AMD_RESET_METHOD_MODE1, 527 AMD_RESET_METHOD_MODE2, 528 AMD_RESET_METHOD_BACO, 529 AMD_RESET_METHOD_PCI, 530 }; 531 532 struct amdgpu_video_codec_info { 533 u32 codec_type; 534 u32 max_width; 535 u32 max_height; 536 u32 max_pixels_per_frame; 537 u32 max_level; 538 }; 539 540 #define codec_info_build(type, width, height, level) \ 541 .codec_type = type,\ 542 .max_width = width,\ 543 .max_height = height,\ 544 .max_pixels_per_frame = height * width,\ 545 .max_level = level, 546 547 struct amdgpu_video_codecs { 548 const u32 codec_count; 549 const struct amdgpu_video_codec_info *codec_array; 550 }; 551 552 /* 553 * ASIC specific functions. 554 */ 555 struct amdgpu_asic_funcs { 556 bool (*read_disabled_bios)(struct amdgpu_device *adev); 557 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 558 u8 *bios, u32 length_bytes); 559 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 560 u32 sh_num, u32 reg_offset, u32 *value); 561 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 562 int (*reset)(struct amdgpu_device *adev); 563 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 564 /* get the reference clock */ 565 u32 (*get_xclk)(struct amdgpu_device *adev); 566 /* MM block clocks */ 567 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 568 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 569 /* static power management */ 570 int (*get_pcie_lanes)(struct amdgpu_device *adev); 571 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 572 /* get config memsize register */ 573 u32 (*get_config_memsize)(struct amdgpu_device *adev); 574 /* flush hdp write queue */ 575 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 576 /* invalidate hdp read cache */ 577 void (*invalidate_hdp)(struct amdgpu_device *adev, 578 struct amdgpu_ring *ring); 579 /* check if the asic needs a full reset of if soft reset will work */ 580 bool (*need_full_reset)(struct amdgpu_device *adev); 581 /* initialize doorbell layout for specific asic*/ 582 void (*init_doorbell_index)(struct amdgpu_device *adev); 583 /* PCIe bandwidth usage */ 584 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 585 uint64_t *count1); 586 /* do we need to reset the asic at init time (e.g., kexec) */ 587 bool (*need_reset_on_init)(struct amdgpu_device *adev); 588 /* PCIe replay counter */ 589 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 590 /* device supports BACO */ 591 bool (*supports_baco)(struct amdgpu_device *adev); 592 /* pre asic_init quirks */ 593 void (*pre_asic_init)(struct amdgpu_device *adev); 594 /* enter/exit umd stable pstate */ 595 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 596 /* query video codecs */ 597 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 598 const struct amdgpu_video_codecs **codecs); 599 }; 600 601 /* 602 * IOCTL. 603 */ 604 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 605 struct drm_file *filp); 606 607 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 608 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 609 struct drm_file *filp); 610 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 611 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 612 struct drm_file *filp); 613 614 /* VRAM scratch page for HDP bug, default vram page */ 615 struct amdgpu_vram_scratch { 616 struct amdgpu_bo *robj; 617 volatile uint32_t *ptr; 618 u64 gpu_addr; 619 }; 620 621 /* 622 * CGS 623 */ 624 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 625 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 626 627 /* 628 * Core structure, functions and helpers. 629 */ 630 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 631 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 632 633 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 634 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 635 636 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 637 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 638 639 struct amdgpu_mmio_remap { 640 u32 reg_offset; 641 resource_size_t bus_addr; 642 }; 643 644 /* Define the HW IP blocks will be used in driver , add more if necessary */ 645 enum amd_hw_ip_block_type { 646 GC_HWIP = 1, 647 HDP_HWIP, 648 SDMA0_HWIP, 649 SDMA1_HWIP, 650 SDMA2_HWIP, 651 SDMA3_HWIP, 652 SDMA4_HWIP, 653 SDMA5_HWIP, 654 SDMA6_HWIP, 655 SDMA7_HWIP, 656 LSDMA_HWIP, 657 MMHUB_HWIP, 658 ATHUB_HWIP, 659 NBIO_HWIP, 660 MP0_HWIP, 661 MP1_HWIP, 662 UVD_HWIP, 663 VCN_HWIP = UVD_HWIP, 664 JPEG_HWIP = VCN_HWIP, 665 VCN1_HWIP, 666 VCE_HWIP, 667 DF_HWIP, 668 DCE_HWIP, 669 OSSSYS_HWIP, 670 SMUIO_HWIP, 671 PWR_HWIP, 672 NBIF_HWIP, 673 THM_HWIP, 674 CLK_HWIP, 675 UMC_HWIP, 676 RSMU_HWIP, 677 XGMI_HWIP, 678 DCI_HWIP, 679 PCIE_HWIP, 680 MAX_HWIP 681 }; 682 683 #define HWIP_MAX_INSTANCE 11 684 685 #define HW_ID_MAX 300 686 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 687 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 688 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 689 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 690 691 struct amd_powerplay { 692 void *pp_handle; 693 const struct amd_pm_funcs *pp_funcs; 694 }; 695 696 struct ip_discovery_top; 697 698 /* polaris10 kickers */ 699 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 700 ((rid == 0xE3) || \ 701 (rid == 0xE4) || \ 702 (rid == 0xE5) || \ 703 (rid == 0xE7) || \ 704 (rid == 0xEF))) || \ 705 ((did == 0x6FDF) && \ 706 ((rid == 0xE7) || \ 707 (rid == 0xEF) || \ 708 (rid == 0xFF)))) 709 710 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 711 ((rid == 0xE1) || \ 712 (rid == 0xF7))) 713 714 /* polaris11 kickers */ 715 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 716 ((rid == 0xE0) || \ 717 (rid == 0xE5))) || \ 718 ((did == 0x67FF) && \ 719 ((rid == 0xCF) || \ 720 (rid == 0xEF) || \ 721 (rid == 0xFF)))) 722 723 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 724 ((rid == 0xE2))) 725 726 /* polaris12 kickers */ 727 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 728 ((rid == 0xC0) || \ 729 (rid == 0xC1) || \ 730 (rid == 0xC3) || \ 731 (rid == 0xC7))) || \ 732 ((did == 0x6981) && \ 733 ((rid == 0x00) || \ 734 (rid == 0x01) || \ 735 (rid == 0x10)))) 736 737 struct amdgpu_mqd_prop { 738 uint64_t mqd_gpu_addr; 739 uint64_t hqd_base_gpu_addr; 740 uint64_t rptr_gpu_addr; 741 uint64_t wptr_gpu_addr; 742 uint32_t queue_size; 743 bool use_doorbell; 744 uint32_t doorbell_index; 745 uint64_t eop_gpu_addr; 746 uint32_t hqd_pipe_priority; 747 uint32_t hqd_queue_priority; 748 bool hqd_active; 749 }; 750 751 struct amdgpu_mqd { 752 unsigned mqd_size; 753 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 754 struct amdgpu_mqd_prop *p); 755 }; 756 757 #define AMDGPU_RESET_MAGIC_NUM 64 758 #define AMDGPU_MAX_DF_PERFMONS 4 759 #define AMDGPU_PRODUCT_NAME_LEN 64 760 struct amdgpu_reset_domain; 761 762 struct amdgpu_device { 763 struct device self; 764 struct device *dev; 765 struct pci_dev *pdev; 766 struct drm_device ddev; 767 768 pci_chipset_tag_t pc; 769 pcitag_t pa_tag; 770 pci_intr_handle_t intrh; 771 bus_space_tag_t iot; 772 bus_space_tag_t memt; 773 bus_dma_tag_t dmat; 774 void *irqh; 775 776 void (*switchcb)(void *, int, int); 777 void *switchcbarg; 778 void *switchcookie; 779 struct task switchtask; 780 struct rasops_info ro; 781 int console; 782 int primary; 783 784 struct task burner_task; 785 int burner_fblank; 786 787 unsigned long fb_aper_offset; 788 unsigned long fb_aper_size; 789 790 #ifdef CONFIG_DRM_AMD_ACP 791 struct amdgpu_acp acp; 792 #endif 793 struct amdgpu_hive_info *hive; 794 /* ASIC */ 795 enum amd_asic_type asic_type; 796 uint32_t family; 797 uint32_t rev_id; 798 uint32_t external_rev_id; 799 unsigned long flags; 800 unsigned long apu_flags; 801 int usec_timeout; 802 const struct amdgpu_asic_funcs *asic_funcs; 803 bool shutdown; 804 bool need_swiotlb; 805 bool accel_working; 806 struct notifier_block acpi_nb; 807 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 808 #ifdef notyet 809 struct debugfs_blob_wrapper debugfs_vbios_blob; 810 struct debugfs_blob_wrapper debugfs_discovery_blob; 811 #endif 812 struct rwlock srbm_mutex; 813 /* GRBM index mutex. Protects concurrent access to GRBM index */ 814 struct rwlock grbm_idx_mutex; 815 struct dev_pm_domain vga_pm_domain; 816 bool have_disp_power_ref; 817 bool have_atomics_support; 818 819 /* BIOS */ 820 bool is_atom_fw; 821 uint8_t *bios; 822 uint32_t bios_size; 823 uint32_t bios_scratch_reg_offset; 824 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 825 826 /* Register/doorbell mmio */ 827 resource_size_t rmmio_base; 828 resource_size_t rmmio_size; 829 void __iomem *rmmio; 830 bus_space_tag_t rmmio_bst; 831 bus_space_handle_t rmmio_bsh; 832 /* protects concurrent MM_INDEX/DATA based register access */ 833 spinlock_t mmio_idx_lock; 834 struct amdgpu_mmio_remap rmmio_remap; 835 /* protects concurrent SMC based register access */ 836 spinlock_t smc_idx_lock; 837 amdgpu_rreg_t smc_rreg; 838 amdgpu_wreg_t smc_wreg; 839 /* protects concurrent PCIE register access */ 840 spinlock_t pcie_idx_lock; 841 amdgpu_rreg_t pcie_rreg; 842 amdgpu_wreg_t pcie_wreg; 843 amdgpu_rreg_t pciep_rreg; 844 amdgpu_wreg_t pciep_wreg; 845 amdgpu_rreg64_t pcie_rreg64; 846 amdgpu_wreg64_t pcie_wreg64; 847 /* protects concurrent UVD register access */ 848 spinlock_t uvd_ctx_idx_lock; 849 amdgpu_rreg_t uvd_ctx_rreg; 850 amdgpu_wreg_t uvd_ctx_wreg; 851 /* protects concurrent DIDT register access */ 852 spinlock_t didt_idx_lock; 853 amdgpu_rreg_t didt_rreg; 854 amdgpu_wreg_t didt_wreg; 855 /* protects concurrent gc_cac register access */ 856 spinlock_t gc_cac_idx_lock; 857 amdgpu_rreg_t gc_cac_rreg; 858 amdgpu_wreg_t gc_cac_wreg; 859 /* protects concurrent se_cac register access */ 860 spinlock_t se_cac_idx_lock; 861 amdgpu_rreg_t se_cac_rreg; 862 amdgpu_wreg_t se_cac_wreg; 863 /* protects concurrent ENDPOINT (audio) register access */ 864 spinlock_t audio_endpt_idx_lock; 865 amdgpu_block_rreg_t audio_endpt_rreg; 866 amdgpu_block_wreg_t audio_endpt_wreg; 867 struct amdgpu_doorbell doorbell; 868 869 /* clock/pll info */ 870 struct amdgpu_clock clock; 871 872 /* MC */ 873 struct amdgpu_gmc gmc; 874 struct amdgpu_gart gart; 875 dma_addr_t dummy_page_addr; 876 struct amdgpu_vm_manager vm_manager; 877 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 878 unsigned num_vmhubs; 879 880 /* memory management */ 881 struct amdgpu_mman mman; 882 struct amdgpu_vram_scratch vram_scratch; 883 struct amdgpu_wb wb; 884 atomic64_t num_bytes_moved; 885 atomic64_t num_evictions; 886 atomic64_t num_vram_cpu_page_faults; 887 atomic_t gpu_reset_counter; 888 atomic_t vram_lost_counter; 889 890 /* data for buffer migration throttling */ 891 struct { 892 spinlock_t lock; 893 s64 last_update_us; 894 s64 accum_us; /* accumulated microseconds */ 895 s64 accum_us_vis; /* for visible VRAM */ 896 u32 log2_max_MBps; 897 } mm_stats; 898 899 /* display */ 900 bool enable_virtual_display; 901 struct amdgpu_vkms_output *amdgpu_vkms_output; 902 struct amdgpu_mode_info mode_info; 903 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 904 struct work_struct hotplug_work; 905 struct amdgpu_irq_src crtc_irq; 906 struct amdgpu_irq_src vline0_irq; 907 struct amdgpu_irq_src vupdate_irq; 908 struct amdgpu_irq_src pageflip_irq; 909 struct amdgpu_irq_src hpd_irq; 910 struct amdgpu_irq_src dmub_trace_irq; 911 struct amdgpu_irq_src dmub_outbox_irq; 912 913 /* rings */ 914 u64 fence_context; 915 unsigned num_rings; 916 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 917 struct dma_fence __rcu *gang_submit; 918 bool ib_pool_ready; 919 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 920 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 921 922 /* interrupts */ 923 struct amdgpu_irq irq; 924 925 /* powerplay */ 926 struct amd_powerplay powerplay; 927 struct amdgpu_pm pm; 928 u64 cg_flags; 929 u32 pg_flags; 930 931 /* nbio */ 932 struct amdgpu_nbio nbio; 933 934 /* hdp */ 935 struct amdgpu_hdp hdp; 936 937 /* smuio */ 938 struct amdgpu_smuio smuio; 939 940 /* mmhub */ 941 struct amdgpu_mmhub mmhub; 942 943 /* gfxhub */ 944 struct amdgpu_gfxhub gfxhub; 945 946 /* gfx */ 947 struct amdgpu_gfx gfx; 948 949 /* sdma */ 950 struct amdgpu_sdma sdma; 951 952 /* lsdma */ 953 struct amdgpu_lsdma lsdma; 954 955 /* uvd */ 956 struct amdgpu_uvd uvd; 957 958 /* vce */ 959 struct amdgpu_vce vce; 960 961 /* vcn */ 962 struct amdgpu_vcn vcn; 963 964 /* jpeg */ 965 struct amdgpu_jpeg jpeg; 966 967 /* firmwares */ 968 struct amdgpu_firmware firmware; 969 970 /* PSP */ 971 struct psp_context psp; 972 973 /* GDS */ 974 struct amdgpu_gds gds; 975 976 /* KFD */ 977 struct amdgpu_kfd_dev kfd; 978 979 /* UMC */ 980 struct amdgpu_umc umc; 981 982 /* display related functionality */ 983 struct amdgpu_display_manager dm; 984 985 /* mes */ 986 bool enable_mes; 987 bool enable_mes_kiq; 988 struct amdgpu_mes mes; 989 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 990 991 /* df */ 992 struct amdgpu_df df; 993 994 /* MCA */ 995 struct amdgpu_mca mca; 996 997 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 998 uint32_t harvest_ip_mask; 999 int num_ip_blocks; 1000 struct rwlock mn_lock; 1001 DECLARE_HASHTABLE(mn_hash, 7); 1002 1003 /* tracking pinned memory */ 1004 atomic64_t vram_pin_size; 1005 atomic64_t visible_pin_size; 1006 atomic64_t gart_pin_size; 1007 1008 /* soc15 register offset based on ip, instance and segment */ 1009 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1010 1011 /* delayed work_func for deferring clockgating during resume */ 1012 struct delayed_work delayed_init_work; 1013 1014 struct amdgpu_virt virt; 1015 1016 /* link all shadow bo */ 1017 struct list_head shadow_list; 1018 struct rwlock shadow_list_lock; 1019 1020 /* record hw reset is performed */ 1021 bool has_hw_reset; 1022 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1023 1024 /* s3/s4 mask */ 1025 bool in_suspend; 1026 bool in_s3; 1027 bool in_s4; 1028 bool in_s0ix; 1029 1030 enum pp_mp1_state mp1_state; 1031 struct amdgpu_doorbell_index doorbell_index; 1032 1033 struct rwlock notifier_lock; 1034 1035 int asic_reset_res; 1036 struct work_struct xgmi_reset_work; 1037 struct list_head reset_list; 1038 1039 long gfx_timeout; 1040 long sdma_timeout; 1041 long video_timeout; 1042 long compute_timeout; 1043 1044 uint64_t unique_id; 1045 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1046 1047 /* enable runtime pm on the device */ 1048 bool in_runpm; 1049 bool has_pr3; 1050 1051 bool pm_sysfs_en; 1052 bool ucode_sysfs_en; 1053 bool psp_sysfs_en; 1054 1055 /* Chip product information */ 1056 char product_number[20]; 1057 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1058 char serial[20]; 1059 1060 atomic_t throttling_logging_enabled; 1061 struct ratelimit_state throttling_logging_rs; 1062 uint32_t ras_hw_enabled; 1063 uint32_t ras_enabled; 1064 1065 bool no_hw_access; 1066 struct pci_saved_state *pci_state; 1067 pci_channel_state_t pci_channel_state; 1068 1069 struct amdgpu_reset_control *reset_cntl; 1070 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1071 1072 bool ram_is_direct_mapped; 1073 1074 struct list_head ras_list; 1075 1076 struct ip_discovery_top *ip_top; 1077 1078 struct amdgpu_reset_domain *reset_domain; 1079 1080 struct rwlock benchmark_mutex; 1081 1082 /* reset dump register */ 1083 uint32_t *reset_dump_reg_list; 1084 uint32_t *reset_dump_reg_value; 1085 int num_regs; 1086 #ifdef CONFIG_DEV_COREDUMP 1087 struct amdgpu_task_info reset_task_info; 1088 bool reset_vram_lost; 1089 struct timespec64 reset_time; 1090 #endif 1091 1092 bool scpm_enabled; 1093 uint32_t scpm_status; 1094 1095 struct work_struct reset_work; 1096 1097 bool job_hang; 1098 }; 1099 1100 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1101 { 1102 return container_of(ddev, struct amdgpu_device, ddev); 1103 } 1104 1105 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1106 { 1107 return &adev->ddev; 1108 } 1109 1110 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1111 { 1112 return container_of(bdev, struct amdgpu_device, mman.bdev); 1113 } 1114 1115 int amdgpu_device_init(struct amdgpu_device *adev, 1116 uint32_t flags); 1117 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1118 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1119 1120 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1121 1122 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1123 void *buf, size_t size, bool write); 1124 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1125 void *buf, size_t size, bool write); 1126 1127 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1128 void *buf, size_t size, bool write); 1129 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1130 uint32_t reg, uint32_t acc_flags); 1131 void amdgpu_device_wreg(struct amdgpu_device *adev, 1132 uint32_t reg, uint32_t v, 1133 uint32_t acc_flags); 1134 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1135 uint32_t reg, uint32_t v); 1136 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1137 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1138 1139 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1140 u32 pcie_index, u32 pcie_data, 1141 u32 reg_addr); 1142 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1143 u32 pcie_index, u32 pcie_data, 1144 u32 reg_addr); 1145 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1146 u32 pcie_index, u32 pcie_data, 1147 u32 reg_addr, u32 reg_data); 1148 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1149 u32 pcie_index, u32 pcie_data, 1150 u32 reg_addr, u64 reg_data); 1151 1152 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1153 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1154 1155 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1156 struct amdgpu_reset_context *reset_context); 1157 1158 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1159 struct amdgpu_reset_context *reset_context); 1160 1161 int emu_soc_asic_init(struct amdgpu_device *adev); 1162 1163 /* 1164 * Registers read & write functions. 1165 */ 1166 #define AMDGPU_REGS_NO_KIQ (1<<1) 1167 #define AMDGPU_REGS_RLC (1<<2) 1168 1169 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1170 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1171 1172 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1173 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1174 1175 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1176 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1177 1178 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1179 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1180 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1181 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1182 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1183 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1184 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1185 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1186 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1187 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1188 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1189 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1190 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1191 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1192 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1193 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1194 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1195 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1196 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1197 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1198 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1199 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1200 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1201 #define WREG32_P(reg, val, mask) \ 1202 do { \ 1203 uint32_t tmp_ = RREG32(reg); \ 1204 tmp_ &= (mask); \ 1205 tmp_ |= ((val) & ~(mask)); \ 1206 WREG32(reg, tmp_); \ 1207 } while (0) 1208 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1209 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1210 #define WREG32_PLL_P(reg, val, mask) \ 1211 do { \ 1212 uint32_t tmp_ = RREG32_PLL(reg); \ 1213 tmp_ &= (mask); \ 1214 tmp_ |= ((val) & ~(mask)); \ 1215 WREG32_PLL(reg, tmp_); \ 1216 } while (0) 1217 1218 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1219 do { \ 1220 u32 tmp = RREG32_SMC(_Reg); \ 1221 tmp &= (_Mask); \ 1222 tmp |= ((_Val) & ~(_Mask)); \ 1223 WREG32_SMC(_Reg, tmp); \ 1224 } while (0) 1225 1226 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1227 1228 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1229 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1230 1231 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1232 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1233 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1234 1235 #define REG_GET_FIELD(value, reg, field) \ 1236 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1237 1238 #define WREG32_FIELD(reg, field, val) \ 1239 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1240 1241 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1242 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1243 1244 /* 1245 * BIOS helpers. 1246 */ 1247 #define RBIOS8(i) (adev->bios[i]) 1248 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1249 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1250 1251 /* 1252 * ASICs macro. 1253 */ 1254 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1255 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1256 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1257 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1258 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1259 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1260 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1261 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1262 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1263 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1264 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1265 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1266 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1267 #define amdgpu_asic_flush_hdp(adev, r) \ 1268 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1269 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1270 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1271 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0)) 1272 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1273 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1274 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1275 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1276 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1277 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1278 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1279 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1280 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1281 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1282 1283 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1284 1285 /* Common functions */ 1286 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1287 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1288 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1289 struct amdgpu_job *job, 1290 struct amdgpu_reset_context *reset_context); 1291 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1292 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1293 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1294 bool amdgpu_device_pcie_dynamic_switching_supported(void); 1295 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1296 bool amdgpu_device_aspm_support_quirk(void); 1297 1298 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1299 u64 num_vis_bytes); 1300 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1301 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1302 const u32 *registers, 1303 const u32 array_size); 1304 1305 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1306 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1307 bool amdgpu_device_supports_px(struct drm_device *dev); 1308 bool amdgpu_device_supports_boco(struct drm_device *dev); 1309 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1310 bool amdgpu_device_supports_baco(struct drm_device *dev); 1311 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1312 struct amdgpu_device *peer_adev); 1313 int amdgpu_device_baco_enter(struct drm_device *dev); 1314 int amdgpu_device_baco_exit(struct drm_device *dev); 1315 1316 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1317 struct amdgpu_ring *ring); 1318 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1319 struct amdgpu_ring *ring); 1320 1321 void amdgpu_device_halt(struct amdgpu_device *adev); 1322 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1323 u32 reg); 1324 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1325 u32 reg, u32 v); 1326 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1327 struct dma_fence *gang); 1328 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1329 1330 /* atpx handler */ 1331 #if defined(CONFIG_VGA_SWITCHEROO) 1332 void amdgpu_register_atpx_handler(void); 1333 void amdgpu_unregister_atpx_handler(void); 1334 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1335 bool amdgpu_is_atpx_hybrid(void); 1336 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1337 bool amdgpu_has_atpx(void); 1338 #else 1339 static inline void amdgpu_register_atpx_handler(void) {} 1340 static inline void amdgpu_unregister_atpx_handler(void) {} 1341 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1342 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1343 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1344 static inline bool amdgpu_has_atpx(void) { return false; } 1345 #endif 1346 1347 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1348 void *amdgpu_atpx_get_dhandle(void); 1349 #else 1350 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1351 #endif 1352 1353 /* 1354 * KMS 1355 */ 1356 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1357 extern const int amdgpu_max_kms_ioctl; 1358 1359 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1360 void amdgpu_driver_unload_kms(struct drm_device *dev); 1361 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1362 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1363 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1364 struct drm_file *file_priv); 1365 void amdgpu_driver_release_kms(struct drm_device *dev); 1366 1367 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1368 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1369 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1370 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1371 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1372 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1373 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1374 struct drm_file *filp); 1375 1376 /* 1377 * functions used by amdgpu_encoder.c 1378 */ 1379 struct amdgpu_afmt_acr { 1380 u32 clock; 1381 1382 int n_32khz; 1383 int cts_32khz; 1384 1385 int n_44_1khz; 1386 int cts_44_1khz; 1387 1388 int n_48khz; 1389 int cts_48khz; 1390 1391 }; 1392 1393 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1394 1395 /* amdgpu_acpi.c */ 1396 1397 /* ATCS Device/Driver State */ 1398 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1399 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1400 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1401 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1402 1403 #if defined(CONFIG_ACPI) 1404 int amdgpu_acpi_init(struct amdgpu_device *adev); 1405 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1406 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1407 bool amdgpu_acpi_is_power_shift_control_supported(void); 1408 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1409 u8 perf_req, bool advertise); 1410 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1411 u8 dev_state, bool drv_state); 1412 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1413 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1414 1415 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1416 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1417 void amdgpu_acpi_detect(void); 1418 #else 1419 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1420 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1421 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1422 static inline void amdgpu_acpi_detect(void) { } 1423 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1424 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1425 u8 dev_state, bool drv_state) { return 0; } 1426 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1427 enum amdgpu_ss ss_state) { return 0; } 1428 #endif 1429 1430 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1431 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1432 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1433 #else 1434 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1435 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1436 #endif 1437 1438 #if defined(CONFIG_DRM_AMD_DC) 1439 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1440 #else 1441 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1442 #endif 1443 1444 1445 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1446 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1447 1448 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1449 pci_channel_state_t state); 1450 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1451 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1452 void amdgpu_pci_resume(struct pci_dev *pdev); 1453 1454 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1455 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1456 1457 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1458 1459 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1460 enum amd_clockgating_state state); 1461 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1462 enum amd_powergating_state state); 1463 1464 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1465 { 1466 return amdgpu_gpu_recovery != 0 && 1467 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1468 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1469 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1470 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1471 } 1472 1473 #include "amdgpu_object.h" 1474 1475 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1476 { 1477 return adev->gmc.tmz_enabled; 1478 } 1479 1480 int amdgpu_in_reset(struct amdgpu_device *adev); 1481 1482 #endif 1483