1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/rbtree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <drm/ttm/ttm_bo_api.h> 40 #include <drm/ttm/ttm_bo_driver.h> 41 #include <drm/ttm/ttm_placement.h> 42 #include <drm/ttm/ttm_module.h> 43 #include <drm/ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 #include <drm/gpu_scheduler.h> 49 50 #include <dev/wscons/wsconsio.h> 51 #include <dev/wscons/wsdisplayvar.h> 52 #include <dev/rasops/rasops.h> 53 54 #include <kgd_kfd_interface.h> 55 #include "dm_pp_interface.h" 56 #include "kgd_pp_interface.h" 57 58 #include "amd_shared.h" 59 #include "amdgpu_mode.h" 60 #include "amdgpu_ih.h" 61 #include "amdgpu_irq.h" 62 #include "amdgpu_ucode.h" 63 #include "amdgpu_ttm.h" 64 #include "amdgpu_psp.h" 65 #include "amdgpu_gds.h" 66 #include "amdgpu_sync.h" 67 #include "amdgpu_ring.h" 68 #include "amdgpu_vm.h" 69 #include "amdgpu_dpm.h" 70 #include "amdgpu_acp.h" 71 #include "amdgpu_uvd.h" 72 #include "amdgpu_vce.h" 73 #include "amdgpu_vcn.h" 74 #include "amdgpu_mn.h" 75 #include "amdgpu_gmc.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_gart.h" 79 #include "amdgpu_debugfs.h" 80 #include "amdgpu_job.h" 81 #include "amdgpu_bo_list.h" 82 83 /* 84 * Modules parameters. 85 */ 86 extern int amdgpu_modeset; 87 extern int amdgpu_vram_limit; 88 extern int amdgpu_vis_vram_limit; 89 extern int amdgpu_gart_size; 90 extern int amdgpu_gtt_size; 91 extern int amdgpu_moverate; 92 extern int amdgpu_benchmarking; 93 extern int amdgpu_testing; 94 extern int amdgpu_audio; 95 extern int amdgpu_disp_priority; 96 extern int amdgpu_hw_i2c; 97 extern int amdgpu_pcie_gen2; 98 extern int amdgpu_msi; 99 extern int amdgpu_lockup_timeout; 100 extern int amdgpu_dpm; 101 extern int amdgpu_fw_load_type; 102 extern int amdgpu_aspm; 103 extern int amdgpu_runtime_pm; 104 extern uint amdgpu_ip_block_mask; 105 extern int amdgpu_bapm; 106 extern int amdgpu_deep_color; 107 extern int amdgpu_vm_size; 108 extern int amdgpu_vm_block_size; 109 extern int amdgpu_vm_fragment_size; 110 extern int amdgpu_vm_fault_stop; 111 extern int amdgpu_vm_debug; 112 extern int amdgpu_vm_update_mode; 113 extern int amdgpu_dc; 114 extern int amdgpu_sched_jobs; 115 extern int amdgpu_sched_hw_submission; 116 extern uint amdgpu_pcie_gen_cap; 117 extern uint amdgpu_pcie_lane_cap; 118 extern uint amdgpu_cg_mask; 119 extern uint amdgpu_pg_mask; 120 extern uint amdgpu_sdma_phase_quantum; 121 extern char *amdgpu_disable_cu; 122 extern char *amdgpu_virtual_display; 123 extern uint amdgpu_pp_feature_mask; 124 extern int amdgpu_vram_page_split; 125 extern int amdgpu_ngg; 126 extern int amdgpu_prim_buf_per_se; 127 extern int amdgpu_pos_buf_per_se; 128 extern int amdgpu_cntl_sb_buf_per_se; 129 extern int amdgpu_param_buf_per_se; 130 extern int amdgpu_job_hang_limit; 131 extern int amdgpu_lbpw; 132 extern int amdgpu_compute_multipipe; 133 extern int amdgpu_gpu_recovery; 134 extern int amdgpu_emu_mode; 135 extern uint amdgpu_smu_memory_pool_size; 136 137 #ifdef CONFIG_DRM_AMDGPU_SI 138 extern int amdgpu_si_support; 139 #endif 140 #ifdef CONFIG_DRM_AMDGPU_CIK 141 extern int amdgpu_cik_support; 142 #endif 143 144 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 145 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 146 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 147 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 148 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 149 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 150 #define AMDGPU_IB_POOL_SIZE 16 151 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 152 #define AMDGPUFB_CONN_LIMIT 4 153 #define AMDGPU_BIOS_NUM_SCRATCH 16 154 155 /* max number of IP instances */ 156 #define AMDGPU_MAX_SDMA_INSTANCES 2 157 158 /* hard reset data */ 159 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 160 161 /* reset flags */ 162 #define AMDGPU_RESET_GFX (1 << 0) 163 #define AMDGPU_RESET_COMPUTE (1 << 1) 164 #define AMDGPU_RESET_DMA (1 << 2) 165 #define AMDGPU_RESET_CP (1 << 3) 166 #define AMDGPU_RESET_GRBM (1 << 4) 167 #define AMDGPU_RESET_DMA1 (1 << 5) 168 #define AMDGPU_RESET_RLC (1 << 6) 169 #define AMDGPU_RESET_SEM (1 << 7) 170 #define AMDGPU_RESET_IH (1 << 8) 171 #define AMDGPU_RESET_VMC (1 << 9) 172 #define AMDGPU_RESET_MC (1 << 10) 173 #define AMDGPU_RESET_DISPLAY (1 << 11) 174 #define AMDGPU_RESET_UVD (1 << 12) 175 #define AMDGPU_RESET_VCE (1 << 13) 176 #define AMDGPU_RESET_VCE1 (1 << 14) 177 178 /* GFX current status */ 179 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 180 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 181 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 182 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 183 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 184 185 /* max cursor sizes (in pixels) */ 186 #define CIK_CURSOR_WIDTH 128 187 #define CIK_CURSOR_HEIGHT 128 188 189 struct amdgpu_device; 190 struct amdgpu_ib; 191 struct amdgpu_cs_parser; 192 struct amdgpu_job; 193 struct amdgpu_irq_src; 194 struct amdgpu_fpriv; 195 struct amdgpu_bo_va_mapping; 196 struct amdgpu_atif; 197 198 enum amdgpu_cp_irq { 199 AMDGPU_CP_IRQ_GFX_EOP = 0, 200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 203 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 206 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 207 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 208 209 AMDGPU_CP_IRQ_LAST 210 }; 211 212 enum amdgpu_sdma_irq { 213 AMDGPU_SDMA_IRQ_TRAP0 = 0, 214 AMDGPU_SDMA_IRQ_TRAP1, 215 216 AMDGPU_SDMA_IRQ_LAST 217 }; 218 219 enum amdgpu_thermal_irq { 220 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 221 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 222 223 AMDGPU_THERMAL_IRQ_LAST 224 }; 225 226 enum amdgpu_kiq_irq { 227 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 228 AMDGPU_CP_KIQ_IRQ_LAST 229 }; 230 231 int amdgpu_device_ip_set_clockgating_state(void *dev, 232 enum amd_ip_block_type block_type, 233 enum amd_clockgating_state state); 234 int amdgpu_device_ip_set_powergating_state(void *dev, 235 enum amd_ip_block_type block_type, 236 enum amd_powergating_state state); 237 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 238 u32 *flags); 239 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 240 enum amd_ip_block_type block_type); 241 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 242 enum amd_ip_block_type block_type); 243 244 #define AMDGPU_MAX_IP_NUM 16 245 246 struct amdgpu_ip_block_status { 247 bool valid; 248 bool sw; 249 bool hw; 250 bool late_initialized; 251 bool hang; 252 }; 253 254 struct amdgpu_ip_block_version { 255 const enum amd_ip_block_type type; 256 const u32 major; 257 const u32 minor; 258 const u32 rev; 259 const struct amd_ip_funcs *funcs; 260 }; 261 262 struct amdgpu_ip_block { 263 struct amdgpu_ip_block_status status; 264 const struct amdgpu_ip_block_version *version; 265 }; 266 267 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 268 enum amd_ip_block_type type, 269 u32 major, u32 minor); 270 271 struct amdgpu_ip_block * 272 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 273 enum amd_ip_block_type type); 274 275 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 276 const struct amdgpu_ip_block_version *ip_block_version); 277 278 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 279 struct amdgpu_buffer_funcs { 280 /* maximum bytes in a single operation */ 281 uint32_t copy_max_bytes; 282 283 /* number of dw to reserve per operation */ 284 unsigned copy_num_dw; 285 286 /* used for buffer migration */ 287 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 288 /* src addr in bytes */ 289 uint64_t src_offset, 290 /* dst addr in bytes */ 291 uint64_t dst_offset, 292 /* number of byte to transfer */ 293 uint32_t byte_count); 294 295 /* maximum bytes in a single operation */ 296 uint32_t fill_max_bytes; 297 298 /* number of dw to reserve per operation */ 299 unsigned fill_num_dw; 300 301 /* used for buffer clearing */ 302 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 303 /* value to write to memory */ 304 uint32_t src_data, 305 /* dst addr in bytes */ 306 uint64_t dst_offset, 307 /* number of byte to fill */ 308 uint32_t byte_count); 309 }; 310 311 /* provided by hw blocks that can write ptes, e.g., sdma */ 312 struct amdgpu_vm_pte_funcs { 313 /* number of dw to reserve per operation */ 314 unsigned copy_pte_num_dw; 315 316 /* copy pte entries from GART */ 317 void (*copy_pte)(struct amdgpu_ib *ib, 318 uint64_t pe, uint64_t src, 319 unsigned count); 320 321 /* write pte one entry at a time with addr mapping */ 322 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 323 uint64_t value, unsigned count, 324 uint32_t incr); 325 /* for linear pte/pde updates without addr mapping */ 326 void (*set_pte_pde)(struct amdgpu_ib *ib, 327 uint64_t pe, 328 uint64_t addr, unsigned count, 329 uint32_t incr, uint64_t flags); 330 }; 331 332 /* provided by the ih block */ 333 struct amdgpu_ih_funcs { 334 /* ring read/write ptr handling, called from interrupt context */ 335 u32 (*get_wptr)(struct amdgpu_device *adev); 336 bool (*prescreen_iv)(struct amdgpu_device *adev); 337 void (*decode_iv)(struct amdgpu_device *adev, 338 struct amdgpu_iv_entry *entry); 339 void (*set_rptr)(struct amdgpu_device *adev); 340 }; 341 342 /* 343 * BIOS. 344 */ 345 bool amdgpu_get_bios(struct amdgpu_device *adev); 346 bool amdgpu_read_bios(struct amdgpu_device *adev); 347 348 /* 349 * Clocks 350 */ 351 352 #define AMDGPU_MAX_PPLL 3 353 354 struct amdgpu_clock { 355 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 356 struct amdgpu_pll spll; 357 struct amdgpu_pll mpll; 358 /* 10 Khz units */ 359 uint32_t default_mclk; 360 uint32_t default_sclk; 361 uint32_t default_dispclk; 362 uint32_t current_dispclk; 363 uint32_t dp_extclk; 364 uint32_t max_pixel_clock; 365 }; 366 367 /* 368 * GEM. 369 */ 370 371 #define AMDGPU_GEM_DOMAIN_MAX 0x3 372 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 373 374 void amdgpu_gem_object_free(struct drm_gem_object *obj); 375 int amdgpu_gem_object_open(struct drm_gem_object *obj, 376 struct drm_file *file_priv); 377 void amdgpu_gem_object_close(struct drm_gem_object *obj, 378 struct drm_file *file_priv); 379 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 380 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 381 struct drm_gem_object * 382 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 383 struct dma_buf_attachment *attach, 384 struct sg_table *sg); 385 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 386 struct drm_gem_object *gobj, 387 int flags); 388 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, 389 struct dma_buf *dma_buf); 390 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 391 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 392 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 393 #ifdef notyet 394 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 395 #endif 396 397 /* sub-allocation manager, it has to be protected by another lock. 398 * By conception this is an helper for other part of the driver 399 * like the indirect buffer or semaphore, which both have their 400 * locking. 401 * 402 * Principe is simple, we keep a list of sub allocation in offset 403 * order (first entry has offset == 0, last entry has the highest 404 * offset). 405 * 406 * When allocating new object we first check if there is room at 407 * the end total_size - (last_object_offset + last_object_size) >= 408 * alloc_size. If so we allocate new object there. 409 * 410 * When there is not enough room at the end, we start waiting for 411 * each sub object until we reach object_offset+object_size >= 412 * alloc_size, this object then become the sub object we return. 413 * 414 * Alignment can't be bigger than page size. 415 * 416 * Hole are not considered for allocation to keep things simple. 417 * Assumption is that there won't be hole (all object on same 418 * alignment). 419 */ 420 421 #define AMDGPU_SA_NUM_FENCE_LISTS 32 422 423 struct amdgpu_sa_manager { 424 wait_queue_head_t wq; 425 struct amdgpu_bo *bo; 426 struct list_head *hole; 427 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 428 struct list_head olist; 429 unsigned size; 430 uint64_t gpu_addr; 431 void *cpu_ptr; 432 uint32_t domain; 433 uint32_t align; 434 }; 435 436 /* sub-allocation buffer */ 437 struct amdgpu_sa_bo { 438 struct list_head olist; 439 struct list_head flist; 440 struct amdgpu_sa_manager *manager; 441 unsigned soffset; 442 unsigned eoffset; 443 struct dma_fence *fence; 444 }; 445 446 /* 447 * GEM objects. 448 */ 449 void amdgpu_gem_force_release(struct amdgpu_device *adev); 450 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 451 int alignment, u32 initial_domain, 452 u64 flags, enum ttm_bo_type type, 453 struct reservation_object *resv, 454 struct drm_gem_object **obj); 455 456 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 457 struct drm_device *dev, 458 struct drm_mode_create_dumb *args); 459 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 460 struct drm_device *dev, 461 uint32_t handle, uint64_t *offset_p); 462 int amdgpu_fence_slab_init(void); 463 void amdgpu_fence_slab_fini(void); 464 465 /* 466 * GPU doorbell structures, functions & helpers 467 */ 468 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 469 { 470 AMDGPU_DOORBELL_KIQ = 0x000, 471 AMDGPU_DOORBELL_HIQ = 0x001, 472 AMDGPU_DOORBELL_DIQ = 0x002, 473 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 474 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 475 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 476 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 477 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 478 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 479 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 480 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 481 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 482 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 483 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 484 AMDGPU_DOORBELL_IH = 0x1E8, 485 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 486 AMDGPU_DOORBELL_INVALID = 0xFFFF 487 } AMDGPU_DOORBELL_ASSIGNMENT; 488 489 struct amdgpu_doorbell { 490 /* doorbell mmio */ 491 resource_size_t base; 492 resource_size_t size; 493 #ifdef __linux__ 494 u32 __iomem *ptr; 495 #endif 496 bus_space_tag_t bst; 497 bus_space_handle_t bsh; 498 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 499 }; 500 501 /* 502 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 503 */ 504 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 505 { 506 /* 507 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 508 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 509 * Compute related doorbells are allocated from 0x00 to 0x8a 510 */ 511 512 513 /* kernel scheduling */ 514 AMDGPU_DOORBELL64_KIQ = 0x00, 515 516 /* HSA interface queue and debug queue */ 517 AMDGPU_DOORBELL64_HIQ = 0x01, 518 AMDGPU_DOORBELL64_DIQ = 0x02, 519 520 /* Compute engines */ 521 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 522 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 523 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 524 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 525 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 526 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 527 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 528 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 529 530 /* User queue doorbell range (128 doorbells) */ 531 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 532 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 533 534 /* Graphics engine */ 535 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 536 537 /* 538 * Other graphics doorbells can be allocated here: from 0x8c to 0xef 539 * Graphics voltage island aperture 1 540 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 541 */ 542 543 /* sDMA engines */ 544 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 545 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 546 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 547 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 548 549 /* Interrupt handler */ 550 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 551 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 552 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 553 554 /* VCN engine use 32 bits doorbell */ 555 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 556 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 557 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 558 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 559 560 /* overlap the doorbell assignment with VCN as they are mutually exclusive 561 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 562 */ 563 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 564 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 565 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 566 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 567 568 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 569 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 570 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 571 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 572 573 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 574 AMDGPU_DOORBELL64_INVALID = 0xFFFF 575 } AMDGPU_DOORBELL64_ASSIGNMENT; 576 577 /* 578 * IRQS. 579 */ 580 581 struct amdgpu_flip_work { 582 struct delayed_work flip_work; 583 struct work_struct unpin_work; 584 struct amdgpu_device *adev; 585 int crtc_id; 586 u32 target_vblank; 587 uint64_t base; 588 struct drm_pending_vblank_event *event; 589 struct amdgpu_bo *old_abo; 590 struct dma_fence *excl; 591 unsigned shared_count; 592 struct dma_fence **shared; 593 struct dma_fence_cb cb; 594 bool async; 595 }; 596 597 598 /* 599 * CP & rings. 600 */ 601 602 struct amdgpu_ib { 603 struct amdgpu_sa_bo *sa_bo; 604 uint32_t length_dw; 605 uint64_t gpu_addr; 606 uint32_t *ptr; 607 uint32_t flags; 608 }; 609 610 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 611 612 /* 613 * Queue manager 614 */ 615 struct amdgpu_queue_mapper { 616 int hw_ip; 617 struct rwlock lock; 618 /* protected by lock */ 619 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; 620 }; 621 622 struct amdgpu_queue_mgr { 623 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; 624 }; 625 626 int amdgpu_queue_mgr_init(struct amdgpu_device *adev, 627 struct amdgpu_queue_mgr *mgr); 628 int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, 629 struct amdgpu_queue_mgr *mgr); 630 int amdgpu_queue_mgr_map(struct amdgpu_device *adev, 631 struct amdgpu_queue_mgr *mgr, 632 u32 hw_ip, u32 instance, u32 ring, 633 struct amdgpu_ring **out_ring); 634 635 /* 636 * context related structures 637 */ 638 639 struct amdgpu_ctx_ring { 640 uint64_t sequence; 641 struct dma_fence **fences; 642 struct drm_sched_entity entity; 643 }; 644 645 struct amdgpu_ctx { 646 struct kref refcount; 647 struct amdgpu_device *adev; 648 struct amdgpu_queue_mgr queue_mgr; 649 unsigned reset_counter; 650 unsigned reset_counter_query; 651 uint32_t vram_lost_counter; 652 spinlock_t ring_lock; 653 struct dma_fence **fences; 654 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 655 bool preamble_presented; 656 enum drm_sched_priority init_priority; 657 enum drm_sched_priority override_priority; 658 struct rwlock lock; 659 atomic_t guilty; 660 }; 661 662 struct amdgpu_ctx_mgr { 663 struct amdgpu_device *adev; 664 struct rwlock lock; 665 /* protected by lock */ 666 struct idr ctx_handles; 667 }; 668 669 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 670 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 671 672 int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 673 struct dma_fence *fence, uint64_t *seq); 674 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 675 struct amdgpu_ring *ring, uint64_t seq); 676 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 677 enum drm_sched_priority priority); 678 679 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 680 struct drm_file *filp); 681 682 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id); 683 684 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 685 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr); 686 void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr); 687 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 688 689 690 /* 691 * file private structure 692 */ 693 694 struct amdgpu_fpriv { 695 struct amdgpu_vm vm; 696 struct amdgpu_bo_va *prt_va; 697 struct amdgpu_bo_va *csa_va; 698 struct rwlock bo_list_lock; 699 struct idr bo_list_handles; 700 struct amdgpu_ctx_mgr ctx_mgr; 701 }; 702 703 /* 704 * GFX stuff 705 */ 706 #include "clearstate_defs.h" 707 708 struct amdgpu_rlc_funcs { 709 void (*enter_safe_mode)(struct amdgpu_device *adev); 710 void (*exit_safe_mode)(struct amdgpu_device *adev); 711 }; 712 713 struct amdgpu_rlc { 714 /* for power gating */ 715 struct amdgpu_bo *save_restore_obj; 716 uint64_t save_restore_gpu_addr; 717 volatile uint32_t *sr_ptr; 718 const u32 *reg_list; 719 u32 reg_list_size; 720 /* for clear state */ 721 struct amdgpu_bo *clear_state_obj; 722 uint64_t clear_state_gpu_addr; 723 volatile uint32_t *cs_ptr; 724 const struct cs_section_def *cs_data; 725 u32 clear_state_size; 726 /* for cp tables */ 727 struct amdgpu_bo *cp_table_obj; 728 uint64_t cp_table_gpu_addr; 729 volatile uint32_t *cp_table_ptr; 730 u32 cp_table_size; 731 732 /* safe mode for updating CG/PG state */ 733 bool in_safe_mode; 734 const struct amdgpu_rlc_funcs *funcs; 735 736 /* for firmware data */ 737 u32 save_and_restore_offset; 738 u32 clear_state_descriptor_offset; 739 u32 avail_scratch_ram_locations; 740 u32 reg_restore_list_size; 741 u32 reg_list_format_start; 742 u32 reg_list_format_separate_start; 743 u32 starting_offsets_start; 744 u32 reg_list_format_size_bytes; 745 u32 reg_list_size_bytes; 746 u32 reg_list_format_direct_reg_list_length; 747 u32 save_restore_list_cntl_size_bytes; 748 u32 save_restore_list_gpm_size_bytes; 749 u32 save_restore_list_srm_size_bytes; 750 751 u32 *register_list_format; 752 u32 *register_restore; 753 u8 *save_restore_list_cntl; 754 u8 *save_restore_list_gpm; 755 u8 *save_restore_list_srm; 756 757 bool is_rlc_v2_1; 758 }; 759 760 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 761 762 struct amdgpu_mec { 763 struct amdgpu_bo *hpd_eop_obj; 764 u64 hpd_eop_gpu_addr; 765 struct amdgpu_bo *mec_fw_obj; 766 u64 mec_fw_gpu_addr; 767 u32 num_mec; 768 u32 num_pipe_per_mec; 769 u32 num_queue_per_pipe; 770 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 771 772 /* These are the resources for which amdgpu takes ownership */ 773 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 774 }; 775 776 struct amdgpu_kiq { 777 u64 eop_gpu_addr; 778 struct amdgpu_bo *eop_obj; 779 spinlock_t ring_lock; 780 struct amdgpu_ring ring; 781 struct amdgpu_irq_src irq; 782 }; 783 784 /* 785 * GPU scratch registers structures, functions & helpers 786 */ 787 struct amdgpu_scratch { 788 unsigned num_reg; 789 uint32_t reg_base; 790 uint32_t free_mask; 791 }; 792 793 /* 794 * GFX configurations 795 */ 796 #define AMDGPU_GFX_MAX_SE 4 797 #define AMDGPU_GFX_MAX_SH_PER_SE 2 798 799 struct amdgpu_rb_config { 800 uint32_t rb_backend_disable; 801 uint32_t user_rb_backend_disable; 802 uint32_t raster_config; 803 uint32_t raster_config_1; 804 }; 805 806 struct gb_addr_config { 807 uint16_t pipe_interleave_size; 808 uint8_t num_pipes; 809 uint8_t max_compress_frags; 810 uint8_t num_banks; 811 uint8_t num_se; 812 uint8_t num_rb_per_se; 813 }; 814 815 struct amdgpu_gfx_config { 816 unsigned max_shader_engines; 817 unsigned max_tile_pipes; 818 unsigned max_cu_per_sh; 819 unsigned max_sh_per_se; 820 unsigned max_backends_per_se; 821 unsigned max_texture_channel_caches; 822 unsigned max_gprs; 823 unsigned max_gs_threads; 824 unsigned max_hw_contexts; 825 unsigned sc_prim_fifo_size_frontend; 826 unsigned sc_prim_fifo_size_backend; 827 unsigned sc_hiz_tile_fifo_size; 828 unsigned sc_earlyz_tile_fifo_size; 829 830 unsigned num_tile_pipes; 831 unsigned backend_enable_mask; 832 unsigned mem_max_burst_length_bytes; 833 unsigned mem_row_size_in_kb; 834 unsigned shader_engine_tile_size; 835 unsigned num_gpus; 836 unsigned multi_gpu_tile_size; 837 unsigned mc_arb_ramcfg; 838 unsigned gb_addr_config; 839 unsigned num_rbs; 840 unsigned gs_vgt_table_depth; 841 unsigned gs_prim_buffer_depth; 842 843 uint32_t tile_mode_array[32]; 844 uint32_t macrotile_mode_array[16]; 845 846 struct gb_addr_config gb_addr_config_fields; 847 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 848 849 /* gfx configure feature */ 850 uint32_t double_offchip_lds_buf; 851 /* cached value of DB_DEBUG2 */ 852 uint32_t db_debug2; 853 }; 854 855 struct amdgpu_cu_info { 856 uint32_t simd_per_cu; 857 uint32_t max_waves_per_simd; 858 uint32_t wave_front_size; 859 uint32_t max_scratch_slots_per_cu; 860 uint32_t lds_size; 861 862 /* total active CU number */ 863 uint32_t number; 864 uint32_t ao_cu_mask; 865 uint32_t ao_cu_bitmap[4][4]; 866 uint32_t bitmap[4][4]; 867 }; 868 869 struct amdgpu_gfx_funcs { 870 /* get the gpu clock counter */ 871 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 872 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 873 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 874 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 875 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 876 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue); 877 }; 878 879 struct amdgpu_ngg_buf { 880 struct amdgpu_bo *bo; 881 uint64_t gpu_addr; 882 uint32_t size; 883 uint32_t bo_size; 884 }; 885 886 enum { 887 NGG_PRIM = 0, 888 NGG_POS, 889 NGG_CNTL, 890 NGG_PARAM, 891 NGG_BUF_MAX 892 }; 893 894 struct amdgpu_ngg { 895 struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 896 uint32_t gds_reserve_addr; 897 uint32_t gds_reserve_size; 898 bool init; 899 }; 900 901 struct sq_work { 902 struct work_struct work; 903 unsigned ih_data; 904 }; 905 906 struct amdgpu_gfx { 907 struct rwlock gpu_clock_mutex; 908 struct amdgpu_gfx_config config; 909 struct amdgpu_rlc rlc; 910 struct amdgpu_mec mec; 911 struct amdgpu_kiq kiq; 912 struct amdgpu_scratch scratch; 913 const struct firmware *me_fw; /* ME firmware */ 914 uint32_t me_fw_version; 915 const struct firmware *pfp_fw; /* PFP firmware */ 916 uint32_t pfp_fw_version; 917 const struct firmware *ce_fw; /* CE firmware */ 918 uint32_t ce_fw_version; 919 const struct firmware *rlc_fw; /* RLC firmware */ 920 uint32_t rlc_fw_version; 921 const struct firmware *mec_fw; /* MEC firmware */ 922 uint32_t mec_fw_version; 923 const struct firmware *mec2_fw; /* MEC2 firmware */ 924 uint32_t mec2_fw_version; 925 uint32_t me_feature_version; 926 uint32_t ce_feature_version; 927 uint32_t pfp_feature_version; 928 uint32_t rlc_feature_version; 929 uint32_t rlc_srlc_fw_version; 930 uint32_t rlc_srlc_feature_version; 931 uint32_t rlc_srlg_fw_version; 932 uint32_t rlc_srlg_feature_version; 933 uint32_t rlc_srls_fw_version; 934 uint32_t rlc_srls_feature_version; 935 uint32_t mec_feature_version; 936 uint32_t mec2_feature_version; 937 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 938 unsigned num_gfx_rings; 939 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 940 unsigned num_compute_rings; 941 struct amdgpu_irq_src eop_irq; 942 struct amdgpu_irq_src priv_reg_irq; 943 struct amdgpu_irq_src priv_inst_irq; 944 struct amdgpu_irq_src cp_ecc_error_irq; 945 struct amdgpu_irq_src sq_irq; 946 struct sq_work sq_work; 947 948 /* gfx status */ 949 uint32_t gfx_current_status; 950 /* ce ram size*/ 951 unsigned ce_ram_size; 952 struct amdgpu_cu_info cu_info; 953 const struct amdgpu_gfx_funcs *funcs; 954 955 /* reset mask */ 956 uint32_t grbm_soft_reset; 957 uint32_t srbm_soft_reset; 958 /* s3/s4 mask */ 959 bool in_suspend; 960 /* NGG */ 961 struct amdgpu_ngg ngg; 962 963 /* pipe reservation */ 964 struct rwlock pipe_reserve_mutex; 965 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 966 }; 967 968 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 969 unsigned size, struct amdgpu_ib *ib); 970 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 971 struct dma_fence *f); 972 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 973 struct amdgpu_ib *ibs, struct amdgpu_job *job, 974 struct dma_fence **f); 975 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 976 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 977 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 978 979 /* 980 * CS. 981 */ 982 struct amdgpu_cs_chunk { 983 uint32_t chunk_id; 984 uint32_t length_dw; 985 void *kdata; 986 }; 987 988 struct amdgpu_cs_parser { 989 struct amdgpu_device *adev; 990 struct drm_file *filp; 991 struct amdgpu_ctx *ctx; 992 993 /* chunks */ 994 unsigned nchunks; 995 struct amdgpu_cs_chunk *chunks; 996 997 /* scheduler job object */ 998 struct amdgpu_job *job; 999 struct amdgpu_ring *ring; 1000 1001 /* buffer objects */ 1002 struct ww_acquire_ctx ticket; 1003 struct amdgpu_bo_list *bo_list; 1004 struct amdgpu_mn *mn; 1005 struct amdgpu_bo_list_entry vm_pd; 1006 struct list_head validated; 1007 struct dma_fence *fence; 1008 uint64_t bytes_moved_threshold; 1009 uint64_t bytes_moved_vis_threshold; 1010 uint64_t bytes_moved; 1011 uint64_t bytes_moved_vis; 1012 struct amdgpu_bo_list_entry *evictable; 1013 1014 /* user fence */ 1015 struct amdgpu_bo_list_entry uf_entry; 1016 1017 unsigned num_post_dep_syncobjs; 1018 struct drm_syncobj **post_dep_syncobjs; 1019 }; 1020 1021 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1022 uint32_t ib_idx, int idx) 1023 { 1024 return p->job->ibs[ib_idx].ptr[idx]; 1025 } 1026 1027 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1028 uint32_t ib_idx, int idx, 1029 uint32_t value) 1030 { 1031 p->job->ibs[ib_idx].ptr[idx] = value; 1032 } 1033 1034 /* 1035 * Writeback 1036 */ 1037 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 1038 1039 struct amdgpu_wb { 1040 struct amdgpu_bo *wb_obj; 1041 volatile uint32_t *wb; 1042 uint64_t gpu_addr; 1043 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1044 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1045 }; 1046 1047 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 1048 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 1049 1050 /* 1051 * SDMA 1052 */ 1053 struct amdgpu_sdma_instance { 1054 /* SDMA firmware */ 1055 const struct firmware *fw; 1056 uint32_t fw_version; 1057 uint32_t feature_version; 1058 1059 struct amdgpu_ring ring; 1060 bool burst_nop; 1061 }; 1062 1063 struct amdgpu_sdma { 1064 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1065 #ifdef CONFIG_DRM_AMDGPU_SI 1066 //SI DMA has a difference trap irq number for the second engine 1067 struct amdgpu_irq_src trap_irq_1; 1068 #endif 1069 struct amdgpu_irq_src trap_irq; 1070 struct amdgpu_irq_src illegal_inst_irq; 1071 int num_instances; 1072 uint32_t srbm_soft_reset; 1073 }; 1074 1075 /* 1076 * Firmware 1077 */ 1078 enum amdgpu_firmware_load_type { 1079 AMDGPU_FW_LOAD_DIRECT = 0, 1080 AMDGPU_FW_LOAD_SMU, 1081 AMDGPU_FW_LOAD_PSP, 1082 }; 1083 1084 struct amdgpu_firmware { 1085 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1086 enum amdgpu_firmware_load_type load_type; 1087 struct amdgpu_bo *fw_buf; 1088 unsigned int fw_size; 1089 unsigned int max_ucodes; 1090 /* firmwares are loaded by psp instead of smu from vega10 */ 1091 const struct amdgpu_psp_funcs *funcs; 1092 struct amdgpu_bo *rbuf; 1093 struct rwlock mutex; 1094 1095 /* gpu info firmware data pointer */ 1096 const struct firmware *gpu_info_fw; 1097 1098 void *fw_buf_ptr; 1099 uint64_t fw_buf_mc; 1100 }; 1101 1102 /* 1103 * Benchmarking 1104 */ 1105 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1106 1107 1108 /* 1109 * Testing 1110 */ 1111 void amdgpu_test_moves(struct amdgpu_device *adev); 1112 1113 1114 /* 1115 * amdgpu smumgr functions 1116 */ 1117 struct amdgpu_smumgr_funcs { 1118 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1119 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1120 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1121 }; 1122 1123 /* 1124 * amdgpu smumgr 1125 */ 1126 struct amdgpu_smumgr { 1127 struct amdgpu_bo *toc_buf; 1128 struct amdgpu_bo *smu_buf; 1129 /* asic priv smu data */ 1130 void *priv; 1131 spinlock_t smu_lock; 1132 /* smumgr functions */ 1133 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1134 /* ucode loading complete flag */ 1135 uint32_t fw_flags; 1136 }; 1137 1138 /* 1139 * ASIC specific register table accessible by UMD 1140 */ 1141 struct amdgpu_allowed_register_entry { 1142 uint32_t reg_offset; 1143 bool grbm_indexed; 1144 }; 1145 1146 /* 1147 * ASIC specific functions. 1148 */ 1149 struct amdgpu_asic_funcs { 1150 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1151 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1152 u8 *bios, u32 length_bytes); 1153 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1154 u32 sh_num, u32 reg_offset, u32 *value); 1155 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1156 int (*reset)(struct amdgpu_device *adev); 1157 /* get the reference clock */ 1158 u32 (*get_xclk)(struct amdgpu_device *adev); 1159 /* MM block clocks */ 1160 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1161 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1162 /* static power management */ 1163 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1164 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1165 /* get config memsize register */ 1166 u32 (*get_config_memsize)(struct amdgpu_device *adev); 1167 /* flush hdp write queue */ 1168 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 1169 /* invalidate hdp read cache */ 1170 void (*invalidate_hdp)(struct amdgpu_device *adev, 1171 struct amdgpu_ring *ring); 1172 /* check if the asic needs a full reset of if soft reset will work */ 1173 bool (*need_full_reset)(struct amdgpu_device *adev); 1174 }; 1175 1176 /* 1177 * IOCTL. 1178 */ 1179 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1180 struct drm_file *filp); 1181 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1182 struct drm_file *filp); 1183 1184 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1185 struct drm_file *filp); 1186 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1187 struct drm_file *filp); 1188 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1189 struct drm_file *filp); 1190 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1191 struct drm_file *filp); 1192 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1193 struct drm_file *filp); 1194 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1195 struct drm_file *filp); 1196 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1197 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 1198 struct drm_file *filp); 1199 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1200 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1201 struct drm_file *filp); 1202 1203 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1204 struct drm_file *filp); 1205 1206 /* VRAM scratch page for HDP bug, default vram page */ 1207 struct amdgpu_vram_scratch { 1208 struct amdgpu_bo *robj; 1209 volatile uint32_t *ptr; 1210 u64 gpu_addr; 1211 }; 1212 1213 /* 1214 * ACPI 1215 */ 1216 struct amdgpu_atcs_functions { 1217 bool get_ext_state; 1218 bool pcie_perf_req; 1219 bool pcie_dev_rdy; 1220 bool pcie_bus_width; 1221 }; 1222 1223 struct amdgpu_atcs { 1224 struct amdgpu_atcs_functions functions; 1225 }; 1226 1227 /* 1228 * Firmware VRAM reservation 1229 */ 1230 struct amdgpu_fw_vram_usage { 1231 u64 start_offset; 1232 u64 size; 1233 struct amdgpu_bo *reserved_bo; 1234 void *va; 1235 }; 1236 1237 /* 1238 * CGS 1239 */ 1240 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1241 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1242 1243 /* 1244 * Core structure, functions and helpers. 1245 */ 1246 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1247 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1248 1249 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1250 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1251 1252 1253 /* 1254 * amdgpu nbio functions 1255 * 1256 */ 1257 struct nbio_hdp_flush_reg { 1258 u32 ref_and_mask_cp0; 1259 u32 ref_and_mask_cp1; 1260 u32 ref_and_mask_cp2; 1261 u32 ref_and_mask_cp3; 1262 u32 ref_and_mask_cp4; 1263 u32 ref_and_mask_cp5; 1264 u32 ref_and_mask_cp6; 1265 u32 ref_and_mask_cp7; 1266 u32 ref_and_mask_cp8; 1267 u32 ref_and_mask_cp9; 1268 u32 ref_and_mask_sdma0; 1269 u32 ref_and_mask_sdma1; 1270 }; 1271 1272 struct amdgpu_nbio_funcs { 1273 const struct nbio_hdp_flush_reg *hdp_flush_reg; 1274 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 1275 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 1276 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 1277 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 1278 u32 (*get_rev_id)(struct amdgpu_device *adev); 1279 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 1280 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 1281 u32 (*get_memsize)(struct amdgpu_device *adev); 1282 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 1283 bool use_doorbell, int doorbell_index); 1284 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 1285 bool enable); 1286 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 1287 bool enable); 1288 void (*ih_doorbell_range)(struct amdgpu_device *adev, 1289 bool use_doorbell, int doorbell_index); 1290 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 1291 bool enable); 1292 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 1293 bool enable); 1294 void (*get_clockgating_state)(struct amdgpu_device *adev, 1295 u32 *flags); 1296 void (*ih_control)(struct amdgpu_device *adev); 1297 void (*init_registers)(struct amdgpu_device *adev); 1298 void (*detect_hw_virt)(struct amdgpu_device *adev); 1299 }; 1300 1301 struct amdgpu_df_funcs { 1302 void (*init)(struct amdgpu_device *adev); 1303 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 1304 bool enable); 1305 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 1306 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 1307 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 1308 bool enable); 1309 void (*get_clockgating_state)(struct amdgpu_device *adev, 1310 u32 *flags); 1311 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 1312 bool enable); 1313 }; 1314 /* Define the HW IP blocks will be used in driver , add more if necessary */ 1315 enum amd_hw_ip_block_type { 1316 GC_HWIP = 1, 1317 HDP_HWIP, 1318 SDMA0_HWIP, 1319 SDMA1_HWIP, 1320 MMHUB_HWIP, 1321 ATHUB_HWIP, 1322 NBIO_HWIP, 1323 MP0_HWIP, 1324 MP1_HWIP, 1325 UVD_HWIP, 1326 VCN_HWIP = UVD_HWIP, 1327 VCE_HWIP, 1328 DF_HWIP, 1329 DCE_HWIP, 1330 OSSSYS_HWIP, 1331 SMUIO_HWIP, 1332 PWR_HWIP, 1333 NBIF_HWIP, 1334 THM_HWIP, 1335 CLK_HWIP, 1336 MAX_HWIP 1337 }; 1338 1339 #define HWIP_MAX_INSTANCE 6 1340 1341 struct amd_powerplay { 1342 void *pp_handle; 1343 const struct amd_pm_funcs *pp_funcs; 1344 uint32_t pp_feature; 1345 }; 1346 1347 #define AMDGPU_RESET_MAGIC_NUM 64 1348 struct amdgpu_device { 1349 struct device self; 1350 struct device *dev; 1351 struct drm_device *ddev; 1352 struct pci_dev *pdev; 1353 1354 #ifdef CONFIG_DRM_AMD_ACP 1355 struct amdgpu_acp acp; 1356 #endif 1357 1358 pci_chipset_tag_t pc; 1359 pcitag_t pa_tag; 1360 pci_intr_handle_t intrh; 1361 bus_space_tag_t iot; 1362 bus_space_tag_t memt; 1363 bus_dma_tag_t dmat; 1364 void *irqh; 1365 1366 void (*switchcb)(void *, int, int); 1367 void *switchcbarg; 1368 void *switchcookie; 1369 struct task switchtask; 1370 struct rasops_info ro; 1371 int console; 1372 int primary; 1373 1374 struct task burner_task; 1375 int burner_fblank; 1376 1377 unsigned long fb_aper_offset; 1378 unsigned long fb_aper_size; 1379 1380 /* ASIC */ 1381 enum amd_asic_type asic_type; 1382 uint32_t family; 1383 uint32_t rev_id; 1384 uint32_t external_rev_id; 1385 unsigned long flags; 1386 int usec_timeout; 1387 const struct amdgpu_asic_funcs *asic_funcs; 1388 bool shutdown; 1389 bool need_dma32; 1390 bool need_swiotlb; 1391 bool accel_working; 1392 struct work_struct reset_work; 1393 struct notifier_block acpi_nb; 1394 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1395 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1396 unsigned debugfs_count; 1397 #if defined(CONFIG_DEBUG_FS) 1398 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1399 #endif 1400 struct amdgpu_atif *atif; 1401 struct amdgpu_atcs atcs; 1402 struct rwlock srbm_mutex; 1403 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1404 struct rwlock grbm_idx_mutex; 1405 struct dev_pm_domain vga_pm_domain; 1406 bool have_disp_power_ref; 1407 1408 /* BIOS */ 1409 bool is_atom_fw; 1410 uint8_t *bios; 1411 uint32_t bios_size; 1412 struct amdgpu_bo *stolen_vga_memory; 1413 uint32_t bios_scratch_reg_offset; 1414 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1415 1416 /* Register/doorbell mmio */ 1417 resource_size_t rmmio_base; 1418 resource_size_t rmmio_size; 1419 #ifdef __linux__ 1420 void __iomem *rmmio; 1421 #endif 1422 bus_space_tag_t rmmio_bst; 1423 bus_space_handle_t rmmio_bsh; 1424 /* protects concurrent MM_INDEX/DATA based register access */ 1425 spinlock_t mmio_idx_lock; 1426 /* protects concurrent SMC based register access */ 1427 spinlock_t smc_idx_lock; 1428 amdgpu_rreg_t smc_rreg; 1429 amdgpu_wreg_t smc_wreg; 1430 /* protects concurrent PCIE register access */ 1431 spinlock_t pcie_idx_lock; 1432 amdgpu_rreg_t pcie_rreg; 1433 amdgpu_wreg_t pcie_wreg; 1434 amdgpu_rreg_t pciep_rreg; 1435 amdgpu_wreg_t pciep_wreg; 1436 /* protects concurrent UVD register access */ 1437 spinlock_t uvd_ctx_idx_lock; 1438 amdgpu_rreg_t uvd_ctx_rreg; 1439 amdgpu_wreg_t uvd_ctx_wreg; 1440 /* protects concurrent DIDT register access */ 1441 spinlock_t didt_idx_lock; 1442 amdgpu_rreg_t didt_rreg; 1443 amdgpu_wreg_t didt_wreg; 1444 /* protects concurrent gc_cac register access */ 1445 spinlock_t gc_cac_idx_lock; 1446 amdgpu_rreg_t gc_cac_rreg; 1447 amdgpu_wreg_t gc_cac_wreg; 1448 /* protects concurrent se_cac register access */ 1449 spinlock_t se_cac_idx_lock; 1450 amdgpu_rreg_t se_cac_rreg; 1451 amdgpu_wreg_t se_cac_wreg; 1452 /* protects concurrent ENDPOINT (audio) register access */ 1453 spinlock_t audio_endpt_idx_lock; 1454 amdgpu_block_rreg_t audio_endpt_rreg; 1455 amdgpu_block_wreg_t audio_endpt_wreg; 1456 #ifdef notyet 1457 void __iomem *rio_mem; 1458 #endif 1459 bus_space_tag_t rio_mem_bst; 1460 bus_space_handle_t rio_mem_bsh; 1461 resource_size_t rio_mem_size; 1462 struct amdgpu_doorbell doorbell; 1463 1464 /* clock/pll info */ 1465 struct amdgpu_clock clock; 1466 1467 /* MC */ 1468 struct amdgpu_gmc gmc; 1469 struct amdgpu_gart gart; 1470 dma_addr_t dummy_page_addr; 1471 struct amdgpu_vm_manager vm_manager; 1472 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 1473 1474 /* memory management */ 1475 struct amdgpu_mman mman; 1476 struct amdgpu_vram_scratch vram_scratch; 1477 struct amdgpu_wb wb; 1478 atomic64_t num_bytes_moved; 1479 atomic64_t num_evictions; 1480 atomic64_t num_vram_cpu_page_faults; 1481 atomic_t gpu_reset_counter; 1482 atomic_t vram_lost_counter; 1483 1484 /* data for buffer migration throttling */ 1485 struct { 1486 spinlock_t lock; 1487 s64 last_update_us; 1488 s64 accum_us; /* accumulated microseconds */ 1489 s64 accum_us_vis; /* for visible VRAM */ 1490 u32 log2_max_MBps; 1491 } mm_stats; 1492 1493 /* display */ 1494 bool enable_virtual_display; 1495 struct amdgpu_mode_info mode_info; 1496 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 1497 struct work_struct hotplug_work; 1498 struct amdgpu_irq_src crtc_irq; 1499 struct amdgpu_irq_src pageflip_irq; 1500 struct amdgpu_irq_src hpd_irq; 1501 1502 /* rings */ 1503 u64 fence_context; 1504 unsigned num_rings; 1505 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1506 bool ib_pool_ready; 1507 struct amdgpu_sa_manager ring_tmp_bo; 1508 1509 /* interrupts */ 1510 struct amdgpu_irq irq; 1511 1512 /* powerplay */ 1513 struct amd_powerplay powerplay; 1514 bool pp_force_state_enabled; 1515 1516 /* dpm */ 1517 struct amdgpu_pm pm; 1518 u32 cg_flags; 1519 u32 pg_flags; 1520 1521 /* amdgpu smumgr */ 1522 struct amdgpu_smumgr smu; 1523 1524 /* gfx */ 1525 struct amdgpu_gfx gfx; 1526 1527 /* sdma */ 1528 struct amdgpu_sdma sdma; 1529 1530 /* uvd */ 1531 struct amdgpu_uvd uvd; 1532 1533 /* vce */ 1534 struct amdgpu_vce vce; 1535 1536 /* vcn */ 1537 struct amdgpu_vcn vcn; 1538 1539 /* firmwares */ 1540 struct amdgpu_firmware firmware; 1541 1542 /* PSP */ 1543 struct psp_context psp; 1544 1545 /* GDS */ 1546 struct amdgpu_gds gds; 1547 1548 /* display related functionality */ 1549 struct amdgpu_display_manager dm; 1550 1551 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1552 int num_ip_blocks; 1553 struct rwlock mn_lock; 1554 DECLARE_HASHTABLE(mn_hash, 7); 1555 1556 /* tracking pinned memory */ 1557 atomic64_t vram_pin_size; 1558 atomic64_t visible_pin_size; 1559 atomic64_t gart_pin_size; 1560 1561 /* amdkfd interface */ 1562 struct kfd_dev *kfd; 1563 1564 /* soc15 register offset based on ip, instance and segment */ 1565 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1566 1567 const struct amdgpu_nbio_funcs *nbio_funcs; 1568 const struct amdgpu_df_funcs *df_funcs; 1569 1570 /* delayed work_func for deferring clockgating during resume */ 1571 struct delayed_work late_init_work; 1572 1573 struct amdgpu_virt virt; 1574 /* firmware VRAM reservation */ 1575 struct amdgpu_fw_vram_usage fw_vram_usage; 1576 1577 /* link all shadow bo */ 1578 struct list_head shadow_list; 1579 struct rwlock shadow_list_lock; 1580 /* keep an lru list of rings by HW IP */ 1581 struct list_head ring_lru_list; 1582 spinlock_t ring_lru_list_lock; 1583 1584 /* record hw reset is performed */ 1585 bool has_hw_reset; 1586 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1587 1588 /* record last mm index being written through WREG32*/ 1589 unsigned long last_mm_index; 1590 bool in_gpu_reset; 1591 struct rwlock lock_reset; 1592 }; 1593 1594 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1595 { 1596 return container_of(bdev, struct amdgpu_device, mman.bdev); 1597 } 1598 1599 int amdgpu_device_init(struct amdgpu_device *adev, 1600 struct drm_device *ddev, 1601 struct pci_dev *pdev, 1602 uint32_t flags); 1603 void amdgpu_device_fini(struct amdgpu_device *adev); 1604 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1605 1606 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1607 uint32_t acc_flags); 1608 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1609 uint32_t acc_flags); 1610 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1611 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1612 1613 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1614 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1615 1616 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1617 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1618 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1619 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1620 1621 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1622 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1623 1624 int emu_soc_asic_init(struct amdgpu_device *adev); 1625 1626 /* 1627 * Registers read & write functions. 1628 */ 1629 1630 #define AMDGPU_REGS_IDX (1<<0) 1631 #define AMDGPU_REGS_NO_KIQ (1<<1) 1632 1633 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1634 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1635 1636 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1637 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1638 1639 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1640 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1641 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1642 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1643 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1644 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1645 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1646 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1647 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1648 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1649 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1650 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1651 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1652 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1653 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1654 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1655 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1656 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1657 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1658 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1659 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1660 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1661 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1662 #define WREG32_P(reg, val, mask) \ 1663 do { \ 1664 uint32_t tmp_ = RREG32(reg); \ 1665 tmp_ &= (mask); \ 1666 tmp_ |= ((val) & ~(mask)); \ 1667 WREG32(reg, tmp_); \ 1668 } while (0) 1669 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1670 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1671 #define WREG32_PLL_P(reg, val, mask) \ 1672 do { \ 1673 uint32_t tmp_ = RREG32_PLL(reg); \ 1674 tmp_ &= (mask); \ 1675 tmp_ |= ((val) & ~(mask)); \ 1676 WREG32_PLL(reg, tmp_); \ 1677 } while (0) 1678 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1679 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1680 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1681 1682 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1683 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1684 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1685 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1686 1687 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1688 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1689 1690 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1691 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1692 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1693 1694 #define REG_GET_FIELD(value, reg, field) \ 1695 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1696 1697 #define WREG32_FIELD(reg, field, val) \ 1698 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1699 1700 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1701 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1702 1703 /* 1704 * BIOS helpers. 1705 */ 1706 #define RBIOS8(i) (adev->bios[i]) 1707 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1708 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1709 1710 static inline struct amdgpu_sdma_instance * 1711 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1712 { 1713 struct amdgpu_device *adev = ring->adev; 1714 int i; 1715 1716 for (i = 0; i < adev->sdma.num_instances; i++) 1717 if (&adev->sdma.instance[i].ring == ring) 1718 break; 1719 1720 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1721 return &adev->sdma.instance[i]; 1722 else 1723 return NULL; 1724 } 1725 1726 /* 1727 * ASICs macro. 1728 */ 1729 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1730 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1731 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1732 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1733 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1734 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1735 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1736 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1737 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1738 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1739 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1740 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1741 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1742 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1743 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1744 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid)) 1745 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 1746 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 1747 #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1748 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 1749 #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags)) 1750 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1751 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1752 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1753 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1754 #define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib))) 1755 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1756 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1757 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1758 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1759 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1760 #define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c)) 1761 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1762 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1763 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1764 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1765 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1766 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1767 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1768 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1769 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 1770 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 1771 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 1772 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 1773 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1774 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1775 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1776 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1777 #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) 1778 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1779 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1780 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1781 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1782 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1783 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1784 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1785 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1786 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1787 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1788 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1789 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1790 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1791 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1792 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1793 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1794 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1795 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1796 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 1797 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q)) 1798 1799 /* Common functions */ 1800 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1801 struct amdgpu_job* job, bool force); 1802 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1803 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1804 void amdgpu_display_update_priority(struct amdgpu_device *adev); 1805 1806 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1807 u64 num_vis_bytes); 1808 void amdgpu_device_vram_location(struct amdgpu_device *adev, 1809 struct amdgpu_gmc *mc, u64 base); 1810 void amdgpu_device_gart_location(struct amdgpu_device *adev, 1811 struct amdgpu_gmc *mc); 1812 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1813 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1814 const u32 *registers, 1815 const u32 array_size); 1816 1817 bool amdgpu_device_is_px(struct drm_device *dev); 1818 /* atpx handler */ 1819 #if defined(CONFIG_VGA_SWITCHEROO) 1820 void amdgpu_register_atpx_handler(void); 1821 void amdgpu_unregister_atpx_handler(void); 1822 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1823 bool amdgpu_is_atpx_hybrid(void); 1824 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1825 bool amdgpu_has_atpx(void); 1826 #else 1827 static inline void amdgpu_register_atpx_handler(void) {} 1828 static inline void amdgpu_unregister_atpx_handler(void) {} 1829 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1830 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1831 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1832 static inline bool amdgpu_has_atpx(void) { return false; } 1833 #endif 1834 1835 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1836 void *amdgpu_atpx_get_dhandle(void); 1837 #else 1838 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1839 #endif 1840 1841 /* 1842 * KMS 1843 */ 1844 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1845 extern const int amdgpu_max_kms_ioctl; 1846 1847 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1848 void amdgpu_driver_unload_kms(struct drm_device *dev); 1849 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1850 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1851 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1852 struct drm_file *file_priv); 1853 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1854 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1855 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1856 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1857 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1858 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1859 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1860 unsigned long arg); 1861 1862 /* 1863 * functions used by amdgpu_encoder.c 1864 */ 1865 struct amdgpu_afmt_acr { 1866 u32 clock; 1867 1868 int n_32khz; 1869 int cts_32khz; 1870 1871 int n_44_1khz; 1872 int cts_44_1khz; 1873 1874 int n_48khz; 1875 int cts_48khz; 1876 1877 }; 1878 1879 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1880 1881 /* amdgpu_acpi.c */ 1882 #if defined(CONFIG_ACPI) 1883 int amdgpu_acpi_init(struct amdgpu_device *adev); 1884 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1885 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1886 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1887 u8 perf_req, bool advertise); 1888 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1889 #else 1890 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1891 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1892 #endif 1893 1894 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1895 uint64_t addr, struct amdgpu_bo **bo, 1896 struct amdgpu_bo_va_mapping **mapping); 1897 1898 #if defined(CONFIG_DRM_AMD_DC) 1899 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1900 #else 1901 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1902 #endif 1903 1904 #include "amdgpu_object.h" 1905 #endif 1906