1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_module.h> 59 #include <drm/ttm/ttm_execbuf_util.h> 60 61 #include <drm/amdgpu_drm.h> 62 #include <drm/drm_gem.h> 63 #include <drm/drm_ioctl.h> 64 #include <drm/gpu_scheduler.h> 65 66 #include <dev/wscons/wsconsio.h> 67 #include <dev/wscons/wsdisplayvar.h> 68 #include <dev/rasops/rasops.h> 69 70 #include <kgd_kfd_interface.h> 71 #include "dm_pp_interface.h" 72 #include "kgd_pp_interface.h" 73 74 #include "amd_shared.h" 75 #include "amdgpu_mode.h" 76 #include "amdgpu_ih.h" 77 #include "amdgpu_irq.h" 78 #include "amdgpu_ucode.h" 79 #include "amdgpu_ttm.h" 80 #include "amdgpu_psp.h" 81 #include "amdgpu_gds.h" 82 #include "amdgpu_sync.h" 83 #include "amdgpu_ring.h" 84 #include "amdgpu_vm.h" 85 #include "amdgpu_dpm.h" 86 #include "amdgpu_acp.h" 87 #include "amdgpu_uvd.h" 88 #include "amdgpu_vce.h" 89 #include "amdgpu_vcn.h" 90 #include "amdgpu_jpeg.h" 91 #include "amdgpu_mn.h" 92 #include "amdgpu_gmc.h" 93 #include "amdgpu_gfx.h" 94 #include "amdgpu_sdma.h" 95 #include "amdgpu_nbio.h" 96 #include "amdgpu_dm.h" 97 #include "amdgpu_virt.h" 98 #include "amdgpu_csa.h" 99 #include "amdgpu_gart.h" 100 #include "amdgpu_debugfs.h" 101 #include "amdgpu_job.h" 102 #include "amdgpu_bo_list.h" 103 #include "amdgpu_gem.h" 104 #include "amdgpu_doorbell.h" 105 #include "amdgpu_amdkfd.h" 106 #include "amdgpu_smu.h" 107 #include "amdgpu_discovery.h" 108 #include "amdgpu_mes.h" 109 #include "amdgpu_umc.h" 110 #include "amdgpu_mmhub.h" 111 #include "amdgpu_gfxhub.h" 112 #include "amdgpu_df.h" 113 114 #define MAX_GPU_INSTANCE 16 115 116 struct amdgpu_gpu_instance 117 { 118 struct amdgpu_device *adev; 119 int mgpu_fan_enabled; 120 }; 121 122 struct amdgpu_mgpu_info 123 { 124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 125 struct rwlock mutex; 126 uint32_t num_gpu; 127 uint32_t num_dgpu; 128 uint32_t num_apu; 129 }; 130 131 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 132 133 /* 134 * Modules parameters. 135 */ 136 extern int amdgpu_modeset; 137 extern int amdgpu_vram_limit; 138 extern int amdgpu_vis_vram_limit; 139 extern int amdgpu_gart_size; 140 extern int amdgpu_gtt_size; 141 extern int amdgpu_moverate; 142 extern int amdgpu_benchmarking; 143 extern int amdgpu_testing; 144 extern int amdgpu_audio; 145 extern int amdgpu_disp_priority; 146 extern int amdgpu_hw_i2c; 147 extern int amdgpu_pcie_gen2; 148 extern int amdgpu_msi; 149 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 150 extern int amdgpu_dpm; 151 extern int amdgpu_fw_load_type; 152 extern int amdgpu_aspm; 153 extern int amdgpu_runtime_pm; 154 extern uint amdgpu_ip_block_mask; 155 extern int amdgpu_bapm; 156 extern int amdgpu_deep_color; 157 extern int amdgpu_vm_size; 158 extern int amdgpu_vm_block_size; 159 extern int amdgpu_vm_fragment_size; 160 extern int amdgpu_vm_fault_stop; 161 extern int amdgpu_vm_debug; 162 extern int amdgpu_vm_update_mode; 163 extern int amdgpu_exp_hw_support; 164 extern int amdgpu_dc; 165 extern int amdgpu_sched_jobs; 166 extern int amdgpu_sched_hw_submission; 167 extern uint amdgpu_pcie_gen_cap; 168 extern uint amdgpu_pcie_lane_cap; 169 extern uint amdgpu_cg_mask; 170 extern uint amdgpu_pg_mask; 171 extern uint amdgpu_sdma_phase_quantum; 172 extern char *amdgpu_disable_cu; 173 extern char *amdgpu_virtual_display; 174 extern uint amdgpu_pp_feature_mask; 175 extern uint amdgpu_force_long_training; 176 extern int amdgpu_job_hang_limit; 177 extern int amdgpu_lbpw; 178 extern int amdgpu_compute_multipipe; 179 extern int amdgpu_gpu_recovery; 180 extern int amdgpu_emu_mode; 181 extern uint amdgpu_smu_memory_pool_size; 182 extern uint amdgpu_dc_feature_mask; 183 extern uint amdgpu_dc_debug_mask; 184 extern uint amdgpu_dm_abm_level; 185 extern int amdgpu_backlight; 186 extern struct amdgpu_mgpu_info mgpu_info; 187 extern int amdgpu_ras_enable; 188 extern uint amdgpu_ras_mask; 189 extern int amdgpu_bad_page_threshold; 190 extern int amdgpu_async_gfx_ring; 191 extern int amdgpu_mcbp; 192 extern int amdgpu_discovery; 193 extern int amdgpu_mes; 194 extern int amdgpu_noretry; 195 extern int amdgpu_force_asic_type; 196 #ifdef CONFIG_HSA_AMD 197 extern int sched_policy; 198 extern bool debug_evictions; 199 extern bool no_system_mem_limit; 200 #else 201 static const int sched_policy = KFD_SCHED_POLICY_HWS; 202 static const bool debug_evictions; /* = false */ 203 static const bool no_system_mem_limit; 204 #endif 205 206 extern int amdgpu_tmz; 207 extern int amdgpu_reset_method; 208 209 #ifdef CONFIG_DRM_AMDGPU_SI 210 extern int amdgpu_si_support; 211 #endif 212 #ifdef CONFIG_DRM_AMDGPU_CIK 213 extern int amdgpu_cik_support; 214 #endif 215 extern int amdgpu_num_kcq; 216 217 #define AMDGPU_VM_MAX_NUM_CTX 4096 218 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 219 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 220 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 221 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 222 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 223 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 224 #define AMDGPUFB_CONN_LIMIT 4 225 #define AMDGPU_BIOS_NUM_SCRATCH 16 226 227 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 228 229 /* hard reset data */ 230 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 231 232 /* reset flags */ 233 #define AMDGPU_RESET_GFX (1 << 0) 234 #define AMDGPU_RESET_COMPUTE (1 << 1) 235 #define AMDGPU_RESET_DMA (1 << 2) 236 #define AMDGPU_RESET_CP (1 << 3) 237 #define AMDGPU_RESET_GRBM (1 << 4) 238 #define AMDGPU_RESET_DMA1 (1 << 5) 239 #define AMDGPU_RESET_RLC (1 << 6) 240 #define AMDGPU_RESET_SEM (1 << 7) 241 #define AMDGPU_RESET_IH (1 << 8) 242 #define AMDGPU_RESET_VMC (1 << 9) 243 #define AMDGPU_RESET_MC (1 << 10) 244 #define AMDGPU_RESET_DISPLAY (1 << 11) 245 #define AMDGPU_RESET_UVD (1 << 12) 246 #define AMDGPU_RESET_VCE (1 << 13) 247 #define AMDGPU_RESET_VCE1 (1 << 14) 248 249 /* max cursor sizes (in pixels) */ 250 #define CIK_CURSOR_WIDTH 128 251 #define CIK_CURSOR_HEIGHT 128 252 253 struct amdgpu_device; 254 struct amdgpu_ib; 255 struct amdgpu_cs_parser; 256 struct amdgpu_job; 257 struct amdgpu_irq_src; 258 struct amdgpu_fpriv; 259 struct amdgpu_bo_va_mapping; 260 struct amdgpu_atif; 261 struct kfd_vm_fault_info; 262 struct amdgpu_hive_info; 263 264 enum amdgpu_cp_irq { 265 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 266 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 267 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 268 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 269 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 270 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 271 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 272 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 273 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 274 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 275 276 AMDGPU_CP_IRQ_LAST 277 }; 278 279 enum amdgpu_thermal_irq { 280 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 281 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 282 283 AMDGPU_THERMAL_IRQ_LAST 284 }; 285 286 enum amdgpu_kiq_irq { 287 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 288 AMDGPU_CP_KIQ_IRQ_LAST 289 }; 290 291 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 292 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 293 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 294 295 int amdgpu_device_ip_set_clockgating_state(void *dev, 296 enum amd_ip_block_type block_type, 297 enum amd_clockgating_state state); 298 int amdgpu_device_ip_set_powergating_state(void *dev, 299 enum amd_ip_block_type block_type, 300 enum amd_powergating_state state); 301 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 302 u32 *flags); 303 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 304 enum amd_ip_block_type block_type); 305 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 306 enum amd_ip_block_type block_type); 307 308 #define AMDGPU_MAX_IP_NUM 16 309 310 struct amdgpu_ip_block_status { 311 bool valid; 312 bool sw; 313 bool hw; 314 bool late_initialized; 315 bool hang; 316 }; 317 318 struct amdgpu_ip_block_version { 319 const enum amd_ip_block_type type; 320 const u32 major; 321 const u32 minor; 322 const u32 rev; 323 const struct amd_ip_funcs *funcs; 324 }; 325 326 #define HW_REV(_Major, _Minor, _Rev) \ 327 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 328 329 struct amdgpu_ip_block { 330 struct amdgpu_ip_block_status status; 331 const struct amdgpu_ip_block_version *version; 332 }; 333 334 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 335 enum amd_ip_block_type type, 336 u32 major, u32 minor); 337 338 struct amdgpu_ip_block * 339 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 340 enum amd_ip_block_type type); 341 342 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 343 const struct amdgpu_ip_block_version *ip_block_version); 344 345 /* 346 * BIOS. 347 */ 348 bool amdgpu_get_bios(struct amdgpu_device *adev); 349 bool amdgpu_read_bios(struct amdgpu_device *adev); 350 351 /* 352 * Clocks 353 */ 354 355 #define AMDGPU_MAX_PPLL 3 356 357 struct amdgpu_clock { 358 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 359 struct amdgpu_pll spll; 360 struct amdgpu_pll mpll; 361 /* 10 Khz units */ 362 uint32_t default_mclk; 363 uint32_t default_sclk; 364 uint32_t default_dispclk; 365 uint32_t current_dispclk; 366 uint32_t dp_extclk; 367 uint32_t max_pixel_clock; 368 }; 369 370 /* sub-allocation manager, it has to be protected by another lock. 371 * By conception this is an helper for other part of the driver 372 * like the indirect buffer or semaphore, which both have their 373 * locking. 374 * 375 * Principe is simple, we keep a list of sub allocation in offset 376 * order (first entry has offset == 0, last entry has the highest 377 * offset). 378 * 379 * When allocating new object we first check if there is room at 380 * the end total_size - (last_object_offset + last_object_size) >= 381 * alloc_size. If so we allocate new object there. 382 * 383 * When there is not enough room at the end, we start waiting for 384 * each sub object until we reach object_offset+object_size >= 385 * alloc_size, this object then become the sub object we return. 386 * 387 * Alignment can't be bigger than page size. 388 * 389 * Hole are not considered for allocation to keep things simple. 390 * Assumption is that there won't be hole (all object on same 391 * alignment). 392 */ 393 394 #define AMDGPU_SA_NUM_FENCE_LISTS 32 395 396 struct amdgpu_sa_manager { 397 wait_queue_head_t wq; 398 struct amdgpu_bo *bo; 399 struct list_head *hole; 400 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 401 struct list_head olist; 402 unsigned size; 403 uint64_t gpu_addr; 404 void *cpu_ptr; 405 uint32_t domain; 406 uint32_t align; 407 }; 408 409 /* sub-allocation buffer */ 410 struct amdgpu_sa_bo { 411 struct list_head olist; 412 struct list_head flist; 413 struct amdgpu_sa_manager *manager; 414 unsigned soffset; 415 unsigned eoffset; 416 struct dma_fence *fence; 417 }; 418 419 int amdgpu_fence_slab_init(void); 420 void amdgpu_fence_slab_fini(void); 421 422 /* 423 * IRQS. 424 */ 425 426 struct amdgpu_flip_work { 427 struct delayed_work flip_work; 428 struct work_struct unpin_work; 429 struct amdgpu_device *adev; 430 int crtc_id; 431 u32 target_vblank; 432 uint64_t base; 433 struct drm_pending_vblank_event *event; 434 struct amdgpu_bo *old_abo; 435 struct dma_fence *excl; 436 unsigned shared_count; 437 struct dma_fence **shared; 438 struct dma_fence_cb cb; 439 bool async; 440 }; 441 442 443 /* 444 * CP & rings. 445 */ 446 447 struct amdgpu_ib { 448 struct amdgpu_sa_bo *sa_bo; 449 uint32_t length_dw; 450 uint64_t gpu_addr; 451 uint32_t *ptr; 452 uint32_t flags; 453 }; 454 455 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 456 457 /* 458 * file private structure 459 */ 460 461 struct amdgpu_fpriv { 462 struct amdgpu_vm vm; 463 struct amdgpu_bo_va *prt_va; 464 struct amdgpu_bo_va *csa_va; 465 struct rwlock bo_list_lock; 466 struct idr bo_list_handles; 467 struct amdgpu_ctx_mgr ctx_mgr; 468 }; 469 470 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 471 472 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 473 unsigned size, 474 enum amdgpu_ib_pool_type pool, 475 struct amdgpu_ib *ib); 476 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 477 struct dma_fence *f); 478 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 479 struct amdgpu_ib *ibs, struct amdgpu_job *job, 480 struct dma_fence **f); 481 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 482 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 483 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 484 485 /* 486 * CS. 487 */ 488 struct amdgpu_cs_chunk { 489 uint32_t chunk_id; 490 uint32_t length_dw; 491 void *kdata; 492 }; 493 494 struct amdgpu_cs_post_dep { 495 struct drm_syncobj *syncobj; 496 struct dma_fence_chain *chain; 497 u64 point; 498 }; 499 500 struct amdgpu_cs_parser { 501 struct amdgpu_device *adev; 502 struct drm_file *filp; 503 struct amdgpu_ctx *ctx; 504 505 /* chunks */ 506 unsigned nchunks; 507 struct amdgpu_cs_chunk *chunks; 508 509 /* scheduler job object */ 510 struct amdgpu_job *job; 511 struct drm_sched_entity *entity; 512 513 /* buffer objects */ 514 struct ww_acquire_ctx ticket; 515 struct amdgpu_bo_list *bo_list; 516 struct amdgpu_mn *mn; 517 struct amdgpu_bo_list_entry vm_pd; 518 struct list_head validated; 519 struct dma_fence *fence; 520 uint64_t bytes_moved_threshold; 521 uint64_t bytes_moved_vis_threshold; 522 uint64_t bytes_moved; 523 uint64_t bytes_moved_vis; 524 525 /* user fence */ 526 struct amdgpu_bo_list_entry uf_entry; 527 528 unsigned num_post_deps; 529 struct amdgpu_cs_post_dep *post_deps; 530 }; 531 532 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 533 uint32_t ib_idx, int idx) 534 { 535 return p->job->ibs[ib_idx].ptr[idx]; 536 } 537 538 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 539 uint32_t ib_idx, int idx, 540 uint32_t value) 541 { 542 p->job->ibs[ib_idx].ptr[idx] = value; 543 } 544 545 /* 546 * Writeback 547 */ 548 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 549 550 struct amdgpu_wb { 551 struct amdgpu_bo *wb_obj; 552 volatile uint32_t *wb; 553 uint64_t gpu_addr; 554 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 555 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 556 }; 557 558 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 559 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 560 561 /* 562 * Benchmarking 563 */ 564 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 565 566 567 /* 568 * Testing 569 */ 570 void amdgpu_test_moves(struct amdgpu_device *adev); 571 572 /* 573 * ASIC specific register table accessible by UMD 574 */ 575 struct amdgpu_allowed_register_entry { 576 uint32_t reg_offset; 577 bool grbm_indexed; 578 }; 579 580 enum amd_reset_method { 581 AMD_RESET_METHOD_LEGACY = 0, 582 AMD_RESET_METHOD_MODE0, 583 AMD_RESET_METHOD_MODE1, 584 AMD_RESET_METHOD_MODE2, 585 AMD_RESET_METHOD_BACO 586 }; 587 588 /* 589 * ASIC specific functions. 590 */ 591 struct amdgpu_asic_funcs { 592 bool (*read_disabled_bios)(struct amdgpu_device *adev); 593 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 594 u8 *bios, u32 length_bytes); 595 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 596 u32 sh_num, u32 reg_offset, u32 *value); 597 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 598 int (*reset)(struct amdgpu_device *adev); 599 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 600 /* get the reference clock */ 601 u32 (*get_xclk)(struct amdgpu_device *adev); 602 /* MM block clocks */ 603 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 604 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 605 /* static power management */ 606 int (*get_pcie_lanes)(struct amdgpu_device *adev); 607 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 608 /* get config memsize register */ 609 u32 (*get_config_memsize)(struct amdgpu_device *adev); 610 /* flush hdp write queue */ 611 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 612 /* invalidate hdp read cache */ 613 void (*invalidate_hdp)(struct amdgpu_device *adev, 614 struct amdgpu_ring *ring); 615 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 616 /* check if the asic needs a full reset of if soft reset will work */ 617 bool (*need_full_reset)(struct amdgpu_device *adev); 618 /* initialize doorbell layout for specific asic*/ 619 void (*init_doorbell_index)(struct amdgpu_device *adev); 620 /* PCIe bandwidth usage */ 621 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 622 uint64_t *count1); 623 /* do we need to reset the asic at init time (e.g., kexec) */ 624 bool (*need_reset_on_init)(struct amdgpu_device *adev); 625 /* PCIe replay counter */ 626 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 627 /* device supports BACO */ 628 bool (*supports_baco)(struct amdgpu_device *adev); 629 /* pre asic_init quirks */ 630 void (*pre_asic_init)(struct amdgpu_device *adev); 631 }; 632 633 /* 634 * IOCTL. 635 */ 636 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 637 struct drm_file *filp); 638 639 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 640 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 641 struct drm_file *filp); 642 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 643 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 644 struct drm_file *filp); 645 646 /* VRAM scratch page for HDP bug, default vram page */ 647 struct amdgpu_vram_scratch { 648 struct amdgpu_bo *robj; 649 volatile uint32_t *ptr; 650 u64 gpu_addr; 651 }; 652 653 /* 654 * ACPI 655 */ 656 struct amdgpu_atcs_functions { 657 bool get_ext_state; 658 bool pcie_perf_req; 659 bool pcie_dev_rdy; 660 bool pcie_bus_width; 661 }; 662 663 struct amdgpu_atcs { 664 struct amdgpu_atcs_functions functions; 665 }; 666 667 /* 668 * CGS 669 */ 670 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 671 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 672 673 /* 674 * Core structure, functions and helpers. 675 */ 676 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 677 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 678 679 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 680 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 681 682 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 683 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 684 685 struct amdgpu_mmio_remap { 686 u32 reg_offset; 687 resource_size_t bus_addr; 688 }; 689 690 /* Define the HW IP blocks will be used in driver , add more if necessary */ 691 enum amd_hw_ip_block_type { 692 GC_HWIP = 1, 693 HDP_HWIP, 694 SDMA0_HWIP, 695 SDMA1_HWIP, 696 SDMA2_HWIP, 697 SDMA3_HWIP, 698 SDMA4_HWIP, 699 SDMA5_HWIP, 700 SDMA6_HWIP, 701 SDMA7_HWIP, 702 MMHUB_HWIP, 703 ATHUB_HWIP, 704 NBIO_HWIP, 705 MP0_HWIP, 706 MP1_HWIP, 707 UVD_HWIP, 708 VCN_HWIP = UVD_HWIP, 709 JPEG_HWIP = VCN_HWIP, 710 VCE_HWIP, 711 DF_HWIP, 712 DCE_HWIP, 713 OSSSYS_HWIP, 714 SMUIO_HWIP, 715 PWR_HWIP, 716 NBIF_HWIP, 717 THM_HWIP, 718 CLK_HWIP, 719 UMC_HWIP, 720 RSMU_HWIP, 721 MAX_HWIP 722 }; 723 724 #define HWIP_MAX_INSTANCE 10 725 726 struct amd_powerplay { 727 void *pp_handle; 728 const struct amd_pm_funcs *pp_funcs; 729 }; 730 731 #define AMDGPU_RESET_MAGIC_NUM 64 732 #define AMDGPU_MAX_DF_PERFMONS 4 733 struct amdgpu_device { 734 struct device self; 735 struct device *dev; 736 struct pci_dev *pdev; 737 struct drm_device ddev; 738 739 pci_chipset_tag_t pc; 740 pcitag_t pa_tag; 741 pci_intr_handle_t intrh; 742 bus_space_tag_t iot; 743 bus_space_tag_t memt; 744 bus_dma_tag_t dmat; 745 void *irqh; 746 747 void (*switchcb)(void *, int, int); 748 void *switchcbarg; 749 void *switchcookie; 750 struct task switchtask; 751 struct rasops_info ro; 752 int console; 753 int primary; 754 755 struct task burner_task; 756 int burner_fblank; 757 758 unsigned long fb_aper_offset; 759 unsigned long fb_aper_size; 760 761 #ifdef CONFIG_DRM_AMD_ACP 762 struct amdgpu_acp acp; 763 #endif 764 struct amdgpu_hive_info *hive; 765 /* ASIC */ 766 enum amd_asic_type asic_type; 767 uint32_t family; 768 uint32_t rev_id; 769 uint32_t external_rev_id; 770 unsigned long flags; 771 unsigned long apu_flags; 772 int usec_timeout; 773 const struct amdgpu_asic_funcs *asic_funcs; 774 bool shutdown; 775 bool need_swiotlb; 776 bool accel_working; 777 struct notifier_block acpi_nb; 778 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 779 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 780 unsigned debugfs_count; 781 #if defined(CONFIG_DEBUG_FS) 782 struct dentry *debugfs_preempt; 783 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 784 #endif 785 struct amdgpu_atif *atif; 786 struct amdgpu_atcs atcs; 787 struct rwlock srbm_mutex; 788 /* GRBM index mutex. Protects concurrent access to GRBM index */ 789 struct rwlock grbm_idx_mutex; 790 struct dev_pm_domain vga_pm_domain; 791 bool have_disp_power_ref; 792 bool have_atomics_support; 793 794 /* BIOS */ 795 bool is_atom_fw; 796 uint8_t *bios; 797 uint32_t bios_size; 798 uint32_t bios_scratch_reg_offset; 799 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 800 801 /* Register/doorbell mmio */ 802 resource_size_t rmmio_base; 803 resource_size_t rmmio_size; 804 void __iomem *rmmio; 805 bus_space_tag_t rmmio_bst; 806 bus_space_handle_t rmmio_bsh; 807 /* protects concurrent MM_INDEX/DATA based register access */ 808 spinlock_t mmio_idx_lock; 809 struct amdgpu_mmio_remap rmmio_remap; 810 /* protects concurrent SMC based register access */ 811 spinlock_t smc_idx_lock; 812 amdgpu_rreg_t smc_rreg; 813 amdgpu_wreg_t smc_wreg; 814 /* protects concurrent PCIE register access */ 815 spinlock_t pcie_idx_lock; 816 amdgpu_rreg_t pcie_rreg; 817 amdgpu_wreg_t pcie_wreg; 818 amdgpu_rreg_t pciep_rreg; 819 amdgpu_wreg_t pciep_wreg; 820 amdgpu_rreg64_t pcie_rreg64; 821 amdgpu_wreg64_t pcie_wreg64; 822 /* protects concurrent UVD register access */ 823 spinlock_t uvd_ctx_idx_lock; 824 amdgpu_rreg_t uvd_ctx_rreg; 825 amdgpu_wreg_t uvd_ctx_wreg; 826 /* protects concurrent DIDT register access */ 827 spinlock_t didt_idx_lock; 828 amdgpu_rreg_t didt_rreg; 829 amdgpu_wreg_t didt_wreg; 830 /* protects concurrent gc_cac register access */ 831 spinlock_t gc_cac_idx_lock; 832 amdgpu_rreg_t gc_cac_rreg; 833 amdgpu_wreg_t gc_cac_wreg; 834 /* protects concurrent se_cac register access */ 835 spinlock_t se_cac_idx_lock; 836 amdgpu_rreg_t se_cac_rreg; 837 amdgpu_wreg_t se_cac_wreg; 838 /* protects concurrent ENDPOINT (audio) register access */ 839 spinlock_t audio_endpt_idx_lock; 840 amdgpu_block_rreg_t audio_endpt_rreg; 841 amdgpu_block_wreg_t audio_endpt_wreg; 842 #ifdef notyet 843 void __iomem *rio_mem; 844 #endif 845 bus_space_tag_t rio_mem_bst; 846 bus_space_handle_t rio_mem_bsh; 847 resource_size_t rio_mem_size; 848 struct amdgpu_doorbell doorbell; 849 850 /* clock/pll info */ 851 struct amdgpu_clock clock; 852 853 /* MC */ 854 struct amdgpu_gmc gmc; 855 struct amdgpu_gart gart; 856 dma_addr_t dummy_page_addr; 857 struct amdgpu_vm_manager vm_manager; 858 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 859 unsigned num_vmhubs; 860 861 /* memory management */ 862 struct amdgpu_mman mman; 863 struct amdgpu_vram_scratch vram_scratch; 864 struct amdgpu_wb wb; 865 atomic64_t num_bytes_moved; 866 atomic64_t num_evictions; 867 atomic64_t num_vram_cpu_page_faults; 868 atomic_t gpu_reset_counter; 869 atomic_t vram_lost_counter; 870 871 /* data for buffer migration throttling */ 872 struct { 873 spinlock_t lock; 874 s64 last_update_us; 875 s64 accum_us; /* accumulated microseconds */ 876 s64 accum_us_vis; /* for visible VRAM */ 877 u32 log2_max_MBps; 878 } mm_stats; 879 880 /* display */ 881 bool enable_virtual_display; 882 struct amdgpu_mode_info mode_info; 883 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 884 struct work_struct hotplug_work; 885 struct amdgpu_irq_src crtc_irq; 886 struct amdgpu_irq_src vupdate_irq; 887 struct amdgpu_irq_src pageflip_irq; 888 struct amdgpu_irq_src hpd_irq; 889 890 /* rings */ 891 u64 fence_context; 892 unsigned num_rings; 893 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 894 bool ib_pool_ready; 895 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 896 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 897 898 /* interrupts */ 899 struct amdgpu_irq irq; 900 901 /* powerplay */ 902 struct amd_powerplay powerplay; 903 bool pp_force_state_enabled; 904 905 /* smu */ 906 struct smu_context smu; 907 908 /* dpm */ 909 struct amdgpu_pm pm; 910 u32 cg_flags; 911 u32 pg_flags; 912 913 /* nbio */ 914 struct amdgpu_nbio nbio; 915 916 /* mmhub */ 917 struct amdgpu_mmhub mmhub; 918 919 /* gfxhub */ 920 struct amdgpu_gfxhub gfxhub; 921 922 /* gfx */ 923 struct amdgpu_gfx gfx; 924 925 /* sdma */ 926 struct amdgpu_sdma sdma; 927 928 /* uvd */ 929 struct amdgpu_uvd uvd; 930 931 /* vce */ 932 struct amdgpu_vce vce; 933 934 /* vcn */ 935 struct amdgpu_vcn vcn; 936 937 /* jpeg */ 938 struct amdgpu_jpeg jpeg; 939 940 /* firmwares */ 941 struct amdgpu_firmware firmware; 942 943 /* PSP */ 944 struct psp_context psp; 945 946 /* GDS */ 947 struct amdgpu_gds gds; 948 949 /* KFD */ 950 struct amdgpu_kfd_dev kfd; 951 952 /* UMC */ 953 struct amdgpu_umc umc; 954 955 /* display related functionality */ 956 struct amdgpu_display_manager dm; 957 958 /* mes */ 959 bool enable_mes; 960 struct amdgpu_mes mes; 961 962 /* df */ 963 struct amdgpu_df df; 964 965 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 966 int num_ip_blocks; 967 struct rwlock mn_lock; 968 DECLARE_HASHTABLE(mn_hash, 7); 969 970 /* tracking pinned memory */ 971 atomic64_t vram_pin_size; 972 atomic64_t visible_pin_size; 973 atomic64_t gart_pin_size; 974 975 /* soc15 register offset based on ip, instance and segment */ 976 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 977 978 /* delayed work_func for deferring clockgating during resume */ 979 struct delayed_work delayed_init_work; 980 981 struct amdgpu_virt virt; 982 983 /* link all shadow bo */ 984 struct list_head shadow_list; 985 struct rwlock shadow_list_lock; 986 987 /* record hw reset is performed */ 988 bool has_hw_reset; 989 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 990 991 /* s3/s4 mask */ 992 bool in_suspend; 993 bool in_hibernate; 994 995 atomic_t in_gpu_reset; 996 enum pp_mp1_state mp1_state; 997 struct rwlock reset_sem; 998 struct amdgpu_doorbell_index doorbell_index; 999 1000 struct rwlock notifier_lock; 1001 1002 int asic_reset_res; 1003 struct work_struct xgmi_reset_work; 1004 1005 long gfx_timeout; 1006 long sdma_timeout; 1007 long video_timeout; 1008 long compute_timeout; 1009 1010 uint64_t unique_id; 1011 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1012 1013 /* enable runtime pm on the device */ 1014 bool runpm; 1015 bool in_runpm; 1016 1017 bool pm_sysfs_en; 1018 bool ucode_sysfs_en; 1019 1020 /* Chip product information */ 1021 char product_number[16]; 1022 char product_name[32]; 1023 char serial[20]; 1024 1025 struct amdgpu_autodump autodump; 1026 1027 atomic_t throttling_logging_enabled; 1028 #ifdef notyet 1029 struct ratelimit_state throttling_logging_rs; 1030 #endif 1031 uint32_t ras_features; 1032 1033 bool in_pci_err_recovery; 1034 struct pci_saved_state *pci_state; 1035 }; 1036 1037 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1038 { 1039 return container_of(ddev, struct amdgpu_device, ddev); 1040 } 1041 1042 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1043 { 1044 return &adev->ddev; 1045 } 1046 1047 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1048 { 1049 return container_of(bdev, struct amdgpu_device, mman.bdev); 1050 } 1051 1052 int amdgpu_device_init(struct amdgpu_device *adev, 1053 uint32_t flags); 1054 void amdgpu_device_fini(struct amdgpu_device *adev); 1055 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1056 1057 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1058 uint32_t *buf, size_t size, bool write); 1059 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1060 uint32_t reg, uint32_t acc_flags); 1061 void amdgpu_device_wreg(struct amdgpu_device *adev, 1062 uint32_t reg, uint32_t v, 1063 uint32_t acc_flags); 1064 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1065 uint32_t reg, uint32_t v); 1066 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1067 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1068 1069 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1070 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1071 1072 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1073 u32 pcie_index, u32 pcie_data, 1074 u32 reg_addr); 1075 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1076 u32 pcie_index, u32 pcie_data, 1077 u32 reg_addr); 1078 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1079 u32 pcie_index, u32 pcie_data, 1080 u32 reg_addr, u32 reg_data); 1081 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1082 u32 pcie_index, u32 pcie_data, 1083 u32 reg_addr, u64 reg_data); 1084 1085 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1086 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1087 1088 int emu_soc_asic_init(struct amdgpu_device *adev); 1089 1090 /* 1091 * Registers read & write functions. 1092 */ 1093 #define AMDGPU_REGS_NO_KIQ (1<<1) 1094 1095 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1096 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1097 1098 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1099 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1100 1101 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1102 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1103 1104 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1105 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1106 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1107 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1108 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1109 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1110 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1111 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1112 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1113 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1114 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1115 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1116 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1117 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1118 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1119 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1120 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1121 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1122 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1123 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1124 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1125 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1126 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1127 #define WREG32_P(reg, val, mask) \ 1128 do { \ 1129 uint32_t tmp_ = RREG32(reg); \ 1130 tmp_ &= (mask); \ 1131 tmp_ |= ((val) & ~(mask)); \ 1132 WREG32(reg, tmp_); \ 1133 } while (0) 1134 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1135 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1136 #define WREG32_PLL_P(reg, val, mask) \ 1137 do { \ 1138 uint32_t tmp_ = RREG32_PLL(reg); \ 1139 tmp_ &= (mask); \ 1140 tmp_ |= ((val) & ~(mask)); \ 1141 WREG32_PLL(reg, tmp_); \ 1142 } while (0) 1143 1144 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1145 do { \ 1146 u32 tmp = RREG32_SMC(_Reg); \ 1147 tmp &= (_Mask); \ 1148 tmp |= ((_Val) & ~(_Mask)); \ 1149 WREG32_SMC(_Reg, tmp); \ 1150 } while (0) 1151 1152 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1153 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1154 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1155 1156 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1157 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1158 1159 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1160 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1161 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1162 1163 #define REG_GET_FIELD(value, reg, field) \ 1164 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1165 1166 #define WREG32_FIELD(reg, field, val) \ 1167 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1168 1169 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1170 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1171 1172 /* 1173 * BIOS helpers. 1174 */ 1175 #define RBIOS8(i) (adev->bios[i]) 1176 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1177 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1178 1179 /* 1180 * ASICs macro. 1181 */ 1182 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1183 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1184 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1185 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1186 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1187 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1188 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1189 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1190 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1191 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1192 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1193 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1194 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1195 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1196 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1197 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1198 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1199 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1200 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1201 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1202 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1203 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1204 1205 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1206 1207 /* Common functions */ 1208 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1209 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1210 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1211 struct amdgpu_job* job); 1212 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1213 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1214 1215 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1216 u64 num_vis_bytes); 1217 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1218 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1219 const u32 *registers, 1220 const u32 array_size); 1221 1222 bool amdgpu_device_supports_boco(struct drm_device *dev); 1223 bool amdgpu_device_supports_baco(struct drm_device *dev); 1224 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1225 struct amdgpu_device *peer_adev); 1226 int amdgpu_device_baco_enter(struct drm_device *dev); 1227 int amdgpu_device_baco_exit(struct drm_device *dev); 1228 1229 /* atpx handler */ 1230 #if defined(CONFIG_VGA_SWITCHEROO) 1231 void amdgpu_register_atpx_handler(void); 1232 void amdgpu_unregister_atpx_handler(void); 1233 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1234 bool amdgpu_is_atpx_hybrid(void); 1235 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1236 bool amdgpu_has_atpx(void); 1237 #else 1238 static inline void amdgpu_register_atpx_handler(void) {} 1239 static inline void amdgpu_unregister_atpx_handler(void) {} 1240 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1241 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1242 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1243 static inline bool amdgpu_has_atpx(void) { return false; } 1244 #endif 1245 1246 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1247 void *amdgpu_atpx_get_dhandle(void); 1248 #else 1249 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1250 #endif 1251 1252 /* 1253 * KMS 1254 */ 1255 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1256 extern const int amdgpu_max_kms_ioctl; 1257 1258 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1259 void amdgpu_driver_unload_kms(struct drm_device *dev); 1260 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1261 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1262 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1263 struct drm_file *file_priv); 1264 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1265 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1266 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1267 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1268 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1269 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1270 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1271 unsigned long arg); 1272 1273 /* 1274 * functions used by amdgpu_encoder.c 1275 */ 1276 struct amdgpu_afmt_acr { 1277 u32 clock; 1278 1279 int n_32khz; 1280 int cts_32khz; 1281 1282 int n_44_1khz; 1283 int cts_44_1khz; 1284 1285 int n_48khz; 1286 int cts_48khz; 1287 1288 }; 1289 1290 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1291 1292 /* amdgpu_acpi.c */ 1293 #if defined(CONFIG_ACPI) 1294 int amdgpu_acpi_init(struct amdgpu_device *adev); 1295 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1296 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1297 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1298 u8 perf_req, bool advertise); 1299 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1300 1301 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1302 struct amdgpu_dm_backlight_caps *caps); 1303 #else 1304 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1305 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1306 #endif 1307 1308 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1309 uint64_t addr, struct amdgpu_bo **bo, 1310 struct amdgpu_bo_va_mapping **mapping); 1311 1312 #if defined(CONFIG_DRM_AMD_DC) 1313 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1314 #else 1315 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1316 #endif 1317 1318 1319 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1320 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1321 1322 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1323 pci_channel_state_t state); 1324 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1325 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1326 void amdgpu_pci_resume(struct pci_dev *pdev); 1327 1328 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1329 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1330 1331 #include "amdgpu_object.h" 1332 1333 /* used by df_v3_6.c and amdgpu_pmu.c */ 1334 #define AMDGPU_PMU_ATTR(_name, _object) \ 1335 static ssize_t \ 1336 _name##_show(struct device *dev, \ 1337 struct device_attribute *attr, \ 1338 char *page) \ 1339 { \ 1340 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1341 return sprintf(page, _object "\n"); \ 1342 } \ 1343 \ 1344 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1345 1346 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1347 { 1348 return adev->gmc.tmz_enabled; 1349 } 1350 1351 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1352 { 1353 return atomic_read(&adev->in_gpu_reset); 1354 } 1355 #endif 1356