1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <dev/wscons/wsconsio.h> 66 #include <dev/wscons/wsdisplayvar.h> 67 #include <dev/rasops/rasops.h> 68 69 #include <kgd_kfd_interface.h> 70 #include "dm_pp_interface.h" 71 #include "kgd_pp_interface.h" 72 73 #include "amd_shared.h" 74 #include "amdgpu_mode.h" 75 #include "amdgpu_ih.h" 76 #include "amdgpu_irq.h" 77 #include "amdgpu_ucode.h" 78 #include "amdgpu_ttm.h" 79 #include "amdgpu_psp.h" 80 #include "amdgpu_gds.h" 81 #include "amdgpu_sync.h" 82 #include "amdgpu_ring.h" 83 #include "amdgpu_vm.h" 84 #include "amdgpu_dpm.h" 85 #include "amdgpu_acp.h" 86 #include "amdgpu_uvd.h" 87 #include "amdgpu_vce.h" 88 #include "amdgpu_vcn.h" 89 #include "amdgpu_jpeg.h" 90 #include "amdgpu_mn.h" 91 #include "amdgpu_gmc.h" 92 #include "amdgpu_gfx.h" 93 #include "amdgpu_sdma.h" 94 #include "amdgpu_nbio.h" 95 #include "amdgpu_hdp.h" 96 #include "amdgpu_dm.h" 97 #include "amdgpu_virt.h" 98 #include "amdgpu_csa.h" 99 #include "amdgpu_gart.h" 100 #include "amdgpu_debugfs.h" 101 #include "amdgpu_job.h" 102 #include "amdgpu_bo_list.h" 103 #include "amdgpu_gem.h" 104 #include "amdgpu_doorbell.h" 105 #include "amdgpu_amdkfd.h" 106 #include "amdgpu_smu.h" 107 #include "amdgpu_discovery.h" 108 #include "amdgpu_mes.h" 109 #include "amdgpu_umc.h" 110 #include "amdgpu_mmhub.h" 111 #include "amdgpu_gfxhub.h" 112 #include "amdgpu_df.h" 113 #include "amdgpu_smuio.h" 114 #include "amdgpu_fdinfo.h" 115 #include "amdgpu_mca.h" 116 117 #define MAX_GPU_INSTANCE 16 118 119 struct amdgpu_gpu_instance 120 { 121 struct amdgpu_device *adev; 122 int mgpu_fan_enabled; 123 }; 124 125 struct amdgpu_mgpu_info 126 { 127 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 128 struct rwlock mutex; 129 uint32_t num_gpu; 130 uint32_t num_dgpu; 131 uint32_t num_apu; 132 133 /* delayed reset_func for XGMI configuration if necessary */ 134 struct delayed_work delayed_reset_work; 135 bool pending_reset; 136 }; 137 138 enum amdgpu_ss { 139 AMDGPU_SS_DRV_LOAD, 140 AMDGPU_SS_DEV_D0, 141 AMDGPU_SS_DEV_D3, 142 AMDGPU_SS_DRV_UNLOAD 143 }; 144 145 struct amdgpu_watchdog_timer 146 { 147 bool timeout_fatal_disable; 148 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 149 }; 150 151 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 152 153 /* 154 * Modules parameters. 155 */ 156 extern int amdgpu_modeset; 157 extern int amdgpu_vram_limit; 158 extern int amdgpu_vis_vram_limit; 159 extern int amdgpu_gart_size; 160 extern int amdgpu_gtt_size; 161 extern int amdgpu_moverate; 162 extern int amdgpu_benchmarking; 163 extern int amdgpu_testing; 164 extern int amdgpu_audio; 165 extern int amdgpu_disp_priority; 166 extern int amdgpu_hw_i2c; 167 extern int amdgpu_pcie_gen2; 168 extern int amdgpu_msi; 169 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 170 extern int amdgpu_dpm; 171 extern int amdgpu_fw_load_type; 172 extern int amdgpu_aspm; 173 extern int amdgpu_runtime_pm; 174 extern uint amdgpu_ip_block_mask; 175 extern int amdgpu_bapm; 176 extern int amdgpu_deep_color; 177 extern int amdgpu_vm_size; 178 extern int amdgpu_vm_block_size; 179 extern int amdgpu_vm_fragment_size; 180 extern int amdgpu_vm_fault_stop; 181 extern int amdgpu_vm_debug; 182 extern int amdgpu_vm_update_mode; 183 extern int amdgpu_exp_hw_support; 184 extern int amdgpu_dc; 185 extern int amdgpu_sched_jobs; 186 extern int amdgpu_sched_hw_submission; 187 extern uint amdgpu_pcie_gen_cap; 188 extern uint amdgpu_pcie_lane_cap; 189 extern uint amdgpu_cg_mask; 190 extern uint amdgpu_pg_mask; 191 extern uint amdgpu_sdma_phase_quantum; 192 extern char *amdgpu_disable_cu; 193 extern char *amdgpu_virtual_display; 194 extern uint amdgpu_pp_feature_mask; 195 extern uint amdgpu_force_long_training; 196 extern int amdgpu_job_hang_limit; 197 extern int amdgpu_lbpw; 198 extern int amdgpu_compute_multipipe; 199 extern int amdgpu_gpu_recovery; 200 extern int amdgpu_emu_mode; 201 extern uint amdgpu_smu_memory_pool_size; 202 extern int amdgpu_smu_pptable_id; 203 extern uint amdgpu_dc_feature_mask; 204 extern uint amdgpu_freesync_vid_mode; 205 extern uint amdgpu_dc_debug_mask; 206 extern uint amdgpu_dm_abm_level; 207 extern int amdgpu_backlight; 208 extern struct amdgpu_mgpu_info mgpu_info; 209 extern int amdgpu_ras_enable; 210 extern uint amdgpu_ras_mask; 211 extern int amdgpu_bad_page_threshold; 212 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 213 extern int amdgpu_async_gfx_ring; 214 extern int amdgpu_mcbp; 215 extern int amdgpu_discovery; 216 extern int amdgpu_mes; 217 extern int amdgpu_noretry; 218 extern int amdgpu_force_asic_type; 219 extern int amdgpu_smartshift_bias; 220 #ifdef CONFIG_HSA_AMD 221 extern int sched_policy; 222 extern bool debug_evictions; 223 extern bool no_system_mem_limit; 224 #else 225 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 226 static const bool __maybe_unused debug_evictions; /* = false */ 227 static const bool __maybe_unused no_system_mem_limit; 228 #endif 229 230 extern int amdgpu_tmz; 231 extern int amdgpu_reset_method; 232 233 #ifdef CONFIG_DRM_AMDGPU_SI 234 extern int amdgpu_si_support; 235 #endif 236 #ifdef CONFIG_DRM_AMDGPU_CIK 237 extern int amdgpu_cik_support; 238 #endif 239 extern int amdgpu_num_kcq; 240 241 #define AMDGPU_VM_MAX_NUM_CTX 4096 242 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 243 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 244 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 245 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 246 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 247 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 248 #define AMDGPUFB_CONN_LIMIT 4 249 #define AMDGPU_BIOS_NUM_SCRATCH 16 250 251 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 252 253 /* hard reset data */ 254 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 255 256 /* reset flags */ 257 #define AMDGPU_RESET_GFX (1 << 0) 258 #define AMDGPU_RESET_COMPUTE (1 << 1) 259 #define AMDGPU_RESET_DMA (1 << 2) 260 #define AMDGPU_RESET_CP (1 << 3) 261 #define AMDGPU_RESET_GRBM (1 << 4) 262 #define AMDGPU_RESET_DMA1 (1 << 5) 263 #define AMDGPU_RESET_RLC (1 << 6) 264 #define AMDGPU_RESET_SEM (1 << 7) 265 #define AMDGPU_RESET_IH (1 << 8) 266 #define AMDGPU_RESET_VMC (1 << 9) 267 #define AMDGPU_RESET_MC (1 << 10) 268 #define AMDGPU_RESET_DISPLAY (1 << 11) 269 #define AMDGPU_RESET_UVD (1 << 12) 270 #define AMDGPU_RESET_VCE (1 << 13) 271 #define AMDGPU_RESET_VCE1 (1 << 14) 272 273 /* max cursor sizes (in pixels) */ 274 #define CIK_CURSOR_WIDTH 128 275 #define CIK_CURSOR_HEIGHT 128 276 277 /* smasrt shift bias level limits */ 278 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 279 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 280 281 struct amdgpu_device; 282 struct amdgpu_ib; 283 struct amdgpu_cs_parser; 284 struct amdgpu_job; 285 struct amdgpu_irq_src; 286 struct amdgpu_fpriv; 287 struct amdgpu_bo_va_mapping; 288 struct kfd_vm_fault_info; 289 struct amdgpu_hive_info; 290 struct amdgpu_reset_context; 291 struct amdgpu_reset_control; 292 293 enum amdgpu_cp_irq { 294 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 295 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 296 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 297 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 298 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 299 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 300 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 301 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 302 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 303 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 304 305 AMDGPU_CP_IRQ_LAST 306 }; 307 308 enum amdgpu_thermal_irq { 309 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 310 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 311 312 AMDGPU_THERMAL_IRQ_LAST 313 }; 314 315 enum amdgpu_kiq_irq { 316 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 317 AMDGPU_CP_KIQ_IRQ_LAST 318 }; 319 320 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 321 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 322 #define MAX_KIQ_REG_TRY 1000 323 324 int amdgpu_device_ip_set_clockgating_state(void *dev, 325 enum amd_ip_block_type block_type, 326 enum amd_clockgating_state state); 327 int amdgpu_device_ip_set_powergating_state(void *dev, 328 enum amd_ip_block_type block_type, 329 enum amd_powergating_state state); 330 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 331 u32 *flags); 332 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 333 enum amd_ip_block_type block_type); 334 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 335 enum amd_ip_block_type block_type); 336 337 #define AMDGPU_MAX_IP_NUM 16 338 339 struct amdgpu_ip_block_status { 340 bool valid; 341 bool sw; 342 bool hw; 343 bool late_initialized; 344 bool hang; 345 }; 346 347 struct amdgpu_ip_block_version { 348 const enum amd_ip_block_type type; 349 const u32 major; 350 const u32 minor; 351 const u32 rev; 352 const struct amd_ip_funcs *funcs; 353 }; 354 355 #define HW_REV(_Major, _Minor, _Rev) \ 356 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 357 358 struct amdgpu_ip_block { 359 struct amdgpu_ip_block_status status; 360 const struct amdgpu_ip_block_version *version; 361 }; 362 363 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 364 enum amd_ip_block_type type, 365 u32 major, u32 minor); 366 367 struct amdgpu_ip_block * 368 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 369 enum amd_ip_block_type type); 370 371 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 372 const struct amdgpu_ip_block_version *ip_block_version); 373 374 /* 375 * BIOS. 376 */ 377 bool amdgpu_get_bios(struct amdgpu_device *adev); 378 bool amdgpu_read_bios(struct amdgpu_device *adev); 379 380 /* 381 * Clocks 382 */ 383 384 #define AMDGPU_MAX_PPLL 3 385 386 struct amdgpu_clock { 387 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 388 struct amdgpu_pll spll; 389 struct amdgpu_pll mpll; 390 /* 10 Khz units */ 391 uint32_t default_mclk; 392 uint32_t default_sclk; 393 uint32_t default_dispclk; 394 uint32_t current_dispclk; 395 uint32_t dp_extclk; 396 uint32_t max_pixel_clock; 397 }; 398 399 /* sub-allocation manager, it has to be protected by another lock. 400 * By conception this is an helper for other part of the driver 401 * like the indirect buffer or semaphore, which both have their 402 * locking. 403 * 404 * Principe is simple, we keep a list of sub allocation in offset 405 * order (first entry has offset == 0, last entry has the highest 406 * offset). 407 * 408 * When allocating new object we first check if there is room at 409 * the end total_size - (last_object_offset + last_object_size) >= 410 * alloc_size. If so we allocate new object there. 411 * 412 * When there is not enough room at the end, we start waiting for 413 * each sub object until we reach object_offset+object_size >= 414 * alloc_size, this object then become the sub object we return. 415 * 416 * Alignment can't be bigger than page size. 417 * 418 * Hole are not considered for allocation to keep things simple. 419 * Assumption is that there won't be hole (all object on same 420 * alignment). 421 */ 422 423 #define AMDGPU_SA_NUM_FENCE_LISTS 32 424 425 struct amdgpu_sa_manager { 426 wait_queue_head_t wq; 427 struct amdgpu_bo *bo; 428 struct list_head *hole; 429 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 430 struct list_head olist; 431 unsigned size; 432 uint64_t gpu_addr; 433 void *cpu_ptr; 434 uint32_t domain; 435 uint32_t align; 436 }; 437 438 /* sub-allocation buffer */ 439 struct amdgpu_sa_bo { 440 struct list_head olist; 441 struct list_head flist; 442 struct amdgpu_sa_manager *manager; 443 unsigned soffset; 444 unsigned eoffset; 445 struct dma_fence *fence; 446 }; 447 448 int amdgpu_fence_slab_init(void); 449 void amdgpu_fence_slab_fini(void); 450 451 /* 452 * IRQS. 453 */ 454 455 struct amdgpu_flip_work { 456 struct delayed_work flip_work; 457 struct work_struct unpin_work; 458 struct amdgpu_device *adev; 459 int crtc_id; 460 u32 target_vblank; 461 uint64_t base; 462 struct drm_pending_vblank_event *event; 463 struct amdgpu_bo *old_abo; 464 struct dma_fence *excl; 465 unsigned shared_count; 466 struct dma_fence **shared; 467 struct dma_fence_cb cb; 468 bool async; 469 }; 470 471 472 /* 473 * CP & rings. 474 */ 475 476 struct amdgpu_ib { 477 struct amdgpu_sa_bo *sa_bo; 478 uint32_t length_dw; 479 uint64_t gpu_addr; 480 uint32_t *ptr; 481 uint32_t flags; 482 }; 483 484 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 485 486 /* 487 * file private structure 488 */ 489 490 struct amdgpu_fpriv { 491 struct amdgpu_vm vm; 492 struct amdgpu_bo_va *prt_va; 493 struct amdgpu_bo_va *csa_va; 494 struct rwlock bo_list_lock; 495 struct idr bo_list_handles; 496 struct amdgpu_ctx_mgr ctx_mgr; 497 }; 498 499 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 500 501 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 502 unsigned size, 503 enum amdgpu_ib_pool_type pool, 504 struct amdgpu_ib *ib); 505 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 506 struct dma_fence *f); 507 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 508 struct amdgpu_ib *ibs, struct amdgpu_job *job, 509 struct dma_fence **f); 510 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 511 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 512 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 513 514 /* 515 * CS. 516 */ 517 struct amdgpu_cs_chunk { 518 uint32_t chunk_id; 519 uint32_t length_dw; 520 void *kdata; 521 }; 522 523 struct amdgpu_cs_post_dep { 524 struct drm_syncobj *syncobj; 525 struct dma_fence_chain *chain; 526 u64 point; 527 }; 528 529 struct amdgpu_cs_parser { 530 struct amdgpu_device *adev; 531 struct drm_file *filp; 532 struct amdgpu_ctx *ctx; 533 534 /* chunks */ 535 unsigned nchunks; 536 struct amdgpu_cs_chunk *chunks; 537 538 /* scheduler job object */ 539 struct amdgpu_job *job; 540 struct drm_sched_entity *entity; 541 542 /* buffer objects */ 543 struct ww_acquire_ctx ticket; 544 struct amdgpu_bo_list *bo_list; 545 struct amdgpu_mn *mn; 546 struct amdgpu_bo_list_entry vm_pd; 547 struct list_head validated; 548 struct dma_fence *fence; 549 uint64_t bytes_moved_threshold; 550 uint64_t bytes_moved_vis_threshold; 551 uint64_t bytes_moved; 552 uint64_t bytes_moved_vis; 553 554 /* user fence */ 555 struct amdgpu_bo_list_entry uf_entry; 556 557 unsigned num_post_deps; 558 struct amdgpu_cs_post_dep *post_deps; 559 }; 560 561 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 562 uint32_t ib_idx, int idx) 563 { 564 return p->job->ibs[ib_idx].ptr[idx]; 565 } 566 567 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 568 uint32_t ib_idx, int idx, 569 uint32_t value) 570 { 571 p->job->ibs[ib_idx].ptr[idx] = value; 572 } 573 574 /* 575 * Writeback 576 */ 577 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 578 579 struct amdgpu_wb { 580 struct amdgpu_bo *wb_obj; 581 volatile uint32_t *wb; 582 uint64_t gpu_addr; 583 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 584 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 585 }; 586 587 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 588 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 589 590 /* 591 * Benchmarking 592 */ 593 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 594 595 596 /* 597 * Testing 598 */ 599 void amdgpu_test_moves(struct amdgpu_device *adev); 600 601 /* 602 * ASIC specific register table accessible by UMD 603 */ 604 struct amdgpu_allowed_register_entry { 605 uint32_t reg_offset; 606 bool grbm_indexed; 607 }; 608 609 enum amd_reset_method { 610 AMD_RESET_METHOD_NONE = -1, 611 AMD_RESET_METHOD_LEGACY = 0, 612 AMD_RESET_METHOD_MODE0, 613 AMD_RESET_METHOD_MODE1, 614 AMD_RESET_METHOD_MODE2, 615 AMD_RESET_METHOD_BACO, 616 AMD_RESET_METHOD_PCI, 617 }; 618 619 struct amdgpu_video_codec_info { 620 u32 codec_type; 621 u32 max_width; 622 u32 max_height; 623 u32 max_pixels_per_frame; 624 u32 max_level; 625 }; 626 627 #define codec_info_build(type, width, height, level) \ 628 .codec_type = type,\ 629 .max_width = width,\ 630 .max_height = height,\ 631 .max_pixels_per_frame = height * width,\ 632 .max_level = level, 633 634 struct amdgpu_video_codecs { 635 const u32 codec_count; 636 const struct amdgpu_video_codec_info *codec_array; 637 }; 638 639 /* 640 * ASIC specific functions. 641 */ 642 struct amdgpu_asic_funcs { 643 bool (*read_disabled_bios)(struct amdgpu_device *adev); 644 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 645 u8 *bios, u32 length_bytes); 646 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 647 u32 sh_num, u32 reg_offset, u32 *value); 648 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 649 int (*reset)(struct amdgpu_device *adev); 650 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 651 /* get the reference clock */ 652 u32 (*get_xclk)(struct amdgpu_device *adev); 653 /* MM block clocks */ 654 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 655 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 656 /* static power management */ 657 int (*get_pcie_lanes)(struct amdgpu_device *adev); 658 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 659 /* get config memsize register */ 660 u32 (*get_config_memsize)(struct amdgpu_device *adev); 661 /* flush hdp write queue */ 662 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 663 /* invalidate hdp read cache */ 664 void (*invalidate_hdp)(struct amdgpu_device *adev, 665 struct amdgpu_ring *ring); 666 /* check if the asic needs a full reset of if soft reset will work */ 667 bool (*need_full_reset)(struct amdgpu_device *adev); 668 /* initialize doorbell layout for specific asic*/ 669 void (*init_doorbell_index)(struct amdgpu_device *adev); 670 /* PCIe bandwidth usage */ 671 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 672 uint64_t *count1); 673 /* do we need to reset the asic at init time (e.g., kexec) */ 674 bool (*need_reset_on_init)(struct amdgpu_device *adev); 675 /* PCIe replay counter */ 676 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 677 /* device supports BACO */ 678 bool (*supports_baco)(struct amdgpu_device *adev); 679 /* pre asic_init quirks */ 680 void (*pre_asic_init)(struct amdgpu_device *adev); 681 /* enter/exit umd stable pstate */ 682 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 683 /* query video codecs */ 684 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 685 const struct amdgpu_video_codecs **codecs); 686 }; 687 688 /* 689 * IOCTL. 690 */ 691 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 692 struct drm_file *filp); 693 694 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 695 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 696 struct drm_file *filp); 697 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 698 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 699 struct drm_file *filp); 700 701 /* VRAM scratch page for HDP bug, default vram page */ 702 struct amdgpu_vram_scratch { 703 struct amdgpu_bo *robj; 704 volatile uint32_t *ptr; 705 u64 gpu_addr; 706 }; 707 708 /* 709 * CGS 710 */ 711 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 712 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 713 714 /* 715 * Core structure, functions and helpers. 716 */ 717 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 718 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 719 720 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 721 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 722 723 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 724 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 725 726 struct amdgpu_mmio_remap { 727 u32 reg_offset; 728 resource_size_t bus_addr; 729 }; 730 731 /* Define the HW IP blocks will be used in driver , add more if necessary */ 732 enum amd_hw_ip_block_type { 733 GC_HWIP = 1, 734 HDP_HWIP, 735 SDMA0_HWIP, 736 SDMA1_HWIP, 737 SDMA2_HWIP, 738 SDMA3_HWIP, 739 SDMA4_HWIP, 740 SDMA5_HWIP, 741 SDMA6_HWIP, 742 SDMA7_HWIP, 743 MMHUB_HWIP, 744 ATHUB_HWIP, 745 NBIO_HWIP, 746 MP0_HWIP, 747 MP1_HWIP, 748 UVD_HWIP, 749 VCN_HWIP = UVD_HWIP, 750 JPEG_HWIP = VCN_HWIP, 751 VCE_HWIP, 752 DF_HWIP, 753 DCE_HWIP, 754 OSSSYS_HWIP, 755 SMUIO_HWIP, 756 PWR_HWIP, 757 NBIF_HWIP, 758 THM_HWIP, 759 CLK_HWIP, 760 UMC_HWIP, 761 RSMU_HWIP, 762 MAX_HWIP 763 }; 764 765 #define HWIP_MAX_INSTANCE 10 766 767 struct amd_powerplay { 768 void *pp_handle; 769 const struct amd_pm_funcs *pp_funcs; 770 }; 771 772 /* polaris10 kickers */ 773 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 774 ((rid == 0xE3) || \ 775 (rid == 0xE4) || \ 776 (rid == 0xE5) || \ 777 (rid == 0xE7) || \ 778 (rid == 0xEF))) || \ 779 ((did == 0x6FDF) && \ 780 ((rid == 0xE7) || \ 781 (rid == 0xEF) || \ 782 (rid == 0xFF)))) 783 784 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 785 ((rid == 0xE1) || \ 786 (rid == 0xF7))) 787 788 /* polaris11 kickers */ 789 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 790 ((rid == 0xE0) || \ 791 (rid == 0xE5))) || \ 792 ((did == 0x67FF) && \ 793 ((rid == 0xCF) || \ 794 (rid == 0xEF) || \ 795 (rid == 0xFF)))) 796 797 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 798 ((rid == 0xE2))) 799 800 /* polaris12 kickers */ 801 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 802 ((rid == 0xC0) || \ 803 (rid == 0xC1) || \ 804 (rid == 0xC3) || \ 805 (rid == 0xC7))) || \ 806 ((did == 0x6981) && \ 807 ((rid == 0x00) || \ 808 (rid == 0x01) || \ 809 (rid == 0x10)))) 810 811 #define AMDGPU_RESET_MAGIC_NUM 64 812 #define AMDGPU_MAX_DF_PERFMONS 4 813 struct amdgpu_device { 814 struct device self; 815 struct device *dev; 816 struct pci_dev *pdev; 817 struct drm_device ddev; 818 819 pci_chipset_tag_t pc; 820 pcitag_t pa_tag; 821 pci_intr_handle_t intrh; 822 bus_space_tag_t iot; 823 bus_space_tag_t memt; 824 bus_dma_tag_t dmat; 825 void *irqh; 826 827 void (*switchcb)(void *, int, int); 828 void *switchcbarg; 829 void *switchcookie; 830 struct task switchtask; 831 struct rasops_info ro; 832 int console; 833 int primary; 834 835 struct task burner_task; 836 int burner_fblank; 837 838 unsigned long fb_aper_offset; 839 unsigned long fb_aper_size; 840 841 #ifdef CONFIG_DRM_AMD_ACP 842 struct amdgpu_acp acp; 843 #endif 844 struct amdgpu_hive_info *hive; 845 /* ASIC */ 846 enum amd_asic_type asic_type; 847 uint32_t family; 848 uint32_t rev_id; 849 uint32_t external_rev_id; 850 unsigned long flags; 851 unsigned long apu_flags; 852 int usec_timeout; 853 const struct amdgpu_asic_funcs *asic_funcs; 854 bool shutdown; 855 bool need_swiotlb; 856 bool accel_working; 857 struct notifier_block acpi_nb; 858 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 859 #ifdef notyet 860 struct debugfs_blob_wrapper debugfs_vbios_blob; 861 #endif 862 struct rwlock srbm_mutex; 863 /* GRBM index mutex. Protects concurrent access to GRBM index */ 864 struct rwlock grbm_idx_mutex; 865 struct dev_pm_domain vga_pm_domain; 866 bool have_disp_power_ref; 867 bool have_atomics_support; 868 869 /* BIOS */ 870 bool is_atom_fw; 871 uint8_t *bios; 872 uint32_t bios_size; 873 uint32_t bios_scratch_reg_offset; 874 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 875 876 /* Register/doorbell mmio */ 877 resource_size_t rmmio_base; 878 resource_size_t rmmio_size; 879 void __iomem *rmmio; 880 bus_space_tag_t rmmio_bst; 881 bus_space_handle_t rmmio_bsh; 882 /* protects concurrent MM_INDEX/DATA based register access */ 883 spinlock_t mmio_idx_lock; 884 struct amdgpu_mmio_remap rmmio_remap; 885 /* protects concurrent SMC based register access */ 886 spinlock_t smc_idx_lock; 887 amdgpu_rreg_t smc_rreg; 888 amdgpu_wreg_t smc_wreg; 889 /* protects concurrent PCIE register access */ 890 spinlock_t pcie_idx_lock; 891 amdgpu_rreg_t pcie_rreg; 892 amdgpu_wreg_t pcie_wreg; 893 amdgpu_rreg_t pciep_rreg; 894 amdgpu_wreg_t pciep_wreg; 895 amdgpu_rreg64_t pcie_rreg64; 896 amdgpu_wreg64_t pcie_wreg64; 897 /* protects concurrent UVD register access */ 898 spinlock_t uvd_ctx_idx_lock; 899 amdgpu_rreg_t uvd_ctx_rreg; 900 amdgpu_wreg_t uvd_ctx_wreg; 901 /* protects concurrent DIDT register access */ 902 spinlock_t didt_idx_lock; 903 amdgpu_rreg_t didt_rreg; 904 amdgpu_wreg_t didt_wreg; 905 /* protects concurrent gc_cac register access */ 906 spinlock_t gc_cac_idx_lock; 907 amdgpu_rreg_t gc_cac_rreg; 908 amdgpu_wreg_t gc_cac_wreg; 909 /* protects concurrent se_cac register access */ 910 spinlock_t se_cac_idx_lock; 911 amdgpu_rreg_t se_cac_rreg; 912 amdgpu_wreg_t se_cac_wreg; 913 /* protects concurrent ENDPOINT (audio) register access */ 914 spinlock_t audio_endpt_idx_lock; 915 amdgpu_block_rreg_t audio_endpt_rreg; 916 amdgpu_block_wreg_t audio_endpt_wreg; 917 struct amdgpu_doorbell doorbell; 918 919 /* clock/pll info */ 920 struct amdgpu_clock clock; 921 922 /* MC */ 923 struct amdgpu_gmc gmc; 924 struct amdgpu_gart gart; 925 dma_addr_t dummy_page_addr; 926 struct amdgpu_vm_manager vm_manager; 927 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 928 unsigned num_vmhubs; 929 930 /* memory management */ 931 struct amdgpu_mman mman; 932 struct amdgpu_vram_scratch vram_scratch; 933 struct amdgpu_wb wb; 934 atomic64_t num_bytes_moved; 935 atomic64_t num_evictions; 936 atomic64_t num_vram_cpu_page_faults; 937 atomic_t gpu_reset_counter; 938 atomic_t vram_lost_counter; 939 940 /* data for buffer migration throttling */ 941 struct { 942 spinlock_t lock; 943 s64 last_update_us; 944 s64 accum_us; /* accumulated microseconds */ 945 s64 accum_us_vis; /* for visible VRAM */ 946 u32 log2_max_MBps; 947 } mm_stats; 948 949 /* display */ 950 bool enable_virtual_display; 951 struct amdgpu_vkms_output *amdgpu_vkms_output; 952 struct amdgpu_mode_info mode_info; 953 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 954 struct work_struct hotplug_work; 955 struct amdgpu_irq_src crtc_irq; 956 struct amdgpu_irq_src vline0_irq; 957 struct amdgpu_irq_src vupdate_irq; 958 struct amdgpu_irq_src pageflip_irq; 959 struct amdgpu_irq_src hpd_irq; 960 struct amdgpu_irq_src dmub_trace_irq; 961 struct amdgpu_irq_src dmub_outbox_irq; 962 963 /* rings */ 964 u64 fence_context; 965 unsigned num_rings; 966 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 967 bool ib_pool_ready; 968 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 969 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 970 971 /* interrupts */ 972 struct amdgpu_irq irq; 973 974 /* powerplay */ 975 struct amd_powerplay powerplay; 976 bool pp_force_state_enabled; 977 978 /* smu */ 979 struct smu_context smu; 980 981 /* dpm */ 982 struct amdgpu_pm pm; 983 u32 cg_flags; 984 u32 pg_flags; 985 986 /* nbio */ 987 struct amdgpu_nbio nbio; 988 989 /* hdp */ 990 struct amdgpu_hdp hdp; 991 992 /* smuio */ 993 struct amdgpu_smuio smuio; 994 995 /* mmhub */ 996 struct amdgpu_mmhub mmhub; 997 998 /* gfxhub */ 999 struct amdgpu_gfxhub gfxhub; 1000 1001 /* gfx */ 1002 struct amdgpu_gfx gfx; 1003 1004 /* sdma */ 1005 struct amdgpu_sdma sdma; 1006 1007 /* uvd */ 1008 struct amdgpu_uvd uvd; 1009 1010 /* vce */ 1011 struct amdgpu_vce vce; 1012 1013 /* vcn */ 1014 struct amdgpu_vcn vcn; 1015 1016 /* jpeg */ 1017 struct amdgpu_jpeg jpeg; 1018 1019 /* firmwares */ 1020 struct amdgpu_firmware firmware; 1021 1022 /* PSP */ 1023 struct psp_context psp; 1024 1025 /* GDS */ 1026 struct amdgpu_gds gds; 1027 1028 /* KFD */ 1029 struct amdgpu_kfd_dev kfd; 1030 1031 /* UMC */ 1032 struct amdgpu_umc umc; 1033 1034 /* display related functionality */ 1035 struct amdgpu_display_manager dm; 1036 1037 /* mes */ 1038 bool enable_mes; 1039 struct amdgpu_mes mes; 1040 1041 /* df */ 1042 struct amdgpu_df df; 1043 1044 /* MCA */ 1045 struct amdgpu_mca mca; 1046 1047 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1048 uint32_t harvest_ip_mask; 1049 int num_ip_blocks; 1050 struct rwlock mn_lock; 1051 DECLARE_HASHTABLE(mn_hash, 7); 1052 1053 /* tracking pinned memory */ 1054 atomic64_t vram_pin_size; 1055 atomic64_t visible_pin_size; 1056 atomic64_t gart_pin_size; 1057 1058 /* soc15 register offset based on ip, instance and segment */ 1059 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1060 1061 /* delayed work_func for deferring clockgating during resume */ 1062 struct delayed_work delayed_init_work; 1063 1064 struct amdgpu_virt virt; 1065 1066 /* link all shadow bo */ 1067 struct list_head shadow_list; 1068 struct rwlock shadow_list_lock; 1069 1070 /* record hw reset is performed */ 1071 bool has_hw_reset; 1072 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1073 1074 /* s3/s4 mask */ 1075 bool in_suspend; 1076 bool in_s3; 1077 bool in_s4; 1078 bool in_s0ix; 1079 1080 atomic_t in_gpu_reset; 1081 enum pp_mp1_state mp1_state; 1082 struct rwlock reset_sem; 1083 struct amdgpu_doorbell_index doorbell_index; 1084 1085 struct rwlock notifier_lock; 1086 1087 int asic_reset_res; 1088 struct work_struct xgmi_reset_work; 1089 struct list_head reset_list; 1090 1091 long gfx_timeout; 1092 long sdma_timeout; 1093 long video_timeout; 1094 long compute_timeout; 1095 1096 uint64_t unique_id; 1097 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1098 1099 /* enable runtime pm on the device */ 1100 bool runpm; 1101 bool in_runpm; 1102 bool has_pr3; 1103 bool is_fw_fb; 1104 1105 bool pm_sysfs_en; 1106 bool ucode_sysfs_en; 1107 1108 /* Chip product information */ 1109 char product_number[16]; 1110 char product_name[32]; 1111 char serial[20]; 1112 1113 atomic_t throttling_logging_enabled; 1114 struct ratelimit_state throttling_logging_rs; 1115 uint32_t ras_hw_enabled; 1116 uint32_t ras_enabled; 1117 1118 bool no_hw_access; 1119 struct pci_saved_state *pci_state; 1120 pci_channel_state_t pci_channel_state; 1121 1122 struct amdgpu_reset_control *reset_cntl; 1123 }; 1124 1125 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1126 { 1127 return container_of(ddev, struct amdgpu_device, ddev); 1128 } 1129 1130 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1131 { 1132 return &adev->ddev; 1133 } 1134 1135 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1136 { 1137 return container_of(bdev, struct amdgpu_device, mman.bdev); 1138 } 1139 1140 int amdgpu_device_init(struct amdgpu_device *adev, 1141 uint32_t flags); 1142 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1143 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1144 1145 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1146 1147 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1148 void *buf, size_t size, bool write); 1149 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1150 void *buf, size_t size, bool write); 1151 1152 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1153 void *buf, size_t size, bool write); 1154 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1155 uint32_t reg, uint32_t acc_flags); 1156 void amdgpu_device_wreg(struct amdgpu_device *adev, 1157 uint32_t reg, uint32_t v, 1158 uint32_t acc_flags); 1159 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1160 uint32_t reg, uint32_t v); 1161 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1162 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1163 1164 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1165 u32 pcie_index, u32 pcie_data, 1166 u32 reg_addr); 1167 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1168 u32 pcie_index, u32 pcie_data, 1169 u32 reg_addr); 1170 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1171 u32 pcie_index, u32 pcie_data, 1172 u32 reg_addr, u32 reg_data); 1173 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1174 u32 pcie_index, u32 pcie_data, 1175 u32 reg_addr, u64 reg_data); 1176 1177 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1178 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1179 1180 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1181 struct amdgpu_reset_context *reset_context); 1182 1183 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1184 struct amdgpu_reset_context *reset_context); 1185 1186 int emu_soc_asic_init(struct amdgpu_device *adev); 1187 1188 /* 1189 * Registers read & write functions. 1190 */ 1191 #define AMDGPU_REGS_NO_KIQ (1<<1) 1192 #define AMDGPU_REGS_RLC (1<<2) 1193 1194 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1195 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1196 1197 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1198 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1199 1200 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1201 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1202 1203 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1204 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1205 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1206 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1207 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1208 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1209 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1210 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1211 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1212 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1213 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1214 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1215 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1216 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1217 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1218 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1219 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1220 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1221 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1222 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1223 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1224 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1225 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1226 #define WREG32_P(reg, val, mask) \ 1227 do { \ 1228 uint32_t tmp_ = RREG32(reg); \ 1229 tmp_ &= (mask); \ 1230 tmp_ |= ((val) & ~(mask)); \ 1231 WREG32(reg, tmp_); \ 1232 } while (0) 1233 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1234 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1235 #define WREG32_PLL_P(reg, val, mask) \ 1236 do { \ 1237 uint32_t tmp_ = RREG32_PLL(reg); \ 1238 tmp_ &= (mask); \ 1239 tmp_ |= ((val) & ~(mask)); \ 1240 WREG32_PLL(reg, tmp_); \ 1241 } while (0) 1242 1243 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1244 do { \ 1245 u32 tmp = RREG32_SMC(_Reg); \ 1246 tmp &= (_Mask); \ 1247 tmp |= ((_Val) & ~(_Mask)); \ 1248 WREG32_SMC(_Reg, tmp); \ 1249 } while (0) 1250 1251 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1252 1253 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1254 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1255 1256 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1257 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1258 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1259 1260 #define REG_GET_FIELD(value, reg, field) \ 1261 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1262 1263 #define WREG32_FIELD(reg, field, val) \ 1264 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1265 1266 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1267 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1268 1269 /* 1270 * BIOS helpers. 1271 */ 1272 #define RBIOS8(i) (adev->bios[i]) 1273 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1274 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1275 1276 /* 1277 * ASICs macro. 1278 */ 1279 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1280 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1281 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1282 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1283 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1284 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1285 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1286 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1287 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1288 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1289 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1290 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1291 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1292 #define amdgpu_asic_flush_hdp(adev, r) \ 1293 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1294 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1295 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1296 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1297 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1298 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1299 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1300 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1301 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1302 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1303 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1304 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1305 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1306 1307 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1308 1309 /* Common functions */ 1310 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1311 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1312 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1313 struct amdgpu_job* job); 1314 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1315 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1316 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1317 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1318 1319 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1320 u64 num_vis_bytes); 1321 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1322 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1323 const u32 *registers, 1324 const u32 array_size); 1325 1326 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1327 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1328 bool amdgpu_device_supports_px(struct drm_device *dev); 1329 bool amdgpu_device_supports_boco(struct drm_device *dev); 1330 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1331 bool amdgpu_device_supports_baco(struct drm_device *dev); 1332 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1333 struct amdgpu_device *peer_adev); 1334 int amdgpu_device_baco_enter(struct drm_device *dev); 1335 int amdgpu_device_baco_exit(struct drm_device *dev); 1336 1337 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1338 struct amdgpu_ring *ring); 1339 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1340 struct amdgpu_ring *ring); 1341 1342 /* atpx handler */ 1343 #if defined(CONFIG_VGA_SWITCHEROO) 1344 void amdgpu_register_atpx_handler(void); 1345 void amdgpu_unregister_atpx_handler(void); 1346 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1347 bool amdgpu_is_atpx_hybrid(void); 1348 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1349 bool amdgpu_has_atpx(void); 1350 #else 1351 static inline void amdgpu_register_atpx_handler(void) {} 1352 static inline void amdgpu_unregister_atpx_handler(void) {} 1353 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1354 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1355 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1356 static inline bool amdgpu_has_atpx(void) { return false; } 1357 #endif 1358 1359 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1360 void *amdgpu_atpx_get_dhandle(void); 1361 #else 1362 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1363 #endif 1364 1365 /* 1366 * KMS 1367 */ 1368 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1369 extern const int amdgpu_max_kms_ioctl; 1370 1371 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1372 void amdgpu_driver_unload_kms(struct drm_device *dev); 1373 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1374 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1375 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1376 struct drm_file *file_priv); 1377 void amdgpu_driver_release_kms(struct drm_device *dev); 1378 1379 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1380 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1381 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1382 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1383 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1384 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1385 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1386 unsigned long arg); 1387 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1388 struct drm_file *filp); 1389 1390 /* 1391 * functions used by amdgpu_encoder.c 1392 */ 1393 struct amdgpu_afmt_acr { 1394 u32 clock; 1395 1396 int n_32khz; 1397 int cts_32khz; 1398 1399 int n_44_1khz; 1400 int cts_44_1khz; 1401 1402 int n_48khz; 1403 int cts_48khz; 1404 1405 }; 1406 1407 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1408 1409 /* amdgpu_acpi.c */ 1410 1411 /* ATCS Device/Driver State */ 1412 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1413 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1414 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1415 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1416 1417 #if defined(CONFIG_ACPI) 1418 int amdgpu_acpi_init(struct amdgpu_device *adev); 1419 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1420 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1421 bool amdgpu_acpi_is_power_shift_control_supported(void); 1422 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1423 u8 perf_req, bool advertise); 1424 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1425 u8 dev_state, bool drv_state); 1426 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1427 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1428 1429 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1430 void amdgpu_acpi_detect(void); 1431 #else 1432 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1433 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1434 static inline void amdgpu_acpi_detect(void) { } 1435 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1436 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1437 u8 dev_state, bool drv_state) { return 0; } 1438 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1439 enum amdgpu_ss ss_state) { return 0; } 1440 #endif 1441 1442 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1443 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1444 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1445 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1446 #else 1447 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1448 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1449 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1450 #endif 1451 1452 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1453 uint64_t addr, struct amdgpu_bo **bo, 1454 struct amdgpu_bo_va_mapping **mapping); 1455 1456 #if defined(CONFIG_DRM_AMD_DC) 1457 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1458 #else 1459 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1460 #endif 1461 1462 1463 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1464 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1465 1466 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1467 pci_channel_state_t state); 1468 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1469 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1470 void amdgpu_pci_resume(struct pci_dev *pdev); 1471 1472 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1473 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1474 1475 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1476 1477 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1478 enum amd_clockgating_state state); 1479 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1480 enum amd_powergating_state state); 1481 1482 #include "amdgpu_object.h" 1483 1484 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1485 { 1486 return adev->gmc.tmz_enabled; 1487 } 1488 1489 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1490 { 1491 return atomic_read(&adev->in_gpu_reset); 1492 } 1493 #endif 1494