1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 64 #include <dev/wscons/wsconsio.h> 65 #include <dev/wscons/wsdisplayvar.h> 66 #include <dev/rasops/rasops.h> 67 68 #include <kgd_kfd_interface.h> 69 #include "dm_pp_interface.h" 70 #include "kgd_pp_interface.h" 71 72 #include "amd_shared.h" 73 #include "amdgpu_mode.h" 74 #include "amdgpu_ih.h" 75 #include "amdgpu_irq.h" 76 #include "amdgpu_ucode.h" 77 #include "amdgpu_ttm.h" 78 #include "amdgpu_psp.h" 79 #include "amdgpu_gds.h" 80 #include "amdgpu_sync.h" 81 #include "amdgpu_ring.h" 82 #include "amdgpu_vm.h" 83 #include "amdgpu_dpm.h" 84 #include "amdgpu_acp.h" 85 #include "amdgpu_uvd.h" 86 #include "amdgpu_vce.h" 87 #include "amdgpu_vcn.h" 88 #include "amdgpu_jpeg.h" 89 #include "amdgpu_mn.h" 90 #include "amdgpu_gmc.h" 91 #include "amdgpu_gfx.h" 92 #include "amdgpu_sdma.h" 93 #include "amdgpu_lsdma.h" 94 #include "amdgpu_nbio.h" 95 #include "amdgpu_hdp.h" 96 #include "amdgpu_dm.h" 97 #include "amdgpu_virt.h" 98 #include "amdgpu_csa.h" 99 #include "amdgpu_mes_ctx.h" 100 #include "amdgpu_gart.h" 101 #include "amdgpu_debugfs.h" 102 #include "amdgpu_job.h" 103 #include "amdgpu_bo_list.h" 104 #include "amdgpu_gem.h" 105 #include "amdgpu_doorbell.h" 106 #include "amdgpu_amdkfd.h" 107 #include "amdgpu_discovery.h" 108 #include "amdgpu_mes.h" 109 #include "amdgpu_umc.h" 110 #include "amdgpu_mmhub.h" 111 #include "amdgpu_gfxhub.h" 112 #include "amdgpu_df.h" 113 #include "amdgpu_smuio.h" 114 #include "amdgpu_fdinfo.h" 115 #include "amdgpu_mca.h" 116 #include "amdgpu_ras.h" 117 118 #define MAX_GPU_INSTANCE 16 119 120 struct amdgpu_gpu_instance 121 { 122 struct amdgpu_device *adev; 123 int mgpu_fan_enabled; 124 }; 125 126 struct amdgpu_mgpu_info 127 { 128 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 129 struct rwlock mutex; 130 uint32_t num_gpu; 131 uint32_t num_dgpu; 132 uint32_t num_apu; 133 134 /* delayed reset_func for XGMI configuration if necessary */ 135 struct delayed_work delayed_reset_work; 136 bool pending_reset; 137 }; 138 139 enum amdgpu_ss { 140 AMDGPU_SS_DRV_LOAD, 141 AMDGPU_SS_DEV_D0, 142 AMDGPU_SS_DEV_D3, 143 AMDGPU_SS_DRV_UNLOAD 144 }; 145 146 struct amdgpu_watchdog_timer 147 { 148 bool timeout_fatal_disable; 149 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 150 }; 151 152 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 153 154 /* 155 * Modules parameters. 156 */ 157 extern int amdgpu_modeset; 158 extern int amdgpu_vram_limit; 159 extern int amdgpu_vis_vram_limit; 160 extern int amdgpu_gart_size; 161 extern int amdgpu_gtt_size; 162 extern int amdgpu_moverate; 163 extern int amdgpu_audio; 164 extern int amdgpu_disp_priority; 165 extern int amdgpu_hw_i2c; 166 extern int amdgpu_pcie_gen2; 167 extern int amdgpu_msi; 168 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 169 extern int amdgpu_dpm; 170 extern int amdgpu_fw_load_type; 171 extern int amdgpu_aspm; 172 extern int amdgpu_runtime_pm; 173 extern uint amdgpu_ip_block_mask; 174 extern int amdgpu_bapm; 175 extern int amdgpu_deep_color; 176 extern int amdgpu_vm_size; 177 extern int amdgpu_vm_block_size; 178 extern int amdgpu_vm_fragment_size; 179 extern int amdgpu_vm_fault_stop; 180 extern int amdgpu_vm_debug; 181 extern int amdgpu_vm_update_mode; 182 extern int amdgpu_exp_hw_support; 183 extern int amdgpu_dc; 184 extern int amdgpu_sched_jobs; 185 extern int amdgpu_sched_hw_submission; 186 extern uint amdgpu_pcie_gen_cap; 187 extern uint amdgpu_pcie_lane_cap; 188 extern u64 amdgpu_cg_mask; 189 extern uint amdgpu_pg_mask; 190 extern uint amdgpu_sdma_phase_quantum; 191 extern char *amdgpu_disable_cu; 192 extern char *amdgpu_virtual_display; 193 extern uint amdgpu_pp_feature_mask; 194 extern uint amdgpu_force_long_training; 195 extern int amdgpu_job_hang_limit; 196 extern int amdgpu_lbpw; 197 extern int amdgpu_compute_multipipe; 198 extern int amdgpu_gpu_recovery; 199 extern int amdgpu_emu_mode; 200 extern uint amdgpu_smu_memory_pool_size; 201 extern int amdgpu_smu_pptable_id; 202 extern uint amdgpu_dc_feature_mask; 203 extern uint amdgpu_freesync_vid_mode; 204 extern uint amdgpu_dc_debug_mask; 205 extern uint amdgpu_dc_visual_confirm; 206 extern uint amdgpu_dm_abm_level; 207 extern int amdgpu_backlight; 208 extern struct amdgpu_mgpu_info mgpu_info; 209 extern int amdgpu_ras_enable; 210 extern uint amdgpu_ras_mask; 211 extern int amdgpu_bad_page_threshold; 212 extern bool amdgpu_ignore_bad_page_threshold; 213 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 214 extern int amdgpu_async_gfx_ring; 215 extern int amdgpu_mcbp; 216 extern int amdgpu_discovery; 217 extern int amdgpu_mes; 218 extern int amdgpu_mes_kiq; 219 extern int amdgpu_noretry; 220 extern int amdgpu_force_asic_type; 221 extern int amdgpu_smartshift_bias; 222 extern int amdgpu_use_xgmi_p2p; 223 #ifdef CONFIG_HSA_AMD 224 extern int sched_policy; 225 extern bool debug_evictions; 226 extern bool no_system_mem_limit; 227 #else 228 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 229 static const bool __maybe_unused debug_evictions; /* = false */ 230 static const bool __maybe_unused no_system_mem_limit; 231 #endif 232 #ifdef CONFIG_HSA_AMD_P2P 233 extern bool pcie_p2p; 234 #endif 235 236 extern int amdgpu_tmz; 237 extern int amdgpu_reset_method; 238 239 #ifdef CONFIG_DRM_AMDGPU_SI 240 extern int amdgpu_si_support; 241 #endif 242 #ifdef CONFIG_DRM_AMDGPU_CIK 243 extern int amdgpu_cik_support; 244 #endif 245 extern int amdgpu_num_kcq; 246 247 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 248 extern int amdgpu_vcnfw_log; 249 extern int amdgpu_sg_display; 250 251 #define AMDGPU_VM_MAX_NUM_CTX 4096 252 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 253 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 254 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 255 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 256 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 257 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 258 #define AMDGPUFB_CONN_LIMIT 4 259 #define AMDGPU_BIOS_NUM_SCRATCH 16 260 261 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 262 263 /* hard reset data */ 264 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 265 266 /* reset flags */ 267 #define AMDGPU_RESET_GFX (1 << 0) 268 #define AMDGPU_RESET_COMPUTE (1 << 1) 269 #define AMDGPU_RESET_DMA (1 << 2) 270 #define AMDGPU_RESET_CP (1 << 3) 271 #define AMDGPU_RESET_GRBM (1 << 4) 272 #define AMDGPU_RESET_DMA1 (1 << 5) 273 #define AMDGPU_RESET_RLC (1 << 6) 274 #define AMDGPU_RESET_SEM (1 << 7) 275 #define AMDGPU_RESET_IH (1 << 8) 276 #define AMDGPU_RESET_VMC (1 << 9) 277 #define AMDGPU_RESET_MC (1 << 10) 278 #define AMDGPU_RESET_DISPLAY (1 << 11) 279 #define AMDGPU_RESET_UVD (1 << 12) 280 #define AMDGPU_RESET_VCE (1 << 13) 281 #define AMDGPU_RESET_VCE1 (1 << 14) 282 283 /* max cursor sizes (in pixels) */ 284 #define CIK_CURSOR_WIDTH 128 285 #define CIK_CURSOR_HEIGHT 128 286 287 /* smart shift bias level limits */ 288 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 289 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 290 291 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 292 #define AMDGPU_SWCTF_EXTRA_DELAY 50 293 294 struct amdgpu_device; 295 struct amdgpu_irq_src; 296 struct amdgpu_fpriv; 297 struct amdgpu_bo_va_mapping; 298 struct kfd_vm_fault_info; 299 struct amdgpu_hive_info; 300 struct amdgpu_reset_context; 301 struct amdgpu_reset_control; 302 303 enum amdgpu_cp_irq { 304 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 305 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 306 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 307 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 308 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 309 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 310 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 311 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 312 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 313 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 314 315 AMDGPU_CP_IRQ_LAST 316 }; 317 318 enum amdgpu_thermal_irq { 319 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 320 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 321 322 AMDGPU_THERMAL_IRQ_LAST 323 }; 324 325 enum amdgpu_kiq_irq { 326 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 327 AMDGPU_CP_KIQ_IRQ_LAST 328 }; 329 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 330 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 331 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 332 #define MAX_KIQ_REG_TRY 1000 333 334 int amdgpu_device_ip_set_clockgating_state(void *dev, 335 enum amd_ip_block_type block_type, 336 enum amd_clockgating_state state); 337 int amdgpu_device_ip_set_powergating_state(void *dev, 338 enum amd_ip_block_type block_type, 339 enum amd_powergating_state state); 340 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 341 u64 *flags); 342 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 343 enum amd_ip_block_type block_type); 344 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 345 enum amd_ip_block_type block_type); 346 347 #define AMDGPU_MAX_IP_NUM 16 348 349 struct amdgpu_ip_block_status { 350 bool valid; 351 bool sw; 352 bool hw; 353 bool late_initialized; 354 bool hang; 355 }; 356 357 struct amdgpu_ip_block_version { 358 const enum amd_ip_block_type type; 359 const u32 major; 360 const u32 minor; 361 const u32 rev; 362 const struct amd_ip_funcs *funcs; 363 }; 364 365 #define HW_REV(_Major, _Minor, _Rev) \ 366 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 367 368 struct amdgpu_ip_block { 369 struct amdgpu_ip_block_status status; 370 const struct amdgpu_ip_block_version *version; 371 }; 372 373 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 374 enum amd_ip_block_type type, 375 u32 major, u32 minor); 376 377 struct amdgpu_ip_block * 378 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 379 enum amd_ip_block_type type); 380 381 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 382 const struct amdgpu_ip_block_version *ip_block_version); 383 384 /* 385 * BIOS. 386 */ 387 bool amdgpu_get_bios(struct amdgpu_device *adev); 388 bool amdgpu_read_bios(struct amdgpu_device *adev); 389 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 390 u8 *bios, u32 length_bytes); 391 /* 392 * Clocks 393 */ 394 395 #define AMDGPU_MAX_PPLL 3 396 397 struct amdgpu_clock { 398 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 399 struct amdgpu_pll spll; 400 struct amdgpu_pll mpll; 401 /* 10 Khz units */ 402 uint32_t default_mclk; 403 uint32_t default_sclk; 404 uint32_t default_dispclk; 405 uint32_t current_dispclk; 406 uint32_t dp_extclk; 407 uint32_t max_pixel_clock; 408 }; 409 410 /* sub-allocation manager, it has to be protected by another lock. 411 * By conception this is an helper for other part of the driver 412 * like the indirect buffer or semaphore, which both have their 413 * locking. 414 * 415 * Principe is simple, we keep a list of sub allocation in offset 416 * order (first entry has offset == 0, last entry has the highest 417 * offset). 418 * 419 * When allocating new object we first check if there is room at 420 * the end total_size - (last_object_offset + last_object_size) >= 421 * alloc_size. If so we allocate new object there. 422 * 423 * When there is not enough room at the end, we start waiting for 424 * each sub object until we reach object_offset+object_size >= 425 * alloc_size, this object then become the sub object we return. 426 * 427 * Alignment can't be bigger than page size. 428 * 429 * Hole are not considered for allocation to keep things simple. 430 * Assumption is that there won't be hole (all object on same 431 * alignment). 432 */ 433 434 #define AMDGPU_SA_NUM_FENCE_LISTS 32 435 436 struct amdgpu_sa_manager { 437 wait_queue_head_t wq; 438 struct amdgpu_bo *bo; 439 struct list_head *hole; 440 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 441 struct list_head olist; 442 unsigned size; 443 uint64_t gpu_addr; 444 void *cpu_ptr; 445 uint32_t domain; 446 uint32_t align; 447 }; 448 449 /* sub-allocation buffer */ 450 struct amdgpu_sa_bo { 451 struct list_head olist; 452 struct list_head flist; 453 struct amdgpu_sa_manager *manager; 454 unsigned soffset; 455 unsigned eoffset; 456 struct dma_fence *fence; 457 }; 458 459 int amdgpu_fence_slab_init(void); 460 void amdgpu_fence_slab_fini(void); 461 462 /* 463 * IRQS. 464 */ 465 466 struct amdgpu_flip_work { 467 struct delayed_work flip_work; 468 struct work_struct unpin_work; 469 struct amdgpu_device *adev; 470 int crtc_id; 471 u32 target_vblank; 472 uint64_t base; 473 struct drm_pending_vblank_event *event; 474 struct amdgpu_bo *old_abo; 475 unsigned shared_count; 476 struct dma_fence **shared; 477 struct dma_fence_cb cb; 478 bool async; 479 }; 480 481 482 /* 483 * file private structure 484 */ 485 486 struct amdgpu_fpriv { 487 struct amdgpu_vm vm; 488 struct amdgpu_bo_va *prt_va; 489 struct amdgpu_bo_va *csa_va; 490 struct rwlock bo_list_lock; 491 struct idr bo_list_handles; 492 struct amdgpu_ctx_mgr ctx_mgr; 493 }; 494 495 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 496 497 /* 498 * Writeback 499 */ 500 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 501 502 struct amdgpu_wb { 503 struct amdgpu_bo *wb_obj; 504 volatile uint32_t *wb; 505 uint64_t gpu_addr; 506 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 507 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 508 }; 509 510 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 511 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 512 513 /* 514 * Benchmarking 515 */ 516 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 517 518 /* 519 * ASIC specific register table accessible by UMD 520 */ 521 struct amdgpu_allowed_register_entry { 522 uint32_t reg_offset; 523 bool grbm_indexed; 524 }; 525 526 enum amd_reset_method { 527 AMD_RESET_METHOD_NONE = -1, 528 AMD_RESET_METHOD_LEGACY = 0, 529 AMD_RESET_METHOD_MODE0, 530 AMD_RESET_METHOD_MODE1, 531 AMD_RESET_METHOD_MODE2, 532 AMD_RESET_METHOD_BACO, 533 AMD_RESET_METHOD_PCI, 534 }; 535 536 struct amdgpu_video_codec_info { 537 u32 codec_type; 538 u32 max_width; 539 u32 max_height; 540 u32 max_pixels_per_frame; 541 u32 max_level; 542 }; 543 544 #define codec_info_build(type, width, height, level) \ 545 .codec_type = type,\ 546 .max_width = width,\ 547 .max_height = height,\ 548 .max_pixels_per_frame = height * width,\ 549 .max_level = level, 550 551 struct amdgpu_video_codecs { 552 const u32 codec_count; 553 const struct amdgpu_video_codec_info *codec_array; 554 }; 555 556 /* 557 * ASIC specific functions. 558 */ 559 struct amdgpu_asic_funcs { 560 bool (*read_disabled_bios)(struct amdgpu_device *adev); 561 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 562 u8 *bios, u32 length_bytes); 563 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 564 u32 sh_num, u32 reg_offset, u32 *value); 565 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 566 int (*reset)(struct amdgpu_device *adev); 567 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 568 /* get the reference clock */ 569 u32 (*get_xclk)(struct amdgpu_device *adev); 570 /* MM block clocks */ 571 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 572 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 573 /* static power management */ 574 int (*get_pcie_lanes)(struct amdgpu_device *adev); 575 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 576 /* get config memsize register */ 577 u32 (*get_config_memsize)(struct amdgpu_device *adev); 578 /* flush hdp write queue */ 579 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 580 /* invalidate hdp read cache */ 581 void (*invalidate_hdp)(struct amdgpu_device *adev, 582 struct amdgpu_ring *ring); 583 /* check if the asic needs a full reset of if soft reset will work */ 584 bool (*need_full_reset)(struct amdgpu_device *adev); 585 /* initialize doorbell layout for specific asic*/ 586 void (*init_doorbell_index)(struct amdgpu_device *adev); 587 /* PCIe bandwidth usage */ 588 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 589 uint64_t *count1); 590 /* do we need to reset the asic at init time (e.g., kexec) */ 591 bool (*need_reset_on_init)(struct amdgpu_device *adev); 592 /* PCIe replay counter */ 593 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 594 /* device supports BACO */ 595 bool (*supports_baco)(struct amdgpu_device *adev); 596 /* pre asic_init quirks */ 597 void (*pre_asic_init)(struct amdgpu_device *adev); 598 /* enter/exit umd stable pstate */ 599 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 600 /* query video codecs */ 601 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 602 const struct amdgpu_video_codecs **codecs); 603 }; 604 605 /* 606 * IOCTL. 607 */ 608 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 609 struct drm_file *filp); 610 611 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 612 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 613 struct drm_file *filp); 614 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 615 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 616 struct drm_file *filp); 617 618 /* VRAM scratch page for HDP bug, default vram page */ 619 struct amdgpu_vram_scratch { 620 struct amdgpu_bo *robj; 621 volatile uint32_t *ptr; 622 u64 gpu_addr; 623 }; 624 625 /* 626 * CGS 627 */ 628 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 629 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 630 631 /* 632 * Core structure, functions and helpers. 633 */ 634 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 635 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 636 637 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 638 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 639 640 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 641 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 642 643 struct amdgpu_mmio_remap { 644 u32 reg_offset; 645 resource_size_t bus_addr; 646 }; 647 648 /* Define the HW IP blocks will be used in driver , add more if necessary */ 649 enum amd_hw_ip_block_type { 650 GC_HWIP = 1, 651 HDP_HWIP, 652 SDMA0_HWIP, 653 SDMA1_HWIP, 654 SDMA2_HWIP, 655 SDMA3_HWIP, 656 SDMA4_HWIP, 657 SDMA5_HWIP, 658 SDMA6_HWIP, 659 SDMA7_HWIP, 660 LSDMA_HWIP, 661 MMHUB_HWIP, 662 ATHUB_HWIP, 663 NBIO_HWIP, 664 MP0_HWIP, 665 MP1_HWIP, 666 UVD_HWIP, 667 VCN_HWIP = UVD_HWIP, 668 JPEG_HWIP = VCN_HWIP, 669 VCN1_HWIP, 670 VCE_HWIP, 671 DF_HWIP, 672 DCE_HWIP, 673 OSSSYS_HWIP, 674 SMUIO_HWIP, 675 PWR_HWIP, 676 NBIF_HWIP, 677 THM_HWIP, 678 CLK_HWIP, 679 UMC_HWIP, 680 RSMU_HWIP, 681 XGMI_HWIP, 682 DCI_HWIP, 683 PCIE_HWIP, 684 MAX_HWIP 685 }; 686 687 #define HWIP_MAX_INSTANCE 11 688 689 #define HW_ID_MAX 300 690 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 691 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 692 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 693 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 694 695 struct amd_powerplay { 696 void *pp_handle; 697 const struct amd_pm_funcs *pp_funcs; 698 }; 699 700 struct ip_discovery_top; 701 702 /* polaris10 kickers */ 703 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 704 ((rid == 0xE3) || \ 705 (rid == 0xE4) || \ 706 (rid == 0xE5) || \ 707 (rid == 0xE7) || \ 708 (rid == 0xEF))) || \ 709 ((did == 0x6FDF) && \ 710 ((rid == 0xE7) || \ 711 (rid == 0xEF) || \ 712 (rid == 0xFF)))) 713 714 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 715 ((rid == 0xE1) || \ 716 (rid == 0xF7))) 717 718 /* polaris11 kickers */ 719 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 720 ((rid == 0xE0) || \ 721 (rid == 0xE5))) || \ 722 ((did == 0x67FF) && \ 723 ((rid == 0xCF) || \ 724 (rid == 0xEF) || \ 725 (rid == 0xFF)))) 726 727 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 728 ((rid == 0xE2))) 729 730 /* polaris12 kickers */ 731 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 732 ((rid == 0xC0) || \ 733 (rid == 0xC1) || \ 734 (rid == 0xC3) || \ 735 (rid == 0xC7))) || \ 736 ((did == 0x6981) && \ 737 ((rid == 0x00) || \ 738 (rid == 0x01) || \ 739 (rid == 0x10)))) 740 741 struct amdgpu_mqd_prop { 742 uint64_t mqd_gpu_addr; 743 uint64_t hqd_base_gpu_addr; 744 uint64_t rptr_gpu_addr; 745 uint64_t wptr_gpu_addr; 746 uint32_t queue_size; 747 bool use_doorbell; 748 uint32_t doorbell_index; 749 uint64_t eop_gpu_addr; 750 uint32_t hqd_pipe_priority; 751 uint32_t hqd_queue_priority; 752 bool hqd_active; 753 }; 754 755 struct amdgpu_mqd { 756 unsigned mqd_size; 757 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 758 struct amdgpu_mqd_prop *p); 759 }; 760 761 #define AMDGPU_RESET_MAGIC_NUM 64 762 #define AMDGPU_MAX_DF_PERFMONS 4 763 #define AMDGPU_PRODUCT_NAME_LEN 64 764 struct amdgpu_reset_domain; 765 766 struct amdgpu_device { 767 struct device self; 768 struct device *dev; 769 struct pci_dev *pdev; 770 struct drm_device ddev; 771 772 pci_chipset_tag_t pc; 773 pcitag_t pa_tag; 774 pci_intr_handle_t intrh; 775 bus_space_tag_t iot; 776 bus_space_tag_t memt; 777 bus_dma_tag_t dmat; 778 void *irqh; 779 780 void (*switchcb)(void *, int, int); 781 void *switchcbarg; 782 void *switchcookie; 783 struct task switchtask; 784 struct rasops_info ro; 785 int console; 786 int primary; 787 788 struct task burner_task; 789 int burner_fblank; 790 791 unsigned long fb_aper_offset; 792 unsigned long fb_aper_size; 793 794 #ifdef CONFIG_DRM_AMD_ACP 795 struct amdgpu_acp acp; 796 #endif 797 struct amdgpu_hive_info *hive; 798 /* ASIC */ 799 enum amd_asic_type asic_type; 800 uint32_t family; 801 uint32_t rev_id; 802 uint32_t external_rev_id; 803 unsigned long flags; 804 unsigned long apu_flags; 805 int usec_timeout; 806 const struct amdgpu_asic_funcs *asic_funcs; 807 bool shutdown; 808 bool need_swiotlb; 809 bool accel_working; 810 struct notifier_block acpi_nb; 811 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 812 #ifdef notyet 813 struct debugfs_blob_wrapper debugfs_vbios_blob; 814 struct debugfs_blob_wrapper debugfs_discovery_blob; 815 #endif 816 struct rwlock srbm_mutex; 817 /* GRBM index mutex. Protects concurrent access to GRBM index */ 818 struct rwlock grbm_idx_mutex; 819 struct dev_pm_domain vga_pm_domain; 820 bool have_disp_power_ref; 821 bool have_atomics_support; 822 823 /* BIOS */ 824 bool is_atom_fw; 825 uint8_t *bios; 826 uint32_t bios_size; 827 uint32_t bios_scratch_reg_offset; 828 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 829 830 /* Register/doorbell mmio */ 831 resource_size_t rmmio_base; 832 resource_size_t rmmio_size; 833 void __iomem *rmmio; 834 bus_space_tag_t rmmio_bst; 835 bus_space_handle_t rmmio_bsh; 836 /* protects concurrent MM_INDEX/DATA based register access */ 837 spinlock_t mmio_idx_lock; 838 struct amdgpu_mmio_remap rmmio_remap; 839 /* protects concurrent SMC based register access */ 840 spinlock_t smc_idx_lock; 841 amdgpu_rreg_t smc_rreg; 842 amdgpu_wreg_t smc_wreg; 843 /* protects concurrent PCIE register access */ 844 spinlock_t pcie_idx_lock; 845 amdgpu_rreg_t pcie_rreg; 846 amdgpu_wreg_t pcie_wreg; 847 amdgpu_rreg_t pciep_rreg; 848 amdgpu_wreg_t pciep_wreg; 849 amdgpu_rreg64_t pcie_rreg64; 850 amdgpu_wreg64_t pcie_wreg64; 851 /* protects concurrent UVD register access */ 852 spinlock_t uvd_ctx_idx_lock; 853 amdgpu_rreg_t uvd_ctx_rreg; 854 amdgpu_wreg_t uvd_ctx_wreg; 855 /* protects concurrent DIDT register access */ 856 spinlock_t didt_idx_lock; 857 amdgpu_rreg_t didt_rreg; 858 amdgpu_wreg_t didt_wreg; 859 /* protects concurrent gc_cac register access */ 860 spinlock_t gc_cac_idx_lock; 861 amdgpu_rreg_t gc_cac_rreg; 862 amdgpu_wreg_t gc_cac_wreg; 863 /* protects concurrent se_cac register access */ 864 spinlock_t se_cac_idx_lock; 865 amdgpu_rreg_t se_cac_rreg; 866 amdgpu_wreg_t se_cac_wreg; 867 /* protects concurrent ENDPOINT (audio) register access */ 868 spinlock_t audio_endpt_idx_lock; 869 amdgpu_block_rreg_t audio_endpt_rreg; 870 amdgpu_block_wreg_t audio_endpt_wreg; 871 struct amdgpu_doorbell doorbell; 872 873 /* clock/pll info */ 874 struct amdgpu_clock clock; 875 876 /* MC */ 877 struct amdgpu_gmc gmc; 878 struct amdgpu_gart gart; 879 dma_addr_t dummy_page_addr; 880 struct amdgpu_vm_manager vm_manager; 881 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 882 unsigned num_vmhubs; 883 884 /* memory management */ 885 struct amdgpu_mman mman; 886 struct amdgpu_vram_scratch vram_scratch; 887 struct amdgpu_wb wb; 888 atomic64_t num_bytes_moved; 889 atomic64_t num_evictions; 890 atomic64_t num_vram_cpu_page_faults; 891 atomic_t gpu_reset_counter; 892 atomic_t vram_lost_counter; 893 894 /* data for buffer migration throttling */ 895 struct { 896 spinlock_t lock; 897 s64 last_update_us; 898 s64 accum_us; /* accumulated microseconds */ 899 s64 accum_us_vis; /* for visible VRAM */ 900 u32 log2_max_MBps; 901 } mm_stats; 902 903 /* display */ 904 bool enable_virtual_display; 905 struct amdgpu_vkms_output *amdgpu_vkms_output; 906 struct amdgpu_mode_info mode_info; 907 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 908 struct work_struct hotplug_work; 909 struct amdgpu_irq_src crtc_irq; 910 struct amdgpu_irq_src vline0_irq; 911 struct amdgpu_irq_src vupdate_irq; 912 struct amdgpu_irq_src pageflip_irq; 913 struct amdgpu_irq_src hpd_irq; 914 struct amdgpu_irq_src dmub_trace_irq; 915 struct amdgpu_irq_src dmub_outbox_irq; 916 917 /* rings */ 918 u64 fence_context; 919 unsigned num_rings; 920 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 921 struct dma_fence __rcu *gang_submit; 922 bool ib_pool_ready; 923 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 924 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 925 926 /* interrupts */ 927 struct amdgpu_irq irq; 928 929 /* powerplay */ 930 struct amd_powerplay powerplay; 931 struct amdgpu_pm pm; 932 u64 cg_flags; 933 u32 pg_flags; 934 935 /* nbio */ 936 struct amdgpu_nbio nbio; 937 938 /* hdp */ 939 struct amdgpu_hdp hdp; 940 941 /* smuio */ 942 struct amdgpu_smuio smuio; 943 944 /* mmhub */ 945 struct amdgpu_mmhub mmhub; 946 947 /* gfxhub */ 948 struct amdgpu_gfxhub gfxhub; 949 950 /* gfx */ 951 struct amdgpu_gfx gfx; 952 953 /* sdma */ 954 struct amdgpu_sdma sdma; 955 956 /* lsdma */ 957 struct amdgpu_lsdma lsdma; 958 959 /* uvd */ 960 struct amdgpu_uvd uvd; 961 962 /* vce */ 963 struct amdgpu_vce vce; 964 965 /* vcn */ 966 struct amdgpu_vcn vcn; 967 968 /* jpeg */ 969 struct amdgpu_jpeg jpeg; 970 971 /* firmwares */ 972 struct amdgpu_firmware firmware; 973 974 /* PSP */ 975 struct psp_context psp; 976 977 /* GDS */ 978 struct amdgpu_gds gds; 979 980 /* KFD */ 981 struct amdgpu_kfd_dev kfd; 982 983 /* UMC */ 984 struct amdgpu_umc umc; 985 986 /* display related functionality */ 987 struct amdgpu_display_manager dm; 988 989 /* mes */ 990 bool enable_mes; 991 bool enable_mes_kiq; 992 struct amdgpu_mes mes; 993 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 994 995 /* df */ 996 struct amdgpu_df df; 997 998 /* MCA */ 999 struct amdgpu_mca mca; 1000 1001 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1002 uint32_t harvest_ip_mask; 1003 int num_ip_blocks; 1004 struct rwlock mn_lock; 1005 DECLARE_HASHTABLE(mn_hash, 7); 1006 1007 /* tracking pinned memory */ 1008 atomic64_t vram_pin_size; 1009 atomic64_t visible_pin_size; 1010 atomic64_t gart_pin_size; 1011 1012 /* soc15 register offset based on ip, instance and segment */ 1013 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1014 1015 /* delayed work_func for deferring clockgating during resume */ 1016 struct delayed_work delayed_init_work; 1017 1018 struct amdgpu_virt virt; 1019 1020 /* link all shadow bo */ 1021 struct list_head shadow_list; 1022 struct rwlock shadow_list_lock; 1023 1024 /* record hw reset is performed */ 1025 bool has_hw_reset; 1026 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1027 1028 /* s3/s4 mask */ 1029 bool in_suspend; 1030 bool in_s3; 1031 bool in_s4; 1032 bool in_s0ix; 1033 1034 enum pp_mp1_state mp1_state; 1035 struct amdgpu_doorbell_index doorbell_index; 1036 1037 struct rwlock notifier_lock; 1038 1039 int asic_reset_res; 1040 struct work_struct xgmi_reset_work; 1041 struct list_head reset_list; 1042 1043 long gfx_timeout; 1044 long sdma_timeout; 1045 long video_timeout; 1046 long compute_timeout; 1047 1048 uint64_t unique_id; 1049 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1050 1051 /* enable runtime pm on the device */ 1052 bool in_runpm; 1053 bool has_pr3; 1054 1055 bool pm_sysfs_en; 1056 bool ucode_sysfs_en; 1057 bool psp_sysfs_en; 1058 1059 /* Chip product information */ 1060 char product_number[20]; 1061 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1062 char serial[20]; 1063 1064 atomic_t throttling_logging_enabled; 1065 struct ratelimit_state throttling_logging_rs; 1066 uint32_t ras_hw_enabled; 1067 uint32_t ras_enabled; 1068 1069 bool no_hw_access; 1070 struct pci_saved_state *pci_state; 1071 pci_channel_state_t pci_channel_state; 1072 1073 struct amdgpu_reset_control *reset_cntl; 1074 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1075 1076 bool ram_is_direct_mapped; 1077 1078 struct list_head ras_list; 1079 1080 struct ip_discovery_top *ip_top; 1081 1082 struct amdgpu_reset_domain *reset_domain; 1083 1084 struct rwlock benchmark_mutex; 1085 1086 /* reset dump register */ 1087 uint32_t *reset_dump_reg_list; 1088 uint32_t *reset_dump_reg_value; 1089 int num_regs; 1090 #ifdef CONFIG_DEV_COREDUMP 1091 struct amdgpu_task_info reset_task_info; 1092 bool reset_vram_lost; 1093 struct timespec64 reset_time; 1094 #endif 1095 1096 bool scpm_enabled; 1097 uint32_t scpm_status; 1098 1099 struct work_struct reset_work; 1100 1101 bool job_hang; 1102 }; 1103 1104 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1105 { 1106 return container_of(ddev, struct amdgpu_device, ddev); 1107 } 1108 1109 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1110 { 1111 return &adev->ddev; 1112 } 1113 1114 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1115 { 1116 return container_of(bdev, struct amdgpu_device, mman.bdev); 1117 } 1118 1119 int amdgpu_device_init(struct amdgpu_device *adev, 1120 uint32_t flags); 1121 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1122 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1123 1124 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1125 1126 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1127 void *buf, size_t size, bool write); 1128 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1129 void *buf, size_t size, bool write); 1130 1131 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1132 void *buf, size_t size, bool write); 1133 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1134 uint32_t reg, uint32_t acc_flags); 1135 void amdgpu_device_wreg(struct amdgpu_device *adev, 1136 uint32_t reg, uint32_t v, 1137 uint32_t acc_flags); 1138 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1139 uint32_t reg, uint32_t v); 1140 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1141 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1142 1143 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1144 u32 pcie_index, u32 pcie_data, 1145 u32 reg_addr); 1146 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1147 u32 pcie_index, u32 pcie_data, 1148 u32 reg_addr); 1149 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1150 u32 pcie_index, u32 pcie_data, 1151 u32 reg_addr, u32 reg_data); 1152 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1153 u32 pcie_index, u32 pcie_data, 1154 u32 reg_addr, u64 reg_data); 1155 1156 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1157 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1158 1159 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1160 struct amdgpu_reset_context *reset_context); 1161 1162 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1163 struct amdgpu_reset_context *reset_context); 1164 1165 int emu_soc_asic_init(struct amdgpu_device *adev); 1166 1167 /* 1168 * Registers read & write functions. 1169 */ 1170 #define AMDGPU_REGS_NO_KIQ (1<<1) 1171 #define AMDGPU_REGS_RLC (1<<2) 1172 1173 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1174 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1175 1176 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1177 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1178 1179 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1180 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1181 1182 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1183 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1184 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1185 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1186 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1187 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1188 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1189 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1190 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1191 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1192 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1193 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1194 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1195 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1196 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1197 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1198 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1199 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1200 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1201 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1202 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1203 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1204 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1205 #define WREG32_P(reg, val, mask) \ 1206 do { \ 1207 uint32_t tmp_ = RREG32(reg); \ 1208 tmp_ &= (mask); \ 1209 tmp_ |= ((val) & ~(mask)); \ 1210 WREG32(reg, tmp_); \ 1211 } while (0) 1212 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1213 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1214 #define WREG32_PLL_P(reg, val, mask) \ 1215 do { \ 1216 uint32_t tmp_ = RREG32_PLL(reg); \ 1217 tmp_ &= (mask); \ 1218 tmp_ |= ((val) & ~(mask)); \ 1219 WREG32_PLL(reg, tmp_); \ 1220 } while (0) 1221 1222 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1223 do { \ 1224 u32 tmp = RREG32_SMC(_Reg); \ 1225 tmp &= (_Mask); \ 1226 tmp |= ((_Val) & ~(_Mask)); \ 1227 WREG32_SMC(_Reg, tmp); \ 1228 } while (0) 1229 1230 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1231 1232 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1233 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1234 1235 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1236 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1237 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1238 1239 #define REG_GET_FIELD(value, reg, field) \ 1240 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1241 1242 #define WREG32_FIELD(reg, field, val) \ 1243 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1244 1245 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1246 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1247 1248 /* 1249 * BIOS helpers. 1250 */ 1251 #define RBIOS8(i) (adev->bios[i]) 1252 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1253 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1254 1255 /* 1256 * ASICs macro. 1257 */ 1258 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1259 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1260 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1261 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1262 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1263 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1264 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1265 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1266 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1267 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1268 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1269 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1270 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1271 #define amdgpu_asic_flush_hdp(adev, r) \ 1272 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1273 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1274 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1275 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0)) 1276 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1277 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1278 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1279 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1280 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1281 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1282 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1283 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1284 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1285 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1286 1287 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1288 1289 /* Common functions */ 1290 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1291 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1292 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1293 struct amdgpu_job *job, 1294 struct amdgpu_reset_context *reset_context); 1295 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1296 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1297 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1298 bool amdgpu_device_pcie_dynamic_switching_supported(void); 1299 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1300 bool amdgpu_device_aspm_support_quirk(void); 1301 1302 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1303 u64 num_vis_bytes); 1304 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1305 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1306 const u32 *registers, 1307 const u32 array_size); 1308 1309 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1310 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1311 bool amdgpu_device_supports_px(struct drm_device *dev); 1312 bool amdgpu_device_supports_boco(struct drm_device *dev); 1313 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1314 bool amdgpu_device_supports_baco(struct drm_device *dev); 1315 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1316 struct amdgpu_device *peer_adev); 1317 int amdgpu_device_baco_enter(struct drm_device *dev); 1318 int amdgpu_device_baco_exit(struct drm_device *dev); 1319 1320 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1321 struct amdgpu_ring *ring); 1322 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1323 struct amdgpu_ring *ring); 1324 1325 void amdgpu_device_halt(struct amdgpu_device *adev); 1326 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1327 u32 reg); 1328 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1329 u32 reg, u32 v); 1330 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1331 struct dma_fence *gang); 1332 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1333 1334 /* atpx handler */ 1335 #if defined(CONFIG_VGA_SWITCHEROO) 1336 void amdgpu_register_atpx_handler(void); 1337 void amdgpu_unregister_atpx_handler(void); 1338 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1339 bool amdgpu_is_atpx_hybrid(void); 1340 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1341 bool amdgpu_has_atpx(void); 1342 #else 1343 static inline void amdgpu_register_atpx_handler(void) {} 1344 static inline void amdgpu_unregister_atpx_handler(void) {} 1345 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1346 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1347 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1348 static inline bool amdgpu_has_atpx(void) { return false; } 1349 #endif 1350 1351 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1352 void *amdgpu_atpx_get_dhandle(void); 1353 #else 1354 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1355 #endif 1356 1357 /* 1358 * KMS 1359 */ 1360 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1361 extern const int amdgpu_max_kms_ioctl; 1362 1363 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1364 void amdgpu_driver_unload_kms(struct drm_device *dev); 1365 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1366 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1367 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1368 struct drm_file *file_priv); 1369 void amdgpu_driver_release_kms(struct drm_device *dev); 1370 1371 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1372 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1373 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1374 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1375 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1376 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1377 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1378 struct drm_file *filp); 1379 1380 /* 1381 * functions used by amdgpu_encoder.c 1382 */ 1383 struct amdgpu_afmt_acr { 1384 u32 clock; 1385 1386 int n_32khz; 1387 int cts_32khz; 1388 1389 int n_44_1khz; 1390 int cts_44_1khz; 1391 1392 int n_48khz; 1393 int cts_48khz; 1394 1395 }; 1396 1397 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1398 1399 /* amdgpu_acpi.c */ 1400 1401 /* ATCS Device/Driver State */ 1402 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1403 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1404 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1405 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1406 1407 #if defined(CONFIG_ACPI) 1408 int amdgpu_acpi_init(struct amdgpu_device *adev); 1409 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1410 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1411 bool amdgpu_acpi_is_power_shift_control_supported(void); 1412 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1413 u8 perf_req, bool advertise); 1414 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1415 u8 dev_state, bool drv_state); 1416 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1417 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1418 1419 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1420 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1421 void amdgpu_acpi_detect(void); 1422 #else 1423 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1424 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1425 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1426 static inline void amdgpu_acpi_detect(void) { } 1427 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1428 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1429 u8 dev_state, bool drv_state) { return 0; } 1430 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1431 enum amdgpu_ss ss_state) { return 0; } 1432 #endif 1433 1434 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1435 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1436 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1437 #else 1438 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1439 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1440 #endif 1441 1442 #if defined(CONFIG_DRM_AMD_DC) 1443 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1444 #else 1445 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1446 #endif 1447 1448 1449 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1450 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1451 1452 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1453 pci_channel_state_t state); 1454 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1455 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1456 void amdgpu_pci_resume(struct pci_dev *pdev); 1457 1458 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1459 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1460 1461 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1462 1463 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1464 enum amd_clockgating_state state); 1465 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1466 enum amd_powergating_state state); 1467 1468 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1469 { 1470 return amdgpu_gpu_recovery != 0 && 1471 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1472 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1473 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1474 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1475 } 1476 1477 #include "amdgpu_object.h" 1478 1479 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1480 { 1481 return adev->gmc.tmz_enabled; 1482 } 1483 1484 int amdgpu_in_reset(struct amdgpu_device *adev); 1485 1486 #endif 1487