1 /* $OpenBSD: cz.c,v 1.6 2002/11/19 18:40:17 jason Exp $ */ 2 /* $NetBSD: cz.c,v 1.15 2001/01/20 19:10:36 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Zembu Labs, Inc. 6 * All rights reserved. 7 * 8 * Authors: Jason R. Thorpe <thorpej@zembu.com> 9 * Bill Studenmund <wrstuden@zembu.com> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Zembu Labs, Inc. 22 * 4. Neither the name of Zembu Labs nor the names of its employees may 23 * be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 27 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 28 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 29 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 40 * 41 * Some notes: 42 * 43 * - The Cyclades-Z has fully automatic hardware (and software!) 44 * flow control. We only utilize RTS/CTS flow control here, 45 * and it is implemented in a very simplistic manner. This 46 * may be an area of future work. 47 * 48 * - The PLX can map the either the board's RAM or host RAM 49 * into the MIPS's memory window. This would enable us to 50 * use less expensive (for us) memory reads/writes to host 51 * RAM, rather than time-consuming reads/writes to PCI 52 * memory space. However, the PLX can only map a 0-128M 53 * window, so we would have to ensure that the DMA address 54 * of the host RAM fits there. This is kind of a pain, 55 * so we just don't bother right now. 56 * 57 * - In a perfect world, we would use the autoconfiguration 58 * mechanism to attach the TTYs that we find. However, 59 * that leads to somewhat icky looking autoconfiguration 60 * messages (one for every TTY, up to 64 per board!). So 61 * we don't do it that way, but assign minors as if there 62 * were the max of 64 ports per board. 63 * 64 * - We don't bother with PPS support here. There are so many 65 * ports, each with a large amount of buffer space, that the 66 * normal mode of operation is to poll the boards regularly 67 * (generally, every 20ms or so). This makes this driver 68 * unsuitable for PPS, as the latency will be generally too 69 * high. 70 */ 71 /* 72 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 73 * for FreeBSD 3.2. 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/proc.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/tty.h> 82 #include <sys/conf.h> 83 #include <sys/time.h> 84 #include <sys/kernel.h> 85 #include <sys/fcntl.h> 86 #include <sys/syslog.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 #include <dev/pci/czreg.h> 92 93 #include <dev/pci/plx9060reg.h> 94 #include <dev/pci/plx9060var.h> 95 96 #include <dev/microcode/cyclades/cyzfirm.h> 97 98 #define CZ_DRIVER_VERSION 0x20000411 99 100 #define CZ_POLL_MS 20 101 102 /* These are the interrupts we always use. */ 103 #define CZ_INTERRUPTS \ 104 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 105 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 106 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 107 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 108 109 /* 110 * cztty_softc: 111 * 112 * Per-channel (TTY) state. 113 */ 114 struct cztty_softc { 115 struct cz_softc *sc_parent; 116 struct tty *sc_tty; 117 118 struct timeout sc_diag_to; 119 120 int sc_channel; /* Also used to flag unattached chan */ 121 #define CZTTY_CHANNEL_DEAD -1 122 123 bus_space_tag_t sc_chan_st; /* channel space tag */ 124 bus_space_handle_t sc_chan_sh; /* channel space handle */ 125 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 126 127 u_int sc_overflows, 128 sc_parity_errors, 129 sc_framing_errors, 130 sc_errors; 131 132 int sc_swflags; 133 134 u_int32_t sc_rs_control_dtr, 135 sc_chanctl_hw_flow, 136 sc_chanctl_comm_baud, 137 sc_chanctl_rs_control, 138 sc_chanctl_comm_data_l, 139 sc_chanctl_comm_parity; 140 }; 141 142 /* 143 * cz_softc: 144 * 145 * Per-board state. 146 */ 147 struct cz_softc { 148 struct device cz_dev; /* generic device info */ 149 struct plx9060_config cz_plx; /* PLX 9060 config info */ 150 bus_space_tag_t cz_win_st; /* window space tag */ 151 bus_space_handle_t cz_win_sh; /* window space handle */ 152 struct timeout cz_timeout; /* timeout for polling-mode */ 153 154 void *cz_ih; /* interrupt handle */ 155 156 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 157 int cz_nchannels; /* number of channels */ 158 int cz_nopenchan; /* number of open channels */ 159 struct cztty_softc *cz_ports; /* our array of ports */ 160 161 bus_addr_t cz_fwctl; /* offset of firmware control */ 162 }; 163 164 int cz_match(struct device *, void *, void *); 165 void cz_attach(struct device *, struct device *, void *); 166 int cz_wait_pci_doorbell(struct cz_softc *, char *); 167 168 struct cfattach cz_ca = { 169 sizeof(struct cz_softc), cz_match, cz_attach 170 }; 171 172 void cz_reset_board(struct cz_softc *); 173 int cz_load_firmware(struct cz_softc *); 174 175 int cz_intr(void *); 176 void cz_poll(void *); 177 int cztty_transmit(struct cztty_softc *, struct tty *); 178 int cztty_receive(struct cztty_softc *, struct tty *); 179 180 struct cztty_softc * cztty_getttysoftc(dev_t dev); 181 int cztty_findmajor(void); 182 int cztty_major; 183 int cztty_attached_ttys; 184 int cz_timeout_ticks; 185 186 cdev_decl(cztty); 187 188 void czttystart(struct tty *tp); 189 int czttyparam(struct tty *tp, struct termios *t); 190 void cztty_shutdown(struct cztty_softc *sc); 191 void cztty_modem(struct cztty_softc *sc, int onoff); 192 void cztty_break(struct cztty_softc *sc, int onoff); 193 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 194 int cztty_to_tiocm(struct cztty_softc *sc); 195 void cztty_diag(void *arg); 196 197 struct cfdriver cz_cd = { 198 0, "cz", DV_TTY 199 }; 200 201 /* 202 * Macros to read and write the PLX. 203 */ 204 #define CZ_PLX_READ(cz, reg) \ 205 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 206 #define CZ_PLX_WRITE(cz, reg, val) \ 207 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 208 (reg), (val)) 209 210 /* 211 * Macros to read and write the FPGA. We must already be in the FPGA 212 * window for this. 213 */ 214 #define CZ_FPGA_READ(cz, reg) \ 215 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 216 #define CZ_FPGA_WRITE(cz, reg, val) \ 217 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 218 219 /* 220 * Macros to read and write the firmware control structures in board RAM. 221 */ 222 #define CZ_FWCTL_READ(cz, off) \ 223 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 224 (cz)->cz_fwctl + (off)) 225 226 #define CZ_FWCTL_WRITE(cz, off, val) \ 227 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 228 (cz)->cz_fwctl + (off), (val)) 229 230 /* 231 * Convenience macros for cztty routines. PLX window MUST be to RAM. 232 */ 233 #define CZTTY_CHAN_READ(sc, off) \ 234 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 235 236 #define CZTTY_CHAN_WRITE(sc, off, val) \ 237 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 238 (off), (val)) 239 240 #define CZTTY_BUF_READ(sc, off) \ 241 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 242 243 #define CZTTY_BUF_WRITE(sc, off, val) \ 244 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 245 (off), (val)) 246 247 /* 248 * Convenience macros. 249 */ 250 #define CZ_WIN_RAM(cz) \ 251 do { \ 252 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 253 delay(100); \ 254 } while (0) 255 256 #define CZ_WIN_FPGA(cz) \ 257 do { \ 258 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 259 delay(100); \ 260 } while (0) 261 262 /***************************************************************************** 263 * Cyclades-Z controller code starts here... 264 *****************************************************************************/ 265 266 /* 267 * cz_match: 268 * 269 * Determine if the given PCI device is a Cyclades-Z board. 270 */ 271 int 272 cz_match(parent, match, aux) 273 struct device *parent; 274 void *match, *aux; 275 { 276 struct pci_attach_args *pa = aux; 277 278 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES && 279 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CYCLADES_CYCLOMZ_2) 280 return (1); 281 return (0); 282 } 283 284 /* 285 * cz_attach: 286 * 287 * A Cyclades-Z board was found; attach it. 288 */ 289 void 290 cz_attach(parent, self, aux) 291 struct device *parent, *self; 292 void *aux; 293 { 294 struct cz_softc *cz = (void *) self; 295 struct pci_attach_args *pa = aux; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 pci_intr_handle_t ih; 298 const char *intrstr = NULL; 299 struct cztty_softc *sc; 300 struct tty *tp; 301 int i; 302 303 printf(": Cyclades-Z multiport serial\n"); 304 305 cz->cz_plx.plx_pc = pa->pa_pc; 306 cz->cz_plx.plx_tag = pa->pa_tag; 307 308 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 309 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 310 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL, 0) != 0) { 311 printf("%s: unable to map PLX registers\n", 312 cz->cz_dev.dv_xname); 313 return; 314 } 315 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 316 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 317 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL, 0) != 0) { 318 printf("%s: unable to map device window\n", 319 cz->cz_dev.dv_xname); 320 return; 321 } 322 323 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 324 cz->cz_nopenchan = 0; 325 326 /* 327 * Make sure that the board is completely stopped. 328 */ 329 CZ_WIN_FPGA(cz); 330 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 331 332 /* 333 * Load the board's firmware. 334 */ 335 if (cz_load_firmware(cz) != 0) 336 return; 337 338 /* 339 * Now that we're ready to roll, map and establish the interrupt 340 * handler. 341 */ 342 if (pci_intr_map(pa, &ih) != 0) { 343 /* 344 * The common case is for Cyclades-Z boards to run 345 * in polling mode, and thus not have an interrupt 346 * mapped for them. Don't bother reporting that 347 * the interrupt is not mappable, since this isn't 348 * really an error. 349 */ 350 cz->cz_ih = NULL; 351 goto polling_mode; 352 } else { 353 intrstr = pci_intr_string(pa->pa_pc, ih); 354 cz->cz_ih = pci_intr_establish(pc, ih, IPL_TTY, 355 cz_intr, cz, cz->cz_dev.dv_xname); 356 } 357 if (cz->cz_ih == NULL) { 358 printf("%s: unable to establish interrupt", 359 cz->cz_dev.dv_xname); 360 if (intrstr != NULL) 361 printf(" at %s", intrstr); 362 printf("\n"); 363 /* We will fall-back on polling mode. */ 364 } else 365 printf("%s: interrupting at %s\n", 366 cz->cz_dev.dv_xname, intrstr); 367 368 polling_mode: 369 if (cz->cz_ih == NULL) { 370 timeout_set(&cz->cz_timeout, cz_poll, cz); 371 if (cz_timeout_ticks == 0) 372 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 373 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 374 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 375 cz_timeout_ticks == 1 ? "" : "s"); 376 } 377 378 if (cztty_major == 0) 379 cztty_major = cztty_findmajor(); 380 /* 381 * Allocate sufficient pointers for the children and 382 * attach them. Set all ports to a reasonable initial 383 * configuration while we're at it: 384 * 385 * disabled 386 * 8N1 387 * default baud rate 388 * hardware flow control. 389 */ 390 CZ_WIN_RAM(cz); 391 392 if (cz->cz_nchannels == 0) { 393 /* No channels? No more work to do! */ 394 return; 395 } 396 397 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 398 M_DEVBUF, M_WAITOK); 399 cztty_attached_ttys += cz->cz_nchannels; 400 memset(cz->cz_ports, 0, 401 sizeof(struct cztty_softc) * cz->cz_nchannels); 402 403 for (i = 0; i < cz->cz_nchannels; i++) { 404 sc = &cz->cz_ports[i]; 405 406 sc->sc_channel = i; 407 sc->sc_chan_st = cz->cz_win_st; 408 sc->sc_parent = cz; 409 410 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 411 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 412 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 413 printf("%s: unable to subregion channel %d control\n", 414 cz->cz_dev.dv_xname, i); 415 sc->sc_channel = CZTTY_CHANNEL_DEAD; 416 continue; 417 } 418 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 419 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 420 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 421 printf("%s: unable to subregion channel %d buffer\n", 422 cz->cz_dev.dv_xname, i); 423 sc->sc_channel = CZTTY_CHANNEL_DEAD; 424 continue; 425 } 426 427 timeout_set(&sc->sc_diag_to, cztty_diag, sc); 428 429 tp = ttymalloc(); 430 tp->t_dev = makedev(cztty_major, 431 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 432 tp->t_oproc = czttystart; 433 tp->t_param = czttyparam; 434 tty_attach(tp); 435 436 sc->sc_tty = tp; 437 438 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 439 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 440 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 441 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 442 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 443 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 444 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 445 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 446 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 447 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 448 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 449 } 450 } 451 452 /* 453 * cz_reset_board: 454 * 455 * Reset the board via the PLX. 456 */ 457 void 458 cz_reset_board(struct cz_softc *cz) 459 { 460 u_int32_t reg; 461 462 reg = CZ_PLX_READ(cz, PLX_CONTROL); 463 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 464 delay(1000); 465 466 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 467 delay(1000); 468 469 /* Now reload the PLX from its EEPROM. */ 470 reg = CZ_PLX_READ(cz, PLX_CONTROL); 471 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 472 delay(1000); 473 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 474 } 475 476 /* 477 * cz_load_firmware: 478 * 479 * Load the ZFIRM firmware into the board's RAM and start it 480 * running. 481 */ 482 int 483 cz_load_firmware(struct cz_softc *cz) 484 { 485 struct zfirm_header *zfh; 486 struct zfirm_config *zfc; 487 struct zfirm_block *zfb, *zblocks; 488 const u_int8_t *cp; 489 const char *board; 490 u_int32_t fid; 491 int i, j, nconfigs, nblocks, nbytes; 492 493 zfh = (struct zfirm_header *) cycladesz_firmware; 494 495 /* Find the config header. */ 496 if (letoh32(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 497 printf("%s: bad ZFIRM config offset: 0x%x\n", 498 cz->cz_dev.dv_xname, letoh32(zfh->zfh_configoff)); 499 return (EIO); 500 } 501 zfc = (struct zfirm_config *)(cycladesz_firmware + 502 letoh32(zfh->zfh_configoff)); 503 nconfigs = letoh32(zfh->zfh_nconfig); 504 505 /* Locate the correct configuration for our board. */ 506 for (i = 0; i < nconfigs; i++, zfc++) { 507 if (letoh32(zfc->zfc_mailbox) == cz->cz_mailbox0 && 508 letoh32(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 509 break; 510 } 511 if (i == nconfigs) { 512 printf("%s: unable to locate config header\n", 513 cz->cz_dev.dv_xname); 514 return (EIO); 515 } 516 517 nblocks = letoh32(zfc->zfc_nblocks); 518 zblocks = (struct zfirm_block *)(cycladesz_firmware + 519 letoh32(zfh->zfh_blockoff)); 520 521 /* 522 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 523 * necessary. 524 */ 525 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 526 #if 0 527 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 528 #endif 529 ) { 530 #ifdef CZ_DEBUG 531 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 532 #endif 533 CZ_WIN_FPGA(cz); 534 for (i = 0; i < nblocks; i++) { 535 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 536 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 537 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FPGA) { 538 nbytes = letoh32(zfb->zfb_size); 539 cp = &cycladesz_firmware[ 540 letoh32(zfb->zfb_fileoff)]; 541 for (j = 0; j < nbytes; j++, cp++) { 542 bus_space_write_1(cz->cz_win_st, 543 cz->cz_win_sh, 0, *cp); 544 /* FPGA needs 30-100us to settle. */ 545 delay(10); 546 } 547 } 548 } 549 #ifdef CZ_DEBUG 550 printf("done\n"); 551 #endif 552 } 553 554 /* Now load the firmware. */ 555 CZ_WIN_RAM(cz); 556 557 for (i = 0; i < nblocks; i++) { 558 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 559 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 560 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 561 const u_int32_t *lp; 562 u_int32_t ro = letoh32(zfb->zfb_ramoff); 563 nbytes = letoh32(zfb->zfb_size); 564 lp = (const u_int32_t *) 565 &cycladesz_firmware[letoh32(zfb->zfb_fileoff)]; 566 for (j = 0; j < nbytes; j += 4, lp++) { 567 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 568 ro + j, letoh32(*lp)); 569 delay(10); 570 } 571 } 572 } 573 574 /* Now restart the MIPS. */ 575 CZ_WIN_FPGA(cz); 576 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 577 578 /* Wait for the MIPS to start, then report the results. */ 579 CZ_WIN_RAM(cz); 580 581 #ifdef CZ_DEBUG 582 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 583 #endif 584 for (i = 0; i < 100; i++) { 585 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 586 ZFIRM_SIG_OFF); 587 if (fid == ZFIRM_SIG) { 588 /* MIPS has booted. */ 589 break; 590 } else if (fid == ZFIRM_HLT) { 591 /* 592 * The MIPS has halted, usually due to a power 593 * shortage on the expansion module. 594 */ 595 printf("%s: MIPS halted; possible power supply " 596 "problem\n", cz->cz_dev.dv_xname); 597 return (EIO); 598 } else { 599 #ifdef CZ_DEBUG 600 if ((i % 8) == 0) 601 printf("."); 602 #endif 603 delay(250000); 604 } 605 } 606 #ifdef CZ_DEBUG 607 printf("\n"); 608 #endif 609 if (i == 100) { 610 CZ_WIN_FPGA(cz); 611 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 612 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 613 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 614 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 615 CZ_FPGA_READ(cz, FPGA_VERSION)); 616 return (EIO); 617 } 618 619 /* 620 * Locate the firmware control structures. 621 */ 622 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 623 ZFIRM_CTRLADDR_OFF); 624 #ifdef CZ_DEBUG 625 printf("%s: FWCTL structure at offset 0x%08lx\n", 626 cz->cz_dev.dv_xname, cz->cz_fwctl); 627 #endif 628 629 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 630 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 631 632 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 633 634 switch (cz->cz_mailbox0) { 635 case MAILBOX0_8Zo_V1: 636 board = "Cyclades-8Zo ver. 1"; 637 break; 638 639 case MAILBOX0_8Zo_V2: 640 board = "Cyclades-8Zo ver. 2"; 641 break; 642 643 case MAILBOX0_Ze_V1: 644 board = "Cyclades-Ze"; 645 break; 646 647 default: 648 board = "unknown Cyclades Z-series"; 649 break; 650 } 651 652 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 653 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 654 if (cz->cz_nchannels == 0) 655 printf("no channels attached, "); 656 else 657 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 658 cz->cz_nchannels, cztty_attached_ttys, 659 cztty_attached_ttys + (cz->cz_nchannels - 1)); 660 printf("firmware %x.%x.%x\n", 661 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 662 663 return (0); 664 } 665 666 /* 667 * cz_poll: 668 * 669 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 670 * ms. 671 */ 672 void 673 cz_poll(void *arg) 674 { 675 int s = spltty(); 676 struct cz_softc *cz = arg; 677 678 cz_intr(cz); 679 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 680 681 splx(s); 682 } 683 684 /* 685 * cz_intr: 686 * 687 * Interrupt service routine. 688 * 689 * We either are receiving an interrupt directly from the board, or we are 690 * in polling mode and it's time to poll. 691 */ 692 int 693 cz_intr(void *arg) 694 { 695 int rval = 0; 696 u_int command, channel, param; 697 struct cz_softc *cz = arg; 698 struct cztty_softc *sc; 699 struct tty *tp; 700 701 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 702 rval = 1; 703 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 704 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 705 706 /* now clear this interrupt, posslibly enabling another */ 707 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 708 709 if (cz->cz_ports == NULL) { 710 #ifdef CZ_DEBUG 711 printf("%s: interrupt on channel %d, but no channels\n", 712 cz->cz_dev.dv_xname, channel); 713 #endif 714 continue; 715 } 716 717 sc = &cz->cz_ports[channel]; 718 719 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 720 break; 721 722 tp = sc->sc_tty; 723 724 switch (command) { 725 case C_CM_TXFEMPTY: /* transmit cases */ 726 case C_CM_TXBEMPTY: 727 case C_CM_TXLOWWM: 728 case C_CM_INTBACK: 729 if (!ISSET(tp->t_state, TS_ISOPEN)) { 730 #ifdef CZ_DEBUG 731 printf("%s: tx intr on closed channel %d\n", 732 cz->cz_dev.dv_xname, channel); 733 #endif 734 break; 735 } 736 737 if (cztty_transmit(sc, tp)) { 738 /* 739 * Do wakeup stuff here. 740 */ 741 ttwakeup(tp); 742 wakeup(tp); 743 } 744 break; 745 746 case C_CM_RXNNDT: /* receive cases */ 747 case C_CM_RXHIWM: 748 case C_CM_INTBACK2: /* from restart ?? */ 749 #if 0 750 case C_CM_ICHAR: 751 #endif 752 if (!ISSET(tp->t_state, TS_ISOPEN)) { 753 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 754 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 755 break; 756 } 757 758 if (cztty_receive(sc, tp)) { 759 /* 760 * Do wakeup stuff here. 761 */ 762 ttwakeup(tp); 763 wakeup(tp); 764 } 765 break; 766 767 case C_CM_MDCD: 768 if (!ISSET(tp->t_state, TS_ISOPEN)) 769 break; 770 771 (void) (*linesw[tp->t_line].l_modem)(tp, 772 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 773 CHNCTL_RS_STATUS))); 774 break; 775 776 case C_CM_MDSR: 777 case C_CM_MRI: 778 case C_CM_MCTS: 779 case C_CM_MRTS: 780 break; 781 782 case C_CM_IOCTLW: 783 break; 784 785 case C_CM_PR_ERROR: 786 sc->sc_parity_errors++; 787 goto error_common; 788 789 case C_CM_FR_ERROR: 790 sc->sc_framing_errors++; 791 goto error_common; 792 793 case C_CM_OVR_ERROR: 794 sc->sc_overflows++; 795 error_common: 796 if (sc->sc_errors++ == 0) 797 timeout_add(&sc->sc_diag_to, 60 * hz); 798 break; 799 800 case C_CM_RXBRK: 801 if (!ISSET(tp->t_state, TS_ISOPEN)) 802 break; 803 804 /* 805 * A break is a \000 character with TTY_FE error 806 * flags set. So TTY_FE by itself works. 807 */ 808 (*linesw[tp->t_line].l_rint)(TTY_FE, tp); 809 ttwakeup(tp); 810 wakeup(tp); 811 break; 812 813 default: 814 #ifdef CZ_DEBUG 815 printf("%s: channel %d: Unknown interrupt 0x%x\n", 816 cz->cz_dev.dv_xname, sc->sc_channel, command); 817 #endif 818 break; 819 } 820 } 821 822 return (rval); 823 } 824 825 /* 826 * cz_wait_pci_doorbell: 827 * 828 * Wait for the pci doorbell to be clear - wait for pending 829 * activity to drain. 830 */ 831 int 832 cz_wait_pci_doorbell(struct cz_softc *cz, char *wstring) 833 { 834 int error; 835 836 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 837 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 838 if ((error != 0) && (error != EWOULDBLOCK)) 839 return (error); 840 } 841 return (0); 842 } 843 844 /***************************************************************************** 845 * Cyclades-Z TTY code starts here... 846 *****************************************************************************/ 847 848 #define CZTTYDIALOUT_MASK 0x80 849 850 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 851 #define CZTTY_CZ(sc) ((sc)->sc_parent) 852 853 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 854 855 struct cztty_softc * 856 cztty_getttysoftc(dev_t dev) 857 { 858 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 859 struct cz_softc *cz; 860 861 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 862 k = j; 863 cz = (struct cz_softc *)device_lookup(&cz_cd, i); 864 if (cz == NULL) 865 continue; 866 if (cz->cz_ports == NULL) 867 continue; 868 j += cz->cz_nchannels; 869 if (j > u) 870 break; 871 } 872 873 if (i >= cz_cd.cd_ndevs) 874 return (NULL); 875 else 876 return (&cz->cz_ports[u - k]); 877 } 878 879 int 880 cztty_findmajor(void) 881 { 882 int maj; 883 884 for (maj = 0; maj < nchrdev; maj++) { 885 if (cdevsw[maj].d_open == czttyopen) 886 break; 887 } 888 889 return (maj == nchrdev) ? 0 : maj; 890 } 891 892 /* 893 * czttytty: 894 * 895 * Return a pointer to our tty. 896 */ 897 struct tty * 898 czttytty(dev_t dev) 899 { 900 struct cztty_softc *sc = CZTTY_SOFTC(dev); 901 902 #ifdef DIAGNOSTIC 903 if (sc == NULL) 904 panic("czttytty"); 905 #endif 906 907 return (sc->sc_tty); 908 } 909 910 /* 911 * cztty_shutdown: 912 * 913 * Shut down a port. 914 */ 915 void 916 cztty_shutdown(struct cztty_softc *sc) 917 { 918 struct cz_softc *cz = CZTTY_CZ(sc); 919 struct tty *tp = sc->sc_tty; 920 int s; 921 922 s = spltty(); 923 924 /* Clear any break condition set with TIOCSBRK. */ 925 cztty_break(sc, 0); 926 927 /* 928 * Hang up if necessary. Wait a bit, so the other side has time to 929 * notice even if we immediately open the port again. 930 */ 931 if (ISSET(tp->t_cflag, HUPCL)) { 932 cztty_modem(sc, 0); 933 (void) tsleep(tp, TTIPRI, ttclos, hz); 934 } 935 936 /* Disable the channel. */ 937 cz_wait_pci_doorbell(cz, "czdis"); 938 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 939 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 940 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 941 942 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 943 #ifdef CZ_DEBUG 944 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 945 #endif 946 timeout_del(&cz->cz_timeout); 947 } 948 949 splx(s); 950 } 951 952 /* 953 * czttyopen: 954 * 955 * Open a Cyclades-Z serial port. 956 */ 957 int 958 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 959 { 960 struct cztty_softc *sc = CZTTY_SOFTC(dev); 961 struct cz_softc *cz; 962 struct tty *tp; 963 int s, error; 964 965 if (sc == NULL) 966 return (ENXIO); 967 968 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 969 return (ENXIO); 970 971 cz = CZTTY_CZ(sc); 972 tp = sc->sc_tty; 973 974 if (ISSET(tp->t_state, TS_ISOPEN) && 975 ISSET(tp->t_state, TS_XCLUDE) && 976 p->p_ucred->cr_uid != 0) 977 return (EBUSY); 978 979 s = spltty(); 980 981 /* 982 * Do the following iff this is a first open. 983 */ 984 if (!ISSET(tp->t_state, TS_ISOPEN)) { 985 struct termios t; 986 987 tp->t_dev = dev; 988 989 /* If we're turning things on, enable interrupts */ 990 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 991 #ifdef CZ_DEBUG 992 printf("%s: Enabling polling.\n", 993 cz->cz_dev.dv_xname); 994 #endif 995 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 996 } 997 998 /* 999 * Enable the channel. Don't actually ring the 1000 * doorbell here; czttyparam() will do it for us. 1001 */ 1002 cz_wait_pci_doorbell(cz, "czopen"); 1003 1004 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1005 1006 /* 1007 * Initialize the termios status to the defaults. Add in the 1008 * sticky bits from TIOCSFLAGS. 1009 */ 1010 t.c_ispeed = 0; 1011 t.c_ospeed = TTYDEF_SPEED; 1012 t.c_cflag = TTYDEF_CFLAG; 1013 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1014 SET(t.c_cflag, CLOCAL); 1015 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1016 SET(t.c_cflag, CRTSCTS); 1017 1018 /* 1019 * Reset the input and output rings. Do this before 1020 * we call czttyparam(), as that function enables 1021 * the channel. 1022 */ 1023 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1024 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1025 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1026 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1027 1028 /* Make sure czttyparam() will see changes. */ 1029 tp->t_ospeed = 0; 1030 (void) czttyparam(tp, &t); 1031 tp->t_iflag = TTYDEF_IFLAG; 1032 tp->t_oflag = TTYDEF_OFLAG; 1033 tp->t_lflag = TTYDEF_LFLAG; 1034 ttychars(tp); 1035 ttsetwater(tp); 1036 1037 /* 1038 * Turn on DTR. We must always do this, even if carrier is not 1039 * present, because otherwise we'd have to use TIOCSDTR 1040 * immediately after setting CLOCAL, which applications do not 1041 * expect. We always assert DTR while the device is open 1042 * unless explicitly requested to deassert it. 1043 */ 1044 cztty_modem(sc, 1); 1045 } 1046 1047 splx(s); 1048 1049 error = ttyopen(CZTTY_DIALOUT(dev), tp); 1050 if (error) 1051 goto bad; 1052 1053 error = (*linesw[tp->t_line].l_open)(dev, tp); 1054 if (error) 1055 goto bad; 1056 1057 return (0); 1058 1059 bad: 1060 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1061 /* 1062 * We failed to open the device, and nobody else had it opened. 1063 * Clean up the state as appropriate. 1064 */ 1065 cztty_shutdown(sc); 1066 } 1067 1068 return (error); 1069 } 1070 1071 /* 1072 * czttyclose: 1073 * 1074 * Close a Cyclades-Z serial port. 1075 */ 1076 int 1077 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1078 { 1079 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1080 struct tty *tp = sc->sc_tty; 1081 1082 /* XXX This is for cons.c. */ 1083 if (!ISSET(tp->t_state, TS_ISOPEN)) 1084 return (0); 1085 1086 (*linesw[tp->t_line].l_close)(tp, flags); 1087 ttyclose(tp); 1088 1089 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1090 /* 1091 * Although we got a last close, the device may still be in 1092 * use; e.g. if this was the dialout node, and there are still 1093 * processes waiting for carrier on the non-dialout node. 1094 */ 1095 cztty_shutdown(sc); 1096 } 1097 1098 return (0); 1099 } 1100 1101 /* 1102 * czttyread: 1103 * 1104 * Read from a Cyclades-Z serial port. 1105 */ 1106 int 1107 czttyread(dev_t dev, struct uio *uio, int flags) 1108 { 1109 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1110 struct tty *tp = sc->sc_tty; 1111 1112 return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); 1113 } 1114 1115 /* 1116 * czttywrite: 1117 * 1118 * Write to a Cyclades-Z serial port. 1119 */ 1120 int 1121 czttywrite(dev_t dev, struct uio *uio, int flags) 1122 { 1123 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1124 struct tty *tp = sc->sc_tty; 1125 1126 return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); 1127 } 1128 1129 #if 0 1130 /* 1131 * czttypoll: 1132 * 1133 * Poll a Cyclades-Z serial port. 1134 */ 1135 int 1136 czttypoll(dev_t dev, int events, struct proc p) 1137 { 1138 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1139 struct tty *tp = sc->sc_tty; 1140 1141 return ((*linesw[tp->t_line].l_poll)(tp, events, p)); 1142 } 1143 #endif 1144 1145 /* 1146 * czttyioctl: 1147 * 1148 * Perform a control operation on a Cyclades-Z serial port. 1149 */ 1150 int 1151 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1152 { 1153 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1154 struct tty *tp = sc->sc_tty; 1155 int s, error; 1156 1157 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1158 if (error >= 0) 1159 return (error); 1160 1161 error = ttioctl(tp, cmd, data, flag, p); 1162 if (error >= 0) 1163 return (error); 1164 1165 error = 0; 1166 1167 s = spltty(); 1168 1169 switch (cmd) { 1170 case TIOCSBRK: 1171 cztty_break(sc, 1); 1172 break; 1173 1174 case TIOCCBRK: 1175 cztty_break(sc, 0); 1176 break; 1177 1178 case TIOCGFLAGS: 1179 *(int *)data = sc->sc_swflags; 1180 break; 1181 1182 case TIOCSFLAGS: 1183 error = suser(p->p_ucred, &p->p_acflag); 1184 if (error) 1185 break; 1186 sc->sc_swflags = *(int *)data; 1187 break; 1188 1189 case TIOCSDTR: 1190 cztty_modem(sc, 1); 1191 break; 1192 1193 case TIOCCDTR: 1194 cztty_modem(sc, 0); 1195 break; 1196 1197 case TIOCMSET: 1198 case TIOCMBIS: 1199 case TIOCMBIC: 1200 tiocm_to_cztty(sc, cmd, *(int *)data); 1201 break; 1202 1203 case TIOCMGET: 1204 *(int *)data = cztty_to_tiocm(sc); 1205 break; 1206 1207 default: 1208 error = ENOTTY; 1209 break; 1210 } 1211 1212 splx(s); 1213 1214 return (error); 1215 } 1216 1217 /* 1218 * cztty_break: 1219 * 1220 * Set or clear BREAK on a port. 1221 */ 1222 void 1223 cztty_break(struct cztty_softc *sc, int onoff) 1224 { 1225 struct cz_softc *cz = CZTTY_CZ(sc); 1226 1227 cz_wait_pci_doorbell(cz, "czbreak"); 1228 1229 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1230 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1231 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1232 } 1233 1234 /* 1235 * cztty_modem: 1236 * 1237 * Set or clear DTR on a port. 1238 */ 1239 void 1240 cztty_modem(struct cztty_softc *sc, int onoff) 1241 { 1242 struct cz_softc *cz = CZTTY_CZ(sc); 1243 1244 if (sc->sc_rs_control_dtr == 0) 1245 return; 1246 1247 cz_wait_pci_doorbell(cz, "czmod"); 1248 1249 if (onoff) 1250 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1251 else 1252 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1253 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1254 1255 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1256 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1257 } 1258 1259 /* 1260 * tiocm_to_cztty: 1261 * 1262 * Process TIOCM* ioctls. 1263 */ 1264 void 1265 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1266 { 1267 struct cz_softc *cz = CZTTY_CZ(sc); 1268 u_int32_t czttybits; 1269 1270 czttybits = 0; 1271 if (ISSET(ttybits, TIOCM_DTR)) 1272 SET(czttybits, C_RS_DTR); 1273 if (ISSET(ttybits, TIOCM_RTS)) 1274 SET(czttybits, C_RS_RTS); 1275 1276 cz_wait_pci_doorbell(cz, "cztiocm"); 1277 1278 switch (how) { 1279 case TIOCMBIC: 1280 CLR(sc->sc_chanctl_rs_control, czttybits); 1281 break; 1282 1283 case TIOCMBIS: 1284 SET(sc->sc_chanctl_rs_control, czttybits); 1285 break; 1286 1287 case TIOCMSET: 1288 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1289 SET(sc->sc_chanctl_rs_control, czttybits); 1290 break; 1291 } 1292 1293 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1294 1295 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1296 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1297 } 1298 1299 /* 1300 * cztty_to_tiocm: 1301 * 1302 * Process the TIOCMGET ioctl. 1303 */ 1304 int 1305 cztty_to_tiocm(struct cztty_softc *sc) 1306 { 1307 struct cz_softc *cz = CZTTY_CZ(sc); 1308 u_int32_t rs_status, op_mode; 1309 int ttybits = 0; 1310 1311 cz_wait_pci_doorbell(cz, "cztty"); 1312 1313 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1314 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1315 1316 if (ISSET(rs_status, C_RS_RTS)) 1317 SET(ttybits, TIOCM_RTS); 1318 if (ISSET(rs_status, C_RS_CTS)) 1319 SET(ttybits, TIOCM_CTS); 1320 if (ISSET(rs_status, C_RS_DCD)) 1321 SET(ttybits, TIOCM_CAR); 1322 if (ISSET(rs_status, C_RS_DTR)) 1323 SET(ttybits, TIOCM_DTR); 1324 if (ISSET(rs_status, C_RS_RI)) 1325 SET(ttybits, TIOCM_RNG); 1326 if (ISSET(rs_status, C_RS_DSR)) 1327 SET(ttybits, TIOCM_DSR); 1328 1329 if (ISSET(op_mode, C_CH_ENABLE)) 1330 SET(ttybits, TIOCM_LE); 1331 1332 return (ttybits); 1333 } 1334 1335 /* 1336 * czttyparam: 1337 * 1338 * Set Cyclades-Z serial port parameters from termios. 1339 * 1340 * XXX Should just copy the whole termios after making 1341 * XXX sure all the changes could be done. 1342 */ 1343 int 1344 czttyparam(struct tty *tp, struct termios *t) 1345 { 1346 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1347 struct cz_softc *cz = CZTTY_CZ(sc); 1348 u_int32_t rs_status; 1349 int ospeed, cflag; 1350 1351 ospeed = t->c_ospeed; 1352 cflag = t->c_cflag; 1353 1354 /* Check requested parameters. */ 1355 if (ospeed < 0) 1356 return (EINVAL); 1357 if (t->c_ispeed && t->c_ispeed != ospeed) 1358 return (EINVAL); 1359 1360 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1361 SET(cflag, CLOCAL); 1362 CLR(cflag, HUPCL); 1363 } 1364 1365 /* 1366 * If there were no changes, don't do anything. This avoids dropping 1367 * input and improves performance when all we did was frob things like 1368 * VMIN and VTIME. 1369 */ 1370 if (tp->t_ospeed == ospeed && 1371 tp->t_cflag == cflag) 1372 return (0); 1373 1374 /* Data bits. */ 1375 sc->sc_chanctl_comm_data_l = 0; 1376 switch (t->c_cflag & CSIZE) { 1377 case CS5: 1378 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1379 break; 1380 1381 case CS6: 1382 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1383 break; 1384 1385 case CS7: 1386 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1387 break; 1388 1389 case CS8: 1390 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1391 break; 1392 } 1393 1394 /* Stop bits. */ 1395 if (t->c_cflag & CSTOPB) { 1396 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1397 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1398 else 1399 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1400 } else 1401 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1402 1403 /* Parity. */ 1404 if (t->c_cflag & PARENB) { 1405 if (t->c_cflag & PARODD) 1406 sc->sc_chanctl_comm_parity = C_PR_ODD; 1407 else 1408 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1409 } else 1410 sc->sc_chanctl_comm_parity = C_PR_NONE; 1411 1412 /* 1413 * Initialize flow control pins depending on the current flow control 1414 * mode. 1415 */ 1416 if (ISSET(t->c_cflag, CRTSCTS)) { 1417 sc->sc_rs_control_dtr = C_RS_DTR; 1418 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1419 } else if (ISSET(t->c_cflag, MDMBUF)) { 1420 sc->sc_rs_control_dtr = 0; 1421 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1422 } else { 1423 /* 1424 * If no flow control, then always set RTS. This will make 1425 * the other side happy if it mistakenly thinks we're doing 1426 * RTS/CTS flow control. 1427 */ 1428 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1429 sc->sc_chanctl_hw_flow = 0; 1430 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1431 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1432 else 1433 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1434 } 1435 1436 /* Baud rate. */ 1437 sc->sc_chanctl_comm_baud = ospeed; 1438 1439 /* Copy to tty. */ 1440 tp->t_ispeed = 0; 1441 tp->t_ospeed = t->c_ospeed; 1442 tp->t_cflag = t->c_cflag; 1443 1444 /* 1445 * Now load the channel control structure. 1446 */ 1447 1448 cz_wait_pci_doorbell(cz, "czparam"); 1449 1450 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1451 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1452 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1453 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1454 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1455 1456 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1457 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1458 1459 cz_wait_pci_doorbell(cz, "czparam"); 1460 1461 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1462 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1463 1464 cz_wait_pci_doorbell(cz, "czparam"); 1465 1466 /* 1467 * Update the tty layer's idea of the carrier bit, in case we changed 1468 * CLOCAL. We don't hang up here; we only do that by explicit 1469 * request. 1470 */ 1471 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1472 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1473 1474 return (0); 1475 } 1476 1477 /* 1478 * czttystart: 1479 * 1480 * Start or restart transmission. 1481 */ 1482 void 1483 czttystart(struct tty *tp) 1484 { 1485 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1486 int s; 1487 1488 s = spltty(); 1489 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1490 goto out; 1491 1492 if (tp->t_outq.c_cc <= tp->t_lowat) { 1493 if (ISSET(tp->t_state, TS_ASLEEP)) { 1494 CLR(tp->t_state, TS_ASLEEP); 1495 wakeup(&tp->t_outq); 1496 } 1497 selwakeup(&tp->t_wsel); 1498 if (tp->t_outq.c_cc == 0) 1499 goto out; 1500 } 1501 1502 cztty_transmit(sc, tp); 1503 out: 1504 splx(s); 1505 } 1506 1507 /* 1508 * czttystop: 1509 * 1510 * Stop output, e.g., for ^S or output flush. 1511 */ 1512 int 1513 czttystop(struct tty *tp, int flag) 1514 { 1515 1516 /* 1517 * XXX We don't do anything here, yet. Mostly, I don't know 1518 * XXX exactly how this should be implemented on this device. 1519 * XXX We've given a big chunk of data to the MIPS already, 1520 * XXX and I don't know how we request the MIPS to stop sending 1521 * XXX the data. So, punt for now. --thorpej 1522 */ 1523 return (0); 1524 } 1525 1526 /* 1527 * cztty_diag: 1528 * 1529 * Issue a scheduled diagnostic message. 1530 */ 1531 void 1532 cztty_diag(void *arg) 1533 { 1534 struct cztty_softc *sc = arg; 1535 struct cz_softc *cz = CZTTY_CZ(sc); 1536 u_int overflows, parity_errors, framing_errors; 1537 int s; 1538 1539 s = spltty(); 1540 1541 overflows = sc->sc_overflows; 1542 sc->sc_overflows = 0; 1543 1544 parity_errors = sc->sc_parity_errors; 1545 sc->sc_parity_errors = 0; 1546 1547 framing_errors = sc->sc_framing_errors; 1548 sc->sc_framing_errors = 0; 1549 1550 sc->sc_errors = 0; 1551 1552 splx(s); 1553 1554 log(LOG_WARNING, 1555 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1556 cz->cz_dev.dv_xname, sc->sc_channel, 1557 overflows, overflows == 1 ? "" : "s", 1558 parity_errors, 1559 framing_errors, framing_errors == 1 ? "" : "s"); 1560 } 1561 1562 /* 1563 * tx and rx ring buffer size macros: 1564 * 1565 * The transmitter and receiver both use ring buffers. For each one, there 1566 * is a get (consumer) and a put (producer) offset. The get value is the 1567 * next byte to be read from the ring, and the put is the next one to be 1568 * put into the ring. get == put means the ring is empty. 1569 * 1570 * For each ring, the firmware controls one of (get, put) and this driver 1571 * controls the other. For transmission, this driver updates put to point 1572 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1573 * for receive, the driver controls put, and this driver controls get. 1574 */ 1575 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1576 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1577 1578 /* 1579 * cztty_transmit() 1580 * 1581 * Look at the tty for this port and start sending. 1582 */ 1583 int 1584 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1585 { 1586 struct cz_softc *cz = CZTTY_CZ(sc); 1587 u_int move, get, put, size, address; 1588 #ifdef HOSTRAMCODE 1589 int error, done = 0; 1590 #else 1591 int done = 0; 1592 #endif 1593 1594 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1595 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1596 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1597 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1598 1599 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1600 #ifdef HOSTRAMCODE 1601 if (0) { 1602 move = min(tp->t_outq.c_cc, move); 1603 error = q_to_b(&tp->t_outq, 0, move); 1604 if (error != move) { 1605 printf("%s: channel %d: error moving to " 1606 "transmit buf\n", cz->cz_dev.dv_xname, 1607 sc->sc_channel); 1608 move = error; 1609 } 1610 } else { 1611 #endif 1612 move = min(ndqb(&tp->t_outq, 0), move); 1613 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1614 address + put, tp->t_outq.c_cf, move); 1615 ndflush(&tp->t_outq, move); 1616 #ifdef HOSTRAMCODE 1617 } 1618 #endif 1619 1620 put = ((put + move) % size); 1621 done = 1; 1622 } 1623 if (done) { 1624 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1625 } 1626 return (done); 1627 } 1628 1629 int 1630 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1631 { 1632 struct cz_softc *cz = CZTTY_CZ(sc); 1633 u_int get, put, size, address; 1634 int done = 0, ch; 1635 1636 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1637 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1638 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1639 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1640 1641 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1642 #ifdef HOSTRAMCODE 1643 if (hostram) 1644 ch = ((char *)fifoaddr)[get]; 1645 } else { 1646 #endif 1647 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1648 address + get); 1649 #ifdef HOSTRAMCODE 1650 } 1651 #endif 1652 (*linesw[tp->t_line].l_rint)(ch, tp); 1653 get = (get + 1) % size; 1654 done = 1; 1655 } 1656 if (done) { 1657 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1658 } 1659 return (done); 1660 } 1661