1 /* $OpenBSD: cz.c,v 1.2 2001/06/25 20:25:55 nate Exp $ */ 2 /* $NetBSD: cz.c,v 1.15 2001/01/20 19:10:36 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Zembu Labs, Inc. 6 * All rights reserved. 7 * 8 * Authors: Jason R. Thorpe <thorpej@zembu.com> 9 * Bill Studenmund <wrstuden@zembu.com> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Zembu Labs, Inc. 22 * 4. Neither the name of Zembu Labs nor the names of its employees may 23 * be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 27 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 28 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 29 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 40 * 41 * Some notes: 42 * 43 * - The Cyclades-Z has fully automatic hardware (and software!) 44 * flow control. We only utilize RTS/CTS flow control here, 45 * and it is implemented in a very simplistic manner. This 46 * may be an area of future work. 47 * 48 * - The PLX can map the either the board's RAM or host RAM 49 * into the MIPS's memory window. This would enable us to 50 * use less expensive (for us) memory reads/writes to host 51 * RAM, rather than time-consuming reads/writes to PCI 52 * memory space. However, the PLX can only map a 0-128M 53 * window, so we would have to ensure that the DMA address 54 * of the host RAM fits there. This is kind of a pain, 55 * so we just don't bother right now. 56 * 57 * - In a perfect world, we would use the autoconfiguration 58 * mechanism to attach the TTYs that we find. However, 59 * that leads to somewhat icky looking autoconfiguration 60 * messages (one for every TTY, up to 64 per board!). So 61 * we don't do it that way, but assign minors as if there 62 * were the max of 64 ports per board. 63 * 64 * - We don't bother with PPS support here. There are so many 65 * ports, each with a large amount of buffer space, that the 66 * normal mode of operation is to poll the boards regularly 67 * (generally, every 20ms or so). This makes this driver 68 * unsuitable for PPS, as the latency will be generally too 69 * high. 70 */ 71 /* 72 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 73 * for FreeBSD 3.2. 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/proc.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/tty.h> 82 #include <sys/conf.h> 83 #include <sys/time.h> 84 #include <sys/kernel.h> 85 #include <sys/fcntl.h> 86 #include <sys/syslog.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 #include <dev/pci/czreg.h> 92 93 #include <dev/pci/plx9060reg.h> 94 #include <dev/pci/plx9060var.h> 95 96 #include <dev/microcode/cyclades/cyzfirm.h> 97 98 #define CZ_DRIVER_VERSION 0x20000411 99 100 #define CZ_POLL_MS 20 101 102 /* These are the interrupts we always use. */ 103 #define CZ_INTERRUPTS \ 104 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 105 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 106 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 107 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 108 109 /* 110 * cztty_softc: 111 * 112 * Per-channel (TTY) state. 113 */ 114 struct cztty_softc { 115 struct cz_softc *sc_parent; 116 struct tty *sc_tty; 117 118 struct timeout sc_diag_to; 119 120 int sc_channel; /* Also used to flag unattached chan */ 121 #define CZTTY_CHANNEL_DEAD -1 122 123 bus_space_tag_t sc_chan_st; /* channel space tag */ 124 bus_space_handle_t sc_chan_sh; /* channel space handle */ 125 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 126 127 u_int sc_overflows, 128 sc_parity_errors, 129 sc_framing_errors, 130 sc_errors; 131 132 int sc_swflags; 133 134 u_int32_t sc_rs_control_dtr, 135 sc_chanctl_hw_flow, 136 sc_chanctl_comm_baud, 137 sc_chanctl_rs_control, 138 sc_chanctl_comm_data_l, 139 sc_chanctl_comm_parity; 140 }; 141 142 /* 143 * cz_softc: 144 * 145 * Per-board state. 146 */ 147 struct cz_softc { 148 struct device cz_dev; /* generic device info */ 149 struct plx9060_config cz_plx; /* PLX 9060 config info */ 150 bus_space_tag_t cz_win_st; /* window space tag */ 151 bus_space_handle_t cz_win_sh; /* window space handle */ 152 struct timeout cz_timeout; /* timeout for polling-mode */ 153 154 void *cz_ih; /* interrupt handle */ 155 156 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 157 int cz_nchannels; /* number of channels */ 158 int cz_nopenchan; /* number of open channels */ 159 struct cztty_softc *cz_ports; /* our array of ports */ 160 161 bus_addr_t cz_fwctl; /* offset of firmware control */ 162 }; 163 164 int cz_match(struct device *, void *, void *); 165 void cz_attach(struct device *, struct device *, void *); 166 int cz_wait_pci_doorbell(struct cz_softc *, char *); 167 168 struct cfattach cz_ca = { 169 sizeof(struct cz_softc), cz_match, cz_attach 170 }; 171 172 void cz_reset_board(struct cz_softc *); 173 int cz_load_firmware(struct cz_softc *); 174 175 int cz_intr(void *); 176 void cz_poll(void *); 177 int cztty_transmit(struct cztty_softc *, struct tty *); 178 int cztty_receive(struct cztty_softc *, struct tty *); 179 180 struct cztty_softc * cztty_getttysoftc(dev_t dev); 181 int cztty_findmajor(void); 182 int cztty_major; 183 int cztty_attached_ttys; 184 int cz_timeout_ticks; 185 186 cdev_decl(cztty); 187 188 void czttystart(struct tty *tp); 189 int czttyparam(struct tty *tp, struct termios *t); 190 void cztty_shutdown(struct cztty_softc *sc); 191 void cztty_modem(struct cztty_softc *sc, int onoff); 192 void cztty_break(struct cztty_softc *sc, int onoff); 193 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 194 int cztty_to_tiocm(struct cztty_softc *sc); 195 void cztty_diag(void *arg); 196 197 struct cfdriver cz_cd = { 198 0, "cz", DV_TTY 199 }; 200 201 /* Macros to clear/set/test flags. */ 202 #define SET(t, f) (t) |= (f) 203 #define CLR(t, f) (t) &= ~(f) 204 #define ISSET(t, f) ((t) & (f)) 205 206 /* 207 * Macros to read and write the PLX. 208 */ 209 #define CZ_PLX_READ(cz, reg) \ 210 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 211 #define CZ_PLX_WRITE(cz, reg, val) \ 212 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 213 (reg), (val)) 214 215 /* 216 * Macros to read and write the FPGA. We must already be in the FPGA 217 * window for this. 218 */ 219 #define CZ_FPGA_READ(cz, reg) \ 220 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 221 #define CZ_FPGA_WRITE(cz, reg, val) \ 222 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 223 224 /* 225 * Macros to read and write the firmware control structures in board RAM. 226 */ 227 #define CZ_FWCTL_READ(cz, off) \ 228 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 229 (cz)->cz_fwctl + (off)) 230 231 #define CZ_FWCTL_WRITE(cz, off, val) \ 232 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 233 (cz)->cz_fwctl + (off), (val)) 234 235 /* 236 * Convenience macros for cztty routines. PLX window MUST be to RAM. 237 */ 238 #define CZTTY_CHAN_READ(sc, off) \ 239 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 240 241 #define CZTTY_CHAN_WRITE(sc, off, val) \ 242 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 243 (off), (val)) 244 245 #define CZTTY_BUF_READ(sc, off) \ 246 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 247 248 #define CZTTY_BUF_WRITE(sc, off, val) \ 249 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 250 (off), (val)) 251 252 /* 253 * Convenience macros. 254 */ 255 #define CZ_WIN_RAM(cz) \ 256 do { \ 257 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 258 delay(100); \ 259 } while (0) 260 261 #define CZ_WIN_FPGA(cz) \ 262 do { \ 263 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 264 delay(100); \ 265 } while (0) 266 267 /***************************************************************************** 268 * Cyclades-Z controller code starts here... 269 *****************************************************************************/ 270 271 /* 272 * cz_match: 273 * 274 * Determine if the given PCI device is a Cyclades-Z board. 275 */ 276 int 277 cz_match(parent, match, aux) 278 struct device *parent; 279 void *match, *aux; 280 { 281 struct pci_attach_args *pa = aux; 282 283 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 284 switch (PCI_PRODUCT(pa->pa_id)) { 285 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 286 return (1); 287 } 288 } 289 290 return (0); 291 } 292 293 /* 294 * cz_attach: 295 * 296 * A Cyclades-Z board was found; attach it. 297 */ 298 void 299 cz_attach(parent, self, aux) 300 struct device *parent, *self; 301 void *aux; 302 { 303 struct cz_softc *cz = (void *) self; 304 struct pci_attach_args *pa = aux; 305 pci_chipset_tag_t pc = pa->pa_pc; 306 pci_intr_handle_t ih; 307 const char *intrstr = NULL; 308 struct cztty_softc *sc; 309 struct tty *tp; 310 int i; 311 312 printf(": Cyclades-Z multiport serial\n"); 313 314 cz->cz_plx.plx_pc = pa->pa_pc; 315 cz->cz_plx.plx_tag = pa->pa_tag; 316 317 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 318 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 319 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL, 0) != 0) { 320 printf("%s: unable to map PLX registers\n", 321 cz->cz_dev.dv_xname); 322 return; 323 } 324 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 325 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 326 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL, 0) != 0) { 327 printf("%s: unable to map device window\n", 328 cz->cz_dev.dv_xname); 329 return; 330 } 331 332 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 333 cz->cz_nopenchan = 0; 334 335 /* 336 * Make sure that the board is completely stopped. 337 */ 338 CZ_WIN_FPGA(cz); 339 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 340 341 /* 342 * Load the board's firmware. 343 */ 344 if (cz_load_firmware(cz) != 0) 345 return; 346 347 /* 348 * Now that we're ready to roll, map and establish the interrupt 349 * handler. 350 */ 351 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 352 pa->pa_intrline, &ih) != 0) { 353 /* 354 * The common case is for Cyclades-Z boards to run 355 * in polling mode, and thus not have an interrupt 356 * mapped for them. Don't bother reporting that 357 * the interrupt is not mappable, since this isn't 358 * really an error. 359 */ 360 cz->cz_ih = NULL; 361 goto polling_mode; 362 } else { 363 intrstr = pci_intr_string(pa->pa_pc, ih); 364 cz->cz_ih = pci_intr_establish(pc, ih, IPL_TTY, 365 cz_intr, cz, cz->cz_dev.dv_xname); 366 } 367 if (cz->cz_ih == NULL) { 368 printf("%s: unable to establish interrupt", 369 cz->cz_dev.dv_xname); 370 if (intrstr != NULL) 371 printf(" at %s", intrstr); 372 printf("\n"); 373 /* We will fall-back on polling mode. */ 374 } else 375 printf("%s: interrupting at %s\n", 376 cz->cz_dev.dv_xname, intrstr); 377 378 polling_mode: 379 if (cz->cz_ih == NULL) { 380 timeout_set(&cz->cz_timeout, cz_poll, cz); 381 if (cz_timeout_ticks == 0) 382 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 383 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 384 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 385 cz_timeout_ticks == 1 ? "" : "s"); 386 } 387 388 if (cztty_major == 0) 389 cztty_major = cztty_findmajor(); 390 /* 391 * Allocate sufficient pointers for the children and 392 * attach them. Set all ports to a reasonable initial 393 * configuration while we're at it: 394 * 395 * disabled 396 * 8N1 397 * default baud rate 398 * hardware flow control. 399 */ 400 CZ_WIN_RAM(cz); 401 402 if (cz->cz_nchannels == 0) { 403 /* No channels? No more work to do! */ 404 return; 405 } 406 407 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 408 M_DEVBUF, M_WAITOK); 409 cztty_attached_ttys += cz->cz_nchannels; 410 memset(cz->cz_ports, 0, 411 sizeof(struct cztty_softc) * cz->cz_nchannels); 412 413 for (i = 0; i < cz->cz_nchannels; i++) { 414 sc = &cz->cz_ports[i]; 415 416 sc->sc_channel = i; 417 sc->sc_chan_st = cz->cz_win_st; 418 sc->sc_parent = cz; 419 420 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 421 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 422 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 423 printf("%s: unable to subregion channel %d control\n", 424 cz->cz_dev.dv_xname, i); 425 sc->sc_channel = CZTTY_CHANNEL_DEAD; 426 continue; 427 } 428 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 429 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 430 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 431 printf("%s: unable to subregion channel %d buffer\n", 432 cz->cz_dev.dv_xname, i); 433 sc->sc_channel = CZTTY_CHANNEL_DEAD; 434 continue; 435 } 436 437 timeout_set(&sc->sc_diag_to, cztty_diag, sc); 438 439 tp = ttymalloc(); 440 tp->t_dev = makedev(cztty_major, 441 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 442 tp->t_oproc = czttystart; 443 tp->t_param = czttyparam; 444 tty_attach(tp); 445 446 sc->sc_tty = tp; 447 448 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 451 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 452 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 453 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 454 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 456 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 457 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 458 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 459 } 460 } 461 462 /* 463 * cz_reset_board: 464 * 465 * Reset the board via the PLX. 466 */ 467 void 468 cz_reset_board(struct cz_softc *cz) 469 { 470 u_int32_t reg; 471 472 reg = CZ_PLX_READ(cz, PLX_CONTROL); 473 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 474 delay(1000); 475 476 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 477 delay(1000); 478 479 /* Now reload the PLX from its EEPROM. */ 480 reg = CZ_PLX_READ(cz, PLX_CONTROL); 481 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 482 delay(1000); 483 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 484 } 485 486 /* 487 * cz_load_firmware: 488 * 489 * Load the ZFIRM firmware into the board's RAM and start it 490 * running. 491 */ 492 int 493 cz_load_firmware(struct cz_softc *cz) 494 { 495 struct zfirm_header *zfh; 496 struct zfirm_config *zfc; 497 struct zfirm_block *zfb, *zblocks; 498 const u_int8_t *cp; 499 const char *board; 500 u_int32_t fid; 501 int i, j, nconfigs, nblocks, nbytes; 502 503 zfh = (struct zfirm_header *) cycladesz_firmware; 504 505 /* Find the config header. */ 506 if (letoh32(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 507 printf("%s: bad ZFIRM config offset: 0x%x\n", 508 cz->cz_dev.dv_xname, letoh32(zfh->zfh_configoff)); 509 return (EIO); 510 } 511 zfc = (struct zfirm_config *)(cycladesz_firmware + 512 letoh32(zfh->zfh_configoff)); 513 nconfigs = letoh32(zfh->zfh_nconfig); 514 515 /* Locate the correct configuration for our board. */ 516 for (i = 0; i < nconfigs; i++, zfc++) { 517 if (letoh32(zfc->zfc_mailbox) == cz->cz_mailbox0 && 518 letoh32(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 519 break; 520 } 521 if (i == nconfigs) { 522 printf("%s: unable to locate config header\n", 523 cz->cz_dev.dv_xname); 524 return (EIO); 525 } 526 527 nblocks = letoh32(zfc->zfc_nblocks); 528 zblocks = (struct zfirm_block *)(cycladesz_firmware + 529 letoh32(zfh->zfh_blockoff)); 530 531 /* 532 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 533 * necessary. 534 */ 535 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 536 #if 0 537 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 538 #endif 539 ) { 540 #ifdef CZ_DEBUG 541 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 542 #endif 543 CZ_WIN_FPGA(cz); 544 for (i = 0; i < nblocks; i++) { 545 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 546 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 547 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FPGA) { 548 nbytes = letoh32(zfb->zfb_size); 549 cp = &cycladesz_firmware[ 550 letoh32(zfb->zfb_fileoff)]; 551 for (j = 0; j < nbytes; j++, cp++) { 552 bus_space_write_1(cz->cz_win_st, 553 cz->cz_win_sh, 0, *cp); 554 /* FPGA needs 30-100us to settle. */ 555 delay(10); 556 } 557 } 558 } 559 #ifdef CZ_DEBUG 560 printf("done\n"); 561 #endif 562 } 563 564 /* Now load the firmware. */ 565 CZ_WIN_RAM(cz); 566 567 for (i = 0; i < nblocks; i++) { 568 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 569 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 570 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 571 const u_int32_t *lp; 572 u_int32_t ro = letoh32(zfb->zfb_ramoff); 573 nbytes = letoh32(zfb->zfb_size); 574 lp = (const u_int32_t *) 575 &cycladesz_firmware[letoh32(zfb->zfb_fileoff)]; 576 for (j = 0; j < nbytes; j += 4, lp++) { 577 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 578 ro + j, letoh32(*lp)); 579 delay(10); 580 } 581 } 582 } 583 584 /* Now restart the MIPS. */ 585 CZ_WIN_FPGA(cz); 586 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 587 588 /* Wait for the MIPS to start, then report the results. */ 589 CZ_WIN_RAM(cz); 590 591 #ifdef CZ_DEBUG 592 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 593 #endif 594 for (i = 0; i < 100; i++) { 595 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 596 ZFIRM_SIG_OFF); 597 if (fid == ZFIRM_SIG) { 598 /* MIPS has booted. */ 599 break; 600 } else if (fid == ZFIRM_HLT) { 601 /* 602 * The MIPS has halted, usually due to a power 603 * shortage on the expansion module. 604 */ 605 printf("%s: MIPS halted; possible power supply " 606 "problem\n", cz->cz_dev.dv_xname); 607 return (EIO); 608 } else { 609 #ifdef CZ_DEBUG 610 if ((i % 8) == 0) 611 printf("."); 612 #endif 613 delay(250000); 614 } 615 } 616 #ifdef CZ_DEBUG 617 printf("\n"); 618 #endif 619 if (i == 100) { 620 CZ_WIN_FPGA(cz); 621 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 622 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 623 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 624 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 625 CZ_FPGA_READ(cz, FPGA_VERSION)); 626 return (EIO); 627 } 628 629 /* 630 * Locate the firmware control structures. 631 */ 632 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 633 ZFIRM_CTRLADDR_OFF); 634 #ifdef CZ_DEBUG 635 printf("%s: FWCTL structure at offset 0x%08lx\n", 636 cz->cz_dev.dv_xname, cz->cz_fwctl); 637 #endif 638 639 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 640 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 641 642 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 643 644 switch (cz->cz_mailbox0) { 645 case MAILBOX0_8Zo_V1: 646 board = "Cyclades-8Zo ver. 1"; 647 break; 648 649 case MAILBOX0_8Zo_V2: 650 board = "Cyclades-8Zo ver. 2"; 651 break; 652 653 case MAILBOX0_Ze_V1: 654 board = "Cyclades-Ze"; 655 break; 656 657 default: 658 board = "unknown Cyclades Z-series"; 659 break; 660 } 661 662 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 663 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 664 if (cz->cz_nchannels == 0) 665 printf("no channels attached, "); 666 else 667 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 668 cz->cz_nchannels, cztty_attached_ttys, 669 cztty_attached_ttys + (cz->cz_nchannels - 1)); 670 printf("firmware %x.%x.%x\n", 671 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 672 673 return (0); 674 } 675 676 /* 677 * cz_poll: 678 * 679 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 680 * ms. 681 */ 682 void 683 cz_poll(void *arg) 684 { 685 int s = spltty(); 686 struct cz_softc *cz = arg; 687 688 cz_intr(cz); 689 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 690 691 splx(s); 692 } 693 694 /* 695 * cz_intr: 696 * 697 * Interrupt service routine. 698 * 699 * We either are receiving an interrupt directly from the board, or we are 700 * in polling mode and it's time to poll. 701 */ 702 int 703 cz_intr(void *arg) 704 { 705 int rval = 0; 706 u_int command, channel, param; 707 struct cz_softc *cz = arg; 708 struct cztty_softc *sc; 709 struct tty *tp; 710 711 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 712 rval = 1; 713 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 714 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 715 716 /* now clear this interrupt, posslibly enabling another */ 717 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 718 719 if (cz->cz_ports == NULL) { 720 #ifdef CZ_DEBUG 721 printf("%s: interrupt on channel %d, but no channels\n", 722 cz->cz_dev.dv_xname, channel); 723 #endif 724 continue; 725 } 726 727 sc = &cz->cz_ports[channel]; 728 729 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 730 break; 731 732 tp = sc->sc_tty; 733 734 switch (command) { 735 case C_CM_TXFEMPTY: /* transmit cases */ 736 case C_CM_TXBEMPTY: 737 case C_CM_TXLOWWM: 738 case C_CM_INTBACK: 739 if (!ISSET(tp->t_state, TS_ISOPEN)) { 740 #ifdef CZ_DEBUG 741 printf("%s: tx intr on closed channel %d\n", 742 cz->cz_dev.dv_xname, channel); 743 #endif 744 break; 745 } 746 747 if (cztty_transmit(sc, tp)) { 748 /* 749 * Do wakeup stuff here. 750 */ 751 ttwakeup(tp); 752 wakeup(tp); 753 } 754 break; 755 756 case C_CM_RXNNDT: /* receive cases */ 757 case C_CM_RXHIWM: 758 case C_CM_INTBACK2: /* from restart ?? */ 759 #if 0 760 case C_CM_ICHAR: 761 #endif 762 if (!ISSET(tp->t_state, TS_ISOPEN)) { 763 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 764 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 765 break; 766 } 767 768 if (cztty_receive(sc, tp)) { 769 /* 770 * Do wakeup stuff here. 771 */ 772 ttwakeup(tp); 773 wakeup(tp); 774 } 775 break; 776 777 case C_CM_MDCD: 778 if (!ISSET(tp->t_state, TS_ISOPEN)) 779 break; 780 781 (void) (*linesw[tp->t_line].l_modem)(tp, 782 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 783 CHNCTL_RS_STATUS))); 784 break; 785 786 case C_CM_MDSR: 787 case C_CM_MRI: 788 case C_CM_MCTS: 789 case C_CM_MRTS: 790 break; 791 792 case C_CM_IOCTLW: 793 break; 794 795 case C_CM_PR_ERROR: 796 sc->sc_parity_errors++; 797 goto error_common; 798 799 case C_CM_FR_ERROR: 800 sc->sc_framing_errors++; 801 goto error_common; 802 803 case C_CM_OVR_ERROR: 804 sc->sc_overflows++; 805 error_common: 806 if (sc->sc_errors++ == 0) 807 timeout_add(&sc->sc_diag_to, 60 * hz); 808 break; 809 810 case C_CM_RXBRK: 811 if (!ISSET(tp->t_state, TS_ISOPEN)) 812 break; 813 814 /* 815 * A break is a \000 character with TTY_FE error 816 * flags set. So TTY_FE by itself works. 817 */ 818 (*linesw[tp->t_line].l_rint)(TTY_FE, tp); 819 ttwakeup(tp); 820 wakeup(tp); 821 break; 822 823 default: 824 #ifdef CZ_DEBUG 825 printf("%s: channel %d: Unknown interrupt 0x%x\n", 826 cz->cz_dev.dv_xname, sc->sc_channel, command); 827 #endif 828 break; 829 } 830 } 831 832 return (rval); 833 } 834 835 /* 836 * cz_wait_pci_doorbell: 837 * 838 * Wait for the pci doorbell to be clear - wait for pending 839 * activity to drain. 840 */ 841 int 842 cz_wait_pci_doorbell(struct cz_softc *cz, char *wstring) 843 { 844 int error; 845 846 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 847 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 848 if ((error != 0) && (error != EWOULDBLOCK)) 849 return (error); 850 } 851 return (0); 852 } 853 854 /***************************************************************************** 855 * Cyclades-Z TTY code starts here... 856 *****************************************************************************/ 857 858 #define CZTTYDIALOUT_MASK 0x80000 859 860 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 861 #define CZTTY_CZ(sc) ((sc)->sc_parent) 862 863 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 864 865 struct cztty_softc * 866 cztty_getttysoftc(dev_t dev) 867 { 868 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 869 struct cz_softc *cz; 870 871 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 872 k = j; 873 cz = (struct cz_softc *)device_lookup(&cz_cd, i); 874 if (cz == NULL) 875 continue; 876 if (cz->cz_ports == NULL) 877 continue; 878 j += cz->cz_nchannels; 879 if (j > u) 880 break; 881 } 882 883 if (i >= cz_cd.cd_ndevs) 884 return (NULL); 885 else 886 return (&cz->cz_ports[u - k]); 887 } 888 889 int 890 cztty_findmajor(void) 891 { 892 int maj; 893 894 for (maj = 0; maj < nchrdev; maj++) { 895 if (cdevsw[maj].d_open == czttyopen) 896 break; 897 } 898 899 return (maj == nchrdev) ? 0 : maj; 900 } 901 902 /* 903 * czttytty: 904 * 905 * Return a pointer to our tty. 906 */ 907 struct tty * 908 czttytty(dev_t dev) 909 { 910 struct cztty_softc *sc = CZTTY_SOFTC(dev); 911 912 #ifdef DIAGNOSTIC 913 if (sc == NULL) 914 panic("czttytty"); 915 #endif 916 917 return (sc->sc_tty); 918 } 919 920 /* 921 * cztty_shutdown: 922 * 923 * Shut down a port. 924 */ 925 void 926 cztty_shutdown(struct cztty_softc *sc) 927 { 928 struct cz_softc *cz = CZTTY_CZ(sc); 929 struct tty *tp = sc->sc_tty; 930 int s; 931 932 s = spltty(); 933 934 /* Clear any break condition set with TIOCSBRK. */ 935 cztty_break(sc, 0); 936 937 /* 938 * Hang up if necessary. Wait a bit, so the other side has time to 939 * notice even if we immediately open the port again. 940 */ 941 if (ISSET(tp->t_cflag, HUPCL)) { 942 cztty_modem(sc, 0); 943 (void) tsleep(tp, TTIPRI, ttclos, hz); 944 } 945 946 /* Disable the channel. */ 947 cz_wait_pci_doorbell(cz, "czdis"); 948 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 949 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 950 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 951 952 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 953 #ifdef CZ_DEBUG 954 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 955 #endif 956 timeout_del(&cz->cz_timeout); 957 } 958 959 splx(s); 960 } 961 962 /* 963 * czttyopen: 964 * 965 * Open a Cyclades-Z serial port. 966 */ 967 int 968 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 969 { 970 struct cztty_softc *sc = CZTTY_SOFTC(dev); 971 struct cz_softc *cz; 972 struct tty *tp; 973 int s, error; 974 975 if (sc == NULL) 976 return (ENXIO); 977 978 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 979 return (ENXIO); 980 981 cz = CZTTY_CZ(sc); 982 tp = sc->sc_tty; 983 984 if (ISSET(tp->t_state, TS_ISOPEN) && 985 ISSET(tp->t_state, TS_XCLUDE) && 986 p->p_ucred->cr_uid != 0) 987 return (EBUSY); 988 989 s = spltty(); 990 991 /* 992 * Do the following iff this is a first open. 993 */ 994 if (!ISSET(tp->t_state, TS_ISOPEN)) { 995 struct termios t; 996 997 tp->t_dev = dev; 998 999 /* If we're turning things on, enable interrupts */ 1000 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 1001 #ifdef CZ_DEBUG 1002 printf("%s: Enabling polling.\n", 1003 cz->cz_dev.dv_xname); 1004 #endif 1005 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 1006 } 1007 1008 /* 1009 * Enable the channel. Don't actually ring the 1010 * doorbell here; czttyparam() will do it for us. 1011 */ 1012 cz_wait_pci_doorbell(cz, "czopen"); 1013 1014 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1015 1016 /* 1017 * Initialize the termios status to the defaults. Add in the 1018 * sticky bits from TIOCSFLAGS. 1019 */ 1020 t.c_ispeed = 0; 1021 t.c_ospeed = TTYDEF_SPEED; 1022 t.c_cflag = TTYDEF_CFLAG; 1023 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1024 SET(t.c_cflag, CLOCAL); 1025 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1026 SET(t.c_cflag, CRTSCTS); 1027 1028 /* 1029 * Reset the input and output rings. Do this before 1030 * we call czttyparam(), as that function enables 1031 * the channel. 1032 */ 1033 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1034 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1035 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1036 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1037 1038 /* Make sure czttyparam() will see changes. */ 1039 tp->t_ospeed = 0; 1040 (void) czttyparam(tp, &t); 1041 tp->t_iflag = TTYDEF_IFLAG; 1042 tp->t_oflag = TTYDEF_OFLAG; 1043 tp->t_lflag = TTYDEF_LFLAG; 1044 ttychars(tp); 1045 ttsetwater(tp); 1046 1047 /* 1048 * Turn on DTR. We must always do this, even if carrier is not 1049 * present, because otherwise we'd have to use TIOCSDTR 1050 * immediately after setting CLOCAL, which applications do not 1051 * expect. We always assert DTR while the device is open 1052 * unless explicitly requested to deassert it. 1053 */ 1054 cztty_modem(sc, 1); 1055 } 1056 1057 splx(s); 1058 1059 error = ttyopen(CZTTY_DIALOUT(dev), tp); 1060 if (error) 1061 goto bad; 1062 1063 error = (*linesw[tp->t_line].l_open)(dev, tp); 1064 if (error) 1065 goto bad; 1066 1067 return (0); 1068 1069 bad: 1070 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1071 /* 1072 * We failed to open the device, and nobody else had it opened. 1073 * Clean up the state as appropriate. 1074 */ 1075 cztty_shutdown(sc); 1076 } 1077 1078 return (error); 1079 } 1080 1081 /* 1082 * czttyclose: 1083 * 1084 * Close a Cyclades-Z serial port. 1085 */ 1086 int 1087 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1088 { 1089 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1090 struct tty *tp = sc->sc_tty; 1091 1092 /* XXX This is for cons.c. */ 1093 if (!ISSET(tp->t_state, TS_ISOPEN)) 1094 return (0); 1095 1096 (*linesw[tp->t_line].l_close)(tp, flags); 1097 ttyclose(tp); 1098 1099 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1100 /* 1101 * Although we got a last close, the device may still be in 1102 * use; e.g. if this was the dialout node, and there are still 1103 * processes waiting for carrier on the non-dialout node. 1104 */ 1105 cztty_shutdown(sc); 1106 } 1107 1108 return (0); 1109 } 1110 1111 /* 1112 * czttyread: 1113 * 1114 * Read from a Cyclades-Z serial port. 1115 */ 1116 int 1117 czttyread(dev_t dev, struct uio *uio, int flags) 1118 { 1119 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1120 struct tty *tp = sc->sc_tty; 1121 1122 return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); 1123 } 1124 1125 /* 1126 * czttywrite: 1127 * 1128 * Write to a Cyclades-Z serial port. 1129 */ 1130 int 1131 czttywrite(dev_t dev, struct uio *uio, int flags) 1132 { 1133 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1134 struct tty *tp = sc->sc_tty; 1135 1136 return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); 1137 } 1138 1139 #if 0 1140 /* 1141 * czttypoll: 1142 * 1143 * Poll a Cyclades-Z serial port. 1144 */ 1145 int 1146 czttypoll(dev_t dev, int events, struct proc p) 1147 { 1148 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1149 struct tty *tp = sc->sc_tty; 1150 1151 return ((*linesw[tp->t_line].l_poll)(tp, events, p)); 1152 } 1153 #endif 1154 1155 /* 1156 * czttyioctl: 1157 * 1158 * Perform a control operation on a Cyclades-Z serial port. 1159 */ 1160 int 1161 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1162 { 1163 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1164 struct tty *tp = sc->sc_tty; 1165 int s, error; 1166 1167 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1168 if (error >= 0) 1169 return (error); 1170 1171 error = ttioctl(tp, cmd, data, flag, p); 1172 if (error >= 0) 1173 return (error); 1174 1175 error = 0; 1176 1177 s = spltty(); 1178 1179 switch (cmd) { 1180 case TIOCSBRK: 1181 cztty_break(sc, 1); 1182 break; 1183 1184 case TIOCCBRK: 1185 cztty_break(sc, 0); 1186 break; 1187 1188 case TIOCGFLAGS: 1189 *(int *)data = sc->sc_swflags; 1190 break; 1191 1192 case TIOCSFLAGS: 1193 error = suser(p->p_ucred, &p->p_acflag); 1194 if (error) 1195 break; 1196 sc->sc_swflags = *(int *)data; 1197 break; 1198 1199 case TIOCSDTR: 1200 cztty_modem(sc, 1); 1201 break; 1202 1203 case TIOCCDTR: 1204 cztty_modem(sc, 0); 1205 break; 1206 1207 case TIOCMSET: 1208 case TIOCMBIS: 1209 case TIOCMBIC: 1210 tiocm_to_cztty(sc, cmd, *(int *)data); 1211 break; 1212 1213 case TIOCMGET: 1214 *(int *)data = cztty_to_tiocm(sc); 1215 break; 1216 1217 default: 1218 error = ENOTTY; 1219 break; 1220 } 1221 1222 splx(s); 1223 1224 return (error); 1225 } 1226 1227 /* 1228 * cztty_break: 1229 * 1230 * Set or clear BREAK on a port. 1231 */ 1232 void 1233 cztty_break(struct cztty_softc *sc, int onoff) 1234 { 1235 struct cz_softc *cz = CZTTY_CZ(sc); 1236 1237 cz_wait_pci_doorbell(cz, "czbreak"); 1238 1239 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1240 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1241 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1242 } 1243 1244 /* 1245 * cztty_modem: 1246 * 1247 * Set or clear DTR on a port. 1248 */ 1249 void 1250 cztty_modem(struct cztty_softc *sc, int onoff) 1251 { 1252 struct cz_softc *cz = CZTTY_CZ(sc); 1253 1254 if (sc->sc_rs_control_dtr == 0) 1255 return; 1256 1257 cz_wait_pci_doorbell(cz, "czmod"); 1258 1259 if (onoff) 1260 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1261 else 1262 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1263 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1264 1265 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1266 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1267 } 1268 1269 /* 1270 * tiocm_to_cztty: 1271 * 1272 * Process TIOCM* ioctls. 1273 */ 1274 void 1275 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1276 { 1277 struct cz_softc *cz = CZTTY_CZ(sc); 1278 u_int32_t czttybits; 1279 1280 czttybits = 0; 1281 if (ISSET(ttybits, TIOCM_DTR)) 1282 SET(czttybits, C_RS_DTR); 1283 if (ISSET(ttybits, TIOCM_RTS)) 1284 SET(czttybits, C_RS_RTS); 1285 1286 cz_wait_pci_doorbell(cz, "cztiocm"); 1287 1288 switch (how) { 1289 case TIOCMBIC: 1290 CLR(sc->sc_chanctl_rs_control, czttybits); 1291 break; 1292 1293 case TIOCMBIS: 1294 SET(sc->sc_chanctl_rs_control, czttybits); 1295 break; 1296 1297 case TIOCMSET: 1298 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1299 SET(sc->sc_chanctl_rs_control, czttybits); 1300 break; 1301 } 1302 1303 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1304 1305 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1306 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1307 } 1308 1309 /* 1310 * cztty_to_tiocm: 1311 * 1312 * Process the TIOCMGET ioctl. 1313 */ 1314 int 1315 cztty_to_tiocm(struct cztty_softc *sc) 1316 { 1317 struct cz_softc *cz = CZTTY_CZ(sc); 1318 u_int32_t rs_status, op_mode; 1319 int ttybits = 0; 1320 1321 cz_wait_pci_doorbell(cz, "cztty"); 1322 1323 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1324 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1325 1326 if (ISSET(rs_status, C_RS_RTS)) 1327 SET(ttybits, TIOCM_RTS); 1328 if (ISSET(rs_status, C_RS_CTS)) 1329 SET(ttybits, TIOCM_CTS); 1330 if (ISSET(rs_status, C_RS_DCD)) 1331 SET(ttybits, TIOCM_CAR); 1332 if (ISSET(rs_status, C_RS_DTR)) 1333 SET(ttybits, TIOCM_DTR); 1334 if (ISSET(rs_status, C_RS_RI)) 1335 SET(ttybits, TIOCM_RNG); 1336 if (ISSET(rs_status, C_RS_DSR)) 1337 SET(ttybits, TIOCM_DSR); 1338 1339 if (ISSET(op_mode, C_CH_ENABLE)) 1340 SET(ttybits, TIOCM_LE); 1341 1342 return (ttybits); 1343 } 1344 1345 /* 1346 * czttyparam: 1347 * 1348 * Set Cyclades-Z serial port parameters from termios. 1349 * 1350 * XXX Should just copy the whole termios after making 1351 * XXX sure all the changes could be done. 1352 */ 1353 int 1354 czttyparam(struct tty *tp, struct termios *t) 1355 { 1356 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1357 struct cz_softc *cz = CZTTY_CZ(sc); 1358 u_int32_t rs_status; 1359 int ospeed, cflag; 1360 1361 ospeed = t->c_ospeed; 1362 cflag = t->c_cflag; 1363 1364 /* Check requested parameters. */ 1365 if (ospeed < 0) 1366 return (EINVAL); 1367 if (t->c_ispeed && t->c_ispeed != ospeed) 1368 return (EINVAL); 1369 1370 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1371 SET(cflag, CLOCAL); 1372 CLR(cflag, HUPCL); 1373 } 1374 1375 /* 1376 * If there were no changes, don't do anything. This avoids dropping 1377 * input and improves performance when all we did was frob things like 1378 * VMIN and VTIME. 1379 */ 1380 if (tp->t_ospeed == ospeed && 1381 tp->t_cflag == cflag) 1382 return (0); 1383 1384 /* Data bits. */ 1385 sc->sc_chanctl_comm_data_l = 0; 1386 switch (t->c_cflag & CSIZE) { 1387 case CS5: 1388 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1389 break; 1390 1391 case CS6: 1392 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1393 break; 1394 1395 case CS7: 1396 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1397 break; 1398 1399 case CS8: 1400 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1401 break; 1402 } 1403 1404 /* Stop bits. */ 1405 if (t->c_cflag & CSTOPB) { 1406 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1407 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1408 else 1409 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1410 } else 1411 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1412 1413 /* Parity. */ 1414 if (t->c_cflag & PARENB) { 1415 if (t->c_cflag & PARODD) 1416 sc->sc_chanctl_comm_parity = C_PR_ODD; 1417 else 1418 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1419 } else 1420 sc->sc_chanctl_comm_parity = C_PR_NONE; 1421 1422 /* 1423 * Initialize flow control pins depending on the current flow control 1424 * mode. 1425 */ 1426 if (ISSET(t->c_cflag, CRTSCTS)) { 1427 sc->sc_rs_control_dtr = C_RS_DTR; 1428 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1429 } else if (ISSET(t->c_cflag, MDMBUF)) { 1430 sc->sc_rs_control_dtr = 0; 1431 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1432 } else { 1433 /* 1434 * If no flow control, then always set RTS. This will make 1435 * the other side happy if it mistakenly thinks we're doing 1436 * RTS/CTS flow control. 1437 */ 1438 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1439 sc->sc_chanctl_hw_flow = 0; 1440 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1441 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1442 else 1443 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1444 } 1445 1446 /* Baud rate. */ 1447 sc->sc_chanctl_comm_baud = ospeed; 1448 1449 /* Copy to tty. */ 1450 tp->t_ispeed = 0; 1451 tp->t_ospeed = t->c_ospeed; 1452 tp->t_cflag = t->c_cflag; 1453 1454 /* 1455 * Now load the channel control structure. 1456 */ 1457 1458 cz_wait_pci_doorbell(cz, "czparam"); 1459 1460 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1461 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1462 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1463 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1464 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1465 1466 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1467 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1468 1469 cz_wait_pci_doorbell(cz, "czparam"); 1470 1471 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1472 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1473 1474 cz_wait_pci_doorbell(cz, "czparam"); 1475 1476 /* 1477 * Update the tty layer's idea of the carrier bit, in case we changed 1478 * CLOCAL. We don't hang up here; we only do that by explicit 1479 * request. 1480 */ 1481 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1482 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1483 1484 return (0); 1485 } 1486 1487 /* 1488 * czttystart: 1489 * 1490 * Start or restart transmission. 1491 */ 1492 void 1493 czttystart(struct tty *tp) 1494 { 1495 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1496 int s; 1497 1498 s = spltty(); 1499 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1500 goto out; 1501 1502 if (tp->t_outq.c_cc <= tp->t_lowat) { 1503 if (ISSET(tp->t_state, TS_ASLEEP)) { 1504 CLR(tp->t_state, TS_ASLEEP); 1505 wakeup(&tp->t_outq); 1506 } 1507 selwakeup(&tp->t_wsel); 1508 if (tp->t_outq.c_cc == 0) 1509 goto out; 1510 } 1511 1512 cztty_transmit(sc, tp); 1513 out: 1514 splx(s); 1515 } 1516 1517 /* 1518 * czttystop: 1519 * 1520 * Stop output, e.g., for ^S or output flush. 1521 */ 1522 int 1523 czttystop(struct tty *tp, int flag) 1524 { 1525 1526 /* 1527 * XXX We don't do anything here, yet. Mostly, I don't know 1528 * XXX exactly how this should be implemented on this device. 1529 * XXX We've given a big chunk of data to the MIPS already, 1530 * XXX and I don't know how we request the MIPS to stop sending 1531 * XXX the data. So, punt for now. --thorpej 1532 */ 1533 return (0); 1534 } 1535 1536 /* 1537 * cztty_diag: 1538 * 1539 * Issue a scheduled diagnostic message. 1540 */ 1541 void 1542 cztty_diag(void *arg) 1543 { 1544 struct cztty_softc *sc = arg; 1545 struct cz_softc *cz = CZTTY_CZ(sc); 1546 u_int overflows, parity_errors, framing_errors; 1547 int s; 1548 1549 s = spltty(); 1550 1551 overflows = sc->sc_overflows; 1552 sc->sc_overflows = 0; 1553 1554 parity_errors = sc->sc_parity_errors; 1555 sc->sc_parity_errors = 0; 1556 1557 framing_errors = sc->sc_framing_errors; 1558 sc->sc_framing_errors = 0; 1559 1560 sc->sc_errors = 0; 1561 1562 splx(s); 1563 1564 log(LOG_WARNING, 1565 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1566 cz->cz_dev.dv_xname, sc->sc_channel, 1567 overflows, overflows == 1 ? "" : "s", 1568 parity_errors, 1569 framing_errors, framing_errors == 1 ? "" : "s"); 1570 } 1571 1572 /* 1573 * tx and rx ring buffer size macros: 1574 * 1575 * The transmitter and receiver both use ring buffers. For each one, there 1576 * is a get (consumer) and a put (producer) offset. The get value is the 1577 * next byte to be read from the ring, and the put is the next one to be 1578 * put into the ring. get == put means the ring is empty. 1579 * 1580 * For each ring, the firmware controls one of (get, put) and this driver 1581 * controls the other. For transmission, this driver updates put to point 1582 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1583 * for receive, the driver controls put, and this driver controls get. 1584 */ 1585 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1586 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1587 1588 /* 1589 * cztty_transmit() 1590 * 1591 * Look at the tty for this port and start sending. 1592 */ 1593 int 1594 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1595 { 1596 struct cz_softc *cz = CZTTY_CZ(sc); 1597 u_int move, get, put, size, address; 1598 #ifdef HOSTRAMCODE 1599 int error, done = 0; 1600 #else 1601 int done = 0; 1602 #endif 1603 1604 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1605 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1606 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1607 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1608 1609 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1610 #ifdef HOSTRAMCODE 1611 if (0) { 1612 move = min(tp->t_outq.c_cc, move); 1613 error = q_to_b(&tp->t_outq, 0, move); 1614 if (error != move) { 1615 printf("%s: channel %d: error moving to " 1616 "transmit buf\n", cz->cz_dev.dv_xname, 1617 sc->sc_channel); 1618 move = error; 1619 } 1620 } else { 1621 #endif 1622 move = min(ndqb(&tp->t_outq, 0), move); 1623 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1624 address + put, tp->t_outq.c_cf, move); 1625 ndflush(&tp->t_outq, move); 1626 #ifdef HOSTRAMCODE 1627 } 1628 #endif 1629 1630 put = ((put + move) % size); 1631 done = 1; 1632 } 1633 if (done) { 1634 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1635 } 1636 return (done); 1637 } 1638 1639 int 1640 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1641 { 1642 struct cz_softc *cz = CZTTY_CZ(sc); 1643 u_int get, put, size, address; 1644 int done = 0, ch; 1645 1646 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1647 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1648 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1649 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1650 1651 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1652 #ifdef HOSTRAMCODE 1653 if (hostram) 1654 ch = ((char *)fifoaddr)[get]; 1655 } else { 1656 #endif 1657 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1658 address + get); 1659 #ifdef HOSTRAMCODE 1660 } 1661 #endif 1662 (*linesw[tp->t_line].l_rint)(ch, tp); 1663 get = (get + 1) % size; 1664 done = 1; 1665 } 1666 if (done) { 1667 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1668 } 1669 return (done); 1670 } 1671