1 /* $OpenBSD: cz.c,v 1.4 2001/09/04 04:01:42 nate Exp $ */ 2 /* $NetBSD: cz.c,v 1.15 2001/01/20 19:10:36 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Zembu Labs, Inc. 6 * All rights reserved. 7 * 8 * Authors: Jason R. Thorpe <thorpej@zembu.com> 9 * Bill Studenmund <wrstuden@zembu.com> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Zembu Labs, Inc. 22 * 4. Neither the name of Zembu Labs nor the names of its employees may 23 * be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 27 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 28 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 29 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 40 * 41 * Some notes: 42 * 43 * - The Cyclades-Z has fully automatic hardware (and software!) 44 * flow control. We only utilize RTS/CTS flow control here, 45 * and it is implemented in a very simplistic manner. This 46 * may be an area of future work. 47 * 48 * - The PLX can map the either the board's RAM or host RAM 49 * into the MIPS's memory window. This would enable us to 50 * use less expensive (for us) memory reads/writes to host 51 * RAM, rather than time-consuming reads/writes to PCI 52 * memory space. However, the PLX can only map a 0-128M 53 * window, so we would have to ensure that the DMA address 54 * of the host RAM fits there. This is kind of a pain, 55 * so we just don't bother right now. 56 * 57 * - In a perfect world, we would use the autoconfiguration 58 * mechanism to attach the TTYs that we find. However, 59 * that leads to somewhat icky looking autoconfiguration 60 * messages (one for every TTY, up to 64 per board!). So 61 * we don't do it that way, but assign minors as if there 62 * were the max of 64 ports per board. 63 * 64 * - We don't bother with PPS support here. There are so many 65 * ports, each with a large amount of buffer space, that the 66 * normal mode of operation is to poll the boards regularly 67 * (generally, every 20ms or so). This makes this driver 68 * unsuitable for PPS, as the latency will be generally too 69 * high. 70 */ 71 /* 72 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 73 * for FreeBSD 3.2. 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/proc.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/tty.h> 82 #include <sys/conf.h> 83 #include <sys/time.h> 84 #include <sys/kernel.h> 85 #include <sys/fcntl.h> 86 #include <sys/syslog.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 #include <dev/pci/czreg.h> 92 93 #include <dev/pci/plx9060reg.h> 94 #include <dev/pci/plx9060var.h> 95 96 #include <dev/microcode/cyclades/cyzfirm.h> 97 98 #define CZ_DRIVER_VERSION 0x20000411 99 100 #define CZ_POLL_MS 20 101 102 /* These are the interrupts we always use. */ 103 #define CZ_INTERRUPTS \ 104 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 105 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 106 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 107 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 108 109 /* 110 * cztty_softc: 111 * 112 * Per-channel (TTY) state. 113 */ 114 struct cztty_softc { 115 struct cz_softc *sc_parent; 116 struct tty *sc_tty; 117 118 struct timeout sc_diag_to; 119 120 int sc_channel; /* Also used to flag unattached chan */ 121 #define CZTTY_CHANNEL_DEAD -1 122 123 bus_space_tag_t sc_chan_st; /* channel space tag */ 124 bus_space_handle_t sc_chan_sh; /* channel space handle */ 125 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 126 127 u_int sc_overflows, 128 sc_parity_errors, 129 sc_framing_errors, 130 sc_errors; 131 132 int sc_swflags; 133 134 u_int32_t sc_rs_control_dtr, 135 sc_chanctl_hw_flow, 136 sc_chanctl_comm_baud, 137 sc_chanctl_rs_control, 138 sc_chanctl_comm_data_l, 139 sc_chanctl_comm_parity; 140 }; 141 142 /* 143 * cz_softc: 144 * 145 * Per-board state. 146 */ 147 struct cz_softc { 148 struct device cz_dev; /* generic device info */ 149 struct plx9060_config cz_plx; /* PLX 9060 config info */ 150 bus_space_tag_t cz_win_st; /* window space tag */ 151 bus_space_handle_t cz_win_sh; /* window space handle */ 152 struct timeout cz_timeout; /* timeout for polling-mode */ 153 154 void *cz_ih; /* interrupt handle */ 155 156 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 157 int cz_nchannels; /* number of channels */ 158 int cz_nopenchan; /* number of open channels */ 159 struct cztty_softc *cz_ports; /* our array of ports */ 160 161 bus_addr_t cz_fwctl; /* offset of firmware control */ 162 }; 163 164 int cz_match(struct device *, void *, void *); 165 void cz_attach(struct device *, struct device *, void *); 166 int cz_wait_pci_doorbell(struct cz_softc *, char *); 167 168 struct cfattach cz_ca = { 169 sizeof(struct cz_softc), cz_match, cz_attach 170 }; 171 172 void cz_reset_board(struct cz_softc *); 173 int cz_load_firmware(struct cz_softc *); 174 175 int cz_intr(void *); 176 void cz_poll(void *); 177 int cztty_transmit(struct cztty_softc *, struct tty *); 178 int cztty_receive(struct cztty_softc *, struct tty *); 179 180 struct cztty_softc * cztty_getttysoftc(dev_t dev); 181 int cztty_findmajor(void); 182 int cztty_major; 183 int cztty_attached_ttys; 184 int cz_timeout_ticks; 185 186 cdev_decl(cztty); 187 188 void czttystart(struct tty *tp); 189 int czttyparam(struct tty *tp, struct termios *t); 190 void cztty_shutdown(struct cztty_softc *sc); 191 void cztty_modem(struct cztty_softc *sc, int onoff); 192 void cztty_break(struct cztty_softc *sc, int onoff); 193 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 194 int cztty_to_tiocm(struct cztty_softc *sc); 195 void cztty_diag(void *arg); 196 197 struct cfdriver cz_cd = { 198 0, "cz", DV_TTY 199 }; 200 201 /* Macros to clear/set/test flags. */ 202 #define SET(t, f) (t) |= (f) 203 #define CLR(t, f) (t) &= ~(f) 204 #define ISSET(t, f) ((t) & (f)) 205 206 /* 207 * Macros to read and write the PLX. 208 */ 209 #define CZ_PLX_READ(cz, reg) \ 210 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 211 #define CZ_PLX_WRITE(cz, reg, val) \ 212 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 213 (reg), (val)) 214 215 /* 216 * Macros to read and write the FPGA. We must already be in the FPGA 217 * window for this. 218 */ 219 #define CZ_FPGA_READ(cz, reg) \ 220 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 221 #define CZ_FPGA_WRITE(cz, reg, val) \ 222 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 223 224 /* 225 * Macros to read and write the firmware control structures in board RAM. 226 */ 227 #define CZ_FWCTL_READ(cz, off) \ 228 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 229 (cz)->cz_fwctl + (off)) 230 231 #define CZ_FWCTL_WRITE(cz, off, val) \ 232 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 233 (cz)->cz_fwctl + (off), (val)) 234 235 /* 236 * Convenience macros for cztty routines. PLX window MUST be to RAM. 237 */ 238 #define CZTTY_CHAN_READ(sc, off) \ 239 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 240 241 #define CZTTY_CHAN_WRITE(sc, off, val) \ 242 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 243 (off), (val)) 244 245 #define CZTTY_BUF_READ(sc, off) \ 246 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 247 248 #define CZTTY_BUF_WRITE(sc, off, val) \ 249 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 250 (off), (val)) 251 252 /* 253 * Convenience macros. 254 */ 255 #define CZ_WIN_RAM(cz) \ 256 do { \ 257 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 258 delay(100); \ 259 } while (0) 260 261 #define CZ_WIN_FPGA(cz) \ 262 do { \ 263 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 264 delay(100); \ 265 } while (0) 266 267 /***************************************************************************** 268 * Cyclades-Z controller code starts here... 269 *****************************************************************************/ 270 271 /* 272 * cz_match: 273 * 274 * Determine if the given PCI device is a Cyclades-Z board. 275 */ 276 int 277 cz_match(parent, match, aux) 278 struct device *parent; 279 void *match, *aux; 280 { 281 struct pci_attach_args *pa = aux; 282 283 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 284 switch (PCI_PRODUCT(pa->pa_id)) { 285 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 286 return (1); 287 } 288 } 289 290 return (0); 291 } 292 293 /* 294 * cz_attach: 295 * 296 * A Cyclades-Z board was found; attach it. 297 */ 298 void 299 cz_attach(parent, self, aux) 300 struct device *parent, *self; 301 void *aux; 302 { 303 struct cz_softc *cz = (void *) self; 304 struct pci_attach_args *pa = aux; 305 pci_chipset_tag_t pc = pa->pa_pc; 306 pci_intr_handle_t ih; 307 const char *intrstr = NULL; 308 struct cztty_softc *sc; 309 struct tty *tp; 310 int i; 311 312 printf(": Cyclades-Z multiport serial\n"); 313 314 cz->cz_plx.plx_pc = pa->pa_pc; 315 cz->cz_plx.plx_tag = pa->pa_tag; 316 317 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 318 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 319 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL, 0) != 0) { 320 printf("%s: unable to map PLX registers\n", 321 cz->cz_dev.dv_xname); 322 return; 323 } 324 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 325 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 326 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL, 0) != 0) { 327 printf("%s: unable to map device window\n", 328 cz->cz_dev.dv_xname); 329 return; 330 } 331 332 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 333 cz->cz_nopenchan = 0; 334 335 /* 336 * Make sure that the board is completely stopped. 337 */ 338 CZ_WIN_FPGA(cz); 339 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 340 341 /* 342 * Load the board's firmware. 343 */ 344 if (cz_load_firmware(cz) != 0) 345 return; 346 347 /* 348 * Now that we're ready to roll, map and establish the interrupt 349 * handler. 350 */ 351 if (pci_intr_map(pa, &ih) != 0) { 352 /* 353 * The common case is for Cyclades-Z boards to run 354 * in polling mode, and thus not have an interrupt 355 * mapped for them. Don't bother reporting that 356 * the interrupt is not mappable, since this isn't 357 * really an error. 358 */ 359 cz->cz_ih = NULL; 360 goto polling_mode; 361 } else { 362 intrstr = pci_intr_string(pa->pa_pc, ih); 363 cz->cz_ih = pci_intr_establish(pc, ih, IPL_TTY, 364 cz_intr, cz, cz->cz_dev.dv_xname); 365 } 366 if (cz->cz_ih == NULL) { 367 printf("%s: unable to establish interrupt", 368 cz->cz_dev.dv_xname); 369 if (intrstr != NULL) 370 printf(" at %s", intrstr); 371 printf("\n"); 372 /* We will fall-back on polling mode. */ 373 } else 374 printf("%s: interrupting at %s\n", 375 cz->cz_dev.dv_xname, intrstr); 376 377 polling_mode: 378 if (cz->cz_ih == NULL) { 379 timeout_set(&cz->cz_timeout, cz_poll, cz); 380 if (cz_timeout_ticks == 0) 381 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 382 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 383 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 384 cz_timeout_ticks == 1 ? "" : "s"); 385 } 386 387 if (cztty_major == 0) 388 cztty_major = cztty_findmajor(); 389 /* 390 * Allocate sufficient pointers for the children and 391 * attach them. Set all ports to a reasonable initial 392 * configuration while we're at it: 393 * 394 * disabled 395 * 8N1 396 * default baud rate 397 * hardware flow control. 398 */ 399 CZ_WIN_RAM(cz); 400 401 if (cz->cz_nchannels == 0) { 402 /* No channels? No more work to do! */ 403 return; 404 } 405 406 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 407 M_DEVBUF, M_WAITOK); 408 cztty_attached_ttys += cz->cz_nchannels; 409 memset(cz->cz_ports, 0, 410 sizeof(struct cztty_softc) * cz->cz_nchannels); 411 412 for (i = 0; i < cz->cz_nchannels; i++) { 413 sc = &cz->cz_ports[i]; 414 415 sc->sc_channel = i; 416 sc->sc_chan_st = cz->cz_win_st; 417 sc->sc_parent = cz; 418 419 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 420 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 421 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 422 printf("%s: unable to subregion channel %d control\n", 423 cz->cz_dev.dv_xname, i); 424 sc->sc_channel = CZTTY_CHANNEL_DEAD; 425 continue; 426 } 427 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 428 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 429 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 430 printf("%s: unable to subregion channel %d buffer\n", 431 cz->cz_dev.dv_xname, i); 432 sc->sc_channel = CZTTY_CHANNEL_DEAD; 433 continue; 434 } 435 436 timeout_set(&sc->sc_diag_to, cztty_diag, sc); 437 438 tp = ttymalloc(); 439 tp->t_dev = makedev(cztty_major, 440 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 441 tp->t_oproc = czttystart; 442 tp->t_param = czttyparam; 443 tty_attach(tp); 444 445 sc->sc_tty = tp; 446 447 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 448 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 451 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 452 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 453 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 454 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 455 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 456 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 457 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 458 } 459 } 460 461 /* 462 * cz_reset_board: 463 * 464 * Reset the board via the PLX. 465 */ 466 void 467 cz_reset_board(struct cz_softc *cz) 468 { 469 u_int32_t reg; 470 471 reg = CZ_PLX_READ(cz, PLX_CONTROL); 472 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 473 delay(1000); 474 475 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 476 delay(1000); 477 478 /* Now reload the PLX from its EEPROM. */ 479 reg = CZ_PLX_READ(cz, PLX_CONTROL); 480 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 481 delay(1000); 482 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 483 } 484 485 /* 486 * cz_load_firmware: 487 * 488 * Load the ZFIRM firmware into the board's RAM and start it 489 * running. 490 */ 491 int 492 cz_load_firmware(struct cz_softc *cz) 493 { 494 struct zfirm_header *zfh; 495 struct zfirm_config *zfc; 496 struct zfirm_block *zfb, *zblocks; 497 const u_int8_t *cp; 498 const char *board; 499 u_int32_t fid; 500 int i, j, nconfigs, nblocks, nbytes; 501 502 zfh = (struct zfirm_header *) cycladesz_firmware; 503 504 /* Find the config header. */ 505 if (letoh32(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 506 printf("%s: bad ZFIRM config offset: 0x%x\n", 507 cz->cz_dev.dv_xname, letoh32(zfh->zfh_configoff)); 508 return (EIO); 509 } 510 zfc = (struct zfirm_config *)(cycladesz_firmware + 511 letoh32(zfh->zfh_configoff)); 512 nconfigs = letoh32(zfh->zfh_nconfig); 513 514 /* Locate the correct configuration for our board. */ 515 for (i = 0; i < nconfigs; i++, zfc++) { 516 if (letoh32(zfc->zfc_mailbox) == cz->cz_mailbox0 && 517 letoh32(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 518 break; 519 } 520 if (i == nconfigs) { 521 printf("%s: unable to locate config header\n", 522 cz->cz_dev.dv_xname); 523 return (EIO); 524 } 525 526 nblocks = letoh32(zfc->zfc_nblocks); 527 zblocks = (struct zfirm_block *)(cycladesz_firmware + 528 letoh32(zfh->zfh_blockoff)); 529 530 /* 531 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 532 * necessary. 533 */ 534 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 535 #if 0 536 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 537 #endif 538 ) { 539 #ifdef CZ_DEBUG 540 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 541 #endif 542 CZ_WIN_FPGA(cz); 543 for (i = 0; i < nblocks; i++) { 544 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 545 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 546 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FPGA) { 547 nbytes = letoh32(zfb->zfb_size); 548 cp = &cycladesz_firmware[ 549 letoh32(zfb->zfb_fileoff)]; 550 for (j = 0; j < nbytes; j++, cp++) { 551 bus_space_write_1(cz->cz_win_st, 552 cz->cz_win_sh, 0, *cp); 553 /* FPGA needs 30-100us to settle. */ 554 delay(10); 555 } 556 } 557 } 558 #ifdef CZ_DEBUG 559 printf("done\n"); 560 #endif 561 } 562 563 /* Now load the firmware. */ 564 CZ_WIN_RAM(cz); 565 566 for (i = 0; i < nblocks; i++) { 567 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 568 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 569 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 570 const u_int32_t *lp; 571 u_int32_t ro = letoh32(zfb->zfb_ramoff); 572 nbytes = letoh32(zfb->zfb_size); 573 lp = (const u_int32_t *) 574 &cycladesz_firmware[letoh32(zfb->zfb_fileoff)]; 575 for (j = 0; j < nbytes; j += 4, lp++) { 576 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 577 ro + j, letoh32(*lp)); 578 delay(10); 579 } 580 } 581 } 582 583 /* Now restart the MIPS. */ 584 CZ_WIN_FPGA(cz); 585 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 586 587 /* Wait for the MIPS to start, then report the results. */ 588 CZ_WIN_RAM(cz); 589 590 #ifdef CZ_DEBUG 591 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 592 #endif 593 for (i = 0; i < 100; i++) { 594 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 595 ZFIRM_SIG_OFF); 596 if (fid == ZFIRM_SIG) { 597 /* MIPS has booted. */ 598 break; 599 } else if (fid == ZFIRM_HLT) { 600 /* 601 * The MIPS has halted, usually due to a power 602 * shortage on the expansion module. 603 */ 604 printf("%s: MIPS halted; possible power supply " 605 "problem\n", cz->cz_dev.dv_xname); 606 return (EIO); 607 } else { 608 #ifdef CZ_DEBUG 609 if ((i % 8) == 0) 610 printf("."); 611 #endif 612 delay(250000); 613 } 614 } 615 #ifdef CZ_DEBUG 616 printf("\n"); 617 #endif 618 if (i == 100) { 619 CZ_WIN_FPGA(cz); 620 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 621 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 622 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 623 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 624 CZ_FPGA_READ(cz, FPGA_VERSION)); 625 return (EIO); 626 } 627 628 /* 629 * Locate the firmware control structures. 630 */ 631 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 632 ZFIRM_CTRLADDR_OFF); 633 #ifdef CZ_DEBUG 634 printf("%s: FWCTL structure at offset 0x%08lx\n", 635 cz->cz_dev.dv_xname, cz->cz_fwctl); 636 #endif 637 638 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 639 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 640 641 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 642 643 switch (cz->cz_mailbox0) { 644 case MAILBOX0_8Zo_V1: 645 board = "Cyclades-8Zo ver. 1"; 646 break; 647 648 case MAILBOX0_8Zo_V2: 649 board = "Cyclades-8Zo ver. 2"; 650 break; 651 652 case MAILBOX0_Ze_V1: 653 board = "Cyclades-Ze"; 654 break; 655 656 default: 657 board = "unknown Cyclades Z-series"; 658 break; 659 } 660 661 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 662 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 663 if (cz->cz_nchannels == 0) 664 printf("no channels attached, "); 665 else 666 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 667 cz->cz_nchannels, cztty_attached_ttys, 668 cztty_attached_ttys + (cz->cz_nchannels - 1)); 669 printf("firmware %x.%x.%x\n", 670 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 671 672 return (0); 673 } 674 675 /* 676 * cz_poll: 677 * 678 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 679 * ms. 680 */ 681 void 682 cz_poll(void *arg) 683 { 684 int s = spltty(); 685 struct cz_softc *cz = arg; 686 687 cz_intr(cz); 688 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 689 690 splx(s); 691 } 692 693 /* 694 * cz_intr: 695 * 696 * Interrupt service routine. 697 * 698 * We either are receiving an interrupt directly from the board, or we are 699 * in polling mode and it's time to poll. 700 */ 701 int 702 cz_intr(void *arg) 703 { 704 int rval = 0; 705 u_int command, channel, param; 706 struct cz_softc *cz = arg; 707 struct cztty_softc *sc; 708 struct tty *tp; 709 710 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 711 rval = 1; 712 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 713 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 714 715 /* now clear this interrupt, posslibly enabling another */ 716 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 717 718 if (cz->cz_ports == NULL) { 719 #ifdef CZ_DEBUG 720 printf("%s: interrupt on channel %d, but no channels\n", 721 cz->cz_dev.dv_xname, channel); 722 #endif 723 continue; 724 } 725 726 sc = &cz->cz_ports[channel]; 727 728 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 729 break; 730 731 tp = sc->sc_tty; 732 733 switch (command) { 734 case C_CM_TXFEMPTY: /* transmit cases */ 735 case C_CM_TXBEMPTY: 736 case C_CM_TXLOWWM: 737 case C_CM_INTBACK: 738 if (!ISSET(tp->t_state, TS_ISOPEN)) { 739 #ifdef CZ_DEBUG 740 printf("%s: tx intr on closed channel %d\n", 741 cz->cz_dev.dv_xname, channel); 742 #endif 743 break; 744 } 745 746 if (cztty_transmit(sc, tp)) { 747 /* 748 * Do wakeup stuff here. 749 */ 750 ttwakeup(tp); 751 wakeup(tp); 752 } 753 break; 754 755 case C_CM_RXNNDT: /* receive cases */ 756 case C_CM_RXHIWM: 757 case C_CM_INTBACK2: /* from restart ?? */ 758 #if 0 759 case C_CM_ICHAR: 760 #endif 761 if (!ISSET(tp->t_state, TS_ISOPEN)) { 762 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 763 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 764 break; 765 } 766 767 if (cztty_receive(sc, tp)) { 768 /* 769 * Do wakeup stuff here. 770 */ 771 ttwakeup(tp); 772 wakeup(tp); 773 } 774 break; 775 776 case C_CM_MDCD: 777 if (!ISSET(tp->t_state, TS_ISOPEN)) 778 break; 779 780 (void) (*linesw[tp->t_line].l_modem)(tp, 781 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 782 CHNCTL_RS_STATUS))); 783 break; 784 785 case C_CM_MDSR: 786 case C_CM_MRI: 787 case C_CM_MCTS: 788 case C_CM_MRTS: 789 break; 790 791 case C_CM_IOCTLW: 792 break; 793 794 case C_CM_PR_ERROR: 795 sc->sc_parity_errors++; 796 goto error_common; 797 798 case C_CM_FR_ERROR: 799 sc->sc_framing_errors++; 800 goto error_common; 801 802 case C_CM_OVR_ERROR: 803 sc->sc_overflows++; 804 error_common: 805 if (sc->sc_errors++ == 0) 806 timeout_add(&sc->sc_diag_to, 60 * hz); 807 break; 808 809 case C_CM_RXBRK: 810 if (!ISSET(tp->t_state, TS_ISOPEN)) 811 break; 812 813 /* 814 * A break is a \000 character with TTY_FE error 815 * flags set. So TTY_FE by itself works. 816 */ 817 (*linesw[tp->t_line].l_rint)(TTY_FE, tp); 818 ttwakeup(tp); 819 wakeup(tp); 820 break; 821 822 default: 823 #ifdef CZ_DEBUG 824 printf("%s: channel %d: Unknown interrupt 0x%x\n", 825 cz->cz_dev.dv_xname, sc->sc_channel, command); 826 #endif 827 break; 828 } 829 } 830 831 return (rval); 832 } 833 834 /* 835 * cz_wait_pci_doorbell: 836 * 837 * Wait for the pci doorbell to be clear - wait for pending 838 * activity to drain. 839 */ 840 int 841 cz_wait_pci_doorbell(struct cz_softc *cz, char *wstring) 842 { 843 int error; 844 845 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 846 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 847 if ((error != 0) && (error != EWOULDBLOCK)) 848 return (error); 849 } 850 return (0); 851 } 852 853 /***************************************************************************** 854 * Cyclades-Z TTY code starts here... 855 *****************************************************************************/ 856 857 #define CZTTYDIALOUT_MASK 0x80 858 859 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 860 #define CZTTY_CZ(sc) ((sc)->sc_parent) 861 862 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 863 864 struct cztty_softc * 865 cztty_getttysoftc(dev_t dev) 866 { 867 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 868 struct cz_softc *cz; 869 870 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 871 k = j; 872 cz = (struct cz_softc *)device_lookup(&cz_cd, i); 873 if (cz == NULL) 874 continue; 875 if (cz->cz_ports == NULL) 876 continue; 877 j += cz->cz_nchannels; 878 if (j > u) 879 break; 880 } 881 882 if (i >= cz_cd.cd_ndevs) 883 return (NULL); 884 else 885 return (&cz->cz_ports[u - k]); 886 } 887 888 int 889 cztty_findmajor(void) 890 { 891 int maj; 892 893 for (maj = 0; maj < nchrdev; maj++) { 894 if (cdevsw[maj].d_open == czttyopen) 895 break; 896 } 897 898 return (maj == nchrdev) ? 0 : maj; 899 } 900 901 /* 902 * czttytty: 903 * 904 * Return a pointer to our tty. 905 */ 906 struct tty * 907 czttytty(dev_t dev) 908 { 909 struct cztty_softc *sc = CZTTY_SOFTC(dev); 910 911 #ifdef DIAGNOSTIC 912 if (sc == NULL) 913 panic("czttytty"); 914 #endif 915 916 return (sc->sc_tty); 917 } 918 919 /* 920 * cztty_shutdown: 921 * 922 * Shut down a port. 923 */ 924 void 925 cztty_shutdown(struct cztty_softc *sc) 926 { 927 struct cz_softc *cz = CZTTY_CZ(sc); 928 struct tty *tp = sc->sc_tty; 929 int s; 930 931 s = spltty(); 932 933 /* Clear any break condition set with TIOCSBRK. */ 934 cztty_break(sc, 0); 935 936 /* 937 * Hang up if necessary. Wait a bit, so the other side has time to 938 * notice even if we immediately open the port again. 939 */ 940 if (ISSET(tp->t_cflag, HUPCL)) { 941 cztty_modem(sc, 0); 942 (void) tsleep(tp, TTIPRI, ttclos, hz); 943 } 944 945 /* Disable the channel. */ 946 cz_wait_pci_doorbell(cz, "czdis"); 947 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 948 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 949 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 950 951 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 952 #ifdef CZ_DEBUG 953 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 954 #endif 955 timeout_del(&cz->cz_timeout); 956 } 957 958 splx(s); 959 } 960 961 /* 962 * czttyopen: 963 * 964 * Open a Cyclades-Z serial port. 965 */ 966 int 967 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 968 { 969 struct cztty_softc *sc = CZTTY_SOFTC(dev); 970 struct cz_softc *cz; 971 struct tty *tp; 972 int s, error; 973 974 if (sc == NULL) 975 return (ENXIO); 976 977 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 978 return (ENXIO); 979 980 cz = CZTTY_CZ(sc); 981 tp = sc->sc_tty; 982 983 if (ISSET(tp->t_state, TS_ISOPEN) && 984 ISSET(tp->t_state, TS_XCLUDE) && 985 p->p_ucred->cr_uid != 0) 986 return (EBUSY); 987 988 s = spltty(); 989 990 /* 991 * Do the following iff this is a first open. 992 */ 993 if (!ISSET(tp->t_state, TS_ISOPEN)) { 994 struct termios t; 995 996 tp->t_dev = dev; 997 998 /* If we're turning things on, enable interrupts */ 999 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 1000 #ifdef CZ_DEBUG 1001 printf("%s: Enabling polling.\n", 1002 cz->cz_dev.dv_xname); 1003 #endif 1004 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 1005 } 1006 1007 /* 1008 * Enable the channel. Don't actually ring the 1009 * doorbell here; czttyparam() will do it for us. 1010 */ 1011 cz_wait_pci_doorbell(cz, "czopen"); 1012 1013 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1014 1015 /* 1016 * Initialize the termios status to the defaults. Add in the 1017 * sticky bits from TIOCSFLAGS. 1018 */ 1019 t.c_ispeed = 0; 1020 t.c_ospeed = TTYDEF_SPEED; 1021 t.c_cflag = TTYDEF_CFLAG; 1022 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1023 SET(t.c_cflag, CLOCAL); 1024 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1025 SET(t.c_cflag, CRTSCTS); 1026 1027 /* 1028 * Reset the input and output rings. Do this before 1029 * we call czttyparam(), as that function enables 1030 * the channel. 1031 */ 1032 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1033 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1034 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1035 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1036 1037 /* Make sure czttyparam() will see changes. */ 1038 tp->t_ospeed = 0; 1039 (void) czttyparam(tp, &t); 1040 tp->t_iflag = TTYDEF_IFLAG; 1041 tp->t_oflag = TTYDEF_OFLAG; 1042 tp->t_lflag = TTYDEF_LFLAG; 1043 ttychars(tp); 1044 ttsetwater(tp); 1045 1046 /* 1047 * Turn on DTR. We must always do this, even if carrier is not 1048 * present, because otherwise we'd have to use TIOCSDTR 1049 * immediately after setting CLOCAL, which applications do not 1050 * expect. We always assert DTR while the device is open 1051 * unless explicitly requested to deassert it. 1052 */ 1053 cztty_modem(sc, 1); 1054 } 1055 1056 splx(s); 1057 1058 error = ttyopen(CZTTY_DIALOUT(dev), tp); 1059 if (error) 1060 goto bad; 1061 1062 error = (*linesw[tp->t_line].l_open)(dev, tp); 1063 if (error) 1064 goto bad; 1065 1066 return (0); 1067 1068 bad: 1069 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1070 /* 1071 * We failed to open the device, and nobody else had it opened. 1072 * Clean up the state as appropriate. 1073 */ 1074 cztty_shutdown(sc); 1075 } 1076 1077 return (error); 1078 } 1079 1080 /* 1081 * czttyclose: 1082 * 1083 * Close a Cyclades-Z serial port. 1084 */ 1085 int 1086 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1087 { 1088 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1089 struct tty *tp = sc->sc_tty; 1090 1091 /* XXX This is for cons.c. */ 1092 if (!ISSET(tp->t_state, TS_ISOPEN)) 1093 return (0); 1094 1095 (*linesw[tp->t_line].l_close)(tp, flags); 1096 ttyclose(tp); 1097 1098 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1099 /* 1100 * Although we got a last close, the device may still be in 1101 * use; e.g. if this was the dialout node, and there are still 1102 * processes waiting for carrier on the non-dialout node. 1103 */ 1104 cztty_shutdown(sc); 1105 } 1106 1107 return (0); 1108 } 1109 1110 /* 1111 * czttyread: 1112 * 1113 * Read from a Cyclades-Z serial port. 1114 */ 1115 int 1116 czttyread(dev_t dev, struct uio *uio, int flags) 1117 { 1118 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1119 struct tty *tp = sc->sc_tty; 1120 1121 return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); 1122 } 1123 1124 /* 1125 * czttywrite: 1126 * 1127 * Write to a Cyclades-Z serial port. 1128 */ 1129 int 1130 czttywrite(dev_t dev, struct uio *uio, int flags) 1131 { 1132 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1133 struct tty *tp = sc->sc_tty; 1134 1135 return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); 1136 } 1137 1138 #if 0 1139 /* 1140 * czttypoll: 1141 * 1142 * Poll a Cyclades-Z serial port. 1143 */ 1144 int 1145 czttypoll(dev_t dev, int events, struct proc p) 1146 { 1147 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1148 struct tty *tp = sc->sc_tty; 1149 1150 return ((*linesw[tp->t_line].l_poll)(tp, events, p)); 1151 } 1152 #endif 1153 1154 /* 1155 * czttyioctl: 1156 * 1157 * Perform a control operation on a Cyclades-Z serial port. 1158 */ 1159 int 1160 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1161 { 1162 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1163 struct tty *tp = sc->sc_tty; 1164 int s, error; 1165 1166 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1167 if (error >= 0) 1168 return (error); 1169 1170 error = ttioctl(tp, cmd, data, flag, p); 1171 if (error >= 0) 1172 return (error); 1173 1174 error = 0; 1175 1176 s = spltty(); 1177 1178 switch (cmd) { 1179 case TIOCSBRK: 1180 cztty_break(sc, 1); 1181 break; 1182 1183 case TIOCCBRK: 1184 cztty_break(sc, 0); 1185 break; 1186 1187 case TIOCGFLAGS: 1188 *(int *)data = sc->sc_swflags; 1189 break; 1190 1191 case TIOCSFLAGS: 1192 error = suser(p->p_ucred, &p->p_acflag); 1193 if (error) 1194 break; 1195 sc->sc_swflags = *(int *)data; 1196 break; 1197 1198 case TIOCSDTR: 1199 cztty_modem(sc, 1); 1200 break; 1201 1202 case TIOCCDTR: 1203 cztty_modem(sc, 0); 1204 break; 1205 1206 case TIOCMSET: 1207 case TIOCMBIS: 1208 case TIOCMBIC: 1209 tiocm_to_cztty(sc, cmd, *(int *)data); 1210 break; 1211 1212 case TIOCMGET: 1213 *(int *)data = cztty_to_tiocm(sc); 1214 break; 1215 1216 default: 1217 error = ENOTTY; 1218 break; 1219 } 1220 1221 splx(s); 1222 1223 return (error); 1224 } 1225 1226 /* 1227 * cztty_break: 1228 * 1229 * Set or clear BREAK on a port. 1230 */ 1231 void 1232 cztty_break(struct cztty_softc *sc, int onoff) 1233 { 1234 struct cz_softc *cz = CZTTY_CZ(sc); 1235 1236 cz_wait_pci_doorbell(cz, "czbreak"); 1237 1238 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1239 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1240 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1241 } 1242 1243 /* 1244 * cztty_modem: 1245 * 1246 * Set or clear DTR on a port. 1247 */ 1248 void 1249 cztty_modem(struct cztty_softc *sc, int onoff) 1250 { 1251 struct cz_softc *cz = CZTTY_CZ(sc); 1252 1253 if (sc->sc_rs_control_dtr == 0) 1254 return; 1255 1256 cz_wait_pci_doorbell(cz, "czmod"); 1257 1258 if (onoff) 1259 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1260 else 1261 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1262 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1263 1264 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1265 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1266 } 1267 1268 /* 1269 * tiocm_to_cztty: 1270 * 1271 * Process TIOCM* ioctls. 1272 */ 1273 void 1274 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1275 { 1276 struct cz_softc *cz = CZTTY_CZ(sc); 1277 u_int32_t czttybits; 1278 1279 czttybits = 0; 1280 if (ISSET(ttybits, TIOCM_DTR)) 1281 SET(czttybits, C_RS_DTR); 1282 if (ISSET(ttybits, TIOCM_RTS)) 1283 SET(czttybits, C_RS_RTS); 1284 1285 cz_wait_pci_doorbell(cz, "cztiocm"); 1286 1287 switch (how) { 1288 case TIOCMBIC: 1289 CLR(sc->sc_chanctl_rs_control, czttybits); 1290 break; 1291 1292 case TIOCMBIS: 1293 SET(sc->sc_chanctl_rs_control, czttybits); 1294 break; 1295 1296 case TIOCMSET: 1297 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1298 SET(sc->sc_chanctl_rs_control, czttybits); 1299 break; 1300 } 1301 1302 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1303 1304 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1305 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1306 } 1307 1308 /* 1309 * cztty_to_tiocm: 1310 * 1311 * Process the TIOCMGET ioctl. 1312 */ 1313 int 1314 cztty_to_tiocm(struct cztty_softc *sc) 1315 { 1316 struct cz_softc *cz = CZTTY_CZ(sc); 1317 u_int32_t rs_status, op_mode; 1318 int ttybits = 0; 1319 1320 cz_wait_pci_doorbell(cz, "cztty"); 1321 1322 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1323 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1324 1325 if (ISSET(rs_status, C_RS_RTS)) 1326 SET(ttybits, TIOCM_RTS); 1327 if (ISSET(rs_status, C_RS_CTS)) 1328 SET(ttybits, TIOCM_CTS); 1329 if (ISSET(rs_status, C_RS_DCD)) 1330 SET(ttybits, TIOCM_CAR); 1331 if (ISSET(rs_status, C_RS_DTR)) 1332 SET(ttybits, TIOCM_DTR); 1333 if (ISSET(rs_status, C_RS_RI)) 1334 SET(ttybits, TIOCM_RNG); 1335 if (ISSET(rs_status, C_RS_DSR)) 1336 SET(ttybits, TIOCM_DSR); 1337 1338 if (ISSET(op_mode, C_CH_ENABLE)) 1339 SET(ttybits, TIOCM_LE); 1340 1341 return (ttybits); 1342 } 1343 1344 /* 1345 * czttyparam: 1346 * 1347 * Set Cyclades-Z serial port parameters from termios. 1348 * 1349 * XXX Should just copy the whole termios after making 1350 * XXX sure all the changes could be done. 1351 */ 1352 int 1353 czttyparam(struct tty *tp, struct termios *t) 1354 { 1355 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1356 struct cz_softc *cz = CZTTY_CZ(sc); 1357 u_int32_t rs_status; 1358 int ospeed, cflag; 1359 1360 ospeed = t->c_ospeed; 1361 cflag = t->c_cflag; 1362 1363 /* Check requested parameters. */ 1364 if (ospeed < 0) 1365 return (EINVAL); 1366 if (t->c_ispeed && t->c_ispeed != ospeed) 1367 return (EINVAL); 1368 1369 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1370 SET(cflag, CLOCAL); 1371 CLR(cflag, HUPCL); 1372 } 1373 1374 /* 1375 * If there were no changes, don't do anything. This avoids dropping 1376 * input and improves performance when all we did was frob things like 1377 * VMIN and VTIME. 1378 */ 1379 if (tp->t_ospeed == ospeed && 1380 tp->t_cflag == cflag) 1381 return (0); 1382 1383 /* Data bits. */ 1384 sc->sc_chanctl_comm_data_l = 0; 1385 switch (t->c_cflag & CSIZE) { 1386 case CS5: 1387 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1388 break; 1389 1390 case CS6: 1391 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1392 break; 1393 1394 case CS7: 1395 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1396 break; 1397 1398 case CS8: 1399 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1400 break; 1401 } 1402 1403 /* Stop bits. */ 1404 if (t->c_cflag & CSTOPB) { 1405 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1406 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1407 else 1408 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1409 } else 1410 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1411 1412 /* Parity. */ 1413 if (t->c_cflag & PARENB) { 1414 if (t->c_cflag & PARODD) 1415 sc->sc_chanctl_comm_parity = C_PR_ODD; 1416 else 1417 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1418 } else 1419 sc->sc_chanctl_comm_parity = C_PR_NONE; 1420 1421 /* 1422 * Initialize flow control pins depending on the current flow control 1423 * mode. 1424 */ 1425 if (ISSET(t->c_cflag, CRTSCTS)) { 1426 sc->sc_rs_control_dtr = C_RS_DTR; 1427 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1428 } else if (ISSET(t->c_cflag, MDMBUF)) { 1429 sc->sc_rs_control_dtr = 0; 1430 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1431 } else { 1432 /* 1433 * If no flow control, then always set RTS. This will make 1434 * the other side happy if it mistakenly thinks we're doing 1435 * RTS/CTS flow control. 1436 */ 1437 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1438 sc->sc_chanctl_hw_flow = 0; 1439 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1440 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1441 else 1442 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1443 } 1444 1445 /* Baud rate. */ 1446 sc->sc_chanctl_comm_baud = ospeed; 1447 1448 /* Copy to tty. */ 1449 tp->t_ispeed = 0; 1450 tp->t_ospeed = t->c_ospeed; 1451 tp->t_cflag = t->c_cflag; 1452 1453 /* 1454 * Now load the channel control structure. 1455 */ 1456 1457 cz_wait_pci_doorbell(cz, "czparam"); 1458 1459 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1460 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1461 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1462 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1463 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1464 1465 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1466 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1467 1468 cz_wait_pci_doorbell(cz, "czparam"); 1469 1470 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1471 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1472 1473 cz_wait_pci_doorbell(cz, "czparam"); 1474 1475 /* 1476 * Update the tty layer's idea of the carrier bit, in case we changed 1477 * CLOCAL. We don't hang up here; we only do that by explicit 1478 * request. 1479 */ 1480 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1481 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1482 1483 return (0); 1484 } 1485 1486 /* 1487 * czttystart: 1488 * 1489 * Start or restart transmission. 1490 */ 1491 void 1492 czttystart(struct tty *tp) 1493 { 1494 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1495 int s; 1496 1497 s = spltty(); 1498 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1499 goto out; 1500 1501 if (tp->t_outq.c_cc <= tp->t_lowat) { 1502 if (ISSET(tp->t_state, TS_ASLEEP)) { 1503 CLR(tp->t_state, TS_ASLEEP); 1504 wakeup(&tp->t_outq); 1505 } 1506 selwakeup(&tp->t_wsel); 1507 if (tp->t_outq.c_cc == 0) 1508 goto out; 1509 } 1510 1511 cztty_transmit(sc, tp); 1512 out: 1513 splx(s); 1514 } 1515 1516 /* 1517 * czttystop: 1518 * 1519 * Stop output, e.g., for ^S or output flush. 1520 */ 1521 int 1522 czttystop(struct tty *tp, int flag) 1523 { 1524 1525 /* 1526 * XXX We don't do anything here, yet. Mostly, I don't know 1527 * XXX exactly how this should be implemented on this device. 1528 * XXX We've given a big chunk of data to the MIPS already, 1529 * XXX and I don't know how we request the MIPS to stop sending 1530 * XXX the data. So, punt for now. --thorpej 1531 */ 1532 return (0); 1533 } 1534 1535 /* 1536 * cztty_diag: 1537 * 1538 * Issue a scheduled diagnostic message. 1539 */ 1540 void 1541 cztty_diag(void *arg) 1542 { 1543 struct cztty_softc *sc = arg; 1544 struct cz_softc *cz = CZTTY_CZ(sc); 1545 u_int overflows, parity_errors, framing_errors; 1546 int s; 1547 1548 s = spltty(); 1549 1550 overflows = sc->sc_overflows; 1551 sc->sc_overflows = 0; 1552 1553 parity_errors = sc->sc_parity_errors; 1554 sc->sc_parity_errors = 0; 1555 1556 framing_errors = sc->sc_framing_errors; 1557 sc->sc_framing_errors = 0; 1558 1559 sc->sc_errors = 0; 1560 1561 splx(s); 1562 1563 log(LOG_WARNING, 1564 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1565 cz->cz_dev.dv_xname, sc->sc_channel, 1566 overflows, overflows == 1 ? "" : "s", 1567 parity_errors, 1568 framing_errors, framing_errors == 1 ? "" : "s"); 1569 } 1570 1571 /* 1572 * tx and rx ring buffer size macros: 1573 * 1574 * The transmitter and receiver both use ring buffers. For each one, there 1575 * is a get (consumer) and a put (producer) offset. The get value is the 1576 * next byte to be read from the ring, and the put is the next one to be 1577 * put into the ring. get == put means the ring is empty. 1578 * 1579 * For each ring, the firmware controls one of (get, put) and this driver 1580 * controls the other. For transmission, this driver updates put to point 1581 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1582 * for receive, the driver controls put, and this driver controls get. 1583 */ 1584 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1585 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1586 1587 /* 1588 * cztty_transmit() 1589 * 1590 * Look at the tty for this port and start sending. 1591 */ 1592 int 1593 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1594 { 1595 struct cz_softc *cz = CZTTY_CZ(sc); 1596 u_int move, get, put, size, address; 1597 #ifdef HOSTRAMCODE 1598 int error, done = 0; 1599 #else 1600 int done = 0; 1601 #endif 1602 1603 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1604 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1605 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1606 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1607 1608 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1609 #ifdef HOSTRAMCODE 1610 if (0) { 1611 move = min(tp->t_outq.c_cc, move); 1612 error = q_to_b(&tp->t_outq, 0, move); 1613 if (error != move) { 1614 printf("%s: channel %d: error moving to " 1615 "transmit buf\n", cz->cz_dev.dv_xname, 1616 sc->sc_channel); 1617 move = error; 1618 } 1619 } else { 1620 #endif 1621 move = min(ndqb(&tp->t_outq, 0), move); 1622 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1623 address + put, tp->t_outq.c_cf, move); 1624 ndflush(&tp->t_outq, move); 1625 #ifdef HOSTRAMCODE 1626 } 1627 #endif 1628 1629 put = ((put + move) % size); 1630 done = 1; 1631 } 1632 if (done) { 1633 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1634 } 1635 return (done); 1636 } 1637 1638 int 1639 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1640 { 1641 struct cz_softc *cz = CZTTY_CZ(sc); 1642 u_int get, put, size, address; 1643 int done = 0, ch; 1644 1645 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1646 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1647 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1648 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1649 1650 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1651 #ifdef HOSTRAMCODE 1652 if (hostram) 1653 ch = ((char *)fifoaddr)[get]; 1654 } else { 1655 #endif 1656 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1657 address + get); 1658 #ifdef HOSTRAMCODE 1659 } 1660 #endif 1661 (*linesw[tp->t_line].l_rint)(ch, tp); 1662 get = (get + 1) % size; 1663 done = 1; 1664 } 1665 if (done) { 1666 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1667 } 1668 return (done); 1669 } 1670