1 /* $OpenBSD: cs4281.c,v 1.22 2008/10/25 22:30:43 jakemsr Exp $ */ 2 /* $Tera: cs4281.c,v 1.18 2000/12/27 14:24:45 tacha Exp $ */ 3 4 /* 5 * Copyright (c) 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4281 driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/pubs/4281.pdf?DocumentID=30 38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/cs4281tm.pdf 39 * 40 * TODO: 41 * 1: midi and FM support 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/malloc.h> 48 #include <sys/fcntl.h> 49 #include <sys/device.h> 50 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/cs4281reg.h> 54 55 #include <sys/audioio.h> 56 #include <dev/audio_if.h> 57 #include <dev/midi_if.h> 58 #include <dev/mulaw.h> 59 #include <dev/auconv.h> 60 61 #include <dev/ic/ac97.h> 62 63 #include <machine/bus.h> 64 65 #define CSCC_PCI_BA0 0x10 66 #define CSCC_PCI_BA1 0x14 67 68 struct cs4281_dma { 69 bus_dmamap_t map; 70 caddr_t addr; /* real dma buffer */ 71 caddr_t dum; /* dummy buffer for audio driver */ 72 bus_dma_segment_t segs[1]; 73 int nsegs; 74 size_t size; 75 struct cs4281_dma *next; 76 }; 77 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 78 #define BUFADDR(p) ((void *)((p)->dum)) 79 #define KERNADDR(p) ((void *)((p)->addr)) 80 81 /* 82 * Software state 83 */ 84 struct cs4281_softc { 85 struct device sc_dev; 86 87 pci_intr_handle_t *sc_ih; 88 89 /* I/O (BA0) */ 90 bus_space_tag_t ba0t; 91 bus_space_handle_t ba0h; 92 93 /* BA1 */ 94 bus_space_tag_t ba1t; 95 bus_space_handle_t ba1h; 96 97 /* DMA */ 98 bus_dma_tag_t sc_dmatag; 99 struct cs4281_dma *sc_dmas; 100 size_t dma_size; 101 size_t dma_align; 102 103 int hw_blocksize; 104 105 /* playback */ 106 void (*sc_pintr)(void *); /* dma completion intr handler */ 107 void *sc_parg; /* arg for sc_intr() */ 108 char *sc_ps, *sc_pe, *sc_pn; 109 int sc_pcount; 110 int sc_pi; 111 struct cs4281_dma *sc_pdma; 112 char *sc_pbuf; 113 int (*halt_output)(void *); 114 #ifdef DIAGNOSTIC 115 char sc_prun; 116 #endif 117 118 /* capturing */ 119 void (*sc_rintr)(void *); /* dma completion intr handler */ 120 void *sc_rarg; /* arg for sc_intr() */ 121 char *sc_rs, *sc_re, *sc_rn; 122 int sc_rcount; 123 int sc_ri; 124 struct cs4281_dma *sc_rdma; 125 char *sc_rbuf; 126 int sc_rparam; /* record format */ 127 int (*halt_input)(void *); 128 #ifdef DIAGNOSTIC 129 char sc_rrun; 130 #endif 131 132 #if NMIDI > 0 133 void (*sc_iintr)(void *, int); /* midi input ready handler */ 134 void (*sc_ointr)(void *); /* midi output ready handler */ 135 void *sc_arg; 136 #endif 137 138 /* AC97 CODEC */ 139 struct ac97_codec_if *codec_if; 140 struct ac97_host_if host_if; 141 142 /* Power Management */ 143 char sc_suspend; 144 void *sc_powerhook; /* Power hook */ 145 u_int16_t ac97_reg[CS4281_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 146 }; 147 148 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 149 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 150 151 #if defined(ENABLE_SECONDARY_CODEC) 152 #define MAX_CHANNELS (4) 153 #define MAX_FIFO_SIZE 32 /* 128/4 channels */ 154 #else 155 #define MAX_CHANNELS (2) 156 #define MAX_FIFO_SIZE 64 /* 128/2 channels */ 157 #endif 158 159 int cs4281_match(struct device *, void *, void *); 160 void cs4281_attach(struct device *, struct device *, void *); 161 int cs4281_intr(void *); 162 int cs4281_query_encoding(void *, struct audio_encoding *); 163 int cs4281_set_params(void *, int, int, struct audio_params *, 164 struct audio_params *); 165 int cs4281_halt_output(void *); 166 int cs4281_halt_input(void *); 167 int cs4281_getdev(void *, struct audio_device *); 168 int cs4281_trigger_output(void *, void *, void *, int, void (*)(void *), 169 void *, struct audio_params *); 170 int cs4281_trigger_input(void *, void *, void *, int, void (*)(void *), 171 void *, struct audio_params *); 172 u_int8_t cs4281_sr2regval(int); 173 void cs4281_set_dac_rate(struct cs4281_softc *, int); 174 void cs4281_set_adc_rate(struct cs4281_softc *, int); 175 int cs4281_init(struct cs4281_softc *); 176 177 int cs4281_open(void *, int); 178 void cs4281_close(void *); 179 int cs4281_round_blocksize(void *, int); 180 int cs4281_get_props(void *); 181 int cs4281_attach_codec(void *, struct ac97_codec_if *); 182 int cs4281_read_codec(void *, u_int8_t , u_int16_t *); 183 int cs4281_write_codec(void *, u_int8_t, u_int16_t); 184 void cs4281_reset_codec(void *); 185 186 void cs4281_power(int, void *); 187 188 int cs4281_mixer_set_port(void *, mixer_ctrl_t *); 189 int cs4281_mixer_get_port(void *, mixer_ctrl_t *); 190 int cs4281_query_devinfo(void *, mixer_devinfo_t *); 191 void *cs4281_malloc(void *, int, size_t, int, int); 192 size_t cs4281_round_buffersize(void *, int, size_t); 193 void cs4281_free(void *, void *, int); 194 paddr_t cs4281_mappage(void *, void *, off_t, int); 195 196 int cs4281_allocmem(struct cs4281_softc *, size_t, int, int, 197 struct cs4281_dma *); 198 int cs4281_src_wait(struct cs4281_softc *); 199 200 #if defined(CS4281_DEBUG) 201 #undef DPRINTF 202 #undef DPRINTFN 203 #define DPRINTF(x) if (cs4281_debug) printf x 204 #define DPRINTFN(n,x) if (cs4281_debug>(n)) printf x 205 int cs4281_debug = 5; 206 #else 207 #define DPRINTF(x) 208 #define DPRINTFN(n,x) 209 #endif 210 211 struct audio_hw_if cs4281_hw_if = { 212 cs4281_open, 213 cs4281_close, 214 NULL, 215 cs4281_query_encoding, 216 cs4281_set_params, 217 cs4281_round_blocksize, 218 NULL, 219 NULL, 220 NULL, 221 NULL, 222 NULL, 223 cs4281_halt_output, 224 cs4281_halt_input, 225 NULL, 226 cs4281_getdev, 227 NULL, 228 cs4281_mixer_set_port, 229 cs4281_mixer_get_port, 230 cs4281_query_devinfo, 231 cs4281_malloc, 232 cs4281_free, 233 cs4281_round_buffersize, 234 NULL, /* cs4281_mappage, */ 235 cs4281_get_props, 236 cs4281_trigger_output, 237 cs4281_trigger_input, 238 NULL 239 }; 240 241 #if NMIDI > 0 242 /* Midi Interface */ 243 void cs4281_midi_close(void *); 244 void cs4281_midi_getinfo(void *, struct midi_info *); 245 int cs4281_midi_open(void *, int, void (*)(void *, int), 246 void (*)(void *), void *); 247 int cs4281_midi_output(void *, int); 248 249 struct midi_hw_if cs4281_midi_hw_if = { 250 cs4281_midi_open, 251 cs4281_midi_close, 252 cs4281_midi_output, 253 cs4281_midi_getinfo, 254 0, 255 }; 256 #endif 257 258 struct cfattach clct_ca = { 259 sizeof(struct cs4281_softc), cs4281_match, cs4281_attach 260 }; 261 262 struct cfdriver clct_cd = { 263 NULL, "clct", DV_DULL 264 }; 265 266 struct audio_device cs4281_device = { 267 "CS4281", 268 "", 269 "cs4281" 270 }; 271 272 273 int 274 cs4281_match(parent, match, aux) 275 struct device *parent; 276 void *match; 277 void *aux; 278 { 279 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 280 281 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS || 282 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CIRRUS_CS4281) 283 return (0); 284 285 return (1); 286 } 287 288 void 289 cs4281_attach(parent, self, aux) 290 struct device *parent; 291 struct device *self; 292 void *aux; 293 { 294 struct cs4281_softc *sc = (struct cs4281_softc *)self; 295 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 296 pci_chipset_tag_t pc = pa->pa_pc; 297 char const *intrstr; 298 pci_intr_handle_t ih; 299 300 /* Map I/O register */ 301 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 302 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->ba0t, 303 &sc->ba0h, NULL, NULL, 0)) { 304 printf("%s: can't map BA0 space\n", sc->sc_dev.dv_xname); 305 return; 306 } 307 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 308 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->ba1t, 309 &sc->ba1h, NULL, NULL, 0)) { 310 printf("%s: can't map BA1 space\n", sc->sc_dev.dv_xname); 311 return; 312 } 313 314 sc->sc_dmatag = pa->pa_dmat; 315 316 /* 317 * Set Power State D0. 318 * Without doing this, 0xffffffff is read from all registers after 319 * using Windows and rebooting into OpenBSD. 320 * On my IBM ThinkPad X20, it is set to D3 after using Windows2000. 321 */ 322 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 323 324 /* Map and establish the interrupt. */ 325 if (pci_intr_map(pa, &ih)) { 326 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 327 return; 328 } 329 intrstr = pci_intr_string(pc, ih); 330 331 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4281_intr, sc, 332 sc->sc_dev.dv_xname); 333 if (sc->sc_ih == NULL) { 334 printf("%s: couldn't establish interrupt",sc->sc_dev.dv_xname); 335 if (intrstr != NULL) 336 printf(" at %s", intrstr); 337 printf("\n"); 338 return; 339 } 340 printf(" %s\n", intrstr); 341 342 /* 343 * Sound System start-up 344 */ 345 if (cs4281_init(sc) != 0) 346 return; 347 348 sc->halt_input = cs4281_halt_input; 349 sc->halt_output = cs4281_halt_output; 350 351 sc->dma_size = CS4281_BUFFER_SIZE / MAX_CHANNELS; 352 sc->dma_align = 0x10; 353 sc->hw_blocksize = sc->dma_size / 2; 354 355 /* AC 97 attachment */ 356 sc->host_if.arg = sc; 357 sc->host_if.attach = cs4281_attach_codec; 358 sc->host_if.read = cs4281_read_codec; 359 sc->host_if.write = cs4281_write_codec; 360 sc->host_if.reset = cs4281_reset_codec; 361 if (ac97_attach(&sc->host_if) != 0) { 362 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 363 return; 364 } 365 audio_attach_mi(&cs4281_hw_if, sc, &sc->sc_dev); 366 367 #if NMIDI > 0 368 midi_attach_mi(&cs4281_midi_hw_if, sc, &sc->sc_dev); 369 #endif 370 371 sc->sc_suspend = PWR_RESUME; 372 sc->sc_powerhook = powerhook_establish(cs4281_power, sc); 373 } 374 375 376 int 377 cs4281_intr(p) 378 void *p; 379 { 380 struct cs4281_softc *sc = p; 381 u_int32_t intr, val; 382 char *empty_dma; 383 384 intr = BA0READ4(sc, CS4281_HISR); 385 if (!(intr & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) { 386 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 387 return (0); 388 } 389 DPRINTF(("cs4281_intr:")); 390 391 if (intr & HISR_DMA0) 392 val = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */ 393 if (intr & HISR_DMA1) 394 val = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */ 395 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 396 397 /* Playback Interrupt */ 398 if (intr & HISR_DMA0) { 399 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0), 400 (int)BA0READ4(sc, CS4281_DCC0))); 401 if (sc->sc_pintr) { 402 if ((sc->sc_pi%sc->sc_pcount) == 0) 403 sc->sc_pintr(sc->sc_parg); 404 } else { 405 printf("unexpected play intr\n"); 406 } 407 /* copy buffer */ 408 ++sc->sc_pi; 409 empty_dma = sc->sc_pdma->addr; 410 if (sc->sc_pi&1) 411 empty_dma += sc->hw_blocksize; 412 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize); 413 sc->sc_pn += sc->hw_blocksize; 414 if (sc->sc_pn >= sc->sc_pe) 415 sc->sc_pn = sc->sc_ps; 416 } 417 if (intr & HISR_DMA1) { 418 val = BA0READ4(sc, CS4281_HDSR1); 419 /* copy from dma */ 420 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1), 421 (int)BA0READ4(sc, CS4281_DCC1))); 422 ++sc->sc_ri; 423 empty_dma = sc->sc_rdma->addr; 424 if ((sc->sc_ri & 1) == 0) 425 empty_dma += sc->hw_blocksize; 426 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize); 427 if (sc->sc_rn >= sc->sc_re) 428 sc->sc_rn = sc->sc_rs; 429 if (sc->sc_rintr) { 430 if ((sc->sc_ri % sc->sc_rcount) == 0) 431 sc->sc_rintr(sc->sc_rarg); 432 } else { 433 printf("unexpected record intr\n"); 434 } 435 } 436 DPRINTF(("\n")); 437 return (1); 438 } 439 440 int 441 cs4281_query_encoding(addr, fp) 442 void *addr; 443 struct audio_encoding *fp; 444 { 445 switch (fp->index) { 446 case 0: 447 strlcpy(fp->name, AudioEulinear, sizeof fp->name); 448 fp->encoding = AUDIO_ENCODING_ULINEAR; 449 fp->precision = 8; 450 fp->flags = 0; 451 break; 452 case 1: 453 strlcpy(fp->name, AudioEmulaw, sizeof fp->name); 454 fp->encoding = AUDIO_ENCODING_ULAW; 455 fp->precision = 8; 456 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 457 break; 458 case 2: 459 strlcpy(fp->name, AudioEalaw, sizeof fp->name); 460 fp->encoding = AUDIO_ENCODING_ALAW; 461 fp->precision = 8; 462 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 463 break; 464 case 3: 465 strlcpy(fp->name, AudioEslinear, sizeof fp->name); 466 fp->encoding = AUDIO_ENCODING_SLINEAR; 467 fp->precision = 8; 468 fp->flags = 0; 469 break; 470 case 4: 471 strlcpy(fp->name, AudioEslinear_le, sizeof fp->name); 472 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 473 fp->precision = 16; 474 fp->flags = 0; 475 break; 476 case 5: 477 strlcpy(fp->name, AudioEulinear_le, sizeof fp->name); 478 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 479 fp->precision = 16; 480 fp->flags = 0; 481 break; 482 case 6: 483 strlcpy(fp->name, AudioEslinear_be, sizeof fp->name); 484 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 485 fp->precision = 16; 486 fp->flags = 0; 487 break; 488 case 7: 489 strlcpy(fp->name, AudioEulinear_be, sizeof fp->name); 490 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 491 fp->precision = 16; 492 fp->flags = 0; 493 break; 494 default: 495 return EINVAL; 496 } 497 return (0); 498 } 499 500 int 501 cs4281_set_params(addr, setmode, usemode, play, rec) 502 void *addr; 503 int setmode, usemode; 504 struct audio_params *play, *rec; 505 { 506 struct cs4281_softc *sc = addr; 507 struct audio_params *p; 508 int mode; 509 510 for (mode = AUMODE_RECORD; mode != -1; 511 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { 512 if ((setmode & mode) == 0) 513 continue; 514 515 p = mode == AUMODE_PLAY ? play : rec; 516 517 if (p == play) { 518 DPRINTFN(5,("play: samp=%ld precision=%d channels=%d\n", 519 p->sample_rate, p->precision, p->channels)); 520 } else { 521 DPRINTFN(5,("rec: samp=%ld precision=%d channels=%d\n", 522 p->sample_rate, p->precision, p->channels)); 523 } 524 if (p->sample_rate < 6023) 525 p->sample_rate = 6023; 526 if (p->sample_rate > 48000) 527 p->sample_rate = 48000; 528 if (p->precision > 16) 529 p->precision = 16; 530 if (p->channels > 2) 531 p->channels = 2; 532 p->factor = 1; 533 p->sw_code = 0; 534 535 switch (p->encoding) { 536 case AUDIO_ENCODING_SLINEAR_BE: 537 break; 538 case AUDIO_ENCODING_SLINEAR_LE: 539 break; 540 case AUDIO_ENCODING_ULINEAR_BE: 541 break; 542 case AUDIO_ENCODING_ULINEAR_LE: 543 break; 544 case AUDIO_ENCODING_ULAW: 545 if (mode == AUMODE_PLAY) { 546 p->sw_code = mulaw_to_slinear8; 547 } else { 548 p->sw_code = slinear8_to_mulaw; 549 } 550 break; 551 case AUDIO_ENCODING_ALAW: 552 if (mode == AUMODE_PLAY) { 553 p->sw_code = alaw_to_slinear8; 554 } else { 555 p->sw_code = slinear8_to_alaw; 556 } 557 break; 558 default: 559 return (EINVAL); 560 } 561 } 562 563 /* set sample rate */ 564 cs4281_set_dac_rate(sc, play->sample_rate); 565 cs4281_set_adc_rate(sc, rec->sample_rate); 566 return (0); 567 } 568 569 int 570 cs4281_halt_output(addr) 571 void *addr; 572 { 573 struct cs4281_softc *sc = addr; 574 575 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 576 #ifdef DIAGNOSTIC 577 sc->sc_prun = 0; 578 #endif 579 return (0); 580 } 581 582 int 583 cs4281_halt_input(addr) 584 void *addr; 585 { 586 struct cs4281_softc *sc = addr; 587 588 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 589 #ifdef DIAGNOSTIC 590 sc->sc_rrun = 0; 591 #endif 592 return (0); 593 } 594 595 /* trivial */ 596 int 597 cs4281_getdev(addr, retp) 598 void *addr; 599 struct audio_device *retp; 600 { 601 *retp = cs4281_device; 602 return (0); 603 } 604 605 606 int 607 cs4281_trigger_output(addr, start, end, blksize, intr, arg, param) 608 void *addr; 609 void *start, *end; 610 int blksize; 611 void (*intr)(void *); 612 void *arg; 613 struct audio_params *param; 614 { 615 struct cs4281_softc *sc = addr; 616 u_int32_t fmt=0; 617 struct cs4281_dma *p; 618 int dma_count; 619 620 #ifdef DIAGNOSTIC 621 if (sc->sc_prun) 622 printf("cs4281_trigger_output: already running\n"); 623 sc->sc_prun = 1; 624 #endif 625 626 DPRINTF(("cs4281_trigger_output: sc=%p start=%p end=%p " 627 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 628 sc->sc_pintr = intr; 629 sc->sc_parg = arg; 630 631 /* stop playback DMA */ 632 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); 633 634 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 635 param->precision, param->factor, param->channels, 636 param->encoding)); 637 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 638 ; 639 if (p == NULL) { 640 printf("cs4281_trigger_output: bad addr %p\n", start); 641 return (EINVAL); 642 } 643 644 sc->sc_pcount = blksize / sc->hw_blocksize; 645 sc->sc_ps = (char *)start; 646 sc->sc_pe = (char *)end; 647 sc->sc_pdma = p; 648 sc->sc_pbuf = KERNADDR(p); 649 sc->sc_pi = 0; 650 sc->sc_pn = sc->sc_ps; 651 if (blksize >= sc->dma_size) { 652 sc->sc_pn = sc->sc_ps + sc->dma_size; 653 memcpy(sc->sc_pbuf, start, sc->dma_size); 654 ++sc->sc_pi; 655 } else { 656 sc->sc_pn = sc->sc_ps + sc->hw_blocksize; 657 memcpy(sc->sc_pbuf, start, sc->hw_blocksize); 658 } 659 660 dma_count = sc->dma_size; 661 if (param->precision * param->factor != 8) 662 dma_count /= 2; /* 16 bit */ 663 if (param->channels > 1) 664 dma_count /= 2; /* Stereo */ 665 666 DPRINTF(("cs4281_trigger_output: DMAADDR(p)=0x%x count=%d\n", 667 (int)DMAADDR(p), dma_count)); 668 BA0WRITE4(sc, CS4281_DBA0, DMAADDR(p)); 669 BA0WRITE4(sc, CS4281_DBC0, dma_count-1); 670 671 /* set playback format */ 672 fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK; 673 if (param->precision * param->factor == 8) 674 fmt |= DMRn_SIZE8; 675 if (param->channels == 1) 676 fmt |= DMRn_MONO; 677 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 678 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 679 fmt |= DMRn_BEND; 680 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 681 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 682 fmt |= DMRn_USIGN; 683 BA0WRITE4(sc, CS4281_DMR0, fmt); 684 685 /* set sample rate */ 686 cs4281_set_dac_rate(sc, param->sample_rate); 687 688 /* start DMA */ 689 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK); 690 /* Enable interrupts */ 691 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 692 693 BA0WRITE4(sc, CS4281_PPRVC, 7); 694 BA0WRITE4(sc, CS4281_PPLVC, 7); 695 696 DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR))); 697 DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR))); 698 DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0))); 699 DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0))); 700 DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0))); 701 DPRINTF(("DACSR=0x%08x(expected 1 for 44kHz 5 for 8kHz)\n", 702 BA0READ4(sc, CS4281_DACSR))); 703 DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA))); 704 DPRINTF(("SSPM&SSPM_PSRCEN =0x%08x(expected 0x00000010)\n", 705 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN)); 706 707 return (0); 708 } 709 710 int 711 cs4281_trigger_input(addr, start, end, blksize, intr, arg, param) 712 void *addr; 713 void *start, *end; 714 int blksize; 715 void (*intr)(void *); 716 void *arg; 717 struct audio_params *param; 718 { 719 struct cs4281_softc *sc = addr; 720 struct cs4281_dma *p; 721 u_int32_t fmt=0; 722 int dma_count; 723 724 printf("cs4281_trigger_input: not implemented yet\n"); 725 #ifdef DIAGNOSTIC 726 if (sc->sc_rrun) 727 printf("cs4281_trigger_input: already running\n"); 728 sc->sc_rrun = 1; 729 #endif 730 DPRINTF(("cs4281_trigger_input: sc=%p start=%p end=%p " 731 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 732 sc->sc_rintr = intr; 733 sc->sc_rarg = arg; 734 735 /* stop recording DMA */ 736 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK); 737 738 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 739 ; 740 if (!p) { 741 printf("cs4281_trigger_input: bad addr %p\n", start); 742 return (EINVAL); 743 } 744 745 sc->sc_rcount = blksize / sc->hw_blocksize; 746 sc->sc_rs = (char *)start; 747 sc->sc_re = (char *)end; 748 sc->sc_rdma = p; 749 sc->sc_rbuf = KERNADDR(p); 750 sc->sc_ri = 0; 751 sc->sc_rn = sc->sc_rs; 752 753 dma_count = sc->dma_size; 754 if (param->precision * param->factor == 8) 755 dma_count /= 2; 756 if (param->channels > 1) 757 dma_count /= 2; 758 759 DPRINTF(("cs4281_trigger_input: DMAADDR(p)=0x%x count=%d\n", 760 (int)DMAADDR(p), dma_count)); 761 BA0WRITE4(sc, CS4281_DBA1, DMAADDR(p)); 762 BA0WRITE4(sc, CS4281_DBC1, dma_count-1); 763 764 /* set recording format */ 765 fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK; 766 if (param->precision * param->factor == 8) 767 fmt |= DMRn_SIZE8; 768 if (param->channels == 1) 769 fmt |= DMRn_MONO; 770 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 771 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 772 fmt |= DMRn_BEND; 773 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 774 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 775 fmt |= DMRn_USIGN; 776 BA0WRITE4(sc, CS4281_DMR1, fmt); 777 778 /* set sample rate */ 779 cs4281_set_adc_rate(sc, param->sample_rate); 780 781 /* Start DMA */ 782 BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK); 783 /* Enable interrupts */ 784 BA0WRITE4(sc, CS4281_HICR, HICR_IEV | HICR_CHGM); 785 786 DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR))); 787 DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR))); 788 DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1))); 789 DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1))); 790 791 return (0); 792 } 793 794 /* convert sample rate to register value */ 795 u_int8_t 796 cs4281_sr2regval(rate) 797 int rate; 798 { 799 u_int8_t retval; 800 801 /* We don't have to change here. but anyway ... */ 802 if (rate > 48000) 803 rate = 48000; 804 if (rate < 6023) 805 rate = 6023; 806 807 switch (rate) { 808 case 8000: 809 retval = 5; 810 break; 811 case 11025: 812 retval = 4; 813 break; 814 case 16000: 815 retval = 3; 816 break; 817 case 22050: 818 retval = 2; 819 break; 820 case 44100: 821 retval = 1; 822 break; 823 case 48000: 824 retval = 0; 825 break; 826 default: 827 retval = 1536000/rate; /* == 24576000/(rate*16) */ 828 } 829 return (retval); 830 } 831 832 833 void 834 cs4281_set_dac_rate(sc, rate) 835 struct cs4281_softc *sc; 836 int rate; 837 { 838 BA0WRITE4(sc, CS4281_DACSR, cs4281_sr2regval(rate)); 839 } 840 841 void 842 cs4281_set_adc_rate(sc, rate) 843 struct cs4281_softc *sc; 844 int rate; 845 { 846 BA0WRITE4(sc, CS4281_ADCSR, cs4281_sr2regval(rate)); 847 } 848 849 int 850 cs4281_init(sc) 851 struct cs4281_softc *sc; 852 { 853 int n; 854 u_int16_t data; 855 u_int32_t dat32; 856 857 /* set "Configuration Write Protect" register to 858 * 0x4281 to allow to write */ 859 BA0WRITE4(sc, CS4281_CWPR, 0x4281); 860 861 /* 862 * Unset "Full Power-Down bit of Extended PCI Power Management 863 * Control" register to release the reset state. 864 */ 865 dat32 = BA0READ4(sc, CS4281_EPPMC); 866 if (dat32 & EPPMC_FPDN) 867 BA0WRITE4(sc, CS4281_EPPMC, dat32 & ~EPPMC_FPDN); 868 869 /* Start PLL out in known state */ 870 BA0WRITE4(sc, CS4281_CLKCR1, 0); 871 /* Start serial ports out in known state */ 872 BA0WRITE4(sc, CS4281_SERMC, 0); 873 874 /* Reset codec */ 875 BA0WRITE4(sc, CS4281_ACCTL, 0); 876 delay(50); /* delay 50us */ 877 878 BA0WRITE4(sc, CS4281_SPMC, 0); 879 delay(100); /* delay 100us */ 880 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 881 #if defined(ENABLE_SECONDARY_CODEC) 882 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 883 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 884 #endif 885 delay(50000); /* XXX: delay 50ms */ 886 887 /* Turn on Sound System clocks based on ABITCLK */ 888 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_DLLP); 889 delay(50000); /* XXX: delay 50ms */ 890 BA0WRITE4(sc, CS4281_CLKCR1, CLKCR1_SWCE | CLKCR1_DLLP); 891 892 /* Set enables for sections that are needed in the SSPM registers */ 893 BA0WRITE4(sc, CS4281_SSPM, 894 SSPM_MIXEN | /* Mixer */ 895 SSPM_CSRCEN | /* Capture SRC */ 896 SSPM_PSRCEN | /* Playback SRC */ 897 SSPM_JSEN | /* Joystick */ 898 SSPM_ACLEN | /* AC LINK */ 899 SSPM_FMEN /* FM */ 900 ); 901 902 /* Wait for clock stabilization */ 903 n = 0; 904 while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON)) 905 != (CLKCR1_DLLRDY | CLKCR1_CLKON)) { 906 delay(100); 907 if (++n > 1000) 908 return (-1); 909 } 910 911 /* Enable ASYNC generation */ 912 BA0WRITE4(sc, CS4281_ACCTL, ACCTL_ESYN); 913 914 /* Wait for Codec ready. Linux driver wait 50ms here */ 915 n = 0; 916 while((BA0READ4(sc, CS4281_ACSTS) & ACSTS_CRDY) == 0) { 917 delay(100); 918 if (++n > 1000) 919 return (-1); 920 } 921 922 #if defined(ENABLE_SECONDARY_CODEC) 923 /* secondary codec ready*/ 924 n = 0; 925 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 926 delay(100); 927 if (++n > 1000) 928 return (-1); 929 } 930 #endif 931 932 /* Set the serial timing configuration */ 933 /* XXX: undocumented but the Linux driver do this */ 934 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 935 936 /* Wait for Codec ready signal */ 937 n = 0; 938 do { 939 delay(1000); 940 if (++n > 1000) { 941 printf("%s: Timeout waiting for Codec ready\n", 942 sc->sc_dev.dv_xname); 943 return -1; 944 } 945 dat32 = BA0READ4(sc, CS4281_ACSTS) & ACSTS_CRDY; 946 } while (dat32 == 0); 947 948 /* Enable Valid Frame output on ASDOUT */ 949 BA0WRITE4(sc, CS4281_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 950 951 /* Wait until Codec Calibration is finished. Codec register 26h */ 952 n = 0; 953 do { 954 delay(1); 955 if (++n > 1000) { 956 printf("%s: Timeout waiting for Codec calibration\n", 957 sc->sc_dev.dv_xname); 958 return -1; 959 } 960 cs4281_read_codec(sc, AC97_REG_POWER, &data); 961 } while ((data & 0x0f) != 0x0f); 962 963 /* Set the serial timing configuration again */ 964 /* XXX: undocumented but the Linux driver do this */ 965 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 966 967 /* Wait until we've sampled input slots 3 & 4 as valid */ 968 n = 0; 969 do { 970 delay(1000); 971 if (++n > 1000) { 972 printf("%s: Timeout waiting for sampled input slots as valid\n", 973 sc->sc_dev.dv_xname); 974 return -1; 975 } 976 dat32 = BA0READ4(sc, CS4281_ACISV) & (ACISV_ISV3 | ACISV_ISV4); 977 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 978 979 /* Start digital data transfer of audio data to the codec */ 980 BA0WRITE4(sc, CS4281_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 981 982 cs4281_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); 983 cs4281_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); 984 985 /* Power on the DAC */ 986 cs4281_read_codec(sc, AC97_REG_POWER, &data); 987 cs4281_write_codec(sc, AC97_REG_POWER, data &= 0xfdff); 988 989 /* Wait until we sample a DAC ready state. 990 * Not documented, but Linux driver does. 991 */ 992 for (n = 0; n < 32; ++n) { 993 delay(1000); 994 cs4281_read_codec(sc, AC97_REG_POWER, &data); 995 if (data & 0x02) 996 break; 997 } 998 999 /* Power on the ADC */ 1000 cs4281_read_codec(sc, AC97_REG_POWER, &data); 1001 cs4281_write_codec(sc, AC97_REG_POWER, data &= 0xfeff); 1002 1003 /* Wait until we sample ADC ready state. 1004 * Not documented, but Linux driver does. 1005 */ 1006 for (n = 0; n < 32; ++n) { 1007 delay(1000); 1008 cs4281_read_codec(sc, AC97_REG_POWER, &data); 1009 if (data & 0x01) 1010 break; 1011 } 1012 1013 #if 0 1014 /* Initialize SSCR register features */ 1015 /* XXX: hardware volume setting */ 1016 BA0WRITE4(sc, CS4281_SSCR, ~SSCR_HVC); /* disable HW volume setting */ 1017 #endif 1018 1019 /* disable Sound Blaster Pro emulation */ 1020 /* XXX: 1021 * Cannot set since the documents does not describe which bit is 1022 * correspond to SSCR_SB. Since the reset value of SSCR is 0, 1023 * we can ignore it.*/ 1024 #if 0 1025 BA0WRITE4(sc, CS4281_SSCR, SSCR_SB); 1026 #endif 1027 1028 /* map AC97 PCM playback to DMA Channel 0 */ 1029 /* Reset FEN bit to setup first */ 1030 BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN)); 1031 /* 1032 *| RS[4:0]/| | 1033 *| LS[4:0] | AC97 | Slot Function 1034 *|---------+--------+-------------------- 1035 *| 0 | 3 | Left PCM Playback 1036 *| 1 | 4 | Right PCM Playback 1037 *| 2 | 5 | Phone Line 1 DAC 1038 *| 3 | 6 | Center PCM Playback 1039 *.... 1040 * quoted from Table 29(p109) 1041 */ 1042 dat32 = 0x01 << 24 | /* RS[4:0] = 1 see above */ 1043 0x00 << 16 | /* LS[4:0] = 0 see above */ 1044 0x0f << 8 | /* SZ[6:0] = 15 size of buffer */ 1045 0x00 << 0 ; /* OF[6:0] = 0 offset */ 1046 BA0WRITE4(sc, CS4281_FCR0, dat32); 1047 BA0WRITE4(sc, CS4281_FCR0, dat32 | FCRn_FEN); 1048 1049 /* map AC97 PCM record to DMA Channel 1 */ 1050 /* Reset FEN bit to setup first */ 1051 BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN)); 1052 /* 1053 *| RS[4:0]/| 1054 *| LS[4:0] | AC97 | Slot Function 1055 *|---------+------+------------------- 1056 *| 10 | 3 | Left PCM Record 1057 *| 11 | 4 | Right PCM Record 1058 *| 12 | 5 | Phone Line 1 ADC 1059 *| 13 | 6 | Mic ADC 1060 *.... 1061 * quoted from Table 30(p109) 1062 */ 1063 dat32 = 0x0b << 24 | /* RS[4:0] = 11 See above */ 1064 0x0a << 16 | /* LS[4:0] = 10 See above */ 1065 0x0f << 8 | /* SZ[6:0] = 15 Size of buffer */ 1066 0x10 << 0 ; /* OF[6:0] = 16 offset */ 1067 1068 /* XXX: I cannot understand why FCRn_PSH is needed here. */ 1069 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_PSH); 1070 BA0WRITE4(sc, CS4281_FCR1, dat32 | FCRn_FEN); 1071 1072 #if 0 1073 /* Disable DMA Channel 2, 3 */ 1074 BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN)); 1075 BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN)); 1076 #endif 1077 1078 /* Set the SRC Slot Assignment accordingly */ 1079 /*| PLSS[4:0]/ 1080 *| PRSS[4:0] | AC97 | Slot Function 1081 *|-----------+------+---------------- 1082 *| 0 | 3 | Left PCM Playback 1083 *| 1 | 4 | Right PCM Playback 1084 *| 2 | 5 | phone line 1 DAC 1085 *| 3 | 6 | Center PCM Playback 1086 *| 4 | 7 | Left Surround PCM Playback 1087 *| 5 | 8 | Right Surround PCM Playback 1088 *...... 1089 * 1090 *| CLSS[4:0]/ 1091 *| CRSS[4:0] | AC97 | Codec |Slot Function 1092 *|-----------+------+-------+----------------- 1093 *| 10 | 3 |Primary| Left PCM Record 1094 *| 11 | 4 |Primary| Right PCM Record 1095 *| 12 | 5 |Primary| Phone Line 1 ADC 1096 *| 13 | 6 |Primary| Mic ADC 1097 *|..... 1098 *| 20 | 3 | Sec. | Left PCM Record 1099 *| 21 | 4 | Sec. | Right PCM Record 1100 *| 22 | 5 | Sec. | Phone Line 1 ADC 1101 *| 23 | 6 | Sec. | Mic ADC 1102 */ 1103 dat32 = 0x0b << 24 | /* CRSS[4:0] Right PCM Record(primary) */ 1104 0x0a << 16 | /* CLSS[4:0] Left PCM Record(primary) */ 1105 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 1106 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ 1107 BA0WRITE4(sc, CS4281_SRCSA, dat32); 1108 1109 /* Set interrupt to occurred at Half and Full terminal 1110 * count interrupt enable for DMA channel 0 and 1. 1111 * To keep DMA stop, set MSK. 1112 */ 1113 dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; 1114 BA0WRITE4(sc, CS4281_DCR0, dat32); 1115 BA0WRITE4(sc, CS4281_DCR1, dat32); 1116 1117 /* Set Auto-Initialize Control enable */ 1118 BA0WRITE4(sc, CS4281_DMR0, 1119 DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); 1120 BA0WRITE4(sc, CS4281_DMR1, 1121 DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); 1122 1123 /* Clear DMA Mask in HIMR */ 1124 dat32 = BA0READ4(sc, CS4281_HIMR) & 0xfffbfcff; 1125 BA0WRITE4(sc, CS4281_HIMR, dat32); 1126 return (0); 1127 } 1128 1129 void 1130 cs4281_power(why, v) 1131 int why; 1132 void *v; 1133 { 1134 struct cs4281_softc *sc = (struct cs4281_softc *)v; 1135 int i; 1136 1137 DPRINTF(("%s: cs4281_power why=%d\n", sc->sc_dev.dv_xname, why)); 1138 if (why != PWR_RESUME) { 1139 sc->sc_suspend = why; 1140 1141 cs4281_halt_output(sc); 1142 cs4281_halt_input(sc); 1143 /* Save AC97 registers */ 1144 for (i = 1; i <= CS4281_SAVE_REG_MAX; i++) { 1145 if (i == 0x04) /* AC97_REG_MASTER_TONE */ 1146 continue; 1147 cs4281_read_codec(sc, 2*i, &sc->ac97_reg[i>>1]); 1148 } 1149 /* should I powerdown here ? */ 1150 cs4281_write_codec(sc, AC97_REG_POWER, CS4281_POWER_DOWN_ALL); 1151 } else { 1152 if (sc->sc_suspend == PWR_RESUME) { 1153 printf("cs4281_power: odd, resume without suspend.\n"); 1154 sc->sc_suspend = why; 1155 return; 1156 } 1157 sc->sc_suspend = why; 1158 cs4281_init(sc); 1159 cs4281_reset_codec(sc); 1160 1161 /* restore ac97 registers */ 1162 for (i = 1; i <= CS4281_SAVE_REG_MAX; i++) { 1163 if (i == 0x04) /* AC97_REG_MASTER_TONE */ 1164 continue; 1165 cs4281_write_codec(sc, 2*i, sc->ac97_reg[i>>1]); 1166 } 1167 } 1168 } 1169 1170 void 1171 cs4281_reset_codec(void *addr) 1172 { 1173 struct cs4281_softc *sc; 1174 u_int16_t data; 1175 u_int32_t dat32; 1176 int n; 1177 1178 sc = addr; 1179 1180 DPRINTFN(3,("cs4281_reset_codec\n")); 1181 1182 /* Reset codec */ 1183 BA0WRITE4(sc, CS4281_ACCTL, 0); 1184 delay(50); /* delay 50us */ 1185 1186 BA0WRITE4(sc, CS4281_SPMC, 0); 1187 delay(100); /* delay 100us */ 1188 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN); 1189 #if defined(ENABLE_SECONDARY_CODEC) 1190 BA0WRITE4(sc, CS4281_SPMC, SPMC_RSTN | SPCM_ASDIN2E); 1191 BA0WRITE4(sc, CS4281_SERMC, SERMC_TCID); 1192 #endif 1193 delay(50000); /* XXX: delay 50ms */ 1194 1195 /* Enable ASYNC generation */ 1196 BA0WRITE4(sc, CS4281_ACCTL, ACCTL_ESYN); 1197 1198 /* Wait for Codec ready. Linux driver wait 50ms here */ 1199 n = 0; 1200 while((BA0READ4(sc, CS4281_ACSTS) & ACSTS_CRDY) == 0) { 1201 delay(100); 1202 if (++n > 1000) { 1203 printf("reset_codec: AC97 codec ready timeout\n"); 1204 return; 1205 } 1206 } 1207 #if defined(ENABLE_SECONDARY_CODEC) 1208 /* secondary codec ready*/ 1209 n = 0; 1210 while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) { 1211 delay(100); 1212 if (++n > 1000) 1213 return; 1214 } 1215 #endif 1216 /* Set the serial timing configuration */ 1217 /* XXX: undocumented but the Linux driver do this */ 1218 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1219 1220 /* Wait for Codec ready signal */ 1221 n = 0; 1222 do { 1223 delay(1000); 1224 if (++n > 1000) { 1225 printf("%s: Timeout waiting for Codec ready\n", 1226 sc->sc_dev.dv_xname); 1227 return; 1228 } 1229 dat32 = BA0READ4(sc, CS4281_ACSTS) & ACSTS_CRDY; 1230 } while (dat32 == 0); 1231 1232 /* Enable Valid Frame output on ASDOUT */ 1233 BA0WRITE4(sc, CS4281_ACCTL, ACCTL_ESYN | ACCTL_VFRM); 1234 1235 /* Wait until Codec Calibration is finished. Codec register 26h */ 1236 n = 0; 1237 do { 1238 delay(1); 1239 if (++n > 1000) { 1240 printf("%s: Timeout waiting for Codec calibration\n", 1241 sc->sc_dev.dv_xname); 1242 return ; 1243 } 1244 cs4281_read_codec(sc, AC97_REG_POWER, &data); 1245 } while ((data & 0x0f) != 0x0f); 1246 1247 /* Set the serial timing configuration again */ 1248 /* XXX: undocumented but the Linux driver do this */ 1249 BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); 1250 1251 /* Wait until we've sampled input slots 3 & 4 as valid */ 1252 n = 0; 1253 do { 1254 delay(1000); 1255 if (++n > 1000) { 1256 printf("%s: Timeout waiting for sampled input slots as valid\n", 1257 sc->sc_dev.dv_xname); 1258 return; 1259 } 1260 dat32 = BA0READ4(sc, CS4281_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; 1261 } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); 1262 1263 /* Start digital data transfer of audio data to the codec */ 1264 BA0WRITE4(sc, CS4281_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); 1265 } 1266 1267 int 1268 cs4281_open(void *addr, int flags) 1269 { 1270 return (0); 1271 } 1272 1273 void 1274 cs4281_close(void *addr) 1275 { 1276 struct cs4281_softc *sc; 1277 1278 sc = addr; 1279 1280 (*sc->halt_output)(sc); 1281 (*sc->halt_input)(sc); 1282 1283 sc->sc_pintr = 0; 1284 sc->sc_rintr = 0; 1285 } 1286 1287 int 1288 cs4281_round_blocksize(void *addr, int blk) 1289 { 1290 struct cs4281_softc *sc; 1291 int retval; 1292 1293 DPRINTFN(5,("cs4281_round_blocksize blk=%d -> ", blk)); 1294 1295 sc=addr; 1296 if (blk < sc->hw_blocksize) 1297 retval = sc->hw_blocksize; 1298 else 1299 retval = blk & -(sc->hw_blocksize); 1300 1301 DPRINTFN(5,("%d\n", retval)); 1302 1303 return (retval); 1304 } 1305 1306 int 1307 cs4281_mixer_set_port(void *addr, mixer_ctrl_t *cp) 1308 { 1309 struct cs4281_softc *sc; 1310 int val; 1311 1312 sc = addr; 1313 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1314 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1315 return (val); 1316 } 1317 1318 int 1319 cs4281_mixer_get_port(void *addr, mixer_ctrl_t *cp) 1320 { 1321 struct cs4281_softc *sc; 1322 1323 sc = addr; 1324 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1325 } 1326 1327 1328 int 1329 cs4281_query_devinfo(void *addr, mixer_devinfo_t *dip) 1330 { 1331 struct cs4281_softc *sc; 1332 1333 sc = addr; 1334 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1335 } 1336 1337 void * 1338 cs4281_malloc(void *addr, int direction, size_t size, int pool, int flags) 1339 { 1340 struct cs4281_softc *sc; 1341 struct cs4281_dma *p; 1342 int error; 1343 1344 sc = addr; 1345 1346 p = malloc(sizeof(*p), pool, flags); 1347 if (!p) 1348 return (0); 1349 1350 error = cs4281_allocmem(sc, size, pool, flags, p); 1351 1352 if (error) { 1353 free(p, pool); 1354 return (0); 1355 } 1356 1357 p->next = sc->sc_dmas; 1358 sc->sc_dmas = p; 1359 return (BUFADDR(p)); 1360 } 1361 1362 1363 1364 void 1365 cs4281_free(void *addr, void *ptr, int pool) 1366 { 1367 struct cs4281_softc *sc; 1368 struct cs4281_dma **pp, *p; 1369 1370 sc = addr; 1371 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1372 if (BUFADDR(p) == ptr) { 1373 bus_dmamap_unload(sc->sc_dmatag, p->map); 1374 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1375 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1376 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1377 free(p->dum, pool); 1378 *pp = p->next; 1379 free(p, pool); 1380 return; 1381 } 1382 } 1383 } 1384 1385 size_t 1386 cs4281_round_buffersize(void *addr, int direction, size_t size) 1387 { 1388 /* The real dma buffersize are 4KB for CS4280 1389 * and 64kB/MAX_CHANNELS for CS4281. 1390 * But they are too small for high quality audio, 1391 * let the upper layer(audio) use a larger buffer. 1392 * (originally suggested by Lennart Augustsson.) 1393 */ 1394 return (size); 1395 } 1396 1397 paddr_t 1398 cs4281_mappage(void *addr, void *mem, off_t off, int prot) 1399 { 1400 struct cs4281_softc *sc; 1401 struct cs4281_dma *p; 1402 1403 sc = addr; 1404 if (off < 0) 1405 return -1; 1406 1407 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1408 ; 1409 1410 if (!p) { 1411 DPRINTF(("cs4281_mappage: bad buffer address\n")); 1412 return (-1); 1413 } 1414 1415 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, off, prot, 1416 BUS_DMA_WAITOK)); 1417 } 1418 1419 1420 int 1421 cs4281_get_props(void *addr) 1422 { 1423 int retval; 1424 1425 retval = AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1426 #ifdef MMAP_READY 1427 retval |= AUDIO_PROP_MMAP; 1428 #endif 1429 return (retval); 1430 } 1431 1432 /* AC97 */ 1433 int 1434 cs4281_attach_codec(void *addr, struct ac97_codec_if *codec_if) 1435 { 1436 struct cs4281_softc *sc; 1437 1438 DPRINTF(("cs4281_attach_codec:\n")); 1439 sc = addr; 1440 sc->codec_if = codec_if; 1441 return (0); 1442 } 1443 1444 1445 int 1446 cs4281_read_codec(void *addr, u_int8_t ac97_addr, u_int16_t *ac97_data) 1447 { 1448 struct cs4281_softc *sc; 1449 u_int32_t acctl; 1450 int n; 1451 1452 sc = addr; 1453 1454 DPRINTFN(5,("read_codec: add=0x%02x ", ac97_addr)); 1455 /* 1456 * Make sure that there is not data sitting around from a preivous 1457 * uncompleted access. 1458 */ 1459 BA0READ4(sc, CS4281_ACSDA); 1460 1461 /* Set up AC97 control registers. */ 1462 BA0WRITE4(sc, CS4281_ACCAD, ac97_addr); 1463 BA0WRITE4(sc, CS4281_ACCDA, 0); 1464 1465 acctl = ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV; 1466 BA0WRITE4(sc, CS4281_ACCTL, acctl); 1467 1468 if (cs4281_src_wait(sc) < 0) { 1469 printf("%s: AC97 read prob. (DCV!=0) for add=0x%0x\n", 1470 sc->sc_dev.dv_xname, ac97_addr); 1471 return 1; 1472 } 1473 1474 /* wait for valid status bit is active */ 1475 n = 0; 1476 while ((BA0READ4(sc, CS4281_ACSTS) & ACSTS_VSTS) == 0) { 1477 delay(1); 1478 while (++n > 1000) { 1479 printf("%s: AC97 read fail (VSTS==0) for add=0x%0x\n", 1480 sc->sc_dev.dv_xname, ac97_addr); 1481 return 1; 1482 } 1483 } 1484 *ac97_data = BA0READ4(sc, CS4281_ACSDA); 1485 DPRINTFN(5,("data=0x%04x\n", *ac97_data)); 1486 return (0); 1487 } 1488 1489 int 1490 cs4281_write_codec(void *addr, u_int8_t ac97_addr, u_int16_t ac97_data) 1491 { 1492 struct cs4281_softc *sc; 1493 u_int32_t acctl; 1494 1495 sc = addr; 1496 1497 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", ac97_addr, ac97_data)); 1498 BA0WRITE4(sc, CS4281_ACCAD, ac97_addr); 1499 BA0WRITE4(sc, CS4281_ACCDA, ac97_data); 1500 1501 acctl = ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV; 1502 BA0WRITE4(sc, CS4281_ACCTL, acctl); 1503 1504 if (cs4281_src_wait(sc) < 0) { 1505 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 1506 "0x%04x\n", sc->sc_dev.dv_xname, ac97_addr, ac97_data); 1507 return (1); 1508 } 1509 return (0); 1510 } 1511 1512 int 1513 cs4281_allocmem(struct cs4281_softc *sc, size_t size, int pool, int flags, 1514 struct cs4281_dma *p) 1515 { 1516 int error; 1517 size_t align; 1518 1519 align = sc->dma_align; 1520 p->size = sc->dma_size; 1521 /* allocate memory for upper audio driver */ 1522 p->dum = malloc(size, pool, flags); 1523 if (!p->dum) 1524 return (1); 1525 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1526 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1527 &p->nsegs, BUS_DMA_NOWAIT); 1528 if (error) { 1529 printf("%s: unable to allocate dma. error=%d\n", 1530 sc->sc_dev.dv_xname, error); 1531 return (error); 1532 } 1533 1534 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1535 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1536 if (error) { 1537 printf("%s: unable to map dma, error=%d\n", 1538 sc->sc_dev.dv_xname, error); 1539 goto free; 1540 } 1541 1542 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1543 0, BUS_DMA_NOWAIT, &p->map); 1544 if (error) { 1545 printf("%s: unable to create dma map, error=%d\n", 1546 sc->sc_dev.dv_xname, error); 1547 goto unmap; 1548 } 1549 1550 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1551 BUS_DMA_NOWAIT); 1552 if (error) { 1553 printf("%s: unable to load dma map, error=%d\n", 1554 sc->sc_dev.dv_xname, error); 1555 goto destroy; 1556 } 1557 return (0); 1558 1559 destroy: 1560 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1561 unmap: 1562 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1563 free: 1564 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1565 return (error); 1566 } 1567 1568 1569 int 1570 cs4281_src_wait(sc) 1571 struct cs4281_softc *sc; 1572 { 1573 int n; 1574 1575 n = 0; 1576 while ((BA0READ4(sc, CS4281_ACCTL) & ACCTL_DCV)) { 1577 delay(1000); 1578 if (++n > 1000) 1579 return (-1); 1580 } 1581 return (0); 1582 } 1583