1 /* $OpenBSD: cs4280.c,v 1.17 2003/04/27 11:22:53 ho Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 #include <sys/types.h> 75 #include <sys/systm.h> 76 77 #include <dev/pci/pcidevs.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/cs4280reg.h> 80 #include <dev/microcode/cirruslogic/cs4280_image.h> 81 82 #include <sys/audioio.h> 83 #include <dev/audio_if.h> 84 #include <dev/midi_if.h> 85 #include <dev/mulaw.h> 86 #include <dev/auconv.h> 87 88 #include <dev/ic/ac97.h> 89 90 #include <machine/bus.h> 91 92 #define CSCC_PCI_BA0 0x10 93 #define CSCC_PCI_BA1 0x14 94 95 struct cs4280_dma { 96 bus_dmamap_t map; 97 caddr_t addr; /* real dma buffer */ 98 caddr_t dum; /* dummy buffer for audio driver */ 99 bus_dma_segment_t segs[1]; 100 int nsegs; 101 size_t size; 102 struct cs4280_dma *next; 103 }; 104 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 105 #define BUFADDR(p) ((void *)((p)->dum)) 106 #define KERNADDR(p) ((void *)((p)->addr)) 107 108 /* 109 * Software state 110 */ 111 struct cs4280_softc { 112 struct device sc_dev; 113 114 pci_intr_handle_t * sc_ih; 115 116 /* I/O (BA0) */ 117 bus_space_tag_t ba0t; 118 bus_space_handle_t ba0h; 119 120 /* BA1 */ 121 bus_space_tag_t ba1t; 122 bus_space_handle_t ba1h; 123 124 /* DMA */ 125 bus_dma_tag_t sc_dmatag; 126 struct cs4280_dma *sc_dmas; 127 128 void (*sc_pintr)(void *); /* dma completion intr handler */ 129 void *sc_parg; /* arg for sc_intr() */ 130 char *sc_ps, *sc_pe, *sc_pn; 131 int sc_pcount; 132 int sc_pi; 133 struct cs4280_dma *sc_pdma; 134 char *sc_pbuf; 135 #ifdef DIAGNOSTIC 136 char sc_prun; 137 #endif 138 139 void (*sc_rintr)(void *); /* dma completion intr handler */ 140 void *sc_rarg; /* arg for sc_intr() */ 141 char *sc_rs, *sc_re, *sc_rn; 142 int sc_rcount; 143 int sc_ri; 144 struct cs4280_dma *sc_rdma; 145 char *sc_rbuf; 146 int sc_rparam; /* record format */ 147 #ifdef DIAGNOSTIC 148 char sc_rrun; 149 #endif 150 151 #if NMIDI > 0 152 void (*sc_iintr)(void *, int); /* midi input ready handler */ 153 void (*sc_ointr)(void *); /* midi output ready handler */ 154 void *sc_arg; 155 #endif 156 157 u_int32_t pctl; 158 u_int32_t cctl; 159 160 struct ac97_codec_if *codec_if; 161 struct ac97_host_if host_if; 162 163 char sc_suspend; 164 void *sc_powerhook; /* Power Hook */ 165 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 166 }; 167 168 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 169 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 170 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 171 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 172 173 int cs4280_match(struct device *, void *, void *); 174 void cs4280_attach(struct device *, struct device *, void *); 175 int cs4280_intr(void *); 176 void cs4280_reset(void *); 177 int cs4280_download_image(struct cs4280_softc *); 178 179 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 180 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t, 181 struct cs4280_dma *); 182 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *); 183 184 #ifdef CS4280_DEBUG 185 int cs4280_check_images(struct cs4280_softc *); 186 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 187 u_int32_t); 188 #endif 189 190 struct cfdriver clcs_cd = { 191 NULL, "clcs", DV_DULL 192 }; 193 194 struct cfattach clcs_ca = { 195 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 196 }; 197 198 int cs4280_init(struct cs4280_softc *, int); 199 int cs4280_open(void *, int); 200 void cs4280_close(void *); 201 202 int cs4280_query_encoding(void *, struct audio_encoding *); 203 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 204 int cs4280_round_blocksize(void *, int); 205 206 int cs4280_halt_output(void *); 207 int cs4280_halt_input(void *); 208 209 int cs4280_getdev(void *, struct audio_device *); 210 211 int cs4280_mixer_set_port(void *, mixer_ctrl_t *); 212 int cs4280_mixer_get_port(void *, mixer_ctrl_t *); 213 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip); 214 void *cs4280_malloc(void *, int, size_t, int, int); 215 void cs4280_free(void *, void *, int); 216 size_t cs4280_round_buffersize(void *, int, size_t); 217 paddr_t cs4280_mappage(void *, void *, off_t, int); 218 int cs4280_get_props(void *); 219 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 220 void *, struct audio_params *); 221 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *); 223 224 225 void cs4280_set_dac_rate(struct cs4280_softc *, int ); 226 void cs4280_set_adc_rate(struct cs4280_softc *, int ); 227 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *, 228 char *); 229 int cs4280_src_wait(struct cs4280_softc *); 230 int cs4280_attach_codec(void *sc, struct ac97_codec_if *); 231 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d); 232 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d); 233 void cs4280_reset_codec(void *sc); 234 235 void cs4280_power(int, void *); 236 237 void cs4280_clear_fifos(struct cs4280_softc *); 238 239 #if NMIDI > 0 240 void cs4280_midi_close(void *); 241 void cs4280_midi_getinfo(void *, struct midi_info *); 242 int cs4280_midi_open(void *, int, void (*)(void *, int), 243 void (*)(void *), void *); 244 int cs4280_midi_output(void *, int); 245 #endif 246 247 struct audio_hw_if cs4280_hw_if = { 248 cs4280_open, 249 cs4280_close, 250 NULL, 251 cs4280_query_encoding, 252 cs4280_set_params, 253 cs4280_round_blocksize, 254 NULL, 255 NULL, 256 NULL, 257 NULL, 258 NULL, 259 cs4280_halt_output, 260 cs4280_halt_input, 261 NULL, 262 cs4280_getdev, 263 NULL, 264 cs4280_mixer_set_port, 265 cs4280_mixer_get_port, 266 cs4280_query_devinfo, 267 cs4280_malloc, 268 cs4280_free, 269 cs4280_round_buffersize, 270 0, /* cs4280_mappage, */ 271 cs4280_get_props, 272 cs4280_trigger_output, 273 cs4280_trigger_input, 274 }; 275 276 #if NMIDI > 0 277 struct midi_hw_if cs4280_midi_hw_if = { 278 cs4280_midi_open, 279 cs4280_midi_close, 280 cs4280_midi_output, 281 cs4280_midi_getinfo, 282 0, 283 }; 284 #endif 285 286 287 288 struct audio_device cs4280_device = { 289 "CS4280", 290 "", 291 "cs4280" 292 }; 293 294 const struct pci_matchid cs4280_devices[] = { 295 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, 296 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, 297 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4614 }, 298 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 }, 299 }; 300 301 int 302 cs4280_match(parent, ma, aux) 303 struct device *parent; 304 void *ma; 305 void *aux; 306 { 307 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, 308 sizeof(cs4280_devices)/sizeof(cs4280_devices[0]))); 309 } 310 311 int 312 cs4280_read_codec(sc_, add, data) 313 void *sc_; 314 u_int8_t add; 315 u_int16_t *data; 316 { 317 struct cs4280_softc *sc = sc_; 318 int n; 319 320 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 321 /* 322 * Make sure that there is not data sitting around from a preivous 323 * uncompleted access. 324 */ 325 BA0READ4(sc, CS4280_ACSDA); 326 327 /* Set up AC97 control registers. */ 328 BA0WRITE4(sc, CS4280_ACCAD, add); 329 BA0WRITE4(sc, CS4280_ACCDA, 0); 330 BA0WRITE4(sc, CS4280_ACCTL, 331 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 332 333 if (cs4280_src_wait(sc) < 0) { 334 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 335 sc->sc_dev.dv_xname, add); 336 return (1); 337 } 338 339 /* wait for valid status bit is active */ 340 n = 0; 341 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 342 delay(1); 343 while (++n > 1000) { 344 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 345 sc->sc_dev.dv_xname, add); 346 return (1); 347 } 348 } 349 *data = BA0READ4(sc, CS4280_ACSDA); 350 DPRINTFN(5,("data=0x%04x\n", *data)); 351 return (0); 352 } 353 354 int 355 cs4280_write_codec(sc_, add, data) 356 void *sc_; 357 u_int8_t add; 358 u_int16_t data; 359 { 360 struct cs4280_softc *sc = sc_; 361 362 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 363 BA0WRITE4(sc, CS4280_ACCAD, add); 364 BA0WRITE4(sc, CS4280_ACCDA, data); 365 BA0WRITE4(sc, CS4280_ACCTL, 366 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 367 368 if (cs4280_src_wait(sc) < 0) { 369 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 370 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 371 return (1); 372 } 373 return (0); 374 } 375 376 int 377 cs4280_src_wait(sc) 378 struct cs4280_softc *sc; 379 { 380 int n; 381 n = 0; 382 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 383 delay(1000); 384 while (++n > 1000) 385 return (-1); 386 } 387 return (0); 388 } 389 390 391 void 392 cs4280_set_adc_rate(sc, rate) 393 struct cs4280_softc *sc; 394 int rate; 395 { 396 /* calculate capture rate: 397 * 398 * capture_coefficient_increment = -round(rate*128*65536/48000; 399 * capture_phase_increment = floor(48000*65536*1024/rate); 400 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 401 * cy = floor(cx/200); 402 * capture_sample_rate_correction = cx - 200*cy; 403 * capture_delay = ceil(24*48000/rate); 404 * capture_num_triplets = floor(65536*rate/24000); 405 * capture_group_length = 24000/GCD(rate, 24000); 406 * where GCD means "Greatest Common Divisor". 407 * 408 * capture_coefficient_increment, capture_phase_increment and 409 * capture_num_triplets are 32-bit signed quantities. 410 * capture_sample_rate_correction and capture_group_length are 411 * 16-bit signed quantities. 412 * capture_delay is a 14-bit unsigned quantity. 413 */ 414 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 415 u_int16_t csrc, cgl, cdlay; 416 417 /* XXX 418 * Even though, embedded_audio_spec says capture rate range 11025 to 419 * 48000, dhwiface.cpp says, 420 * 421 * "We can only decimate by up to a factor of 1/9th the hardware rate. 422 * Return an error if an attempt is made to stray outside that limit." 423 * 424 * so assume range as 48000/9 to 48000 425 */ 426 427 if (rate < 8000) 428 rate = 8000; 429 if (rate > 48000) 430 rate = 48000; 431 432 cx = rate << 16; 433 cci = cx / 48000; 434 cx -= cci * 48000; 435 cx <<= 7; 436 cci <<= 7; 437 cci += cx / 48000; 438 cci = - cci; 439 440 cx = 48000 << 16; 441 cpi = cx / rate; 442 cx -= cpi * rate; 443 cx <<= 10; 444 cpi <<= 10; 445 cy = cx / rate; 446 cpi += cy; 447 cx -= cy * rate; 448 449 cy = cx / 200; 450 csrc = cx - 200*cy; 451 452 cdlay = ((48000 * 24) + rate - 1) / rate; 453 #if 0 454 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 455 #endif 456 457 cnt = rate << 16; 458 cnt /= 24000; 459 460 cgl = 1; 461 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 462 if (((rate / tmp1) * tmp1) != rate) 463 cgl *= 2; 464 } 465 if (((rate / 3) * 3) != rate) 466 cgl *= 3; 467 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 468 if (((rate / tmp1) * tmp1) != rate) 469 cgl *= 5; 470 } 471 #if 0 472 /* XXX what manual says */ 473 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 474 tmp1 |= csrc<<16; 475 BA1WRITE4(sc, CS4280_CSRC, tmp1); 476 #else 477 /* suggested by cs461x.c (ALSA driver) */ 478 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 479 #endif 480 481 #if 0 482 /* I am confused. The sample rate calculation section says 483 * cci *is* 32-bit signed quantity but in the parameter description 484 * section, CCI only assigned 16bit. 485 * I believe size of the variable. 486 */ 487 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 488 tmp1 |= cci<<16; 489 BA1WRITE4(sc, CS4280_CCI, tmp1); 490 #else 491 BA1WRITE4(sc, CS4280_CCI, cci); 492 #endif 493 494 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 495 tmp1 |= cdlay <<18; 496 BA1WRITE4(sc, CS4280_CD, tmp1); 497 498 BA1WRITE4(sc, CS4280_CPI, cpi); 499 500 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 501 tmp1 |= cgl; 502 BA1WRITE4(sc, CS4280_CGL, tmp1); 503 504 BA1WRITE4(sc, CS4280_CNT, cnt); 505 506 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 507 tmp1 |= cgl; 508 BA1WRITE4(sc, CS4280_CGC, tmp1); 509 } 510 511 void 512 cs4280_set_dac_rate(sc, rate) 513 struct cs4280_softc *sc; 514 int rate; 515 { 516 /* 517 * playback rate may range from 8000Hz to 48000Hz 518 * 519 * play_phase_increment = floor(rate*65536*1024/48000) 520 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 521 * py=floor(px/200) 522 * play_sample_rate_correction = px - 200*py 523 * 524 * play_phase_increment is a 32bit signed quantity. 525 * play_sample_rate_correction is a 16bit signed quantity. 526 */ 527 int32_t ppi; 528 int16_t psrc; 529 u_int32_t px, py; 530 531 if (rate < 8000) 532 rate = 8000; 533 if (rate > 48000) 534 rate = 48000; 535 px = rate << 16; 536 ppi = px/48000; 537 px -= ppi*48000; 538 ppi <<= 10; 539 px <<= 10; 540 py = px / 48000; 541 ppi += py; 542 px -= py*48000; 543 py = px/200; 544 px -= py*200; 545 psrc = px; 546 #if 0 547 /* what manual says */ 548 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 549 BA1WRITE4(sc, CS4280_PSRC, 550 ( ((psrc<<16) & PSRC_MASK) | px )); 551 #else 552 /* suggested by cs461x.c (ALSA driver) */ 553 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 554 #endif 555 BA1WRITE4(sc, CS4280_PPI, ppi); 556 } 557 558 void 559 cs4280_attach(parent, self, aux) 560 struct device *parent; 561 struct device *self; 562 void *aux; 563 { 564 struct cs4280_softc *sc = (struct cs4280_softc *) self; 565 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 566 pci_chipset_tag_t pc = pa->pa_pc; 567 char const *intrstr; 568 pci_intr_handle_t ih; 569 mixer_ctrl_t ctl; 570 u_int32_t mem; 571 572 /* Map I/O register */ 573 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 574 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 575 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 576 printf(": can't map BA0 space\n"); 577 return; 578 } 579 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 580 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 581 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 582 printf(": can't map BA1 space\n"); 583 return; 584 } 585 586 sc->sc_dmatag = pa->pa_dmat; 587 588 /* Enable the device (set bus master flag) */ 589 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 590 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 591 PCI_COMMAND_MASTER_ENABLE); 592 593 /* LATENCY_TIMER setting */ 594 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 595 if ( PCI_LATTIMER(mem) < 32 ) { 596 mem &= 0xffff00ff; 597 mem |= 0x00002000; 598 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 599 } 600 601 /* Map and establish the interrupt. */ 602 if (pci_intr_map(pa, &ih)) { 603 printf(": couldn't map interrupt\n"); 604 return; 605 } 606 intrstr = pci_intr_string(pc, ih); 607 608 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc, 609 sc->sc_dev.dv_xname); 610 if (sc->sc_ih == NULL) { 611 printf(": couldn't establish interrupt"); 612 if (intrstr != NULL) 613 printf(" at %s", intrstr); 614 printf("\n"); 615 return; 616 } 617 printf(": %s\n", intrstr); 618 619 /* Initialization */ 620 if(cs4280_init(sc, 1) != 0) 621 return; 622 623 /* AC 97 attachement */ 624 sc->host_if.arg = sc; 625 sc->host_if.attach = cs4280_attach_codec; 626 sc->host_if.read = cs4280_read_codec; 627 sc->host_if.write = cs4280_write_codec; 628 sc->host_if.reset = cs4280_reset_codec; 629 630 if (ac97_attach(&sc->host_if) != 0) { 631 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 632 return; 633 } 634 635 /* Turn mute off of DAC, CD and master volumes by default */ 636 ctl.type = AUDIO_MIXER_ENUM; 637 ctl.un.ord = 0; /* off */ 638 639 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 640 AudioNmaster, AudioNmute); 641 cs4280_mixer_set_port(sc, &ctl); 642 643 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 644 AudioNdac, AudioNmute); 645 cs4280_mixer_set_port(sc, &ctl); 646 647 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 648 AudioNcd, AudioNmute); 649 cs4280_mixer_set_port(sc, &ctl); 650 651 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 652 653 #if NMIDI > 0 654 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 655 #endif 656 sc->sc_suspend = PWR_RESUME; 657 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 658 } 659 660 int 661 cs4280_intr(p) 662 void *p; 663 { 664 /* 665 * XXX 666 * 667 * Since CS4280 has only 4kB dma buffer and 668 * interrupt occurs every 2kB block, I create dummy buffer 669 * which returns to audio driver and actual dma buffer 670 * using in DMA transfer. 671 * 672 * 673 * ring buffer in audio.c is pointed by BUFADDR 674 * <------ ring buffer size == 64kB ------> 675 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 676 * |= = = =|= = = =|= = = =|= = = =|= = = =| 677 * | | | | | | <- call audio_intp every 678 * sc->sc_[pr]_count time. 679 * 680 * actual dma buffer is pointed by KERNADDR 681 * <-> dma buffer size = 4kB 682 * |= =| 683 * 684 * 685 */ 686 struct cs4280_softc *sc = p; 687 u_int32_t intr, mem; 688 char * empty_dma; 689 int handled = 0; 690 691 /* grab interrupt register then clear it */ 692 intr = BA0READ4(sc, CS4280_HISR); 693 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 694 695 /* Playback Interrupt */ 696 if (intr & HISR_PINT) { 697 handled = 1; 698 mem = BA1READ4(sc, CS4280_PFIE); 699 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 700 if (sc->sc_pintr) { 701 if ((sc->sc_pi%sc->sc_pcount) == 0) 702 sc->sc_pintr(sc->sc_parg); 703 } else { 704 printf("unexpected play intr\n"); 705 } 706 /* copy buffer */ 707 ++sc->sc_pi; 708 empty_dma = sc->sc_pdma->addr; 709 if (sc->sc_pi&1) 710 empty_dma += CS4280_ICHUNK; 711 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 712 sc->sc_pn += CS4280_ICHUNK; 713 if (sc->sc_pn >= sc->sc_pe) 714 sc->sc_pn = sc->sc_ps; 715 BA1WRITE4(sc, CS4280_PFIE, mem); 716 } 717 /* Capture Interrupt */ 718 if (intr & HISR_CINT) { 719 int i; 720 int16_t rdata; 721 722 handled = 1; 723 mem = BA1READ4(sc, CS4280_CIE); 724 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 725 ++sc->sc_ri; 726 empty_dma = sc->sc_rdma->addr; 727 if ((sc->sc_ri&1) == 0) 728 empty_dma += CS4280_ICHUNK; 729 730 /* 731 * XXX 732 * I think this audio data conversion should be 733 * happend in upper layer, but I put this here 734 * since there is no conversion function available. 735 */ 736 switch(sc->sc_rparam) { 737 case CF_16BIT_STEREO: 738 /* just copy it */ 739 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 740 sc->sc_rn += CS4280_ICHUNK; 741 break; 742 case CF_16BIT_MONO: 743 for (i = 0; i < 512; i++) { 744 rdata = *((int16_t *)empty_dma)++>>1; 745 rdata += *((int16_t *)empty_dma)++>>1; 746 *((int16_t *)sc->sc_rn)++ = rdata; 747 } 748 break; 749 case CF_8BIT_STEREO: 750 for (i = 0; i < 512; i++) { 751 rdata = *((int16_t*)empty_dma)++; 752 *sc->sc_rn++ = rdata >> 8; 753 rdata = *((int16_t*)empty_dma)++; 754 *sc->sc_rn++ = rdata >> 8; 755 } 756 break; 757 case CF_8BIT_MONO: 758 for (i = 0; i < 512; i++) { 759 rdata = *((int16_t*)empty_dma)++ >>1; 760 rdata += *((int16_t*)empty_dma)++ >>1; 761 *sc->sc_rn++ = rdata >>8; 762 } 763 break; 764 default: 765 /* Should not reach here */ 766 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 767 } 768 if (sc->sc_rn >= sc->sc_re) 769 sc->sc_rn = sc->sc_rs; 770 BA1WRITE4(sc, CS4280_CIE, mem); 771 if (sc->sc_rintr) { 772 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 773 sc->sc_rintr(sc->sc_rarg); 774 } else { 775 printf("unexpected record intr\n"); 776 } 777 } 778 779 #if NMIDI > 0 780 /* Midi port Interrupt */ 781 if (intr & HISR_MIDI) { 782 int data; 783 784 handled = 1; 785 DPRINTF(("i: %d: ", 786 BA0READ4(sc, CS4280_MIDSR))); 787 /* Read the received data */ 788 while ((sc->sc_iintr != NULL) && 789 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 790 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 791 DPRINTF(("r:%x\n",data)); 792 sc->sc_iintr(sc->sc_arg, data); 793 } 794 795 /* Write the data */ 796 #if 1 797 /* XXX: 798 * It seems "Transmit Buffer Full" never activate until EOI 799 * is deliverd. Shall I throw EOI top of this routine ? 800 */ 801 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 802 DPRINTF(("w: ")); 803 if (sc->sc_ointr != NULL) 804 sc->sc_ointr(sc->sc_arg); 805 } 806 #else 807 while ((sc->sc_ointr != NULL) && 808 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 809 DPRINTF(("w: ")); 810 sc->sc_ointr(sc->sc_arg); 811 } 812 #endif 813 DPRINTF(("\n")); 814 } 815 #endif 816 817 return handled; 818 } 819 820 821 /* Download Proceessor Code and Data image */ 822 823 int 824 cs4280_download(sc, src, offset, len) 825 struct cs4280_softc *sc; 826 const u_int32_t *src; 827 u_int32_t offset, len; 828 { 829 u_int32_t ctr; 830 831 #ifdef CS4280_DEBUG 832 u_int32_t con, data; 833 u_int8_t c0,c1,c2,c3; 834 #endif 835 if ((offset&3) || (len&3)) 836 return (-1); 837 838 len /= sizeof(u_int32_t); 839 for (ctr = 0; ctr < len; ctr++) { 840 /* XXX: 841 * I cannot confirm this is the right thing or not 842 * on BIG-ENDIAN machines. 843 */ 844 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 845 #ifdef CS4280_DEBUG 846 data = htole32(*(src+ctr)); 847 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 848 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 849 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 850 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 851 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 852 if (data != con ) { 853 printf("0x%06x: write=0x%08x read=0x%08x\n", 854 offset+ctr*4, data, con); 855 return (-1); 856 } 857 #endif 858 } 859 return (0); 860 } 861 862 int 863 cs4280_download_image(sc) 864 struct cs4280_softc *sc; 865 { 866 int idx, err; 867 u_int32_t offset = 0; 868 869 err = 0; 870 871 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 872 err = cs4280_download(sc, &BA1Struct.map[offset], 873 BA1Struct.memory[idx].offset, 874 BA1Struct.memory[idx].size); 875 if (err != 0) { 876 printf("%s: load_image failed at %d\n", 877 sc->sc_dev.dv_xname, idx); 878 return (-1); 879 } 880 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 881 } 882 return (err); 883 } 884 885 #ifdef CS4280_DEBUG 886 int 887 cs4280_checkimage(sc, src, offset, len) 888 struct cs4280_softc *sc; 889 u_int32_t *src; 890 u_int32_t offset, len; 891 { 892 u_int32_t ctr, data; 893 int err = 0; 894 895 if ((offset&3) || (len&3)) 896 return -1; 897 898 len /= sizeof(u_int32_t); 899 for (ctr = 0; ctr < len; ctr++) { 900 /* I cannot confirm this is the right thing 901 * on BIG-ENDIAN machines 902 */ 903 data = BA1READ4(sc, offset+ctr*4); 904 if (data != htole32(*(src+ctr))) { 905 printf("0x%06x: 0x%08x(0x%08x)\n", 906 offset+ctr*4, data, *(src+ctr)); 907 *(src+ctr) = data; 908 ++err; 909 } 910 } 911 return (err); 912 } 913 914 int 915 cs4280_check_images(sc) 916 struct cs4280_softc *sc; 917 { 918 int idx, err; 919 u_int32_t offset = 0; 920 921 err = 0; 922 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 923 for (idx = 0; idx < 1; ++idx) { 924 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 925 BA1Struct.memory[idx].offset, 926 BA1Struct.memory[idx].size); 927 if (err != 0) { 928 printf("%s: check_image failed at %d\n", 929 sc->sc_dev.dv_xname, idx); 930 } 931 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 932 } 933 return (err); 934 } 935 936 #endif 937 938 int 939 cs4280_attach_codec(sc_, codec_if) 940 void *sc_; 941 struct ac97_codec_if *codec_if; 942 { 943 struct cs4280_softc *sc = sc_; 944 945 sc->codec_if = codec_if; 946 return (0); 947 } 948 949 void 950 cs4280_reset_codec(sc_) 951 void *sc_; 952 { 953 struct cs4280_softc *sc = sc_; 954 int n; 955 956 /* Reset codec */ 957 BA0WRITE4(sc, CS4280_ACCTL, 0); 958 delay(100); /* delay 100us */ 959 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 960 961 /* 962 * It looks like we do the following procedure, too 963 */ 964 965 /* Enable AC-link sync generation */ 966 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 967 delay(50*1000); /* XXX delay 50ms */ 968 969 /* Assert valid frame signal */ 970 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 971 972 /* Wait for valid AC97 input slot */ 973 n = 0; 974 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 975 delay(1000); 976 if (++n > 1000) { 977 printf("reset_codec: AC97 inputs slot ready timeout\n"); 978 return; 979 } 980 } 981 } 982 983 984 /* Processor Soft Reset */ 985 void 986 cs4280_reset(sc_) 987 void *sc_; 988 { 989 struct cs4280_softc *sc = sc_; 990 991 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 992 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 993 delay(100); 994 /* Clear RSTSP bit in SPCR */ 995 BA1WRITE4(sc, CS4280_SPCR, 0); 996 /* enable DMA reqest */ 997 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 998 } 999 1000 int 1001 cs4280_open(addr, flags) 1002 void *addr; 1003 int flags; 1004 { 1005 return (0); 1006 } 1007 1008 void 1009 cs4280_close(addr) 1010 void *addr; 1011 { 1012 struct cs4280_softc *sc = addr; 1013 1014 cs4280_halt_output(sc); 1015 cs4280_halt_input(sc); 1016 1017 sc->sc_pintr = 0; 1018 sc->sc_rintr = 0; 1019 } 1020 1021 int 1022 cs4280_query_encoding(addr, fp) 1023 void *addr; 1024 struct audio_encoding *fp; 1025 { 1026 switch (fp->index) { 1027 case 0: 1028 strlcpy(fp->name, AudioEulinear, sizeof fp->name); 1029 fp->encoding = AUDIO_ENCODING_ULINEAR; 1030 fp->precision = 8; 1031 fp->flags = 0; 1032 break; 1033 case 1: 1034 strlcpy(fp->name, AudioEmulaw, sizeof fp->name); 1035 fp->encoding = AUDIO_ENCODING_ULAW; 1036 fp->precision = 8; 1037 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1038 break; 1039 case 2: 1040 strlcpy(fp->name, AudioEalaw, sizeof fp->name); 1041 fp->encoding = AUDIO_ENCODING_ALAW; 1042 fp->precision = 8; 1043 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1044 break; 1045 case 3: 1046 strlcpy(fp->name, AudioEslinear, sizeof fp->name); 1047 fp->encoding = AUDIO_ENCODING_SLINEAR; 1048 fp->precision = 8; 1049 fp->flags = 0; 1050 break; 1051 case 4: 1052 strlcpy(fp->name, AudioEslinear_le, sizeof fp->name); 1053 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1054 fp->precision = 16; 1055 fp->flags = 0; 1056 break; 1057 case 5: 1058 strlcpy(fp->name, AudioEulinear_le, sizeof fp->name); 1059 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1060 fp->precision = 16; 1061 fp->flags = 0; 1062 break; 1063 case 6: 1064 strlcpy(fp->name, AudioEslinear_be, sizeof fp->name); 1065 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1066 fp->precision = 16; 1067 fp->flags = 0; 1068 break; 1069 case 7: 1070 strlcpy(fp->name, AudioEulinear_be, sizeof fp->name); 1071 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1072 fp->precision = 16; 1073 fp->flags = 0; 1074 break; 1075 default: 1076 return (EINVAL); 1077 } 1078 return (0); 1079 } 1080 1081 int 1082 cs4280_set_params(addr, setmode, usemode, play, rec) 1083 void *addr; 1084 int setmode, usemode; 1085 struct audio_params *play, *rec; 1086 { 1087 struct cs4280_softc *sc = addr; 1088 struct audio_params *p; 1089 int mode; 1090 1091 for (mode = AUMODE_RECORD; mode != -1; 1092 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1093 if ((setmode & mode) == 0) 1094 continue; 1095 1096 p = mode == AUMODE_PLAY ? play : rec; 1097 1098 if (p == play) { 1099 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1100 p->sample_rate, p->precision, p->channels)); 1101 /* play back data format may be 8- or 16-bit and 1102 * either stereo or mono. 1103 * playback rate may range from 8000Hz to 48000Hz 1104 */ 1105 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1106 (p->precision != 8 && p->precision != 16) || 1107 (p->channels != 1 && p->channels != 2) ) { 1108 return (EINVAL); 1109 } 1110 } else { 1111 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1112 p->sample_rate, p->precision, p->channels)); 1113 /* capture data format must be 16bit stereo 1114 * and sample rate range from 11025Hz to 48000Hz. 1115 * 1116 * XXX: it looks like to work with 8000Hz, 1117 * although data sheets say lower limit is 1118 * 11025 Hz. 1119 */ 1120 1121 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1122 (p->precision != 8 && p->precision != 16) || 1123 (p->channels != 1 && p->channels != 2) ) { 1124 return (EINVAL); 1125 } 1126 } 1127 p->factor = 1; 1128 p->sw_code = 0; 1129 1130 /* capturing data is slinear */ 1131 switch (p->encoding) { 1132 case AUDIO_ENCODING_SLINEAR_BE: 1133 if (mode == AUMODE_RECORD) { 1134 if (p->precision == 16) 1135 p->sw_code = swap_bytes; 1136 } 1137 break; 1138 case AUDIO_ENCODING_SLINEAR_LE: 1139 break; 1140 case AUDIO_ENCODING_ULINEAR_BE: 1141 if (mode == AUMODE_RECORD) { 1142 if (p->precision == 16) 1143 p->sw_code = change_sign16_swap_bytes; 1144 else 1145 p->sw_code = change_sign8; 1146 } 1147 break; 1148 case AUDIO_ENCODING_ULINEAR_LE: 1149 if (mode == AUMODE_RECORD) { 1150 if (p->precision == 16) 1151 p->sw_code = change_sign16; 1152 else 1153 p->sw_code = change_sign8; 1154 } 1155 break; 1156 case AUDIO_ENCODING_ULAW: 1157 if (mode == AUMODE_PLAY) { 1158 p->factor = 2; 1159 p->sw_code = mulaw_to_slinear16; 1160 } else { 1161 p->sw_code = slinear8_to_mulaw; 1162 } 1163 break; 1164 case AUDIO_ENCODING_ALAW: 1165 if (mode == AUMODE_PLAY) { 1166 p->factor = 2; 1167 p->sw_code = alaw_to_slinear16; 1168 } else { 1169 p->sw_code = slinear8_to_alaw; 1170 } 1171 break; 1172 default: 1173 return (EINVAL); 1174 } 1175 } 1176 1177 /* set sample rate */ 1178 cs4280_set_dac_rate(sc, play->sample_rate); 1179 cs4280_set_adc_rate(sc, rec->sample_rate); 1180 return (0); 1181 } 1182 1183 int 1184 cs4280_round_blocksize(hdl, blk) 1185 void *hdl; 1186 int blk; 1187 { 1188 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1189 } 1190 1191 size_t 1192 cs4280_round_buffersize(addr, direction, size) 1193 void *addr; 1194 int direction; 1195 size_t size; 1196 { 1197 /* although real dma buffer size is 4KB, 1198 * let the audio.c driver use a larger buffer. 1199 * ( suggested by Lennart Augustsson. ) 1200 */ 1201 return (size); 1202 } 1203 1204 int 1205 cs4280_get_props(hdl) 1206 void *hdl; 1207 { 1208 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1209 #ifdef notyet 1210 /* XXX 1211 * How can I mmap ? 1212 */ 1213 AUDIO_PROP_MMAP 1214 #endif 1215 1216 } 1217 1218 int 1219 cs4280_mixer_get_port(addr, cp) 1220 void *addr; 1221 mixer_ctrl_t *cp; 1222 { 1223 struct cs4280_softc *sc = addr; 1224 1225 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1226 } 1227 1228 paddr_t 1229 cs4280_mappage(addr, mem, off, prot) 1230 void *addr; 1231 void *mem; 1232 off_t off; 1233 int prot; 1234 { 1235 struct cs4280_softc *sc = addr; 1236 struct cs4280_dma *p; 1237 1238 if (off < 0) 1239 return (-1); 1240 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1241 ; 1242 if (!p) { 1243 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1244 return (-1); 1245 } 1246 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1247 off, prot, BUS_DMA_WAITOK)); 1248 } 1249 1250 1251 int 1252 cs4280_query_devinfo(addr, dip) 1253 void *addr; 1254 mixer_devinfo_t *dip; 1255 { 1256 struct cs4280_softc *sc = addr; 1257 1258 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1259 } 1260 1261 int 1262 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1263 struct cs4280_softc *sc; 1264 char *class, *device, *qualifier; 1265 { 1266 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1267 device, qualifier)); 1268 } 1269 1270 int 1271 cs4280_halt_output(addr) 1272 void *addr; 1273 { 1274 struct cs4280_softc *sc = addr; 1275 u_int32_t mem; 1276 1277 mem = BA1READ4(sc, CS4280_PCTL); 1278 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1279 #ifdef DIAGNOSTIC 1280 sc->sc_prun = 0; 1281 #endif 1282 return (0); 1283 } 1284 1285 int 1286 cs4280_halt_input(addr) 1287 void *addr; 1288 { 1289 struct cs4280_softc *sc = addr; 1290 u_int32_t mem; 1291 1292 mem = BA1READ4(sc, CS4280_CCTL); 1293 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1294 #ifdef DIAGNOSTIC 1295 sc->sc_rrun = 0; 1296 #endif 1297 return (0); 1298 } 1299 1300 int 1301 cs4280_getdev(addr, retp) 1302 void *addr; 1303 struct audio_device *retp; 1304 { 1305 *retp = cs4280_device; 1306 return (0); 1307 } 1308 1309 int 1310 cs4280_mixer_set_port(addr, cp) 1311 void *addr; 1312 mixer_ctrl_t *cp; 1313 { 1314 struct cs4280_softc *sc = addr; 1315 int val; 1316 1317 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1318 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1319 return (val); 1320 } 1321 1322 1323 int 1324 cs4280_freemem(sc, p) 1325 struct cs4280_softc *sc; 1326 struct cs4280_dma *p; 1327 { 1328 bus_dmamap_unload(sc->sc_dmatag, p->map); 1329 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1330 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1331 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1332 return (0); 1333 } 1334 1335 int 1336 cs4280_allocmem(sc, size, align, p) 1337 struct cs4280_softc *sc; 1338 size_t size; 1339 size_t align; 1340 struct cs4280_dma *p; 1341 { 1342 int error; 1343 1344 /* XXX */ 1345 p->size = size; 1346 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1347 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1348 &p->nsegs, BUS_DMA_NOWAIT); 1349 if (error) { 1350 printf("%s: unable to allocate dma, error=%d\n", 1351 sc->sc_dev.dv_xname, error); 1352 return (error); 1353 } 1354 1355 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1356 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1357 if (error) { 1358 printf("%s: unable to map dma, error=%d\n", 1359 sc->sc_dev.dv_xname, error); 1360 goto free; 1361 } 1362 1363 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1364 0, BUS_DMA_NOWAIT, &p->map); 1365 if (error) { 1366 printf("%s: unable to create dma map, error=%d\n", 1367 sc->sc_dev.dv_xname, error); 1368 goto unmap; 1369 } 1370 1371 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1372 BUS_DMA_NOWAIT); 1373 if (error) { 1374 printf("%s: unable to load dma map, error=%d\n", 1375 sc->sc_dev.dv_xname, error); 1376 goto destroy; 1377 } 1378 return (0); 1379 1380 destroy: 1381 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1382 unmap: 1383 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1384 free: 1385 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1386 return (error); 1387 } 1388 1389 1390 void * 1391 cs4280_malloc(addr, direction, size, pool, flags) 1392 void *addr; 1393 int direction; 1394 size_t size; 1395 int pool, flags; 1396 { 1397 struct cs4280_softc *sc = addr; 1398 struct cs4280_dma *p; 1399 caddr_t q; 1400 int error; 1401 1402 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1403 q = malloc(size, pool, flags); 1404 if (!q) 1405 return (0); 1406 p = malloc(sizeof(*p), pool, flags); 1407 if (!p) { 1408 free(q,pool); 1409 return (0); 1410 } 1411 /* 1412 * cs4280 has fixed 4kB buffer 1413 */ 1414 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1415 1416 if (error) { 1417 free(q, pool); 1418 free(p, pool); 1419 return (0); 1420 } 1421 1422 p->next = sc->sc_dmas; 1423 sc->sc_dmas = p; 1424 p->dum = q; /* return to audio driver */ 1425 1426 return (p->dum); 1427 } 1428 1429 void 1430 cs4280_free(addr, ptr, pool) 1431 void *addr; 1432 void *ptr; 1433 int pool; 1434 { 1435 struct cs4280_softc *sc = addr; 1436 struct cs4280_dma **pp, *p; 1437 1438 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1439 if (BUFADDR(p) == ptr) { 1440 cs4280_freemem(sc, p); 1441 *pp = p->next; 1442 free(p->dum, pool); 1443 free(p, pool); 1444 return; 1445 } 1446 } 1447 } 1448 1449 int 1450 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1451 void *addr; 1452 void *start, *end; 1453 int blksize; 1454 void (*intr)(void *); 1455 void *arg; 1456 struct audio_params *param; 1457 { 1458 struct cs4280_softc *sc = addr; 1459 u_int32_t pfie, pctl, mem, pdtc; 1460 struct cs4280_dma *p; 1461 1462 #ifdef DIAGNOSTIC 1463 if (sc->sc_prun) 1464 printf("cs4280_trigger_output: already running\n"); 1465 sc->sc_prun = 1; 1466 #endif 1467 1468 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1469 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1470 sc->sc_pintr = intr; 1471 sc->sc_parg = arg; 1472 1473 /* stop playback DMA */ 1474 mem = BA1READ4(sc, CS4280_PCTL); 1475 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1476 1477 /* setup PDTC */ 1478 pdtc = BA1READ4(sc, CS4280_PDTC); 1479 pdtc &= ~PDTC_MASK; 1480 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1481 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1482 1483 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1484 param->precision, param->factor, param->channels, 1485 param->encoding)); 1486 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1487 ; 1488 if (p == NULL) { 1489 printf("cs4280_trigger_output: bad addr %p\n", start); 1490 return (EINVAL); 1491 } 1492 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1493 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1494 "4kB align\n", DMAADDR(p)); 1495 return (EINVAL); 1496 } 1497 1498 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1499 sc->sc_ps = (char *)start; 1500 sc->sc_pe = (char *)end; 1501 sc->sc_pdma = p; 1502 sc->sc_pbuf = KERNADDR(p); 1503 sc->sc_pi = 0; 1504 sc->sc_pn = sc->sc_ps; 1505 if (blksize >= CS4280_DCHUNK) { 1506 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1507 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1508 ++sc->sc_pi; 1509 } else { 1510 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1511 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1512 } 1513 1514 /* initiate playback dma */ 1515 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1516 1517 /* set PFIE */ 1518 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1519 1520 if (param->precision * param->factor == 8) 1521 pfie |= PFIE_8BIT; 1522 if (param->channels == 1) 1523 pfie |= PFIE_MONO; 1524 1525 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1526 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1527 pfie |= PFIE_SWAPPED; 1528 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1529 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1530 pfie |= PFIE_UNSIGNED; 1531 1532 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1533 1534 cs4280_set_dac_rate(sc, param->sample_rate); 1535 1536 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1537 pctl |= sc->pctl; 1538 BA1WRITE4(sc, CS4280_PCTL, pctl); 1539 return (0); 1540 } 1541 1542 int 1543 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1544 void *addr; 1545 void *start, *end; 1546 int blksize; 1547 void (*intr)(void *); 1548 void *arg; 1549 struct audio_params *param; 1550 { 1551 struct cs4280_softc *sc = addr; 1552 u_int32_t cctl, cie; 1553 struct cs4280_dma *p; 1554 1555 #ifdef DIAGNOSTIC 1556 if (sc->sc_rrun) 1557 printf("cs4280_trigger_input: already running\n"); 1558 sc->sc_rrun = 1; 1559 #endif 1560 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1561 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1562 sc->sc_rintr = intr; 1563 sc->sc_rarg = arg; 1564 1565 sc->sc_ri = 0; 1566 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1567 sc->sc_rs = (char *)start; 1568 sc->sc_re = (char *)end; 1569 sc->sc_rn = sc->sc_rs; 1570 1571 /* setup format information for internal converter */ 1572 sc->sc_rparam = 0; 1573 if (param->precision == 8) { 1574 sc->sc_rparam += CF_8BIT; 1575 sc->sc_rcount <<= 1; 1576 } 1577 if (param->channels == 1) { 1578 sc->sc_rparam += CF_MONO; 1579 sc->sc_rcount <<= 1; 1580 } 1581 1582 /* stop capture DMA */ 1583 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1584 BA1WRITE4(sc, CS4280_CCTL, cctl); 1585 1586 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1587 ; 1588 if (!p) { 1589 printf("cs4280_trigger_input: bad addr %p\n", start); 1590 return (EINVAL); 1591 } 1592 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1593 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1594 "4kB align\n", DMAADDR(p)); 1595 return (EINVAL); 1596 } 1597 sc->sc_rdma = p; 1598 sc->sc_rbuf = KERNADDR(p); 1599 1600 /* initiate capture dma */ 1601 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1602 1603 /* set CIE */ 1604 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1605 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1606 1607 cs4280_set_adc_rate(sc, param->sample_rate); 1608 1609 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1610 cctl |= sc->cctl; 1611 BA1WRITE4(sc, CS4280_CCTL, cctl); 1612 return (0); 1613 } 1614 1615 1616 int 1617 cs4280_init(sc, init) 1618 struct cs4280_softc *sc; 1619 int init; 1620 { 1621 int n; 1622 u_int32_t mem; 1623 1624 /* Start PLL out in known state */ 1625 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1626 /* Start serial ports out in known state */ 1627 BA0WRITE4(sc, CS4280_SERMC1, 0); 1628 1629 /* Specify type of CODEC */ 1630 /* XXX should no be here */ 1631 #define SERACC_CODEC_TYPE_1_03 1632 #ifdef SERACC_CODEC_TYPE_1_03 1633 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1634 #else 1635 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1636 #endif 1637 1638 /* Reset codec */ 1639 BA0WRITE4(sc, CS4280_ACCTL, 0); 1640 delay(100); /* delay 100us */ 1641 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1642 1643 /* Enable AC-link sync generation */ 1644 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1645 delay(50*1000); /* delay 50ms */ 1646 1647 /* Set the serial port timing configuration */ 1648 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1649 1650 /* Setup clock control */ 1651 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1652 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1653 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1654 1655 /* Power up the PLL */ 1656 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1657 delay(50*1000); /* delay 50ms */ 1658 1659 /* Turn on clock */ 1660 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1661 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1662 1663 /* Set the serial port FIFO pointer to the 1664 * first sample in FIFO. (not documented) */ 1665 cs4280_clear_fifos(sc); 1666 1667 #if 0 1668 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1669 BA0WRITE4(sc, CS4280_SERBSP, 0); 1670 #endif 1671 1672 /* Configure the serial port */ 1673 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1674 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1675 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1676 1677 /* Wait for CODEC ready */ 1678 n = 0; 1679 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1680 delay(125); 1681 if (++n > 1000) { 1682 printf("%s: codec ready timeout\n", 1683 sc->sc_dev.dv_xname); 1684 return(1); 1685 } 1686 } 1687 1688 /* Assert valid frame signal */ 1689 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1690 1691 /* Wait for valid AC97 input slot */ 1692 n = 0; 1693 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1694 (ACISV_ISV3 | ACISV_ISV4)) { 1695 delay(1000); 1696 if (++n > 1000) { 1697 printf("AC97 inputs slot ready timeout\n"); 1698 return(1); 1699 } 1700 } 1701 1702 /* Set AC97 output slot valid signals */ 1703 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1704 1705 /* reset the processor */ 1706 cs4280_reset(sc); 1707 1708 /* Download the image to the processor */ 1709 if (cs4280_download_image(sc) != 0) { 1710 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1711 return(1); 1712 } 1713 1714 /* Save playback parameter and then write zero. 1715 * this ensures that DMA doesn't immediately occur upon 1716 * starting the processor core 1717 */ 1718 mem = BA1READ4(sc, CS4280_PCTL); 1719 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1720 cs4280_halt_output(sc); 1721 1722 /* Save capture parameter and then write zero. 1723 * this ensures that DMA doesn't immediately occur upon 1724 * starting the processor core 1725 */ 1726 mem = BA1READ4(sc, CS4280_CCTL); 1727 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1728 cs4280_halt_input(sc); 1729 1730 /* MSH: need to power up ADC and DAC? */ 1731 1732 /* Processor Startup Procedure */ 1733 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1734 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1735 1736 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1737 n = 0; 1738 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1739 delay(10); 1740 if (++n > 1000) { 1741 printf("SPCR 1->0 transition timeout\n"); 1742 return(1); 1743 } 1744 } 1745 1746 n = 0; 1747 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1748 delay(10); 1749 if (++n > 1000) { 1750 printf("SPCS 0->1 transition timeout\n"); 1751 return(1); 1752 } 1753 } 1754 /* Processor is now running !!! */ 1755 1756 /* Setup volume */ 1757 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1758 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1759 1760 /* Interrupt enable */ 1761 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1762 1763 /* playback interrupt enable */ 1764 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1765 mem |= PFIE_PI_ENABLE; 1766 BA1WRITE4(sc, CS4280_PFIE, mem); 1767 /* capture interrupt enable */ 1768 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1769 mem |= CIE_CI_ENABLE; 1770 BA1WRITE4(sc, CS4280_CIE, mem); 1771 1772 #if NMIDI > 0 1773 /* Reset midi port */ 1774 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1775 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1776 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1777 /* midi interrupt enable */ 1778 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1779 BA0WRITE4(sc, CS4280_MIDCR, mem); 1780 #endif 1781 return(0); 1782 } 1783 1784 void 1785 cs4280_power(why, v) 1786 int why; 1787 void *v; 1788 { 1789 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1790 int i; 1791 1792 DPRINTF(("%s: cs4280_power why=%d\n", 1793 sc->sc_dev.dv_xname, why)); 1794 if (why != PWR_RESUME) { 1795 sc->sc_suspend = why; 1796 1797 cs4280_halt_output(sc); 1798 cs4280_halt_input(sc); 1799 /* Save AC97 registers */ 1800 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1801 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1802 continue; 1803 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1804 } 1805 /* should I powerdown here ? */ 1806 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1807 } else { 1808 if (sc->sc_suspend == PWR_RESUME) { 1809 printf("cs4280_power: odd, resume without suspend.\n"); 1810 sc->sc_suspend = why; 1811 return; 1812 } 1813 sc->sc_suspend = why; 1814 cs4280_init(sc, 0); 1815 cs4280_reset_codec(sc); 1816 1817 /* restore ac97 registers */ 1818 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1819 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1820 continue; 1821 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1822 } 1823 } 1824 } 1825 1826 void 1827 cs4280_clear_fifos(sc) 1828 struct cs4280_softc *sc; 1829 { 1830 int pd = 0, cnt, n; 1831 u_int32_t mem; 1832 1833 /* 1834 * If device power down, power up the device and keep power down 1835 * state. 1836 */ 1837 mem = BA0READ4(sc, CS4280_CLKCR1); 1838 if (!(mem & CLKCR1_SWCE)) { 1839 printf("cs4280_clear_fifo: power down found.\n"); 1840 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1841 pd = 1; 1842 } 1843 BA0WRITE4(sc, CS4280_SERBWP, 0); 1844 for (cnt = 0; cnt < 256; cnt++) { 1845 n = 0; 1846 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1847 delay(1000); 1848 if (++n > 1000) { 1849 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1850 break; 1851 } 1852 } 1853 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1854 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1855 } 1856 if (pd) 1857 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1858 } 1859 1860 #if NMIDI > 0 1861 int 1862 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1863 void *addr; 1864 int flags; 1865 void (*iintr)(void *, int); 1866 void (*ointr)(void *); 1867 void *arg; 1868 { 1869 struct cs4280_softc *sc = addr; 1870 u_int32_t mem; 1871 1872 DPRINTF(("midi_open\n")); 1873 sc->sc_iintr = iintr; 1874 sc->sc_ointr = ointr; 1875 sc->sc_arg = arg; 1876 1877 /* midi interrupt enable */ 1878 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1879 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1880 BA0WRITE4(sc, CS4280_MIDCR, mem); 1881 #ifdef CS4280_DEBUG 1882 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1883 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1884 return(EINVAL); 1885 } 1886 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1887 #endif 1888 return (0); 1889 } 1890 1891 void 1892 cs4280_midi_close(addr) 1893 void *addr; 1894 { 1895 struct cs4280_softc *sc = addr; 1896 u_int32_t mem; 1897 1898 DPRINTF(("midi_close\n")); 1899 mem = BA0READ4(sc, CS4280_MIDCR); 1900 mem &= ~MIDCR_MASK; 1901 BA0WRITE4(sc, CS4280_MIDCR, mem); 1902 1903 sc->sc_iintr = 0; 1904 sc->sc_ointr = 0; 1905 } 1906 1907 int 1908 cs4280_midi_output(addr, d) 1909 void *addr; 1910 int d; 1911 { 1912 struct cs4280_softc *sc = addr; 1913 u_int32_t mem; 1914 int x; 1915 1916 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1917 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1918 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1919 mem |= d & MIDWP_MASK; 1920 DPRINTFN(5,("midi_output d=0x%08x",d)); 1921 BA0WRITE4(sc, CS4280_MIDWP, mem); 1922 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1923 DPRINTF(("Bad write data: %d %d", 1924 mem, BA0READ4(sc, CS4280_MIDWP))); 1925 return(EIO); 1926 } 1927 return (0); 1928 } 1929 delay(MIDI_BUSY_DELAY); 1930 } 1931 return (EIO); 1932 } 1933 1934 void 1935 cs4280_midi_getinfo(addr, mi) 1936 void *addr; 1937 struct midi_info *mi; 1938 { 1939 mi->name = "CS4280 MIDI UART"; 1940 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1941 } 1942 1943 #endif 1944