1 /* $OpenBSD: cs4280.c,v 1.10 2001/06/18 19:27:17 deraadt Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 #include <sys/types.h> 75 #include <sys/systm.h> 76 77 #include <dev/pci/pcidevs.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/cs4280reg.h> 80 #include <dev/microcode/cirruslogic/cs4280_image.h> 81 82 #include <sys/audioio.h> 83 #include <dev/audio_if.h> 84 #include <dev/midi_if.h> 85 #include <dev/mulaw.h> 86 #include <dev/auconv.h> 87 88 #include <dev/ic/ac97.h> 89 90 #include <machine/bus.h> 91 92 #define CSCC_PCI_BA0 0x10 93 #define CSCC_PCI_BA1 0x14 94 95 struct cs4280_dma { 96 bus_dmamap_t map; 97 caddr_t addr; /* real dma buffer */ 98 caddr_t dum; /* dummy buffer for audio driver */ 99 bus_dma_segment_t segs[1]; 100 int nsegs; 101 size_t size; 102 struct cs4280_dma *next; 103 }; 104 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 105 #define BUFADDR(p) ((void *)((p)->dum)) 106 #define KERNADDR(p) ((void *)((p)->addr)) 107 108 /* 109 * Software state 110 */ 111 struct cs4280_softc { 112 struct device sc_dev; 113 114 pci_intr_handle_t * sc_ih; 115 116 /* I/O (BA0) */ 117 bus_space_tag_t ba0t; 118 bus_space_handle_t ba0h; 119 120 /* BA1 */ 121 bus_space_tag_t ba1t; 122 bus_space_handle_t ba1h; 123 124 /* DMA */ 125 bus_dma_tag_t sc_dmatag; 126 struct cs4280_dma *sc_dmas; 127 128 void (*sc_pintr)(void *); /* dma completion intr handler */ 129 void *sc_parg; /* arg for sc_intr() */ 130 char *sc_ps, *sc_pe, *sc_pn; 131 int sc_pcount; 132 int sc_pi; 133 struct cs4280_dma *sc_pdma; 134 char *sc_pbuf; 135 #ifdef DIAGNOSTIC 136 char sc_prun; 137 #endif 138 139 void (*sc_rintr)(void *); /* dma completion intr handler */ 140 void *sc_rarg; /* arg for sc_intr() */ 141 char *sc_rs, *sc_re, *sc_rn; 142 int sc_rcount; 143 int sc_ri; 144 struct cs4280_dma *sc_rdma; 145 char *sc_rbuf; 146 int sc_rparam; /* record format */ 147 #ifdef DIAGNOSTIC 148 char sc_rrun; 149 #endif 150 151 #if NMIDI > 0 152 void (*sc_iintr)(void *, int); /* midi input ready handler */ 153 void (*sc_ointr)(void *); /* midi output ready handler */ 154 void *sc_arg; 155 #endif 156 157 u_int32_t pctl; 158 u_int32_t cctl; 159 160 struct ac97_codec_if *codec_if; 161 struct ac97_host_if host_if; 162 163 char sc_suspend; 164 void *sc_powerhook; /* Power Hook */ 165 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 166 }; 167 168 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 169 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 170 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 171 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 172 173 int cs4280_match __P((struct device *, void *, void *)); 174 void cs4280_attach __P((struct device *, struct device *, void *)); 175 int cs4280_intr __P((void *)); 176 void cs4280_reset __P((void *)); 177 int cs4280_download_image __P((struct cs4280_softc *)); 178 179 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 180 int cs4280_allocmem __P((struct cs4280_softc *, size_t, size_t, 181 struct cs4280_dma *)); 182 int cs4280_freemem __P((struct cs4280_softc *, struct cs4280_dma *)); 183 184 #ifdef CS4280_DEBUG 185 int cs4280_check_images __P((struct cs4280_softc *)); 186 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 187 u_int32_t); 188 #endif 189 190 struct cfdriver clcs_cd = { 191 NULL, "clcs", DV_DULL 192 }; 193 194 struct cfattach clcs_ca = { 195 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 196 }; 197 198 int cs4280_init __P((struct cs4280_softc *, int)); 199 int cs4280_open __P((void *, int)); 200 void cs4280_close __P((void *)); 201 202 int cs4280_query_encoding __P((void *, struct audio_encoding *)); 203 int cs4280_set_params __P((void *, int, int, struct audio_params *, struct audio_params *)); 204 int cs4280_round_blocksize __P((void *, int)); 205 206 int cs4280_halt_output __P((void *)); 207 int cs4280_halt_input __P((void *)); 208 209 int cs4280_getdev __P((void *, struct audio_device *)); 210 211 int cs4280_mixer_set_port __P((void *, mixer_ctrl_t *)); 212 int cs4280_mixer_get_port __P((void *, mixer_ctrl_t *)); 213 int cs4280_query_devinfo __P((void *addr, mixer_devinfo_t *dip)); 214 void *cs4280_malloc __P((void *, u_long, int, int)); 215 void cs4280_free __P((void *, void *, int)); 216 u_long cs4280_round_buffersize __P((void *, u_long)); 217 paddr_t cs4280_mappage __P((void *, void *, off_t, int)); 218 int cs4280_get_props __P((void *)); 219 int cs4280_trigger_output __P((void *, void *, void *, int, void (*)(void *), 220 void *, struct audio_params *)); 221 int cs4280_trigger_input __P((void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *)); 223 224 225 void cs4280_set_dac_rate __P((struct cs4280_softc *, int )); 226 void cs4280_set_adc_rate __P((struct cs4280_softc *, int )); 227 int cs4280_get_portnum_by_name __P((struct cs4280_softc *, char *, char *, 228 char *)); 229 int cs4280_src_wait __P((struct cs4280_softc *)); 230 int cs4280_attach_codec __P((void *sc, struct ac97_codec_if *)); 231 int cs4280_read_codec __P((void *sc, u_int8_t a, u_int16_t *d)); 232 int cs4280_write_codec __P((void *sc, u_int8_t a, u_int16_t d)); 233 void cs4280_reset_codec __P((void *sc)); 234 235 void cs4280_power __P((int, void *)); 236 237 void cs4280_clear_fifos __P((struct cs4280_softc *)); 238 239 #if NMIDI > 0 240 void cs4280_midi_close __P((void*)); 241 void cs4280_midi_getinfo __P((void *, struct midi_info *)); 242 int cs4280_midi_open __P((void *, int, void (*)(void *, int), 243 void (*)(void *), void *)); 244 int cs4280_midi_output __P((void *, int)); 245 #endif 246 247 struct audio_hw_if cs4280_hw_if = { 248 cs4280_open, 249 cs4280_close, 250 NULL, 251 cs4280_query_encoding, 252 cs4280_set_params, 253 cs4280_round_blocksize, 254 NULL, 255 NULL, 256 NULL, 257 NULL, 258 NULL, 259 cs4280_halt_output, 260 cs4280_halt_input, 261 NULL, 262 cs4280_getdev, 263 NULL, 264 cs4280_mixer_set_port, 265 cs4280_mixer_get_port, 266 cs4280_query_devinfo, 267 cs4280_malloc, 268 cs4280_free, 269 cs4280_round_buffersize, 270 0, /* cs4280_mappage, */ 271 cs4280_get_props, 272 cs4280_trigger_output, 273 cs4280_trigger_input, 274 }; 275 276 #if NMIDI > 0 277 struct midi_hw_if cs4280_midi_hw_if = { 278 cs4280_midi_open, 279 cs4280_midi_close, 280 cs4280_midi_output, 281 cs4280_midi_getinfo, 282 0, 283 }; 284 #endif 285 286 287 288 struct audio_device cs4280_device = { 289 "CS4280", 290 "", 291 "cs4280" 292 }; 293 294 295 int 296 cs4280_match(parent, ma, aux) 297 struct device *parent; 298 void *ma; 299 void *aux; 300 { 301 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 302 303 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS) 304 return (0); 305 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280 || 306 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610 || 307 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4614 || 308 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4615) { 309 return (1); 310 } 311 return (0); 312 } 313 314 int 315 cs4280_read_codec(sc_, add, data) 316 void *sc_; 317 u_int8_t add; 318 u_int16_t *data; 319 { 320 struct cs4280_softc *sc = sc_; 321 int n; 322 323 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 324 /* 325 * Make sure that there is not data sitting around from a preivous 326 * uncompleted access. 327 */ 328 BA0READ4(sc, CS4280_ACSDA); 329 330 /* Set up AC97 control registers. */ 331 BA0WRITE4(sc, CS4280_ACCAD, add); 332 BA0WRITE4(sc, CS4280_ACCDA, 0); 333 BA0WRITE4(sc, CS4280_ACCTL, 334 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 335 336 if (cs4280_src_wait(sc) < 0) { 337 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 338 sc->sc_dev.dv_xname, add); 339 return (1); 340 } 341 342 /* wait for valid status bit is active */ 343 n = 0; 344 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 345 delay(1); 346 while (++n > 1000) { 347 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 348 sc->sc_dev.dv_xname, add); 349 return (1); 350 } 351 } 352 *data = BA0READ4(sc, CS4280_ACSDA); 353 DPRINTFN(5,("data=0x%04x\n", *data)); 354 return (0); 355 } 356 357 int 358 cs4280_write_codec(sc_, add, data) 359 void *sc_; 360 u_int8_t add; 361 u_int16_t data; 362 { 363 struct cs4280_softc *sc = sc_; 364 365 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 366 BA0WRITE4(sc, CS4280_ACCAD, add); 367 BA0WRITE4(sc, CS4280_ACCDA, data); 368 BA0WRITE4(sc, CS4280_ACCTL, 369 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 370 371 if (cs4280_src_wait(sc) < 0) { 372 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 373 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 374 return (1); 375 } 376 return (0); 377 } 378 379 int 380 cs4280_src_wait(sc) 381 struct cs4280_softc *sc; 382 { 383 int n; 384 n = 0; 385 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 386 delay(1000); 387 while (++n > 1000) 388 return (-1); 389 } 390 return (0); 391 } 392 393 394 void 395 cs4280_set_adc_rate(sc, rate) 396 struct cs4280_softc *sc; 397 int rate; 398 { 399 /* calculate capture rate: 400 * 401 * capture_coefficient_increment = -round(rate*128*65536/48000; 402 * capture_phase_increment = floor(48000*65536*1024/rate); 403 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 404 * cy = floor(cx/200); 405 * capture_sample_rate_correction = cx - 200*cy; 406 * capture_delay = ceil(24*48000/rate); 407 * capture_num_triplets = floor(65536*rate/24000); 408 * capture_group_length = 24000/GCD(rate, 24000); 409 * where GCD means "Greatest Common Divisor". 410 * 411 * capture_coefficient_increment, capture_phase_increment and 412 * capture_num_triplets are 32-bit signed quantities. 413 * capture_sample_rate_correction and capture_group_length are 414 * 16-bit signed quantities. 415 * capture_delay is a 14-bit unsigned quantity. 416 */ 417 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 418 u_int16_t csrc, cgl, cdlay; 419 420 /* XXX 421 * Even though, embedded_audio_spec says capture rate range 11025 to 422 * 48000, dhwiface.cpp says, 423 * 424 * "We can only decimate by up to a factor of 1/9th the hardware rate. 425 * Return an error if an attempt is made to stray outside that limit." 426 * 427 * so assume range as 48000/9 to 48000 428 */ 429 430 if (rate < 8000) 431 rate = 8000; 432 if (rate > 48000) 433 rate = 48000; 434 435 cx = rate << 16; 436 cci = cx / 48000; 437 cx -= cci * 48000; 438 cx <<= 7; 439 cci <<= 7; 440 cci += cx / 48000; 441 cci = - cci; 442 443 cx = 48000 << 16; 444 cpi = cx / rate; 445 cx -= cpi * rate; 446 cx <<= 10; 447 cpi <<= 10; 448 cy = cx / rate; 449 cpi += cy; 450 cx -= cy * rate; 451 452 cy = cx / 200; 453 csrc = cx - 200*cy; 454 455 cdlay = ((48000 * 24) + rate - 1) / rate; 456 #if 0 457 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 458 #endif 459 460 cnt = rate << 16; 461 cnt /= 24000; 462 463 cgl = 1; 464 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 465 if (((rate / tmp1) * tmp1) != rate) 466 cgl *= 2; 467 } 468 if (((rate / 3) * 3) != rate) 469 cgl *= 3; 470 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 471 if (((rate / tmp1) * tmp1) != rate) 472 cgl *= 5; 473 } 474 #if 0 475 /* XXX what manual says */ 476 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 477 tmp1 |= csrc<<16; 478 BA1WRITE4(sc, CS4280_CSRC, tmp1); 479 #else 480 /* suggested by cs461x.c (ALSA driver) */ 481 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 482 #endif 483 484 #if 0 485 /* I am confused. The sample rate calculation section says 486 * cci *is* 32-bit signed quantity but in the parameter description 487 * section, CCI only assigned 16bit. 488 * I believe size of the variable. 489 */ 490 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 491 tmp1 |= cci<<16; 492 BA1WRITE4(sc, CS4280_CCI, tmp1); 493 #else 494 BA1WRITE4(sc, CS4280_CCI, cci); 495 #endif 496 497 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 498 tmp1 |= cdlay <<18; 499 BA1WRITE4(sc, CS4280_CD, tmp1); 500 501 BA1WRITE4(sc, CS4280_CPI, cpi); 502 503 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 504 tmp1 |= cgl; 505 BA1WRITE4(sc, CS4280_CGL, tmp1); 506 507 BA1WRITE4(sc, CS4280_CNT, cnt); 508 509 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 510 tmp1 |= cgl; 511 BA1WRITE4(sc, CS4280_CGC, tmp1); 512 } 513 514 void 515 cs4280_set_dac_rate(sc, rate) 516 struct cs4280_softc *sc; 517 int rate; 518 { 519 /* 520 * playback rate may range from 8000Hz to 48000Hz 521 * 522 * play_phase_increment = floor(rate*65536*1024/48000) 523 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 524 * py=floor(px/200) 525 * play_sample_rate_correction = px - 200*py 526 * 527 * play_phase_increment is a 32bit signed quantity. 528 * play_sample_rate_correction is a 16bit signed quantity. 529 */ 530 int32_t ppi; 531 int16_t psrc; 532 u_int32_t px, py; 533 534 if (rate < 8000) 535 rate = 8000; 536 if (rate > 48000) 537 rate = 48000; 538 px = rate << 16; 539 ppi = px/48000; 540 px -= ppi*48000; 541 ppi <<= 10; 542 px <<= 10; 543 py = px / 48000; 544 ppi += py; 545 px -= py*48000; 546 py = px/200; 547 px -= py*200; 548 psrc = px; 549 #if 0 550 /* what manual says */ 551 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 552 BA1WRITE4(sc, CS4280_PSRC, 553 ( ((psrc<<16) & PSRC_MASK) | px )); 554 #else 555 /* suggested by cs461x.c (ALSA driver) */ 556 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 557 #endif 558 BA1WRITE4(sc, CS4280_PPI, ppi); 559 } 560 561 void 562 cs4280_attach(parent, self, aux) 563 struct device *parent; 564 struct device *self; 565 void *aux; 566 { 567 struct cs4280_softc *sc = (struct cs4280_softc *) self; 568 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 569 pci_chipset_tag_t pc = pa->pa_pc; 570 char const *intrstr; 571 pci_intr_handle_t ih; 572 mixer_ctrl_t ctl; 573 u_int32_t mem; 574 575 /* Map I/O register */ 576 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 577 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 578 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 579 printf(": can't map BA0 space\n"); 580 return; 581 } 582 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 583 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 584 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 585 printf(": can't map BA1 space\n"); 586 return; 587 } 588 589 sc->sc_dmatag = pa->pa_dmat; 590 591 /* Enable the device (set bus master flag) */ 592 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 593 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 594 PCI_COMMAND_MASTER_ENABLE); 595 596 /* LATENCY_TIMER setting */ 597 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 598 if ( PCI_LATTIMER(mem) < 32 ) { 599 mem &= 0xffff00ff; 600 mem |= 0x00002000; 601 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 602 } 603 604 /* Map and establish the interrupt. */ 605 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 606 pa->pa_intrline, &ih)) { 607 printf(": couldn't map interrupt\n"); 608 return; 609 } 610 intrstr = pci_intr_string(pc, ih); 611 612 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc, 613 sc->sc_dev.dv_xname); 614 if (sc->sc_ih == NULL) { 615 printf(": couldn't establish interrupt"); 616 if (intrstr != NULL) 617 printf(" at %s", intrstr); 618 printf("\n"); 619 return; 620 } 621 printf(" %s\n", intrstr); 622 623 /* Initialization */ 624 if(cs4280_init(sc, 1) != 0) 625 return; 626 627 /* AC 97 attachement */ 628 sc->host_if.arg = sc; 629 sc->host_if.attach = cs4280_attach_codec; 630 sc->host_if.read = cs4280_read_codec; 631 sc->host_if.write = cs4280_write_codec; 632 sc->host_if.reset = cs4280_reset_codec; 633 634 if (ac97_attach(&sc->host_if) != 0) { 635 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 636 return; 637 } 638 639 /* Turn mute off of DAC, CD and master volumes by default */ 640 ctl.type = AUDIO_MIXER_ENUM; 641 ctl.un.ord = 0; /* off */ 642 643 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 644 AudioNmaster, AudioNmute); 645 cs4280_mixer_set_port(sc, &ctl); 646 647 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 648 AudioNdac, AudioNmute); 649 cs4280_mixer_set_port(sc, &ctl); 650 651 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 652 AudioNcd, AudioNmute); 653 cs4280_mixer_set_port(sc, &ctl); 654 655 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 656 657 #if NMIDI > 0 658 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 659 #endif 660 sc->sc_suspend = PWR_RESUME; 661 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 662 } 663 664 int 665 cs4280_intr(p) 666 void *p; 667 { 668 /* 669 * XXX 670 * 671 * Since CS4280 has only 4kB dma buffer and 672 * interrupt occurs every 2kB block, I create dummy buffer 673 * which returns to audio driver and actual dma buffer 674 * using in DMA transfer. 675 * 676 * 677 * ring buffer in audio.c is pointed by BUFADDR 678 * <------ ring buffer size == 64kB ------> 679 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 680 * |= = = =|= = = =|= = = =|= = = =|= = = =| 681 * | | | | | | <- call audio_intp every 682 * sc->sc_[pr]_count time. 683 * 684 * actual dma buffer is pointed by KERNADDR 685 * <-> dma buffer size = 4kB 686 * |= =| 687 * 688 * 689 */ 690 struct cs4280_softc *sc = p; 691 u_int32_t intr, mem; 692 char * empty_dma; 693 int handled = 0; 694 695 /* grab interrupt register then clear it */ 696 intr = BA0READ4(sc, CS4280_HISR); 697 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 698 699 /* Playback Interrupt */ 700 if (intr & HISR_PINT) { 701 handled = 1; 702 mem = BA1READ4(sc, CS4280_PFIE); 703 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 704 if (sc->sc_pintr) { 705 if ((sc->sc_pi%sc->sc_pcount) == 0) 706 sc->sc_pintr(sc->sc_parg); 707 } else { 708 printf("unexpected play intr\n"); 709 } 710 /* copy buffer */ 711 ++sc->sc_pi; 712 empty_dma = sc->sc_pdma->addr; 713 if (sc->sc_pi&1) 714 empty_dma += CS4280_ICHUNK; 715 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 716 sc->sc_pn += CS4280_ICHUNK; 717 if (sc->sc_pn >= sc->sc_pe) 718 sc->sc_pn = sc->sc_ps; 719 BA1WRITE4(sc, CS4280_PFIE, mem); 720 } 721 /* Capture Interrupt */ 722 if (intr & HISR_CINT) { 723 int i; 724 int16_t rdata; 725 726 handled = 1; 727 mem = BA1READ4(sc, CS4280_CIE); 728 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 729 ++sc->sc_ri; 730 empty_dma = sc->sc_rdma->addr; 731 if ((sc->sc_ri&1) == 0) 732 empty_dma += CS4280_ICHUNK; 733 734 /* 735 * XXX 736 * I think this audio data conversion should be 737 * happend in upper layer, but I put this here 738 * since there is no conversion function available. 739 */ 740 switch(sc->sc_rparam) { 741 case CF_16BIT_STEREO: 742 /* just copy it */ 743 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 744 sc->sc_rn += CS4280_ICHUNK; 745 break; 746 case CF_16BIT_MONO: 747 for (i = 0; i < 512; i++) { 748 rdata = *((int16_t *)empty_dma)++>>1; 749 rdata += *((int16_t *)empty_dma)++>>1; 750 *((int16_t *)sc->sc_rn)++ = rdata; 751 } 752 break; 753 case CF_8BIT_STEREO: 754 for (i = 0; i < 512; i++) { 755 rdata = *((int16_t*)empty_dma)++; 756 *sc->sc_rn++ = rdata >> 8; 757 rdata = *((int16_t*)empty_dma)++; 758 *sc->sc_rn++ = rdata >> 8; 759 } 760 break; 761 case CF_8BIT_MONO: 762 for (i = 0; i < 512; i++) { 763 rdata = *((int16_t*)empty_dma)++ >>1; 764 rdata += *((int16_t*)empty_dma)++ >>1; 765 *sc->sc_rn++ = rdata >>8; 766 } 767 break; 768 default: 769 /* Should not reach here */ 770 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 771 } 772 if (sc->sc_rn >= sc->sc_re) 773 sc->sc_rn = sc->sc_rs; 774 BA1WRITE4(sc, CS4280_CIE, mem); 775 if (sc->sc_rintr) { 776 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 777 sc->sc_rintr(sc->sc_rarg); 778 } else { 779 printf("unexpected record intr\n"); 780 } 781 } 782 783 #if NMIDI > 0 784 /* Midi port Interrupt */ 785 if (intr & HISR_MIDI) { 786 int data; 787 788 handled = 1; 789 DPRINTF(("i: %d: ", 790 BA0READ4(sc, CS4280_MIDSR))); 791 /* Read the received data */ 792 while ((sc->sc_iintr != NULL) && 793 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 794 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 795 DPRINTF(("r:%x\n",data)); 796 sc->sc_iintr(sc->sc_arg, data); 797 } 798 799 /* Write the data */ 800 #if 1 801 /* XXX: 802 * It seems "Transmit Buffer Full" never activate until EOI 803 * is deliverd. Shall I throw EOI top of this routine ? 804 */ 805 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 806 DPRINTF(("w: ")); 807 if (sc->sc_ointr != NULL) 808 sc->sc_ointr(sc->sc_arg); 809 } 810 #else 811 while ((sc->sc_ointr != NULL) && 812 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 813 DPRINTF(("w: ")); 814 sc->sc_ointr(sc->sc_arg); 815 } 816 #endif 817 DPRINTF(("\n")); 818 } 819 #endif 820 821 return handled; 822 } 823 824 825 /* Download Proceessor Code and Data image */ 826 827 int 828 cs4280_download(sc, src, offset, len) 829 struct cs4280_softc *sc; 830 const u_int32_t *src; 831 u_int32_t offset, len; 832 { 833 u_int32_t ctr; 834 835 #ifdef CS4280_DEBUG 836 u_int32_t con, data; 837 u_int8_t c0,c1,c2,c3; 838 #endif 839 if ((offset&3) || (len&3)) 840 return (-1); 841 842 len /= sizeof(u_int32_t); 843 for (ctr = 0; ctr < len; ctr++) { 844 /* XXX: 845 * I cannot confirm this is the right thing or not 846 * on BIG-ENDIAN machines. 847 */ 848 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 849 #ifdef CS4280_DEBUG 850 data = htole32(*(src+ctr)); 851 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 852 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 853 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 854 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 855 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 856 if (data != con ) { 857 printf("0x%06x: write=0x%08x read=0x%08x\n", 858 offset+ctr*4, data, con); 859 return (-1); 860 } 861 #endif 862 } 863 return (0); 864 } 865 866 int 867 cs4280_download_image(sc) 868 struct cs4280_softc *sc; 869 { 870 int idx, err; 871 u_int32_t offset = 0; 872 873 err = 0; 874 875 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 876 err = cs4280_download(sc, &BA1Struct.map[offset], 877 BA1Struct.memory[idx].offset, 878 BA1Struct.memory[idx].size); 879 if (err != 0) { 880 printf("%s: load_image failed at %d\n", 881 sc->sc_dev.dv_xname, idx); 882 return (-1); 883 } 884 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 885 } 886 return (err); 887 } 888 889 #ifdef CS4280_DEBUG 890 int 891 cs4280_checkimage(sc, src, offset, len) 892 struct cs4280_softc *sc; 893 u_int32_t *src; 894 u_int32_t offset, len; 895 { 896 u_int32_t ctr, data; 897 int err = 0; 898 899 if ((offset&3) || (len&3)) 900 return -1; 901 902 len /= sizeof(u_int32_t); 903 for (ctr = 0; ctr < len; ctr++) { 904 /* I cannot confirm this is the right thing 905 * on BIG-ENDIAN machines 906 */ 907 data = BA1READ4(sc, offset+ctr*4); 908 if (data != htole32(*(src+ctr))) { 909 printf("0x%06x: 0x%08x(0x%08x)\n", 910 offset+ctr*4, data, *(src+ctr)); 911 *(src+ctr) = data; 912 ++err; 913 } 914 } 915 return (err); 916 } 917 918 int 919 cs4280_check_images(sc) 920 struct cs4280_softc *sc; 921 { 922 int idx, err; 923 u_int32_t offset = 0; 924 925 err = 0; 926 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 927 for (idx = 0; idx < 1; ++idx) { 928 err = cs4280_checkimage(sc, &BA1Struct.map[offset], 929 BA1Struct.memory[idx].offset, 930 BA1Struct.memory[idx].size); 931 if (err != 0) { 932 printf("%s: check_image failed at %d\n", 933 sc->sc_dev.dv_xname, idx); 934 } 935 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t); 936 } 937 return (err); 938 } 939 940 #endif 941 942 int 943 cs4280_attach_codec(sc_, codec_if) 944 void *sc_; 945 struct ac97_codec_if *codec_if; 946 { 947 struct cs4280_softc *sc = sc_; 948 949 sc->codec_if = codec_if; 950 return (0); 951 } 952 953 void 954 cs4280_reset_codec(sc_) 955 void *sc_; 956 { 957 struct cs4280_softc *sc = sc_; 958 int n; 959 960 /* Reset codec */ 961 BA0WRITE4(sc, CS4280_ACCTL, 0); 962 delay(100); /* delay 100us */ 963 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 964 965 /* 966 * It looks like we do the following procedure, too 967 */ 968 969 /* Enable AC-link sync generation */ 970 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 971 delay(50*1000); /* XXX delay 50ms */ 972 973 /* Assert valid frame signal */ 974 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 975 976 /* Wait for valid AC97 input slot */ 977 n = 0; 978 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 979 delay(1000); 980 if (++n > 1000) { 981 printf("reset_codec: AC97 inputs slot ready timeout\n"); 982 return; 983 } 984 } 985 } 986 987 988 /* Processor Soft Reset */ 989 void 990 cs4280_reset(sc_) 991 void *sc_; 992 { 993 struct cs4280_softc *sc = sc_; 994 995 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 996 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 997 delay(100); 998 /* Clear RSTSP bit in SPCR */ 999 BA1WRITE4(sc, CS4280_SPCR, 0); 1000 /* enable DMA reqest */ 1001 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1002 } 1003 1004 int 1005 cs4280_open(addr, flags) 1006 void *addr; 1007 int flags; 1008 { 1009 return (0); 1010 } 1011 1012 void 1013 cs4280_close(addr) 1014 void *addr; 1015 { 1016 struct cs4280_softc *sc = addr; 1017 1018 cs4280_halt_output(sc); 1019 cs4280_halt_input(sc); 1020 1021 sc->sc_pintr = 0; 1022 sc->sc_rintr = 0; 1023 } 1024 1025 int 1026 cs4280_query_encoding(addr, fp) 1027 void *addr; 1028 struct audio_encoding *fp; 1029 { 1030 switch (fp->index) { 1031 case 0: 1032 strcpy(fp->name, AudioEulinear); 1033 fp->encoding = AUDIO_ENCODING_ULINEAR; 1034 fp->precision = 8; 1035 fp->flags = 0; 1036 break; 1037 case 1: 1038 strcpy(fp->name, AudioEmulaw); 1039 fp->encoding = AUDIO_ENCODING_ULAW; 1040 fp->precision = 8; 1041 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1042 break; 1043 case 2: 1044 strcpy(fp->name, AudioEalaw); 1045 fp->encoding = AUDIO_ENCODING_ALAW; 1046 fp->precision = 8; 1047 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1048 break; 1049 case 3: 1050 strcpy(fp->name, AudioEslinear); 1051 fp->encoding = AUDIO_ENCODING_SLINEAR; 1052 fp->precision = 8; 1053 fp->flags = 0; 1054 break; 1055 case 4: 1056 strcpy(fp->name, AudioEslinear_le); 1057 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1058 fp->precision = 16; 1059 fp->flags = 0; 1060 break; 1061 case 5: 1062 strcpy(fp->name, AudioEulinear_le); 1063 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1064 fp->precision = 16; 1065 fp->flags = 0; 1066 break; 1067 case 6: 1068 strcpy(fp->name, AudioEslinear_be); 1069 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1070 fp->precision = 16; 1071 fp->flags = 0; 1072 break; 1073 case 7: 1074 strcpy(fp->name, AudioEulinear_be); 1075 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1076 fp->precision = 16; 1077 fp->flags = 0; 1078 break; 1079 default: 1080 return (EINVAL); 1081 } 1082 return (0); 1083 } 1084 1085 int 1086 cs4280_set_params(addr, setmode, usemode, play, rec) 1087 void *addr; 1088 int setmode, usemode; 1089 struct audio_params *play, *rec; 1090 { 1091 struct cs4280_softc *sc = addr; 1092 struct audio_params *p; 1093 int mode; 1094 1095 for (mode = AUMODE_RECORD; mode != -1; 1096 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1097 if ((setmode & mode) == 0) 1098 continue; 1099 1100 p = mode == AUMODE_PLAY ? play : rec; 1101 1102 if (p == play) { 1103 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1104 p->sample_rate, p->precision, p->channels)); 1105 /* play back data format may be 8- or 16-bit and 1106 * either stereo or mono. 1107 * playback rate may range from 8000Hz to 48000Hz 1108 */ 1109 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1110 (p->precision != 8 && p->precision != 16) || 1111 (p->channels != 1 && p->channels != 2) ) { 1112 return (EINVAL); 1113 } 1114 } else { 1115 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1116 p->sample_rate, p->precision, p->channels)); 1117 /* capture data format must be 16bit stereo 1118 * and sample rate range from 11025Hz to 48000Hz. 1119 * 1120 * XXX: it looks like to work with 8000Hz, 1121 * although data sheets say lower limit is 1122 * 11025 Hz. 1123 */ 1124 1125 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1126 (p->precision != 8 && p->precision != 16) || 1127 (p->channels != 1 && p->channels != 2) ) { 1128 return (EINVAL); 1129 } 1130 } 1131 p->factor = 1; 1132 p->sw_code = 0; 1133 1134 /* capturing data is slinear */ 1135 switch (p->encoding) { 1136 case AUDIO_ENCODING_SLINEAR_BE: 1137 if (mode == AUMODE_RECORD) { 1138 if (p->precision == 16) 1139 p->sw_code = swap_bytes; 1140 } 1141 break; 1142 case AUDIO_ENCODING_SLINEAR_LE: 1143 break; 1144 case AUDIO_ENCODING_ULINEAR_BE: 1145 if (mode == AUMODE_RECORD) { 1146 if (p->precision == 16) 1147 p->sw_code = change_sign16_swap_bytes; 1148 else 1149 p->sw_code = change_sign8; 1150 } 1151 break; 1152 case AUDIO_ENCODING_ULINEAR_LE: 1153 if (mode == AUMODE_RECORD) { 1154 if (p->precision == 16) 1155 p->sw_code = change_sign16; 1156 else 1157 p->sw_code = change_sign8; 1158 } 1159 break; 1160 case AUDIO_ENCODING_ULAW: 1161 if (mode == AUMODE_PLAY) { 1162 p->factor = 2; 1163 p->sw_code = mulaw_to_slinear16; 1164 } else { 1165 p->sw_code = slinear8_to_mulaw; 1166 } 1167 break; 1168 case AUDIO_ENCODING_ALAW: 1169 if (mode == AUMODE_PLAY) { 1170 p->factor = 2; 1171 p->sw_code = alaw_to_slinear16; 1172 } else { 1173 p->sw_code = slinear8_to_alaw; 1174 } 1175 break; 1176 default: 1177 return (EINVAL); 1178 } 1179 } 1180 1181 /* set sample rate */ 1182 cs4280_set_dac_rate(sc, play->sample_rate); 1183 cs4280_set_adc_rate(sc, rec->sample_rate); 1184 return (0); 1185 } 1186 1187 int 1188 cs4280_round_blocksize(hdl, blk) 1189 void *hdl; 1190 int blk; 1191 { 1192 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1193 } 1194 1195 u_long 1196 cs4280_round_buffersize(addr, size) 1197 void *addr; 1198 u_long size; 1199 { 1200 /* although real dma buffer size is 4KB, 1201 * let the audio.c driver use a larger buffer. 1202 * ( suggested by Lennart Augustsson. ) 1203 */ 1204 return (size); 1205 } 1206 1207 int 1208 cs4280_get_props(hdl) 1209 void *hdl; 1210 { 1211 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1212 #ifdef notyet 1213 /* XXX 1214 * How can I mmap ? 1215 */ 1216 AUDIO_PROP_MMAP 1217 #endif 1218 1219 } 1220 1221 int 1222 cs4280_mixer_get_port(addr, cp) 1223 void *addr; 1224 mixer_ctrl_t *cp; 1225 { 1226 struct cs4280_softc *sc = addr; 1227 1228 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1229 } 1230 1231 paddr_t 1232 cs4280_mappage(addr, mem, off, prot) 1233 void *addr; 1234 void *mem; 1235 off_t off; 1236 int prot; 1237 { 1238 struct cs4280_softc *sc = addr; 1239 struct cs4280_dma *p; 1240 1241 if (off < 0) 1242 return (-1); 1243 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1244 ; 1245 if (!p) { 1246 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1247 return (-1); 1248 } 1249 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1250 off, prot, BUS_DMA_WAITOK)); 1251 } 1252 1253 1254 int 1255 cs4280_query_devinfo(addr, dip) 1256 void *addr; 1257 mixer_devinfo_t *dip; 1258 { 1259 struct cs4280_softc *sc = addr; 1260 1261 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1262 } 1263 1264 int 1265 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1266 struct cs4280_softc *sc; 1267 char *class, *device, *qualifier; 1268 { 1269 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1270 device, qualifier)); 1271 } 1272 1273 int 1274 cs4280_halt_output(addr) 1275 void *addr; 1276 { 1277 struct cs4280_softc *sc = addr; 1278 u_int32_t mem; 1279 1280 mem = BA1READ4(sc, CS4280_PCTL); 1281 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1282 #ifdef DIAGNOSTIC 1283 sc->sc_prun = 0; 1284 #endif 1285 return (0); 1286 } 1287 1288 int 1289 cs4280_halt_input(addr) 1290 void *addr; 1291 { 1292 struct cs4280_softc *sc = addr; 1293 u_int32_t mem; 1294 1295 mem = BA1READ4(sc, CS4280_CCTL); 1296 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1297 #ifdef DIAGNOSTIC 1298 sc->sc_rrun = 0; 1299 #endif 1300 return (0); 1301 } 1302 1303 int 1304 cs4280_getdev(addr, retp) 1305 void *addr; 1306 struct audio_device *retp; 1307 { 1308 *retp = cs4280_device; 1309 return (0); 1310 } 1311 1312 int 1313 cs4280_mixer_set_port(addr, cp) 1314 void *addr; 1315 mixer_ctrl_t *cp; 1316 { 1317 struct cs4280_softc *sc = addr; 1318 int val; 1319 1320 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1321 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1322 return (val); 1323 } 1324 1325 1326 int 1327 cs4280_freemem(sc, p) 1328 struct cs4280_softc *sc; 1329 struct cs4280_dma *p; 1330 { 1331 bus_dmamap_unload(sc->sc_dmatag, p->map); 1332 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1333 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1334 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1335 return (0); 1336 } 1337 1338 int 1339 cs4280_allocmem(sc, size, align, p) 1340 struct cs4280_softc *sc; 1341 size_t size; 1342 size_t align; 1343 struct cs4280_dma *p; 1344 { 1345 int error; 1346 1347 /* XXX */ 1348 p->size = size; 1349 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1350 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1351 &p->nsegs, BUS_DMA_NOWAIT); 1352 if (error) { 1353 printf("%s: unable to allocate dma, error=%d\n", 1354 sc->sc_dev.dv_xname, error); 1355 return (error); 1356 } 1357 1358 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1359 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1360 if (error) { 1361 printf("%s: unable to map dma, error=%d\n", 1362 sc->sc_dev.dv_xname, error); 1363 goto free; 1364 } 1365 1366 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1367 0, BUS_DMA_NOWAIT, &p->map); 1368 if (error) { 1369 printf("%s: unable to create dma map, error=%d\n", 1370 sc->sc_dev.dv_xname, error); 1371 goto unmap; 1372 } 1373 1374 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1375 BUS_DMA_NOWAIT); 1376 if (error) { 1377 printf("%s: unable to load dma map, error=%d\n", 1378 sc->sc_dev.dv_xname, error); 1379 goto destroy; 1380 } 1381 return (0); 1382 1383 destroy: 1384 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1385 unmap: 1386 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1387 free: 1388 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1389 return (error); 1390 } 1391 1392 1393 void * 1394 cs4280_malloc(addr, size, pool, flags) 1395 void *addr; 1396 u_long size; 1397 int pool, flags; 1398 { 1399 struct cs4280_softc *sc = addr; 1400 struct cs4280_dma *p; 1401 caddr_t q; 1402 int error; 1403 1404 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1405 q = malloc(size, pool, flags); 1406 if (!q) 1407 return (0); 1408 p = malloc(sizeof(*p), pool, flags); 1409 if (!p) { 1410 free(q,pool); 1411 return (0); 1412 } 1413 /* 1414 * cs4280 has fixed 4kB buffer 1415 */ 1416 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1417 1418 if (error) { 1419 free(q, pool); 1420 free(p, pool); 1421 return (0); 1422 } 1423 1424 p->next = sc->sc_dmas; 1425 sc->sc_dmas = p; 1426 p->dum = q; /* return to audio driver */ 1427 1428 return (p->dum); 1429 } 1430 1431 void 1432 cs4280_free(addr, ptr, pool) 1433 void *addr; 1434 void *ptr; 1435 int pool; 1436 { 1437 struct cs4280_softc *sc = addr; 1438 struct cs4280_dma **pp, *p; 1439 1440 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1441 if (BUFADDR(p) == ptr) { 1442 cs4280_freemem(sc, p); 1443 *pp = p->next; 1444 free(p->dum, pool); 1445 free(p, pool); 1446 return; 1447 } 1448 } 1449 } 1450 1451 int 1452 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1453 void *addr; 1454 void *start, *end; 1455 int blksize; 1456 void (*intr) __P((void *)); 1457 void *arg; 1458 struct audio_params *param; 1459 { 1460 struct cs4280_softc *sc = addr; 1461 u_int32_t pfie, pctl, mem, pdtc; 1462 struct cs4280_dma *p; 1463 1464 #ifdef DIAGNOSTIC 1465 if (sc->sc_prun) 1466 printf("cs4280_trigger_output: already running\n"); 1467 sc->sc_prun = 1; 1468 #endif 1469 1470 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1471 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1472 sc->sc_pintr = intr; 1473 sc->sc_parg = arg; 1474 1475 /* stop playback DMA */ 1476 mem = BA1READ4(sc, CS4280_PCTL); 1477 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1478 1479 /* setup PDTC */ 1480 pdtc = BA1READ4(sc, CS4280_PDTC); 1481 pdtc &= ~PDTC_MASK; 1482 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1483 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1484 1485 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1486 param->precision, param->factor, param->channels, 1487 param->encoding)); 1488 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1489 ; 1490 if (p == NULL) { 1491 printf("cs4280_trigger_output: bad addr %p\n", start); 1492 return (EINVAL); 1493 } 1494 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1495 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1496 "4kB align\n", DMAADDR(p)); 1497 return (EINVAL); 1498 } 1499 1500 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1501 sc->sc_ps = (char *)start; 1502 sc->sc_pe = (char *)end; 1503 sc->sc_pdma = p; 1504 sc->sc_pbuf = KERNADDR(p); 1505 sc->sc_pi = 0; 1506 sc->sc_pn = sc->sc_ps; 1507 if (blksize >= CS4280_DCHUNK) { 1508 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1509 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1510 ++sc->sc_pi; 1511 } else { 1512 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1513 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1514 } 1515 1516 /* initiate playback dma */ 1517 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1518 1519 /* set PFIE */ 1520 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1521 1522 if (param->precision * param->factor == 8) 1523 pfie |= PFIE_8BIT; 1524 if (param->channels == 1) 1525 pfie |= PFIE_MONO; 1526 1527 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1528 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1529 pfie |= PFIE_SWAPPED; 1530 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1531 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1532 pfie |= PFIE_UNSIGNED; 1533 1534 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1535 1536 cs4280_set_dac_rate(sc, param->sample_rate); 1537 1538 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1539 pctl |= sc->pctl; 1540 BA1WRITE4(sc, CS4280_PCTL, pctl); 1541 return (0); 1542 } 1543 1544 int 1545 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1546 void *addr; 1547 void *start, *end; 1548 int blksize; 1549 void (*intr) __P((void *)); 1550 void *arg; 1551 struct audio_params *param; 1552 { 1553 struct cs4280_softc *sc = addr; 1554 u_int32_t cctl, cie; 1555 struct cs4280_dma *p; 1556 1557 #ifdef DIAGNOSTIC 1558 if (sc->sc_rrun) 1559 printf("cs4280_trigger_input: already running\n"); 1560 sc->sc_rrun = 1; 1561 #endif 1562 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1563 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1564 sc->sc_rintr = intr; 1565 sc->sc_rarg = arg; 1566 1567 sc->sc_ri = 0; 1568 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1569 sc->sc_rs = (char *)start; 1570 sc->sc_re = (char *)end; 1571 sc->sc_rn = sc->sc_rs; 1572 1573 /* setup format information for internal converter */ 1574 sc->sc_rparam = 0; 1575 if (param->precision == 8) { 1576 sc->sc_rparam += CF_8BIT; 1577 sc->sc_rcount <<= 1; 1578 } 1579 if (param->channels == 1) { 1580 sc->sc_rparam += CF_MONO; 1581 sc->sc_rcount <<= 1; 1582 } 1583 1584 /* stop capture DMA */ 1585 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1586 BA1WRITE4(sc, CS4280_CCTL, cctl); 1587 1588 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1589 ; 1590 if (!p) { 1591 printf("cs4280_trigger_input: bad addr %p\n", start); 1592 return (EINVAL); 1593 } 1594 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1595 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1596 "4kB align\n", DMAADDR(p)); 1597 return (EINVAL); 1598 } 1599 sc->sc_rdma = p; 1600 sc->sc_rbuf = KERNADDR(p); 1601 1602 /* initiate capture dma */ 1603 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1604 1605 /* set CIE */ 1606 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1607 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1608 1609 cs4280_set_adc_rate(sc, param->sample_rate); 1610 1611 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1612 cctl |= sc->cctl; 1613 BA1WRITE4(sc, CS4280_CCTL, cctl); 1614 return (0); 1615 } 1616 1617 1618 int 1619 cs4280_init(sc, init) 1620 struct cs4280_softc *sc; 1621 int init; 1622 { 1623 int n; 1624 u_int32_t mem; 1625 1626 /* Start PLL out in known state */ 1627 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1628 /* Start serial ports out in known state */ 1629 BA0WRITE4(sc, CS4280_SERMC1, 0); 1630 1631 /* Specify type of CODEC */ 1632 /* XXX should no be here */ 1633 #define SERACC_CODEC_TYPE_1_03 1634 #ifdef SERACC_CODEC_TYPE_1_03 1635 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1636 #else 1637 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1638 #endif 1639 1640 /* Reset codec */ 1641 BA0WRITE4(sc, CS4280_ACCTL, 0); 1642 delay(100); /* delay 100us */ 1643 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1644 1645 /* Enable AC-link sync generation */ 1646 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1647 delay(50*1000); /* delay 50ms */ 1648 1649 /* Set the serial port timing configuration */ 1650 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1651 1652 /* Setup clock control */ 1653 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1654 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1655 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1656 1657 /* Power up the PLL */ 1658 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1659 delay(50*1000); /* delay 50ms */ 1660 1661 /* Turn on clock */ 1662 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1663 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1664 1665 /* Set the serial port FIFO pointer to the 1666 * first sample in FIFO. (not documented) */ 1667 cs4280_clear_fifos(sc); 1668 1669 #if 0 1670 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1671 BA0WRITE4(sc, CS4280_SERBSP, 0); 1672 #endif 1673 1674 /* Configure the serial port */ 1675 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1676 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1677 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1678 1679 /* Wait for CODEC ready */ 1680 n = 0; 1681 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1682 delay(125); 1683 if (++n > 1000) { 1684 printf("%s: codec ready timeout\n", 1685 sc->sc_dev.dv_xname); 1686 return(1); 1687 } 1688 } 1689 1690 /* Assert valid frame signal */ 1691 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1692 1693 /* Wait for valid AC97 input slot */ 1694 n = 0; 1695 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1696 (ACISV_ISV3 | ACISV_ISV4)) { 1697 delay(1000); 1698 if (++n > 1000) { 1699 printf("AC97 inputs slot ready timeout\n"); 1700 return(1); 1701 } 1702 } 1703 1704 /* Set AC97 output slot valid signals */ 1705 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1706 1707 /* reset the processor */ 1708 cs4280_reset(sc); 1709 1710 /* Download the image to the processor */ 1711 if (cs4280_download_image(sc) != 0) { 1712 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1713 return(1); 1714 } 1715 1716 /* Save playback parameter and then write zero. 1717 * this ensures that DMA doesn't immediately occur upon 1718 * starting the processor core 1719 */ 1720 mem = BA1READ4(sc, CS4280_PCTL); 1721 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1722 cs4280_halt_output(sc); 1723 1724 /* Save capture parameter and then write zero. 1725 * this ensures that DMA doesn't immediately occur upon 1726 * starting the processor core 1727 */ 1728 mem = BA1READ4(sc, CS4280_CCTL); 1729 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1730 cs4280_halt_input(sc); 1731 1732 /* MSH: need to power up ADC and DAC? */ 1733 1734 /* Processor Startup Procedure */ 1735 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1736 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1737 1738 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1739 n = 0; 1740 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1741 delay(10); 1742 if (++n > 1000) { 1743 printf("SPCR 1->0 transition timeout\n"); 1744 return(1); 1745 } 1746 } 1747 1748 n = 0; 1749 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1750 delay(10); 1751 if (++n > 1000) { 1752 printf("SPCS 0->1 transition timeout\n"); 1753 return(1); 1754 } 1755 } 1756 /* Processor is now running !!! */ 1757 1758 /* Setup volume */ 1759 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1760 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1761 1762 /* Interrupt enable */ 1763 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1764 1765 /* playback interrupt enable */ 1766 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1767 mem |= PFIE_PI_ENABLE; 1768 BA1WRITE4(sc, CS4280_PFIE, mem); 1769 /* capture interrupt enable */ 1770 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1771 mem |= CIE_CI_ENABLE; 1772 BA1WRITE4(sc, CS4280_CIE, mem); 1773 1774 #if NMIDI > 0 1775 /* Reset midi port */ 1776 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1777 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1778 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1779 /* midi interrupt enable */ 1780 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1781 BA0WRITE4(sc, CS4280_MIDCR, mem); 1782 #endif 1783 return(0); 1784 } 1785 1786 void 1787 cs4280_power(why, v) 1788 int why; 1789 void *v; 1790 { 1791 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1792 int i; 1793 1794 DPRINTF(("%s: cs4280_power why=%d\n", 1795 sc->sc_dev.dv_xname, why)); 1796 if (why != PWR_RESUME) { 1797 sc->sc_suspend = why; 1798 1799 cs4280_halt_output(sc); 1800 cs4280_halt_input(sc); 1801 /* Save AC97 registers */ 1802 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1803 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1804 continue; 1805 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1806 } 1807 /* should I powerdown here ? */ 1808 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1809 } else { 1810 if (sc->sc_suspend == PWR_RESUME) { 1811 printf("cs4280_power: odd, resume without suspend.\n"); 1812 sc->sc_suspend = why; 1813 return; 1814 } 1815 sc->sc_suspend = why; 1816 cs4280_init(sc, 0); 1817 cs4280_reset_codec(sc); 1818 1819 /* restore ac97 registers */ 1820 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1821 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1822 continue; 1823 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1824 } 1825 } 1826 } 1827 1828 void 1829 cs4280_clear_fifos(sc) 1830 struct cs4280_softc *sc; 1831 { 1832 int pd = 0, cnt, n; 1833 u_int32_t mem; 1834 1835 /* 1836 * If device power down, power up the device and keep power down 1837 * state. 1838 */ 1839 mem = BA0READ4(sc, CS4280_CLKCR1); 1840 if (!(mem & CLKCR1_SWCE)) { 1841 printf("cs4280_clear_fifo: power down found.\n"); 1842 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1843 pd = 1; 1844 } 1845 BA0WRITE4(sc, CS4280_SERBWP, 0); 1846 for (cnt = 0; cnt < 256; cnt++) { 1847 n = 0; 1848 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1849 delay(1000); 1850 if (++n > 1000) { 1851 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1852 break; 1853 } 1854 } 1855 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1856 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1857 } 1858 if (pd) 1859 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1860 } 1861 1862 #if NMIDI > 0 1863 int 1864 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1865 void *addr; 1866 int flags; 1867 void (*iintr)__P((void *, int)); 1868 void (*ointr)__P((void *)); 1869 void *arg; 1870 { 1871 struct cs4280_softc *sc = addr; 1872 u_int32_t mem; 1873 1874 DPRINTF(("midi_open\n")); 1875 sc->sc_iintr = iintr; 1876 sc->sc_ointr = ointr; 1877 sc->sc_arg = arg; 1878 1879 /* midi interrupt enable */ 1880 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1881 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1882 BA0WRITE4(sc, CS4280_MIDCR, mem); 1883 #ifdef CS4280_DEBUG 1884 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1885 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1886 return(EINVAL); 1887 } 1888 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1889 #endif 1890 return (0); 1891 } 1892 1893 void 1894 cs4280_midi_close(addr) 1895 void *addr; 1896 { 1897 struct cs4280_softc *sc = addr; 1898 u_int32_t mem; 1899 1900 DPRINTF(("midi_close\n")); 1901 mem = BA0READ4(sc, CS4280_MIDCR); 1902 mem &= ~MIDCR_MASK; 1903 BA0WRITE4(sc, CS4280_MIDCR, mem); 1904 1905 sc->sc_iintr = 0; 1906 sc->sc_ointr = 0; 1907 } 1908 1909 int 1910 cs4280_midi_output(addr, d) 1911 void *addr; 1912 int d; 1913 { 1914 struct cs4280_softc *sc = addr; 1915 u_int32_t mem; 1916 int x; 1917 1918 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1919 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1920 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1921 mem |= d & MIDWP_MASK; 1922 DPRINTFN(5,("midi_output d=0x%08x",d)); 1923 BA0WRITE4(sc, CS4280_MIDWP, mem); 1924 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1925 DPRINTF(("Bad write data: %d %d", 1926 mem, BA0READ4(sc, CS4280_MIDWP))); 1927 return(EIO); 1928 } 1929 return (0); 1930 } 1931 delay(MIDI_BUSY_DELAY); 1932 } 1933 return (EIO); 1934 } 1935 1936 void 1937 cs4280_midi_getinfo(addr, mi) 1938 void *addr; 1939 struct midi_info *mi; 1940 { 1941 mi->name = "CS4280 MIDI UART"; 1942 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1943 } 1944 1945 #endif 1946