1 /* $OpenBSD: cs4280.c,v 1.33 2009/01/20 20:00:06 grange Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/cs4280reg.h> 78 79 #include <sys/audioio.h> 80 #include <dev/audio_if.h> 81 #include <dev/midi_if.h> 82 #include <dev/mulaw.h> 83 #include <dev/auconv.h> 84 85 #include <dev/ic/ac97.h> 86 87 #include <machine/bus.h> 88 89 #define CSCC_PCI_BA0 0x10 90 #define CSCC_PCI_BA1 0x14 91 92 struct cs4280_dma { 93 bus_dmamap_t map; 94 caddr_t addr; /* real dma buffer */ 95 caddr_t dum; /* dummy buffer for audio driver */ 96 bus_dma_segment_t segs[1]; 97 int nsegs; 98 size_t size; 99 struct cs4280_dma *next; 100 }; 101 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 102 #define BUFADDR(p) ((void *)((p)->dum)) 103 #define KERNADDR(p) ((void *)((p)->addr)) 104 105 /* 106 * Software state 107 */ 108 struct cs4280_softc { 109 struct device sc_dev; 110 111 pci_intr_handle_t * sc_ih; 112 113 /* I/O (BA0) */ 114 bus_space_tag_t ba0t; 115 bus_space_handle_t ba0h; 116 117 /* BA1 */ 118 bus_space_tag_t ba1t; 119 bus_space_handle_t ba1h; 120 121 /* DMA */ 122 bus_dma_tag_t sc_dmatag; 123 struct cs4280_dma *sc_dmas; 124 125 void (*sc_pintr)(void *); /* dma completion intr handler */ 126 void *sc_parg; /* arg for sc_intr() */ 127 char *sc_ps, *sc_pe, *sc_pn; 128 int sc_pcount; 129 int sc_pi; 130 struct cs4280_dma *sc_pdma; 131 char *sc_pbuf; 132 #ifdef DIAGNOSTIC 133 char sc_prun; 134 #endif 135 136 void (*sc_rintr)(void *); /* dma completion intr handler */ 137 void *sc_rarg; /* arg for sc_intr() */ 138 char *sc_rs, *sc_re, *sc_rn; 139 int sc_rcount; 140 int sc_ri; 141 struct cs4280_dma *sc_rdma; 142 char *sc_rbuf; 143 int sc_rparam; /* record format */ 144 #ifdef DIAGNOSTIC 145 char sc_rrun; 146 #endif 147 148 #if NMIDI > 0 149 void (*sc_iintr)(void *, int); /* midi input ready handler */ 150 void (*sc_ointr)(void *); /* midi output ready handler */ 151 void *sc_arg; 152 #endif 153 154 u_int32_t pctl; 155 u_int32_t cctl; 156 157 struct ac97_codec_if *codec_if; 158 struct ac97_host_if host_if; 159 160 char sc_suspend; 161 void *sc_powerhook; /* Power Hook */ 162 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 163 }; 164 165 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 166 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 167 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 168 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 169 170 int cs4280_match(struct device *, void *, void *); 171 void cs4280_attach(struct device *, struct device *, void *); 172 void cs4280_attachhook(void *xsc); 173 int cs4280_intr(void *); 174 void cs4280_reset(void *); 175 int cs4280_download_image(struct cs4280_softc *); 176 177 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 178 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t, 179 struct cs4280_dma *); 180 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *); 181 182 #ifdef CS4280_DEBUG 183 int cs4280_check_images(struct cs4280_softc *); 184 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 185 u_int32_t); 186 #endif 187 188 struct cfdriver clcs_cd = { 189 NULL, "clcs", DV_DULL 190 }; 191 192 struct cfattach clcs_ca = { 193 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 194 }; 195 196 int cs4280_init(struct cs4280_softc *, int); 197 int cs4280_init2(struct cs4280_softc *, int); 198 int cs4280_open(void *, int); 199 void cs4280_close(void *); 200 201 int cs4280_query_encoding(void *, struct audio_encoding *); 202 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 203 int cs4280_round_blocksize(void *, int); 204 void cs4280_get_default_params(void *, int, struct audio_params *); 205 206 int cs4280_halt_output(void *); 207 int cs4280_halt_input(void *); 208 209 int cs4280_getdev(void *, struct audio_device *); 210 211 int cs4280_mixer_set_port(void *, mixer_ctrl_t *); 212 int cs4280_mixer_get_port(void *, mixer_ctrl_t *); 213 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip); 214 void *cs4280_malloc(void *, int, size_t, int, int); 215 void cs4280_free(void *, void *, int); 216 size_t cs4280_round_buffersize(void *, int, size_t); 217 paddr_t cs4280_mappage(void *, void *, off_t, int); 218 int cs4280_get_props(void *); 219 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 220 void *, struct audio_params *); 221 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *); 223 224 225 void cs4280_set_dac_rate(struct cs4280_softc *, int ); 226 void cs4280_set_adc_rate(struct cs4280_softc *, int ); 227 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *, 228 char *); 229 int cs4280_src_wait(struct cs4280_softc *); 230 int cs4280_attach_codec(void *sc, struct ac97_codec_if *); 231 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d); 232 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d); 233 void cs4280_reset_codec(void *sc); 234 235 void cs4280_power(int, void *); 236 237 void cs4280_clear_fifos(struct cs4280_softc *); 238 239 #if NMIDI > 0 240 void cs4280_midi_close(void *); 241 void cs4280_midi_getinfo(void *, struct midi_info *); 242 int cs4280_midi_open(void *, int, void (*)(void *, int), 243 void (*)(void *), void *); 244 int cs4280_midi_output(void *, int); 245 #endif 246 247 struct audio_hw_if cs4280_hw_if = { 248 cs4280_open, 249 cs4280_close, 250 NULL, 251 cs4280_query_encoding, 252 cs4280_set_params, 253 cs4280_round_blocksize, 254 NULL, 255 NULL, 256 NULL, 257 NULL, 258 NULL, 259 cs4280_halt_output, 260 cs4280_halt_input, 261 NULL, 262 cs4280_getdev, 263 NULL, 264 cs4280_mixer_set_port, 265 cs4280_mixer_get_port, 266 cs4280_query_devinfo, 267 cs4280_malloc, 268 cs4280_free, 269 cs4280_round_buffersize, 270 0, /* cs4280_mappage, */ 271 cs4280_get_props, 272 cs4280_trigger_output, 273 cs4280_trigger_input, 274 cs4280_get_default_params 275 }; 276 277 #if NMIDI > 0 278 struct midi_hw_if cs4280_midi_hw_if = { 279 cs4280_midi_open, 280 cs4280_midi_close, 281 cs4280_midi_output, 282 0, /* flush */ 283 cs4280_midi_getinfo, 284 0, /* ioctl */ 285 }; 286 #endif 287 288 289 290 struct audio_device cs4280_device = { 291 "CS4280", 292 "", 293 "cs4280" 294 }; 295 296 const struct pci_matchid cs4280_devices[] = { 297 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, 298 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, 299 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 }, 300 }; 301 302 int 303 cs4280_match(parent, ma, aux) 304 struct device *parent; 305 void *ma; 306 void *aux; 307 { 308 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, 309 sizeof(cs4280_devices)/sizeof(cs4280_devices[0]))); 310 } 311 312 int 313 cs4280_read_codec(sc_, add, data) 314 void *sc_; 315 u_int8_t add; 316 u_int16_t *data; 317 { 318 struct cs4280_softc *sc = sc_; 319 int n; 320 321 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 322 /* 323 * Make sure that there is not data sitting around from a preivous 324 * uncompleted access. 325 */ 326 BA0READ4(sc, CS4280_ACSDA); 327 328 /* Set up AC97 control registers. */ 329 BA0WRITE4(sc, CS4280_ACCAD, add); 330 BA0WRITE4(sc, CS4280_ACCDA, 0); 331 BA0WRITE4(sc, CS4280_ACCTL, 332 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 333 334 if (cs4280_src_wait(sc) < 0) { 335 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 336 sc->sc_dev.dv_xname, add); 337 return (1); 338 } 339 340 /* wait for valid status bit is active */ 341 n = 0; 342 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 343 delay(1); 344 while (++n > 1000) { 345 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 346 sc->sc_dev.dv_xname, add); 347 return (1); 348 } 349 } 350 *data = BA0READ4(sc, CS4280_ACSDA); 351 DPRINTFN(5,("data=0x%04x\n", *data)); 352 return (0); 353 } 354 355 int 356 cs4280_write_codec(sc_, add, data) 357 void *sc_; 358 u_int8_t add; 359 u_int16_t data; 360 { 361 struct cs4280_softc *sc = sc_; 362 363 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 364 BA0WRITE4(sc, CS4280_ACCAD, add); 365 BA0WRITE4(sc, CS4280_ACCDA, data); 366 BA0WRITE4(sc, CS4280_ACCTL, 367 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 368 369 if (cs4280_src_wait(sc) < 0) { 370 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 371 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 372 return (1); 373 } 374 return (0); 375 } 376 377 int 378 cs4280_src_wait(sc) 379 struct cs4280_softc *sc; 380 { 381 int n; 382 383 n = 0; 384 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 385 delay(1000); 386 if (++n > 1000) 387 return (-1); 388 } 389 return (0); 390 } 391 392 393 void 394 cs4280_set_adc_rate(sc, rate) 395 struct cs4280_softc *sc; 396 int rate; 397 { 398 /* calculate capture rate: 399 * 400 * capture_coefficient_increment = -round(rate*128*65536/48000; 401 * capture_phase_increment = floor(48000*65536*1024/rate); 402 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 403 * cy = floor(cx/200); 404 * capture_sample_rate_correction = cx - 200*cy; 405 * capture_delay = ceil(24*48000/rate); 406 * capture_num_triplets = floor(65536*rate/24000); 407 * capture_group_length = 24000/GCD(rate, 24000); 408 * where GCD means "Greatest Common Divisor". 409 * 410 * capture_coefficient_increment, capture_phase_increment and 411 * capture_num_triplets are 32-bit signed quantities. 412 * capture_sample_rate_correction and capture_group_length are 413 * 16-bit signed quantities. 414 * capture_delay is a 14-bit unsigned quantity. 415 */ 416 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 417 u_int16_t csrc, cgl, cdlay; 418 419 /* XXX 420 * Even though, embedded_audio_spec says capture rate range 11025 to 421 * 48000, dhwiface.cpp says, 422 * 423 * "We can only decimate by up to a factor of 1/9th the hardware rate. 424 * Return an error if an attempt is made to stray outside that limit." 425 * 426 * so assume range as 48000/9 to 48000 427 */ 428 429 if (rate < 8000) 430 rate = 8000; 431 if (rate > 48000) 432 rate = 48000; 433 434 cx = rate << 16; 435 cci = cx / 48000; 436 cx -= cci * 48000; 437 cx <<= 7; 438 cci <<= 7; 439 cci += cx / 48000; 440 cci = - cci; 441 442 cx = 48000 << 16; 443 cpi = cx / rate; 444 cx -= cpi * rate; 445 cx <<= 10; 446 cpi <<= 10; 447 cy = cx / rate; 448 cpi += cy; 449 cx -= cy * rate; 450 451 cy = cx / 200; 452 csrc = cx - 200*cy; 453 454 cdlay = ((48000 * 24) + rate - 1) / rate; 455 #if 0 456 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 457 #endif 458 459 cnt = rate << 16; 460 cnt /= 24000; 461 462 cgl = 1; 463 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 464 if (((rate / tmp1) * tmp1) != rate) 465 cgl *= 2; 466 } 467 if (((rate / 3) * 3) != rate) 468 cgl *= 3; 469 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 470 if (((rate / tmp1) * tmp1) != rate) 471 cgl *= 5; 472 } 473 #if 0 474 /* XXX what manual says */ 475 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 476 tmp1 |= csrc<<16; 477 BA1WRITE4(sc, CS4280_CSRC, tmp1); 478 #else 479 /* suggested by cs461x.c (ALSA driver) */ 480 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 481 #endif 482 483 #if 0 484 /* I am confused. The sample rate calculation section says 485 * cci *is* 32-bit signed quantity but in the parameter description 486 * section, CCI only assigned 16bit. 487 * I believe size of the variable. 488 */ 489 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 490 tmp1 |= cci<<16; 491 BA1WRITE4(sc, CS4280_CCI, tmp1); 492 #else 493 BA1WRITE4(sc, CS4280_CCI, cci); 494 #endif 495 496 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 497 tmp1 |= cdlay <<18; 498 BA1WRITE4(sc, CS4280_CD, tmp1); 499 500 BA1WRITE4(sc, CS4280_CPI, cpi); 501 502 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 503 tmp1 |= cgl; 504 BA1WRITE4(sc, CS4280_CGL, tmp1); 505 506 BA1WRITE4(sc, CS4280_CNT, cnt); 507 508 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 509 tmp1 |= cgl; 510 BA1WRITE4(sc, CS4280_CGC, tmp1); 511 } 512 513 void 514 cs4280_set_dac_rate(sc, rate) 515 struct cs4280_softc *sc; 516 int rate; 517 { 518 /* 519 * playback rate may range from 8000Hz to 48000Hz 520 * 521 * play_phase_increment = floor(rate*65536*1024/48000) 522 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 523 * py=floor(px/200) 524 * play_sample_rate_correction = px - 200*py 525 * 526 * play_phase_increment is a 32bit signed quantity. 527 * play_sample_rate_correction is a 16bit signed quantity. 528 */ 529 int32_t ppi; 530 int16_t psrc; 531 u_int32_t px, py; 532 533 if (rate < 8000) 534 rate = 8000; 535 if (rate > 48000) 536 rate = 48000; 537 px = rate << 16; 538 ppi = px/48000; 539 px -= ppi*48000; 540 ppi <<= 10; 541 px <<= 10; 542 py = px / 48000; 543 ppi += py; 544 px -= py*48000; 545 py = px/200; 546 px -= py*200; 547 psrc = px; 548 #if 0 549 /* what manual says */ 550 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 551 BA1WRITE4(sc, CS4280_PSRC, 552 ( ((psrc<<16) & PSRC_MASK) | px )); 553 #else 554 /* suggested by cs461x.c (ALSA driver) */ 555 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 556 #endif 557 BA1WRITE4(sc, CS4280_PPI, ppi); 558 } 559 560 void 561 cs4280_attachhook(void *xsc) 562 { 563 struct cs4280_softc *sc = xsc; 564 mixer_ctrl_t ctl; 565 566 /* Initialization */ 567 if (cs4280_init2(sc, 1) != 0) 568 return; 569 570 printf("%s: firmware loaded\n", sc->sc_dev.dv_xname); 571 572 /* Turn mute off of DAC, CD and master volumes by default */ 573 ctl.type = AUDIO_MIXER_ENUM; 574 ctl.un.ord = 0; /* off */ 575 576 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 577 AudioNmaster, AudioNmute); 578 cs4280_mixer_set_port(sc, &ctl); 579 580 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 581 AudioNdac, AudioNmute); 582 cs4280_mixer_set_port(sc, &ctl); 583 584 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 585 AudioNcd, AudioNmute); 586 cs4280_mixer_set_port(sc, &ctl); 587 588 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 589 590 #if NMIDI > 0 591 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 592 #endif 593 sc->sc_suspend = PWR_RESUME; 594 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 595 } 596 597 void 598 cs4280_attach(parent, self, aux) 599 struct device *parent; 600 struct device *self; 601 void *aux; 602 { 603 struct cs4280_softc *sc = (struct cs4280_softc *) self; 604 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 605 pci_chipset_tag_t pc = pa->pa_pc; 606 char const *intrstr; 607 pci_intr_handle_t ih; 608 u_int32_t mem; 609 610 /* Map I/O register */ 611 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 612 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 613 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 614 printf(": can't map BA0 space\n"); 615 return; 616 } 617 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 618 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 619 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 620 printf(": can't map BA1 space\n"); 621 return; 622 } 623 624 sc->sc_dmatag = pa->pa_dmat; 625 626 /* Get out of power save mode if needed. */ 627 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 628 629 /* LATENCY_TIMER setting */ 630 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 631 if ( PCI_LATTIMER(mem) < 32 ) { 632 mem &= 0xffff00ff; 633 mem |= 0x00002000; 634 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 635 } 636 637 /* Map and establish the interrupt. */ 638 if (pci_intr_map(pa, &ih)) { 639 printf(": couldn't map interrupt\n"); 640 return; 641 } 642 intrstr = pci_intr_string(pc, ih); 643 644 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc, 645 sc->sc_dev.dv_xname); 646 if (sc->sc_ih == NULL) { 647 printf(": couldn't establish interrupt"); 648 if (intrstr != NULL) 649 printf(" at %s", intrstr); 650 printf("\n"); 651 return; 652 } 653 printf(": %s\n", intrstr); 654 655 /* Initialization */ 656 if (cs4280_init(sc, 1) != 0) 657 return; 658 659 mountroothook_establish(cs4280_attachhook, sc); 660 661 /* AC 97 attachement */ 662 sc->host_if.arg = sc; 663 sc->host_if.attach = cs4280_attach_codec; 664 sc->host_if.read = cs4280_read_codec; 665 sc->host_if.write = cs4280_write_codec; 666 sc->host_if.reset = cs4280_reset_codec; 667 668 if (ac97_attach(&sc->host_if) != 0) { 669 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 670 return; 671 } 672 } 673 674 int 675 cs4280_intr(p) 676 void *p; 677 { 678 /* 679 * XXX 680 * 681 * Since CS4280 has only 4kB dma buffer and 682 * interrupt occurs every 2kB block, I create dummy buffer 683 * which returns to audio driver and actual dma buffer 684 * using in DMA transfer. 685 * 686 * 687 * ring buffer in audio.c is pointed by BUFADDR 688 * <------ ring buffer size == 64kB ------> 689 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 690 * |= = = =|= = = =|= = = =|= = = =|= = = =| 691 * | | | | | | <- call audio_intp every 692 * sc->sc_[pr]_count time. 693 * 694 * actual dma buffer is pointed by KERNADDR 695 * <-> dma buffer size = 4kB 696 * |= =| 697 * 698 * 699 */ 700 struct cs4280_softc *sc = p; 701 u_int32_t intr, mem; 702 char * empty_dma; 703 int handled = 0; 704 705 /* grab interrupt register then clear it */ 706 intr = BA0READ4(sc, CS4280_HISR); 707 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 708 709 /* Playback Interrupt */ 710 if (intr & HISR_PINT) { 711 handled = 1; 712 mem = BA1READ4(sc, CS4280_PFIE); 713 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 714 if (sc->sc_pintr) { 715 if ((sc->sc_pi%sc->sc_pcount) == 0) 716 sc->sc_pintr(sc->sc_parg); 717 } else { 718 printf("unexpected play intr\n"); 719 } 720 /* copy buffer */ 721 ++sc->sc_pi; 722 empty_dma = sc->sc_pdma->addr; 723 if (sc->sc_pi&1) 724 empty_dma += CS4280_ICHUNK; 725 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 726 sc->sc_pn += CS4280_ICHUNK; 727 if (sc->sc_pn >= sc->sc_pe) 728 sc->sc_pn = sc->sc_ps; 729 BA1WRITE4(sc, CS4280_PFIE, mem); 730 } 731 /* Capture Interrupt */ 732 if (intr & HISR_CINT) { 733 int i; 734 int16_t rdata; 735 736 handled = 1; 737 mem = BA1READ4(sc, CS4280_CIE); 738 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 739 ++sc->sc_ri; 740 empty_dma = sc->sc_rdma->addr; 741 if ((sc->sc_ri&1) == 0) 742 empty_dma += CS4280_ICHUNK; 743 744 /* 745 * XXX 746 * I think this audio data conversion should be 747 * happend in upper layer, but I put this here 748 * since there is no conversion function available. 749 */ 750 switch(sc->sc_rparam) { 751 case CF_16BIT_STEREO: 752 /* just copy it */ 753 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 754 sc->sc_rn += CS4280_ICHUNK; 755 break; 756 case CF_16BIT_MONO: 757 for (i = 0; i < 512; i++) { 758 rdata = *((int16_t *)empty_dma)>>1; 759 empty_dma += 2; 760 rdata += *((int16_t *)empty_dma)>>1; 761 empty_dma += 2; 762 *((int16_t *)sc->sc_rn) = rdata; 763 sc->sc_rn += 2; 764 } 765 break; 766 case CF_8BIT_STEREO: 767 for (i = 0; i < 512; i++) { 768 rdata = *((int16_t*)empty_dma); 769 empty_dma += 2; 770 *sc->sc_rn++ = rdata >> 8; 771 rdata = *((int16_t*)empty_dma); 772 empty_dma += 2; 773 *sc->sc_rn++ = rdata >> 8; 774 } 775 break; 776 case CF_8BIT_MONO: 777 for (i = 0; i < 512; i++) { 778 rdata = *((int16_t*)empty_dma) >>1; 779 empty_dma += 2; 780 rdata += *((int16_t*)empty_dma) >>1; 781 empty_dma += 2; 782 *sc->sc_rn++ = rdata >>8; 783 } 784 break; 785 default: 786 /* Should not reach here */ 787 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 788 } 789 if (sc->sc_rn >= sc->sc_re) 790 sc->sc_rn = sc->sc_rs; 791 BA1WRITE4(sc, CS4280_CIE, mem); 792 if (sc->sc_rintr) { 793 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 794 sc->sc_rintr(sc->sc_rarg); 795 } else { 796 printf("unexpected record intr\n"); 797 } 798 } 799 800 #if NMIDI > 0 801 /* Midi port Interrupt */ 802 if (intr & HISR_MIDI) { 803 int data; 804 805 handled = 1; 806 DPRINTF(("i: %d: ", 807 BA0READ4(sc, CS4280_MIDSR))); 808 /* Read the received data */ 809 while ((sc->sc_iintr != NULL) && 810 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 811 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 812 DPRINTF(("r:%x\n",data)); 813 sc->sc_iintr(sc->sc_arg, data); 814 } 815 816 /* Write the data */ 817 #if 1 818 /* XXX: 819 * It seems "Transmit Buffer Full" never activate until EOI 820 * is delivered. Shall I throw EOI top of this routine ? 821 */ 822 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 823 DPRINTF(("w: ")); 824 if (sc->sc_ointr != NULL) 825 sc->sc_ointr(sc->sc_arg); 826 } 827 #else 828 while ((sc->sc_ointr != NULL) && 829 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 830 DPRINTF(("w: ")); 831 sc->sc_ointr(sc->sc_arg); 832 } 833 #endif 834 DPRINTF(("\n")); 835 } 836 #endif 837 838 return handled; 839 } 840 841 842 /* Download Proceessor Code and Data image */ 843 844 int 845 cs4280_download(sc, src, offset, len) 846 struct cs4280_softc *sc; 847 const u_int32_t *src; 848 u_int32_t offset, len; 849 { 850 u_int32_t ctr; 851 852 #ifdef CS4280_DEBUG 853 u_int32_t con, data; 854 u_int8_t c0,c1,c2,c3; 855 #endif 856 if ((offset&3) || (len&3)) 857 return (-1); 858 859 len /= sizeof(u_int32_t); 860 for (ctr = 0; ctr < len; ctr++) { 861 /* XXX: 862 * I cannot confirm this is the right thing or not 863 * on BIG-ENDIAN machines. 864 */ 865 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 866 #ifdef CS4280_DEBUG 867 data = htole32(*(src+ctr)); 868 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 869 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 870 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 871 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 872 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 873 if (data != con ) { 874 printf("0x%06x: write=0x%08x read=0x%08x\n", 875 offset+ctr*4, data, con); 876 return (-1); 877 } 878 #endif 879 } 880 return (0); 881 } 882 883 struct BA1struct *BA1Struct; 884 885 int 886 cs4280_download_image(sc) 887 struct cs4280_softc *sc; 888 { 889 int idx, err = 0; 890 u_int32_t offset = 0; 891 static u_char *cs4280_firmware; 892 static size_t cs4280_firmwarelen; 893 894 if (cs4280_firmware == NULL) { 895 err = loadfirmware("cs4280", &cs4280_firmware, 896 &cs4280_firmwarelen); 897 if (err) 898 return (err); 899 } 900 901 BA1Struct = (struct BA1struct *)cs4280_firmware; 902 903 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 904 err = cs4280_download(sc, &BA1Struct->map[offset], 905 BA1Struct->memory[idx].offset, BA1Struct->memory[idx].size); 906 if (err != 0) { 907 printf("%s: load_image failed at %d\n", 908 sc->sc_dev.dv_xname, idx); 909 return (-1); 910 } 911 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 912 } 913 return (err); 914 } 915 916 #ifdef CS4280_DEBUG 917 int 918 cs4280_checkimage(sc, src, offset, len) 919 struct cs4280_softc *sc; 920 u_int32_t *src; 921 u_int32_t offset, len; 922 { 923 u_int32_t ctr, data; 924 int err = 0; 925 926 if ((offset&3) || (len&3)) 927 return -1; 928 929 len /= sizeof(u_int32_t); 930 for (ctr = 0; ctr < len; ctr++) { 931 /* I cannot confirm this is the right thing 932 * on BIG-ENDIAN machines 933 */ 934 data = BA1READ4(sc, offset+ctr*4); 935 if (data != htole32(*(src+ctr))) { 936 printf("0x%06x: 0x%08x(0x%08x)\n", 937 offset+ctr*4, data, *(src+ctr)); 938 *(src+ctr) = data; 939 ++err; 940 } 941 } 942 return (err); 943 } 944 945 int 946 cs4280_check_images(sc) 947 struct cs4280_softc *sc; 948 { 949 int idx, err; 950 u_int32_t offset = 0; 951 952 err = 0; 953 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 954 for (idx = 0; idx < 1; ++idx) { 955 err = cs4280_checkimage(sc, &BA1Struct->map[offset], 956 BA1Struct->memory[idx].offset, 957 BA1Struct->memory[idx].size); 958 if (err != 0) { 959 printf("%s: check_image failed at %d\n", 960 sc->sc_dev.dv_xname, idx); 961 } 962 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 963 } 964 return (err); 965 } 966 967 #endif 968 969 int 970 cs4280_attach_codec(sc_, codec_if) 971 void *sc_; 972 struct ac97_codec_if *codec_if; 973 { 974 struct cs4280_softc *sc = sc_; 975 976 sc->codec_if = codec_if; 977 return (0); 978 } 979 980 void 981 cs4280_reset_codec(sc_) 982 void *sc_; 983 { 984 struct cs4280_softc *sc = sc_; 985 int n; 986 987 /* Reset codec */ 988 BA0WRITE4(sc, CS4280_ACCTL, 0); 989 delay(100); /* delay 100us */ 990 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 991 992 /* 993 * It looks like we do the following procedure, too 994 */ 995 996 /* Enable AC-link sync generation */ 997 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 998 delay(50*1000); /* XXX delay 50ms */ 999 1000 /* Assert valid frame signal */ 1001 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1002 1003 /* Wait for valid AC97 input slot */ 1004 n = 0; 1005 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 1006 delay(1000); 1007 if (++n > 1000) { 1008 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1009 return; 1010 } 1011 } 1012 } 1013 1014 1015 /* Processor Soft Reset */ 1016 void 1017 cs4280_reset(sc_) 1018 void *sc_; 1019 { 1020 struct cs4280_softc *sc = sc_; 1021 1022 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1023 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1024 delay(100); 1025 /* Clear RSTSP bit in SPCR */ 1026 BA1WRITE4(sc, CS4280_SPCR, 0); 1027 /* enable DMA reqest */ 1028 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1029 } 1030 1031 int 1032 cs4280_open(addr, flags) 1033 void *addr; 1034 int flags; 1035 { 1036 return (0); 1037 } 1038 1039 void 1040 cs4280_close(addr) 1041 void *addr; 1042 { 1043 struct cs4280_softc *sc = addr; 1044 1045 cs4280_halt_output(sc); 1046 cs4280_halt_input(sc); 1047 1048 sc->sc_pintr = 0; 1049 sc->sc_rintr = 0; 1050 } 1051 1052 int 1053 cs4280_query_encoding(addr, fp) 1054 void *addr; 1055 struct audio_encoding *fp; 1056 { 1057 switch (fp->index) { 1058 case 0: 1059 strlcpy(fp->name, AudioEulinear, sizeof fp->name); 1060 fp->encoding = AUDIO_ENCODING_ULINEAR; 1061 fp->precision = 8; 1062 fp->flags = 0; 1063 break; 1064 case 1: 1065 strlcpy(fp->name, AudioEmulaw, sizeof fp->name); 1066 fp->encoding = AUDIO_ENCODING_ULAW; 1067 fp->precision = 8; 1068 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1069 break; 1070 case 2: 1071 strlcpy(fp->name, AudioEalaw, sizeof fp->name); 1072 fp->encoding = AUDIO_ENCODING_ALAW; 1073 fp->precision = 8; 1074 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1075 break; 1076 case 3: 1077 strlcpy(fp->name, AudioEslinear, sizeof fp->name); 1078 fp->encoding = AUDIO_ENCODING_SLINEAR; 1079 fp->precision = 8; 1080 fp->flags = 0; 1081 break; 1082 case 4: 1083 strlcpy(fp->name, AudioEslinear_le, sizeof fp->name); 1084 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1085 fp->precision = 16; 1086 fp->flags = 0; 1087 break; 1088 case 5: 1089 strlcpy(fp->name, AudioEulinear_le, sizeof fp->name); 1090 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1091 fp->precision = 16; 1092 fp->flags = 0; 1093 break; 1094 case 6: 1095 strlcpy(fp->name, AudioEslinear_be, sizeof fp->name); 1096 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1097 fp->precision = 16; 1098 fp->flags = 0; 1099 break; 1100 case 7: 1101 strlcpy(fp->name, AudioEulinear_be, sizeof fp->name); 1102 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1103 fp->precision = 16; 1104 fp->flags = 0; 1105 break; 1106 default: 1107 return (EINVAL); 1108 } 1109 return (0); 1110 } 1111 1112 int 1113 cs4280_set_params(addr, setmode, usemode, play, rec) 1114 void *addr; 1115 int setmode, usemode; 1116 struct audio_params *play, *rec; 1117 { 1118 struct cs4280_softc *sc = addr; 1119 struct audio_params *p; 1120 int mode; 1121 1122 for (mode = AUMODE_RECORD; mode != -1; 1123 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1124 if ((setmode & mode) == 0) 1125 continue; 1126 1127 p = mode == AUMODE_PLAY ? play : rec; 1128 if (p == play) { 1129 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1130 p->sample_rate, p->precision, p->channels)); 1131 } else { 1132 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1133 p->sample_rate, p->precision, p->channels)); 1134 } 1135 /* play back data format may be 8- or 16-bit and 1136 * either stereo or mono. 1137 * playback rate may range from 8000Hz to 48000Hz 1138 * 1139 * capture data format must be 16bit stereo 1140 * and sample rate range from 11025Hz to 48000Hz. 1141 * 1142 * XXX: it looks like to work with 8000Hz, 1143 * although data sheets say lower limit is 1144 * 11025 Hz. 1145 */ 1146 if (p->sample_rate < 8000) 1147 p->sample_rate = 8000; 1148 if (p->sample_rate > 48000) 1149 p->sample_rate = 48000; 1150 if (p->precision > 16) 1151 p->precision = 16; 1152 if (p->channels > 2) 1153 p->channels = 2; 1154 p->factor = 1; 1155 p->sw_code = 0; 1156 1157 /* capturing data is slinear */ 1158 switch (p->encoding) { 1159 case AUDIO_ENCODING_SLINEAR_BE: 1160 if (mode == AUMODE_RECORD) { 1161 if (p->precision == 16) 1162 p->sw_code = swap_bytes; 1163 } 1164 break; 1165 case AUDIO_ENCODING_SLINEAR_LE: 1166 break; 1167 case AUDIO_ENCODING_ULINEAR_BE: 1168 if (mode == AUMODE_RECORD) { 1169 if (p->precision == 16) 1170 p->sw_code = change_sign16_swap_bytes_le; 1171 else 1172 p->sw_code = change_sign8; 1173 } 1174 break; 1175 case AUDIO_ENCODING_ULINEAR_LE: 1176 if (mode == AUMODE_RECORD) { 1177 if (p->precision == 16) 1178 p->sw_code = change_sign16_le; 1179 else 1180 p->sw_code = change_sign8; 1181 } 1182 break; 1183 case AUDIO_ENCODING_ULAW: 1184 if (mode == AUMODE_PLAY) { 1185 p->factor = 2; 1186 p->sw_code = mulaw_to_slinear16_le; 1187 } else { 1188 p->sw_code = slinear8_to_mulaw; 1189 } 1190 break; 1191 case AUDIO_ENCODING_ALAW: 1192 if (mode == AUMODE_PLAY) { 1193 p->factor = 2; 1194 p->sw_code = alaw_to_slinear16_le; 1195 } else { 1196 p->sw_code = slinear8_to_alaw; 1197 } 1198 break; 1199 default: 1200 return (EINVAL); 1201 } 1202 } 1203 1204 /* set sample rate */ 1205 cs4280_set_dac_rate(sc, play->sample_rate); 1206 cs4280_set_adc_rate(sc, rec->sample_rate); 1207 return (0); 1208 } 1209 1210 int 1211 cs4280_round_blocksize(hdl, blk) 1212 void *hdl; 1213 int blk; 1214 { 1215 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1216 } 1217 1218 size_t 1219 cs4280_round_buffersize(addr, direction, size) 1220 void *addr; 1221 int direction; 1222 size_t size; 1223 { 1224 /* although real dma buffer size is 4KB, 1225 * let the audio.c driver use a larger buffer. 1226 * ( suggested by Lennart Augustsson. ) 1227 */ 1228 return (size); 1229 } 1230 1231 void 1232 cs4280_get_default_params(void *addr, int mode, struct audio_params *params) 1233 { 1234 ac97_get_default_params(params); 1235 } 1236 1237 int 1238 cs4280_get_props(hdl) 1239 void *hdl; 1240 { 1241 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1242 #ifdef notyet 1243 /* XXX 1244 * How can I mmap ? 1245 */ 1246 AUDIO_PROP_MMAP 1247 #endif 1248 1249 } 1250 1251 int 1252 cs4280_mixer_get_port(addr, cp) 1253 void *addr; 1254 mixer_ctrl_t *cp; 1255 { 1256 struct cs4280_softc *sc = addr; 1257 1258 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1259 } 1260 1261 paddr_t 1262 cs4280_mappage(addr, mem, off, prot) 1263 void *addr; 1264 void *mem; 1265 off_t off; 1266 int prot; 1267 { 1268 struct cs4280_softc *sc = addr; 1269 struct cs4280_dma *p; 1270 1271 if (off < 0) 1272 return (-1); 1273 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1274 ; 1275 if (!p) { 1276 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1277 return (-1); 1278 } 1279 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1280 off, prot, BUS_DMA_WAITOK)); 1281 } 1282 1283 1284 int 1285 cs4280_query_devinfo(addr, dip) 1286 void *addr; 1287 mixer_devinfo_t *dip; 1288 { 1289 struct cs4280_softc *sc = addr; 1290 1291 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1292 } 1293 1294 int 1295 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1296 struct cs4280_softc *sc; 1297 char *class, *device, *qualifier; 1298 { 1299 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1300 device, qualifier)); 1301 } 1302 1303 int 1304 cs4280_halt_output(addr) 1305 void *addr; 1306 { 1307 struct cs4280_softc *sc = addr; 1308 u_int32_t mem; 1309 1310 mem = BA1READ4(sc, CS4280_PCTL); 1311 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1312 #ifdef DIAGNOSTIC 1313 sc->sc_prun = 0; 1314 #endif 1315 return (0); 1316 } 1317 1318 int 1319 cs4280_halt_input(addr) 1320 void *addr; 1321 { 1322 struct cs4280_softc *sc = addr; 1323 u_int32_t mem; 1324 1325 mem = BA1READ4(sc, CS4280_CCTL); 1326 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1327 #ifdef DIAGNOSTIC 1328 sc->sc_rrun = 0; 1329 #endif 1330 return (0); 1331 } 1332 1333 int 1334 cs4280_getdev(addr, retp) 1335 void *addr; 1336 struct audio_device *retp; 1337 { 1338 *retp = cs4280_device; 1339 return (0); 1340 } 1341 1342 int 1343 cs4280_mixer_set_port(addr, cp) 1344 void *addr; 1345 mixer_ctrl_t *cp; 1346 { 1347 struct cs4280_softc *sc = addr; 1348 int val; 1349 1350 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1351 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1352 return (val); 1353 } 1354 1355 1356 int 1357 cs4280_freemem(sc, p) 1358 struct cs4280_softc *sc; 1359 struct cs4280_dma *p; 1360 { 1361 bus_dmamap_unload(sc->sc_dmatag, p->map); 1362 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1363 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1364 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1365 return (0); 1366 } 1367 1368 int 1369 cs4280_allocmem(sc, size, align, p) 1370 struct cs4280_softc *sc; 1371 size_t size; 1372 size_t align; 1373 struct cs4280_dma *p; 1374 { 1375 int error; 1376 1377 /* XXX */ 1378 p->size = size; 1379 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1380 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1381 &p->nsegs, BUS_DMA_NOWAIT); 1382 if (error) { 1383 printf("%s: unable to allocate dma, error=%d\n", 1384 sc->sc_dev.dv_xname, error); 1385 return (error); 1386 } 1387 1388 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1389 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1390 if (error) { 1391 printf("%s: unable to map dma, error=%d\n", 1392 sc->sc_dev.dv_xname, error); 1393 goto free; 1394 } 1395 1396 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1397 0, BUS_DMA_NOWAIT, &p->map); 1398 if (error) { 1399 printf("%s: unable to create dma map, error=%d\n", 1400 sc->sc_dev.dv_xname, error); 1401 goto unmap; 1402 } 1403 1404 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1405 BUS_DMA_NOWAIT); 1406 if (error) { 1407 printf("%s: unable to load dma map, error=%d\n", 1408 sc->sc_dev.dv_xname, error); 1409 goto destroy; 1410 } 1411 return (0); 1412 1413 destroy: 1414 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1415 unmap: 1416 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1417 free: 1418 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1419 return (error); 1420 } 1421 1422 1423 void * 1424 cs4280_malloc(addr, direction, size, pool, flags) 1425 void *addr; 1426 int direction; 1427 size_t size; 1428 int pool, flags; 1429 { 1430 struct cs4280_softc *sc = addr; 1431 struct cs4280_dma *p; 1432 caddr_t q; 1433 int error; 1434 1435 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1436 q = malloc(size, pool, flags); 1437 if (!q) 1438 return (0); 1439 p = malloc(sizeof(*p), pool, flags); 1440 if (!p) { 1441 free(q,pool); 1442 return (0); 1443 } 1444 /* 1445 * cs4280 has fixed 4kB buffer 1446 */ 1447 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1448 1449 if (error) { 1450 free(q, pool); 1451 free(p, pool); 1452 return (0); 1453 } 1454 1455 p->next = sc->sc_dmas; 1456 sc->sc_dmas = p; 1457 p->dum = q; /* return to audio driver */ 1458 1459 return (p->dum); 1460 } 1461 1462 void 1463 cs4280_free(addr, ptr, pool) 1464 void *addr; 1465 void *ptr; 1466 int pool; 1467 { 1468 struct cs4280_softc *sc = addr; 1469 struct cs4280_dma **pp, *p; 1470 1471 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1472 if (BUFADDR(p) == ptr) { 1473 cs4280_freemem(sc, p); 1474 *pp = p->next; 1475 free(p->dum, pool); 1476 free(p, pool); 1477 return; 1478 } 1479 } 1480 } 1481 1482 int 1483 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1484 void *addr; 1485 void *start, *end; 1486 int blksize; 1487 void (*intr)(void *); 1488 void *arg; 1489 struct audio_params *param; 1490 { 1491 struct cs4280_softc *sc = addr; 1492 u_int32_t pfie, pctl, mem, pdtc; 1493 struct cs4280_dma *p; 1494 1495 #ifdef DIAGNOSTIC 1496 if (sc->sc_prun) 1497 printf("cs4280_trigger_output: already running\n"); 1498 sc->sc_prun = 1; 1499 #endif 1500 1501 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1502 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1503 sc->sc_pintr = intr; 1504 sc->sc_parg = arg; 1505 1506 /* stop playback DMA */ 1507 mem = BA1READ4(sc, CS4280_PCTL); 1508 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1509 1510 /* setup PDTC */ 1511 pdtc = BA1READ4(sc, CS4280_PDTC); 1512 pdtc &= ~PDTC_MASK; 1513 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1514 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1515 1516 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1517 param->precision, param->factor, param->channels, 1518 param->encoding)); 1519 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1520 ; 1521 if (p == NULL) { 1522 printf("cs4280_trigger_output: bad addr %p\n", start); 1523 return (EINVAL); 1524 } 1525 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1526 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1527 "4kB align\n", DMAADDR(p)); 1528 return (EINVAL); 1529 } 1530 1531 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1532 sc->sc_ps = (char *)start; 1533 sc->sc_pe = (char *)end; 1534 sc->sc_pdma = p; 1535 sc->sc_pbuf = KERNADDR(p); 1536 sc->sc_pi = 0; 1537 sc->sc_pn = sc->sc_ps; 1538 if (blksize >= CS4280_DCHUNK) { 1539 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1540 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1541 ++sc->sc_pi; 1542 } else { 1543 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1544 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1545 } 1546 1547 /* initiate playback dma */ 1548 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1549 1550 /* set PFIE */ 1551 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1552 1553 if (param->precision * param->factor == 8) 1554 pfie |= PFIE_8BIT; 1555 if (param->channels == 1) 1556 pfie |= PFIE_MONO; 1557 1558 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1559 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1560 pfie |= PFIE_SWAPPED; 1561 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1562 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1563 pfie |= PFIE_UNSIGNED; 1564 1565 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1566 1567 cs4280_set_dac_rate(sc, param->sample_rate); 1568 1569 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1570 pctl |= sc->pctl; 1571 BA1WRITE4(sc, CS4280_PCTL, pctl); 1572 return (0); 1573 } 1574 1575 int 1576 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1577 void *addr; 1578 void *start, *end; 1579 int blksize; 1580 void (*intr)(void *); 1581 void *arg; 1582 struct audio_params *param; 1583 { 1584 struct cs4280_softc *sc = addr; 1585 u_int32_t cctl, cie; 1586 struct cs4280_dma *p; 1587 1588 #ifdef DIAGNOSTIC 1589 if (sc->sc_rrun) 1590 printf("cs4280_trigger_input: already running\n"); 1591 sc->sc_rrun = 1; 1592 #endif 1593 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1594 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1595 sc->sc_rintr = intr; 1596 sc->sc_rarg = arg; 1597 1598 sc->sc_ri = 0; 1599 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1600 sc->sc_rs = (char *)start; 1601 sc->sc_re = (char *)end; 1602 sc->sc_rn = sc->sc_rs; 1603 1604 /* setup format information for internal converter */ 1605 sc->sc_rparam = 0; 1606 if (param->precision == 8) { 1607 sc->sc_rparam += CF_8BIT; 1608 sc->sc_rcount <<= 1; 1609 } 1610 if (param->channels == 1) { 1611 sc->sc_rparam += CF_MONO; 1612 sc->sc_rcount <<= 1; 1613 } 1614 1615 /* stop capture DMA */ 1616 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1617 BA1WRITE4(sc, CS4280_CCTL, cctl); 1618 1619 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1620 ; 1621 if (!p) { 1622 printf("cs4280_trigger_input: bad addr %p\n", start); 1623 return (EINVAL); 1624 } 1625 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1626 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1627 "4kB align\n", DMAADDR(p)); 1628 return (EINVAL); 1629 } 1630 sc->sc_rdma = p; 1631 sc->sc_rbuf = KERNADDR(p); 1632 1633 /* initiate capture dma */ 1634 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1635 1636 /* set CIE */ 1637 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1638 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1639 1640 cs4280_set_adc_rate(sc, param->sample_rate); 1641 1642 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1643 cctl |= sc->cctl; 1644 BA1WRITE4(sc, CS4280_CCTL, cctl); 1645 return (0); 1646 } 1647 1648 1649 int 1650 cs4280_init(sc, init) 1651 struct cs4280_softc *sc; 1652 int init; 1653 { 1654 int n; 1655 u_int32_t mem; 1656 1657 /* Start PLL out in known state */ 1658 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1659 /* Start serial ports out in known state */ 1660 BA0WRITE4(sc, CS4280_SERMC1, 0); 1661 1662 /* Specify type of CODEC */ 1663 /* XXX should no be here */ 1664 #define SERACC_CODEC_TYPE_1_03 1665 #ifdef SERACC_CODEC_TYPE_1_03 1666 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1667 #else 1668 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1669 #endif 1670 1671 /* Reset codec */ 1672 BA0WRITE4(sc, CS4280_ACCTL, 0); 1673 delay(100); /* delay 100us */ 1674 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1675 1676 /* Enable AC-link sync generation */ 1677 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1678 delay(50*1000); /* delay 50ms */ 1679 1680 /* Set the serial port timing configuration */ 1681 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1682 1683 /* Setup clock control */ 1684 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1685 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1686 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1687 1688 /* Power up the PLL */ 1689 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1690 delay(50*1000); /* delay 50ms */ 1691 1692 /* Turn on clock */ 1693 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1694 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1695 1696 /* Set the serial port FIFO pointer to the 1697 * first sample in FIFO. (not documented) */ 1698 cs4280_clear_fifos(sc); 1699 1700 #if 0 1701 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1702 BA0WRITE4(sc, CS4280_SERBSP, 0); 1703 #endif 1704 1705 /* Configure the serial port */ 1706 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1707 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1708 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1709 1710 /* Wait for CODEC ready */ 1711 n = 0; 1712 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1713 delay(125); 1714 if (++n > 1000) { 1715 printf("%s: codec ready timeout\n", 1716 sc->sc_dev.dv_xname); 1717 return(1); 1718 } 1719 } 1720 1721 /* Assert valid frame signal */ 1722 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1723 1724 /* Wait for valid AC97 input slot */ 1725 n = 0; 1726 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1727 (ACISV_ISV3 | ACISV_ISV4)) { 1728 delay(1000); 1729 if (++n > 1000) { 1730 printf("AC97 inputs slot ready timeout\n"); 1731 return(1); 1732 } 1733 } 1734 1735 /* Set AC97 output slot valid signals */ 1736 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1737 1738 /* reset the processor */ 1739 cs4280_reset(sc); 1740 return (0); 1741 } 1742 1743 int 1744 cs4280_init2(sc, init) 1745 struct cs4280_softc *sc; 1746 int init; 1747 { 1748 int n; 1749 u_int32_t mem; 1750 1751 /* Download the image to the processor */ 1752 if (cs4280_download_image(sc) != 0) { 1753 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1754 return(1); 1755 } 1756 1757 /* Save playback parameter and then write zero. 1758 * this ensures that DMA doesn't immediately occur upon 1759 * starting the processor core 1760 */ 1761 mem = BA1READ4(sc, CS4280_PCTL); 1762 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1763 cs4280_halt_output(sc); 1764 1765 /* Save capture parameter and then write zero. 1766 * this ensures that DMA doesn't immediately occur upon 1767 * starting the processor core 1768 */ 1769 mem = BA1READ4(sc, CS4280_CCTL); 1770 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1771 cs4280_halt_input(sc); 1772 1773 /* MSH: need to power up ADC and DAC? */ 1774 1775 /* Processor Startup Procedure */ 1776 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1777 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1778 1779 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1780 n = 0; 1781 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1782 delay(10); 1783 if (++n > 1000) { 1784 printf("SPCR 1->0 transition timeout\n"); 1785 return(1); 1786 } 1787 } 1788 1789 n = 0; 1790 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1791 delay(10); 1792 if (++n > 1000) { 1793 printf("SPCS 0->1 transition timeout\n"); 1794 return(1); 1795 } 1796 } 1797 /* Processor is now running !!! */ 1798 1799 /* Setup volume */ 1800 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1801 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1802 1803 /* Interrupt enable */ 1804 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1805 1806 /* playback interrupt enable */ 1807 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1808 mem |= PFIE_PI_ENABLE; 1809 BA1WRITE4(sc, CS4280_PFIE, mem); 1810 /* capture interrupt enable */ 1811 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1812 mem |= CIE_CI_ENABLE; 1813 BA1WRITE4(sc, CS4280_CIE, mem); 1814 1815 #if NMIDI > 0 1816 /* Reset midi port */ 1817 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1818 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1819 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1820 /* midi interrupt enable */ 1821 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1822 BA0WRITE4(sc, CS4280_MIDCR, mem); 1823 #endif 1824 return(0); 1825 } 1826 1827 void 1828 cs4280_power(why, v) 1829 int why; 1830 void *v; 1831 { 1832 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1833 int i; 1834 1835 DPRINTF(("%s: cs4280_power why=%d\n", 1836 sc->sc_dev.dv_xname, why)); 1837 if (why != PWR_RESUME) { 1838 sc->sc_suspend = why; 1839 1840 cs4280_halt_output(sc); 1841 cs4280_halt_input(sc); 1842 /* Save AC97 registers */ 1843 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1844 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1845 continue; 1846 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1847 } 1848 /* should I powerdown here ? */ 1849 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1850 } else { 1851 if (sc->sc_suspend == PWR_RESUME) { 1852 printf("cs4280_power: odd, resume without suspend.\n"); 1853 sc->sc_suspend = why; 1854 return; 1855 } 1856 sc->sc_suspend = why; 1857 cs4280_init(sc, 0); 1858 cs4280_init2(sc, 0); 1859 cs4280_reset_codec(sc); 1860 1861 /* restore ac97 registers */ 1862 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1863 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1864 continue; 1865 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1866 } 1867 } 1868 } 1869 1870 void 1871 cs4280_clear_fifos(sc) 1872 struct cs4280_softc *sc; 1873 { 1874 int pd = 0, cnt, n; 1875 u_int32_t mem; 1876 1877 /* 1878 * If device power down, power up the device and keep power down 1879 * state. 1880 */ 1881 mem = BA0READ4(sc, CS4280_CLKCR1); 1882 if (!(mem & CLKCR1_SWCE)) { 1883 printf("cs4280_clear_fifo: power down found.\n"); 1884 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1885 pd = 1; 1886 } 1887 BA0WRITE4(sc, CS4280_SERBWP, 0); 1888 for (cnt = 0; cnt < 256; cnt++) { 1889 n = 0; 1890 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1891 delay(1000); 1892 if (++n > 1000) { 1893 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1894 break; 1895 } 1896 } 1897 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1898 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1899 } 1900 if (pd) 1901 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1902 } 1903 1904 #if NMIDI > 0 1905 int 1906 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1907 void *addr; 1908 int flags; 1909 void (*iintr)(void *, int); 1910 void (*ointr)(void *); 1911 void *arg; 1912 { 1913 struct cs4280_softc *sc = addr; 1914 u_int32_t mem; 1915 1916 DPRINTF(("midi_open\n")); 1917 sc->sc_iintr = iintr; 1918 sc->sc_ointr = ointr; 1919 sc->sc_arg = arg; 1920 1921 /* midi interrupt enable */ 1922 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1923 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1924 BA0WRITE4(sc, CS4280_MIDCR, mem); 1925 #ifdef CS4280_DEBUG 1926 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1927 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1928 return(EINVAL); 1929 } 1930 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1931 #endif 1932 return (0); 1933 } 1934 1935 void 1936 cs4280_midi_close(addr) 1937 void *addr; 1938 { 1939 struct cs4280_softc *sc = addr; 1940 u_int32_t mem; 1941 1942 DPRINTF(("midi_close\n")); 1943 mem = BA0READ4(sc, CS4280_MIDCR); 1944 mem &= ~MIDCR_MASK; 1945 BA0WRITE4(sc, CS4280_MIDCR, mem); 1946 1947 sc->sc_iintr = 0; 1948 sc->sc_ointr = 0; 1949 } 1950 1951 int 1952 cs4280_midi_output(addr, d) 1953 void *addr; 1954 int d; 1955 { 1956 struct cs4280_softc *sc = addr; 1957 u_int32_t mem; 1958 int x; 1959 1960 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1961 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1962 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1963 mem |= d & MIDWP_MASK; 1964 DPRINTFN(5,("midi_output d=0x%08x",d)); 1965 BA0WRITE4(sc, CS4280_MIDWP, mem); 1966 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1967 DPRINTF(("Bad write data: %d %d", 1968 mem, BA0READ4(sc, CS4280_MIDWP))); 1969 return(EIO); 1970 } 1971 return (0); 1972 } 1973 delay(MIDI_BUSY_DELAY); 1974 } 1975 return (EIO); 1976 } 1977 1978 void 1979 cs4280_midi_getinfo(addr, mi) 1980 void *addr; 1981 struct midi_info *mi; 1982 { 1983 mi->name = "CS4280 MIDI UART"; 1984 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1985 } 1986 1987 #endif 1988