1 /* $OpenBSD: cs4280.c,v 1.53 2020/01/24 03:29:55 tedu Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/cs4280reg.h> 78 79 #include <sys/audioio.h> 80 #include <dev/audio_if.h> 81 82 #include <dev/ic/ac97.h> 83 84 #include <machine/bus.h> 85 86 #define CSCC_PCI_BA0 0x10 87 #define CSCC_PCI_BA1 0x14 88 89 struct cs4280_dma { 90 bus_dmamap_t map; 91 caddr_t addr; /* real dma buffer */ 92 caddr_t dum; /* dummy buffer for audio driver */ 93 bus_dma_segment_t segs[1]; 94 int nsegs; 95 size_t size; 96 struct cs4280_dma *next; 97 }; 98 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 99 #define BUFADDR(p) ((void *)((p)->dum)) 100 #define KERNADDR(p) ((void *)((p)->addr)) 101 102 /* 103 * Software state 104 */ 105 struct cs4280_softc { 106 struct device sc_dev; 107 108 pci_intr_handle_t * sc_ih; 109 110 /* I/O (BA0) */ 111 bus_space_tag_t ba0t; 112 bus_space_handle_t ba0h; 113 114 /* BA1 */ 115 bus_space_tag_t ba1t; 116 bus_space_handle_t ba1h; 117 118 /* DMA */ 119 bus_dma_tag_t sc_dmatag; 120 struct cs4280_dma *sc_dmas; 121 122 void (*sc_pintr)(void *); /* dma completion intr handler */ 123 void *sc_parg; /* arg for sc_intr() */ 124 char *sc_ps, *sc_pe, *sc_pn; 125 int sc_pcount; 126 int sc_pi; 127 struct cs4280_dma *sc_pdma; 128 char *sc_pbuf; 129 #ifdef DIAGNOSTIC 130 char sc_prun; 131 #endif 132 133 void (*sc_rintr)(void *); /* dma completion intr handler */ 134 void *sc_rarg; /* arg for sc_intr() */ 135 char *sc_rs, *sc_re, *sc_rn; 136 int sc_rcount; 137 int sc_ri; 138 struct cs4280_dma *sc_rdma; 139 char *sc_rbuf; 140 int sc_rparam; /* record format */ 141 #ifdef DIAGNOSTIC 142 char sc_rrun; 143 #endif 144 145 #if NMIDI > 0 146 void (*sc_iintr)(void *, int); /* midi input ready handler */ 147 void (*sc_ointr)(void *); /* midi output ready handler */ 148 void *sc_arg; 149 #endif 150 151 u_int32_t pctl; 152 u_int32_t cctl; 153 154 struct ac97_codec_if *codec_if; 155 struct ac97_host_if host_if; 156 157 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 158 }; 159 160 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 161 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 162 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 163 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 164 165 int cs4280_match(struct device *, void *, void *); 166 void cs4280_attach(struct device *, struct device *, void *); 167 int cs4280_activate(struct device *, int); 168 void cs4280_attachhook(struct device *); 169 int cs4280_intr(void *); 170 void cs4280_reset(void *); 171 int cs4280_download_image(struct cs4280_softc *); 172 173 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 174 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t, 175 struct cs4280_dma *); 176 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *); 177 178 #ifdef CS4280_DEBUG 179 int cs4280_check_images(struct cs4280_softc *); 180 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 181 u_int32_t); 182 #endif 183 184 struct cfdriver clcs_cd = { 185 NULL, "clcs", DV_DULL 186 }; 187 188 struct cfattach clcs_ca = { 189 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach, NULL, 190 cs4280_activate 191 }; 192 193 int cs4280_init(struct cs4280_softc *, int); 194 int cs4280_init2(struct cs4280_softc *, int); 195 int cs4280_open(void *, int); 196 void cs4280_close(void *); 197 198 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 199 int cs4280_round_blocksize(void *, int); 200 201 int cs4280_halt_output(void *); 202 int cs4280_halt_input(void *); 203 204 int cs4280_mixer_set_port(void *, mixer_ctrl_t *); 205 int cs4280_mixer_get_port(void *, mixer_ctrl_t *); 206 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip); 207 void *cs4280_malloc(void *, int, size_t, int, int); 208 void cs4280_free(void *, void *, int); 209 int cs4280_get_props(void *); 210 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 211 void *, struct audio_params *); 212 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 213 void *, struct audio_params *); 214 215 216 void cs4280_set_dac_rate(struct cs4280_softc *, int ); 217 void cs4280_set_adc_rate(struct cs4280_softc *, int ); 218 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *, 219 char *); 220 int cs4280_src_wait(struct cs4280_softc *); 221 int cs4280_attach_codec(void *sc, struct ac97_codec_if *); 222 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d); 223 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d); 224 void cs4280_reset_codec(void *sc); 225 226 void cs4280_clear_fifos(struct cs4280_softc *); 227 228 #if NMIDI > 0 229 void cs4280_midi_close(void *); 230 void cs4280_midi_getinfo(void *, struct midi_info *); 231 int cs4280_midi_open(void *, int, void (*)(void *, int), 232 void (*)(void *), void *); 233 int cs4280_midi_output(void *, int); 234 #endif 235 236 struct audio_hw_if cs4280_hw_if = { 237 cs4280_open, 238 cs4280_close, 239 cs4280_set_params, 240 cs4280_round_blocksize, 241 NULL, 242 NULL, 243 NULL, 244 NULL, 245 NULL, 246 cs4280_halt_output, 247 cs4280_halt_input, 248 NULL, 249 NULL, 250 cs4280_mixer_set_port, 251 cs4280_mixer_get_port, 252 cs4280_query_devinfo, 253 cs4280_malloc, 254 cs4280_free, 255 NULL, 256 cs4280_get_props, 257 cs4280_trigger_output, 258 cs4280_trigger_input 259 }; 260 261 #if NMIDI > 0 262 struct midi_hw_if cs4280_midi_hw_if = { 263 cs4280_midi_open, 264 cs4280_midi_close, 265 cs4280_midi_output, 266 0, /* flush */ 267 cs4280_midi_getinfo, 268 0, /* ioctl */ 269 }; 270 #endif 271 272 273 const struct pci_matchid cs4280_devices[] = { 274 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, 275 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, 276 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 }, 277 }; 278 279 int 280 cs4280_match(struct device *parent, void *ma, void *aux) 281 { 282 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, 283 nitems(cs4280_devices))); 284 } 285 286 int 287 cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data) 288 { 289 struct cs4280_softc *sc = sc_; 290 int n; 291 292 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 293 /* 294 * Make sure that there is not data sitting around from a preivous 295 * uncompleted access. 296 */ 297 BA0READ4(sc, CS4280_ACSDA); 298 299 /* Set up AC97 control registers. */ 300 BA0WRITE4(sc, CS4280_ACCAD, add); 301 BA0WRITE4(sc, CS4280_ACCDA, 0); 302 BA0WRITE4(sc, CS4280_ACCTL, 303 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 304 305 if (cs4280_src_wait(sc) < 0) { 306 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 307 sc->sc_dev.dv_xname, add); 308 return (1); 309 } 310 311 /* wait for valid status bit is active */ 312 n = 0; 313 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 314 delay(1); 315 while (++n > 1000) { 316 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 317 sc->sc_dev.dv_xname, add); 318 return (1); 319 } 320 } 321 *data = BA0READ4(sc, CS4280_ACSDA); 322 DPRINTFN(5,("data=0x%04x\n", *data)); 323 return (0); 324 } 325 326 int 327 cs4280_write_codec(void *sc_, u_int8_t add, u_int16_t data) 328 { 329 struct cs4280_softc *sc = sc_; 330 331 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 332 BA0WRITE4(sc, CS4280_ACCAD, add); 333 BA0WRITE4(sc, CS4280_ACCDA, data); 334 BA0WRITE4(sc, CS4280_ACCTL, 335 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 336 337 if (cs4280_src_wait(sc) < 0) { 338 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 339 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 340 return (1); 341 } 342 return (0); 343 } 344 345 int 346 cs4280_src_wait(struct cs4280_softc *sc) 347 { 348 int n; 349 350 n = 0; 351 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 352 delay(1000); 353 if (++n > 1000) 354 return (-1); 355 } 356 return (0); 357 } 358 359 360 void 361 cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) 362 { 363 /* calculate capture rate: 364 * 365 * capture_coefficient_increment = -round(rate*128*65536/48000; 366 * capture_phase_increment = floor(48000*65536*1024/rate); 367 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 368 * cy = floor(cx/200); 369 * capture_sample_rate_correction = cx - 200*cy; 370 * capture_delay = ceil(24*48000/rate); 371 * capture_num_triplets = floor(65536*rate/24000); 372 * capture_group_length = 24000/GCD(rate, 24000); 373 * where GCD means "Greatest Common Divisor". 374 * 375 * capture_coefficient_increment, capture_phase_increment and 376 * capture_num_triplets are 32-bit signed quantities. 377 * capture_sample_rate_correction and capture_group_length are 378 * 16-bit signed quantities. 379 * capture_delay is a 14-bit unsigned quantity. 380 */ 381 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 382 u_int16_t csrc, cgl, cdlay; 383 384 /* XXX 385 * Even though, embedded_audio_spec says capture rate range 11025 to 386 * 48000, dhwiface.cpp says, 387 * 388 * "We can only decimate by up to a factor of 1/9th the hardware rate. 389 * Return an error if an attempt is made to stray outside that limit." 390 * 391 * so assume range as 48000/9 to 48000 392 */ 393 394 if (rate < 8000) 395 rate = 8000; 396 if (rate > 48000) 397 rate = 48000; 398 399 cx = rate << 16; 400 cci = cx / 48000; 401 cx -= cci * 48000; 402 cx <<= 7; 403 cci <<= 7; 404 cci += cx / 48000; 405 cci = - cci; 406 407 cx = 48000 << 16; 408 cpi = cx / rate; 409 cx -= cpi * rate; 410 cx <<= 10; 411 cpi <<= 10; 412 cy = cx / rate; 413 cpi += cy; 414 cx -= cy * rate; 415 416 cy = cx / 200; 417 csrc = cx - 200*cy; 418 419 cdlay = ((48000 * 24) + rate - 1) / rate; 420 #if 0 421 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 422 #endif 423 424 cnt = rate << 16; 425 cnt /= 24000; 426 427 cgl = 1; 428 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 429 if (((rate / tmp1) * tmp1) != rate) 430 cgl *= 2; 431 } 432 if (((rate / 3) * 3) != rate) 433 cgl *= 3; 434 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 435 if (((rate / tmp1) * tmp1) != rate) 436 cgl *= 5; 437 } 438 #if 0 439 /* XXX what manual says */ 440 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 441 tmp1 |= csrc<<16; 442 BA1WRITE4(sc, CS4280_CSRC, tmp1); 443 #else 444 /* suggested by cs461x.c (ALSA driver) */ 445 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 446 #endif 447 448 #if 0 449 /* I am confused. The sample rate calculation section says 450 * cci *is* 32-bit signed quantity but in the parameter description 451 * section, CCI only assigned 16bit. 452 * I believe size of the variable. 453 */ 454 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 455 tmp1 |= cci<<16; 456 BA1WRITE4(sc, CS4280_CCI, tmp1); 457 #else 458 BA1WRITE4(sc, CS4280_CCI, cci); 459 #endif 460 461 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 462 tmp1 |= cdlay <<18; 463 BA1WRITE4(sc, CS4280_CD, tmp1); 464 465 BA1WRITE4(sc, CS4280_CPI, cpi); 466 467 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 468 tmp1 |= cgl; 469 BA1WRITE4(sc, CS4280_CGL, tmp1); 470 471 BA1WRITE4(sc, CS4280_CNT, cnt); 472 473 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 474 tmp1 |= cgl; 475 BA1WRITE4(sc, CS4280_CGC, tmp1); 476 } 477 478 void 479 cs4280_set_dac_rate(struct cs4280_softc *sc, int rate) 480 { 481 /* 482 * playback rate may range from 8000Hz to 48000Hz 483 * 484 * play_phase_increment = floor(rate*65536*1024/48000) 485 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 486 * py=floor(px/200) 487 * play_sample_rate_correction = px - 200*py 488 * 489 * play_phase_increment is a 32bit signed quantity. 490 * play_sample_rate_correction is a 16bit signed quantity. 491 */ 492 int32_t ppi; 493 int16_t psrc; 494 u_int32_t px, py; 495 496 if (rate < 8000) 497 rate = 8000; 498 if (rate > 48000) 499 rate = 48000; 500 px = rate << 16; 501 ppi = px/48000; 502 px -= ppi*48000; 503 ppi <<= 10; 504 px <<= 10; 505 py = px / 48000; 506 ppi += py; 507 px -= py*48000; 508 py = px/200; 509 px -= py*200; 510 psrc = px; 511 #if 0 512 /* what manual says */ 513 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 514 BA1WRITE4(sc, CS4280_PSRC, 515 ( ((psrc<<16) & PSRC_MASK) | px )); 516 #else 517 /* suggested by cs461x.c (ALSA driver) */ 518 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 519 #endif 520 BA1WRITE4(sc, CS4280_PPI, ppi); 521 } 522 523 void 524 cs4280_attachhook(struct device *self) 525 { 526 struct cs4280_softc *sc = (struct cs4280_softc *)self; 527 mixer_ctrl_t ctl; 528 529 /* Initialization */ 530 if (cs4280_init2(sc, 1) != 0) 531 return; 532 533 printf("%s: firmware loaded\n", sc->sc_dev.dv_xname); 534 535 /* Turn mute off of DAC, CD and master volumes by default */ 536 ctl.type = AUDIO_MIXER_ENUM; 537 ctl.un.ord = 0; /* off */ 538 539 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 540 AudioNmaster, AudioNmute); 541 cs4280_mixer_set_port(sc, &ctl); 542 543 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 544 AudioNdac, AudioNmute); 545 cs4280_mixer_set_port(sc, &ctl); 546 547 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 548 AudioNcd, AudioNmute); 549 cs4280_mixer_set_port(sc, &ctl); 550 551 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 552 553 #if NMIDI > 0 554 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 555 #endif 556 } 557 558 void 559 cs4280_attach(struct device *parent, struct device *self, void *aux) 560 { 561 struct cs4280_softc *sc = (struct cs4280_softc *) self; 562 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 563 pci_chipset_tag_t pc = pa->pa_pc; 564 char const *intrstr; 565 pci_intr_handle_t ih; 566 u_int32_t mem; 567 568 /* Map I/O register */ 569 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 570 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 571 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 572 printf(": can't map BA0 space\n"); 573 return; 574 } 575 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 576 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 577 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 578 printf(": can't map BA1 space\n"); 579 return; 580 } 581 582 sc->sc_dmatag = pa->pa_dmat; 583 584 /* Get out of power save mode if needed. */ 585 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 586 587 /* LATENCY_TIMER setting */ 588 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 589 if ( PCI_LATTIMER(mem) < 32 ) { 590 mem &= 0xffff00ff; 591 mem |= 0x00002000; 592 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 593 } 594 595 /* Map and establish the interrupt. */ 596 if (pci_intr_map(pa, &ih)) { 597 printf(": couldn't map interrupt\n"); 598 return; 599 } 600 intrstr = pci_intr_string(pc, ih); 601 602 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO | IPL_MPSAFE, 603 cs4280_intr, sc, sc->sc_dev.dv_xname); 604 if (sc->sc_ih == NULL) { 605 printf(": couldn't establish interrupt"); 606 if (intrstr != NULL) 607 printf(" at %s", intrstr); 608 printf("\n"); 609 return; 610 } 611 printf(": %s\n", intrstr); 612 613 /* Initialization */ 614 if (cs4280_init(sc, 1) != 0) 615 return; 616 617 config_mountroot(self, cs4280_attachhook); 618 619 /* AC 97 attachement */ 620 sc->host_if.arg = sc; 621 sc->host_if.attach = cs4280_attach_codec; 622 sc->host_if.read = cs4280_read_codec; 623 sc->host_if.write = cs4280_write_codec; 624 sc->host_if.reset = cs4280_reset_codec; 625 626 if (ac97_attach(&sc->host_if) != 0) { 627 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 628 return; 629 } 630 } 631 632 int 633 cs4280_intr(void *p) 634 { 635 /* 636 * XXX 637 * 638 * Since CS4280 has only 4kB dma buffer and 639 * interrupt occurs every 2kB block, I create dummy buffer 640 * which returns to audio driver and actual dma buffer 641 * using in DMA transfer. 642 * 643 * 644 * ring buffer in audio.c is pointed by BUFADDR 645 * <------ ring buffer size == 64kB ------> 646 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 647 * |= = = =|= = = =|= = = =|= = = =|= = = =| 648 * | | | | | | <- call audio_intp every 649 * sc->sc_[pr]_count time. 650 * 651 * actual dma buffer is pointed by KERNADDR 652 * <-> dma buffer size = 4kB 653 * |= =| 654 * 655 * 656 */ 657 struct cs4280_softc *sc = p; 658 u_int32_t intr, mem; 659 char * empty_dma; 660 int handled = 0; 661 662 mtx_enter(&audio_lock); 663 /* grab interrupt register then clear it */ 664 intr = BA0READ4(sc, CS4280_HISR); 665 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 666 667 /* Playback Interrupt */ 668 if (intr & HISR_PINT) { 669 handled = 1; 670 mem = BA1READ4(sc, CS4280_PFIE); 671 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 672 if (sc->sc_pintr) { 673 if ((sc->sc_pi%sc->sc_pcount) == 0) 674 sc->sc_pintr(sc->sc_parg); 675 } else { 676 printf("unexpected play intr\n"); 677 } 678 /* copy buffer */ 679 ++sc->sc_pi; 680 empty_dma = sc->sc_pdma->addr; 681 if (sc->sc_pi&1) 682 empty_dma += CS4280_ICHUNK; 683 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 684 sc->sc_pn += CS4280_ICHUNK; 685 if (sc->sc_pn >= sc->sc_pe) 686 sc->sc_pn = sc->sc_ps; 687 BA1WRITE4(sc, CS4280_PFIE, mem); 688 } 689 /* Capture Interrupt */ 690 if (intr & HISR_CINT) { 691 int i; 692 int16_t rdata; 693 694 handled = 1; 695 mem = BA1READ4(sc, CS4280_CIE); 696 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 697 ++sc->sc_ri; 698 empty_dma = sc->sc_rdma->addr; 699 if ((sc->sc_ri&1) == 0) 700 empty_dma += CS4280_ICHUNK; 701 702 /* 703 * XXX 704 * I think this audio data conversion should be 705 * happened in upper layer, but I put this here 706 * since there is no conversion function available. 707 */ 708 switch(sc->sc_rparam) { 709 case CF_16BIT_STEREO: 710 /* just copy it */ 711 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 712 sc->sc_rn += CS4280_ICHUNK; 713 break; 714 case CF_16BIT_MONO: 715 for (i = 0; i < 512; i++) { 716 rdata = *((int16_t *)empty_dma)>>1; 717 empty_dma += 2; 718 rdata += *((int16_t *)empty_dma)>>1; 719 empty_dma += 2; 720 *((int16_t *)sc->sc_rn) = rdata; 721 sc->sc_rn += 2; 722 } 723 break; 724 case CF_8BIT_STEREO: 725 for (i = 0; i < 512; i++) { 726 rdata = *((int16_t*)empty_dma); 727 empty_dma += 2; 728 *sc->sc_rn++ = rdata >> 8; 729 rdata = *((int16_t*)empty_dma); 730 empty_dma += 2; 731 *sc->sc_rn++ = rdata >> 8; 732 } 733 break; 734 case CF_8BIT_MONO: 735 for (i = 0; i < 512; i++) { 736 rdata = *((int16_t*)empty_dma) >>1; 737 empty_dma += 2; 738 rdata += *((int16_t*)empty_dma) >>1; 739 empty_dma += 2; 740 *sc->sc_rn++ = rdata >>8; 741 } 742 break; 743 default: 744 /* Should not reach here */ 745 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 746 } 747 if (sc->sc_rn >= sc->sc_re) 748 sc->sc_rn = sc->sc_rs; 749 BA1WRITE4(sc, CS4280_CIE, mem); 750 if (sc->sc_rintr) { 751 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 752 sc->sc_rintr(sc->sc_rarg); 753 } else { 754 printf("unexpected record intr\n"); 755 } 756 } 757 758 #if NMIDI > 0 759 /* Midi port Interrupt */ 760 if (intr & HISR_MIDI) { 761 int data; 762 763 handled = 1; 764 DPRINTF(("i: %d: ", 765 BA0READ4(sc, CS4280_MIDSR))); 766 /* Read the received data */ 767 while ((sc->sc_iintr != NULL) && 768 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 769 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 770 DPRINTF(("r:%x\n",data)); 771 sc->sc_iintr(sc->sc_arg, data); 772 } 773 774 /* Write the data */ 775 #if 1 776 /* XXX: 777 * It seems "Transmit Buffer Full" never activate until EOI 778 * is delivered. Shall I throw EOI top of this routine ? 779 */ 780 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 781 DPRINTF(("w: ")); 782 if (sc->sc_ointr != NULL) 783 sc->sc_ointr(sc->sc_arg); 784 } 785 #else 786 while ((sc->sc_ointr != NULL) && 787 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 788 DPRINTF(("w: ")); 789 sc->sc_ointr(sc->sc_arg); 790 } 791 #endif 792 DPRINTF(("\n")); 793 } 794 #endif 795 mtx_leave(&audio_lock); 796 return handled; 797 } 798 799 800 /* Download Proceessor Code and Data image */ 801 802 int 803 cs4280_download(struct cs4280_softc *sc, const u_int32_t *src, u_int32_t offset, 804 u_int32_t len) 805 { 806 u_int32_t ctr; 807 808 #ifdef CS4280_DEBUG 809 u_int32_t con, data; 810 u_int8_t c0,c1,c2,c3; 811 #endif 812 if ((offset&3) || (len&3)) 813 return (-1); 814 815 len /= sizeof(u_int32_t); 816 for (ctr = 0; ctr < len; ctr++) { 817 /* XXX: 818 * I cannot confirm this is the right thing or not 819 * on BIG-ENDIAN machines. 820 */ 821 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 822 #ifdef CS4280_DEBUG 823 data = htole32(*(src+ctr)); 824 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 825 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 826 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 827 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 828 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 829 if (data != con ) { 830 printf("0x%06x: write=0x%08x read=0x%08x\n", 831 offset+ctr*4, data, con); 832 return (-1); 833 } 834 #endif 835 } 836 return (0); 837 } 838 839 struct BA1struct *BA1Struct; 840 841 int 842 cs4280_download_image(struct cs4280_softc *sc) 843 { 844 int idx, err = 0; 845 u_int32_t offset = 0; 846 static u_char *cs4280_firmware; 847 static size_t cs4280_firmwarelen; 848 849 if (cs4280_firmware == NULL) { 850 err = loadfirmware("cs4280", &cs4280_firmware, 851 &cs4280_firmwarelen); 852 if (err) 853 return (err); 854 } 855 856 BA1Struct = (struct BA1struct *)cs4280_firmware; 857 858 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 859 err = cs4280_download(sc, &BA1Struct->map[offset], 860 BA1Struct->memory[idx].offset, BA1Struct->memory[idx].size); 861 if (err != 0) { 862 printf("%s: load_image failed at %d\n", 863 sc->sc_dev.dv_xname, idx); 864 return (-1); 865 } 866 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 867 } 868 return (err); 869 } 870 871 #ifdef CS4280_DEBUG 872 int 873 cs4280_checkimage(struct cs4280_softc *sc, u_int32_t *src, u_int32_t offset, 874 u_int32_t len) 875 { 876 u_int32_t ctr, data; 877 int err = 0; 878 879 if ((offset&3) || (len&3)) 880 return -1; 881 882 len /= sizeof(u_int32_t); 883 for (ctr = 0; ctr < len; ctr++) { 884 /* I cannot confirm this is the right thing 885 * on BIG-ENDIAN machines 886 */ 887 data = BA1READ4(sc, offset+ctr*4); 888 if (data != htole32(*(src+ctr))) { 889 printf("0x%06x: 0x%08x(0x%08x)\n", 890 offset+ctr*4, data, *(src+ctr)); 891 *(src+ctr) = data; 892 ++err; 893 } 894 } 895 return (err); 896 } 897 898 int 899 cs4280_check_images(struct cs4280_softc *sc) 900 { 901 int idx, err; 902 u_int32_t offset = 0; 903 904 err = 0; 905 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 906 for (idx = 0; idx < 1; ++idx) { 907 err = cs4280_checkimage(sc, &BA1Struct->map[offset], 908 BA1Struct->memory[idx].offset, 909 BA1Struct->memory[idx].size); 910 if (err != 0) { 911 printf("%s: check_image failed at %d\n", 912 sc->sc_dev.dv_xname, idx); 913 } 914 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 915 } 916 return (err); 917 } 918 919 #endif 920 921 int 922 cs4280_attach_codec(void *sc_, struct ac97_codec_if *codec_if) 923 { 924 struct cs4280_softc *sc = sc_; 925 926 sc->codec_if = codec_if; 927 return (0); 928 } 929 930 void 931 cs4280_reset_codec(void *sc_) 932 { 933 struct cs4280_softc *sc = sc_; 934 int n; 935 936 /* Reset codec */ 937 BA0WRITE4(sc, CS4280_ACCTL, 0); 938 delay(100); /* delay 100us */ 939 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 940 941 /* 942 * It looks like we do the following procedure, too 943 */ 944 945 /* Enable AC-link sync generation */ 946 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 947 delay(50*1000); /* XXX delay 50ms */ 948 949 /* Assert valid frame signal */ 950 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 951 952 /* Wait for valid AC97 input slot */ 953 n = 0; 954 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 955 delay(1000); 956 if (++n > 1000) { 957 printf("reset_codec: AC97 inputs slot ready timeout\n"); 958 return; 959 } 960 } 961 } 962 963 964 /* Processor Soft Reset */ 965 void 966 cs4280_reset(void *sc_) 967 { 968 struct cs4280_softc *sc = sc_; 969 970 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 971 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 972 delay(100); 973 /* Clear RSTSP bit in SPCR */ 974 BA1WRITE4(sc, CS4280_SPCR, 0); 975 /* enable DMA reqest */ 976 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 977 } 978 979 int 980 cs4280_open(void *addr, int flags) 981 { 982 return (0); 983 } 984 985 void 986 cs4280_close(void *addr) 987 { 988 struct cs4280_softc *sc = addr; 989 990 /* XXX: already called in audio_close() */ 991 cs4280_halt_output(sc); 992 cs4280_halt_input(sc); 993 994 sc->sc_pintr = 0; 995 sc->sc_rintr = 0; 996 } 997 998 int 999 cs4280_set_params(void *addr, int setmode, int usemode, 1000 struct audio_params *play, struct audio_params *rec) 1001 { 1002 struct cs4280_softc *sc = addr; 1003 struct audio_params *p; 1004 int mode; 1005 1006 for (mode = AUMODE_RECORD; mode != -1; 1007 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1008 if ((setmode & mode) == 0) 1009 continue; 1010 1011 p = mode == AUMODE_PLAY ? play : rec; 1012 if (p == play) { 1013 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1014 p->sample_rate, p->precision, p->channels)); 1015 } else { 1016 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1017 p->sample_rate, p->precision, p->channels)); 1018 } 1019 /* play back data format may be 8- or 16-bit and 1020 * either stereo or mono. 1021 * playback rate may range from 8000Hz to 48000Hz 1022 * 1023 * capture data format must be 16bit stereo 1024 * and sample rate range from 11025Hz to 48000Hz. 1025 * 1026 * XXX: it looks like to work with 8000Hz, 1027 * although data sheets say lower limit is 1028 * 11025 Hz. 1029 */ 1030 if (p->sample_rate < 8000) 1031 p->sample_rate = 8000; 1032 if (p->sample_rate > 48000) 1033 p->sample_rate = 48000; 1034 if (p->precision > 16) 1035 p->precision = 16; 1036 if (p->channels > 2) 1037 p->channels = 2; 1038 1039 /* capturing data is slinear */ 1040 switch (p->encoding) { 1041 case AUDIO_ENCODING_SLINEAR_LE: 1042 break; 1043 default: 1044 return (EINVAL); 1045 } 1046 p->bps = AUDIO_BPS(p->precision); 1047 p->msb = 1; 1048 } 1049 1050 /* set sample rate */ 1051 cs4280_set_dac_rate(sc, play->sample_rate); 1052 cs4280_set_adc_rate(sc, rec->sample_rate); 1053 return (0); 1054 } 1055 1056 int 1057 cs4280_round_blocksize(void *hdl, int blk) 1058 { 1059 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1060 } 1061 1062 int 1063 cs4280_get_props(void *hdl) 1064 { 1065 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1066 } 1067 1068 int 1069 cs4280_mixer_get_port(void *addr, mixer_ctrl_t *cp) 1070 { 1071 struct cs4280_softc *sc = addr; 1072 1073 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1074 } 1075 1076 int 1077 cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip) 1078 { 1079 struct cs4280_softc *sc = addr; 1080 1081 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1082 } 1083 1084 int 1085 cs4280_get_portnum_by_name(struct cs4280_softc *sc, char *class, char *device, 1086 char *qualifier) 1087 { 1088 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1089 device, qualifier)); 1090 } 1091 1092 int 1093 cs4280_halt_output(void *addr) 1094 { 1095 struct cs4280_softc *sc = addr; 1096 u_int32_t mem; 1097 1098 mtx_enter(&audio_lock); 1099 mem = BA1READ4(sc, CS4280_PCTL); 1100 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1101 #ifdef DIAGNOSTIC 1102 sc->sc_prun = 0; 1103 #endif 1104 mtx_leave(&audio_lock); 1105 return (0); 1106 } 1107 1108 int 1109 cs4280_halt_input(void *addr) 1110 { 1111 struct cs4280_softc *sc = addr; 1112 u_int32_t mem; 1113 1114 mtx_enter(&audio_lock); 1115 mem = BA1READ4(sc, CS4280_CCTL); 1116 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1117 #ifdef DIAGNOSTIC 1118 sc->sc_rrun = 0; 1119 #endif 1120 mtx_leave(&audio_lock); 1121 return (0); 1122 } 1123 1124 int 1125 cs4280_mixer_set_port(void *addr, mixer_ctrl_t *cp) 1126 { 1127 struct cs4280_softc *sc = addr; 1128 int val; 1129 1130 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1131 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1132 return (val); 1133 } 1134 1135 1136 int 1137 cs4280_freemem(struct cs4280_softc *sc, struct cs4280_dma *p) 1138 { 1139 bus_dmamap_unload(sc->sc_dmatag, p->map); 1140 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1141 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1142 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1143 return (0); 1144 } 1145 1146 int 1147 cs4280_allocmem(struct cs4280_softc *sc, size_t size, size_t align, 1148 struct cs4280_dma *p) 1149 { 1150 int error; 1151 1152 /* XXX */ 1153 p->size = size; 1154 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1155 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1156 &p->nsegs, BUS_DMA_NOWAIT); 1157 if (error) { 1158 printf("%s: unable to allocate dma, error=%d\n", 1159 sc->sc_dev.dv_xname, error); 1160 return (error); 1161 } 1162 1163 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1164 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1165 if (error) { 1166 printf("%s: unable to map dma, error=%d\n", 1167 sc->sc_dev.dv_xname, error); 1168 goto free; 1169 } 1170 1171 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1172 0, BUS_DMA_NOWAIT, &p->map); 1173 if (error) { 1174 printf("%s: unable to create dma map, error=%d\n", 1175 sc->sc_dev.dv_xname, error); 1176 goto unmap; 1177 } 1178 1179 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1180 BUS_DMA_NOWAIT); 1181 if (error) { 1182 printf("%s: unable to load dma map, error=%d\n", 1183 sc->sc_dev.dv_xname, error); 1184 goto destroy; 1185 } 1186 return (0); 1187 1188 destroy: 1189 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1190 unmap: 1191 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1192 free: 1193 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1194 return (error); 1195 } 1196 1197 1198 void * 1199 cs4280_malloc(void *addr, int direction, size_t size, int pool, int flags) 1200 { 1201 struct cs4280_softc *sc = addr; 1202 struct cs4280_dma *p; 1203 caddr_t q; 1204 int error; 1205 1206 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1207 q = malloc(size, pool, flags); 1208 if (!q) 1209 return (0); 1210 p = malloc(sizeof(*p), pool, flags); 1211 if (!p) { 1212 free(q,pool, 0); 1213 return (0); 1214 } 1215 /* 1216 * cs4280 has fixed 4kB buffer 1217 */ 1218 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1219 1220 if (error) { 1221 free(q, pool, 0); 1222 free(p, pool, 0); 1223 return (0); 1224 } 1225 1226 p->next = sc->sc_dmas; 1227 sc->sc_dmas = p; 1228 p->dum = q; /* return to audio driver */ 1229 1230 return (p->dum); 1231 } 1232 1233 void 1234 cs4280_free(void *addr, void *ptr, int pool) 1235 { 1236 struct cs4280_softc *sc = addr; 1237 struct cs4280_dma **pp, *p; 1238 1239 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1240 if (BUFADDR(p) == ptr) { 1241 cs4280_freemem(sc, p); 1242 *pp = p->next; 1243 free(p->dum, pool, 0); 1244 free(p, pool, 0); 1245 return; 1246 } 1247 } 1248 } 1249 1250 int 1251 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 1252 void (*intr)(void *), void *arg, struct audio_params *param) 1253 { 1254 struct cs4280_softc *sc = addr; 1255 u_int32_t pfie, pctl, mem, pdtc; 1256 struct cs4280_dma *p; 1257 1258 #ifdef DIAGNOSTIC 1259 if (sc->sc_prun) 1260 printf("cs4280_trigger_output: already running\n"); 1261 sc->sc_prun = 1; 1262 #endif 1263 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1264 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1265 sc->sc_pintr = intr; 1266 sc->sc_parg = arg; 1267 1268 /* stop playback DMA */ 1269 mem = BA1READ4(sc, CS4280_PCTL); 1270 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1271 1272 /* setup PDTC */ 1273 pdtc = BA1READ4(sc, CS4280_PDTC); 1274 pdtc &= ~PDTC_MASK; 1275 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1276 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1277 1278 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 1279 param->precision, param->channels, 1280 param->encoding)); 1281 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1282 ; 1283 if (p == NULL) { 1284 printf("cs4280_trigger_output: bad addr %p\n", start); 1285 return (EINVAL); 1286 } 1287 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1288 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1289 "4kB align\n", DMAADDR(p)); 1290 return (EINVAL); 1291 } 1292 1293 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1294 sc->sc_ps = (char *)start; 1295 sc->sc_pe = (char *)end; 1296 sc->sc_pdma = p; 1297 sc->sc_pbuf = KERNADDR(p); 1298 sc->sc_pi = 0; 1299 sc->sc_pn = sc->sc_ps; 1300 if (blksize >= CS4280_DCHUNK) { 1301 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1302 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1303 ++sc->sc_pi; 1304 } else { 1305 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1306 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1307 } 1308 1309 /* initiate playback dma */ 1310 mtx_enter(&audio_lock); 1311 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1312 1313 /* set PFIE */ 1314 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1315 1316 if (param->precision == 8) 1317 pfie |= PFIE_8BIT; 1318 if (param->channels == 1) 1319 pfie |= PFIE_MONO; 1320 1321 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1322 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1323 pfie |= PFIE_SWAPPED; 1324 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1325 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1326 pfie |= PFIE_UNSIGNED; 1327 1328 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1329 1330 cs4280_set_dac_rate(sc, param->sample_rate); 1331 1332 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1333 pctl |= sc->pctl; 1334 BA1WRITE4(sc, CS4280_PCTL, pctl); 1335 mtx_leave(&audio_lock); 1336 return (0); 1337 } 1338 1339 int 1340 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 1341 void (*intr)(void *), void *arg, struct audio_params *param) 1342 { 1343 struct cs4280_softc *sc = addr; 1344 u_int32_t cctl, cie; 1345 struct cs4280_dma *p; 1346 1347 #ifdef DIAGNOSTIC 1348 if (sc->sc_rrun) 1349 printf("cs4280_trigger_input: already running\n"); 1350 sc->sc_rrun = 1; 1351 #endif 1352 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1353 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1354 sc->sc_rintr = intr; 1355 sc->sc_rarg = arg; 1356 1357 sc->sc_ri = 0; 1358 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1359 sc->sc_rs = (char *)start; 1360 sc->sc_re = (char *)end; 1361 sc->sc_rn = sc->sc_rs; 1362 1363 /* setup format information for internal converter */ 1364 sc->sc_rparam = 0; 1365 if (param->precision == 8) { 1366 sc->sc_rparam += CF_8BIT; 1367 sc->sc_rcount <<= 1; 1368 } 1369 if (param->channels == 1) { 1370 sc->sc_rparam += CF_MONO; 1371 sc->sc_rcount <<= 1; 1372 } 1373 1374 /* stop capture DMA */ 1375 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1376 BA1WRITE4(sc, CS4280_CCTL, cctl); 1377 1378 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1379 ; 1380 if (!p) { 1381 printf("cs4280_trigger_input: bad addr %p\n", start); 1382 return (EINVAL); 1383 } 1384 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1385 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1386 "4kB align\n", DMAADDR(p)); 1387 return (EINVAL); 1388 } 1389 sc->sc_rdma = p; 1390 sc->sc_rbuf = KERNADDR(p); 1391 1392 /* initiate capture dma */ 1393 mtx_enter(&audio_lock); 1394 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1395 1396 /* set CIE */ 1397 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1398 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1399 1400 cs4280_set_adc_rate(sc, param->sample_rate); 1401 1402 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1403 cctl |= sc->cctl; 1404 BA1WRITE4(sc, CS4280_CCTL, cctl); 1405 mtx_leave(&audio_lock); 1406 return (0); 1407 } 1408 1409 1410 int 1411 cs4280_init(struct cs4280_softc *sc, int init) 1412 { 1413 int n; 1414 u_int32_t mem; 1415 1416 /* Start PLL out in known state */ 1417 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1418 /* Start serial ports out in known state */ 1419 BA0WRITE4(sc, CS4280_SERMC1, 0); 1420 1421 /* Specify type of CODEC */ 1422 /* XXX should no be here */ 1423 #define SERACC_CODEC_TYPE_1_03 1424 #ifdef SERACC_CODEC_TYPE_1_03 1425 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1426 #else 1427 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1428 #endif 1429 1430 /* Reset codec */ 1431 BA0WRITE4(sc, CS4280_ACCTL, 0); 1432 delay(100); /* delay 100us */ 1433 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1434 1435 /* Enable AC-link sync generation */ 1436 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1437 delay(50*1000); /* delay 50ms */ 1438 1439 /* Set the serial port timing configuration */ 1440 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1441 1442 /* Setup clock control */ 1443 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1444 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1445 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1446 1447 /* Power up the PLL */ 1448 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1449 delay(50*1000); /* delay 50ms */ 1450 1451 /* Turn on clock */ 1452 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1453 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1454 1455 /* Set the serial port FIFO pointer to the 1456 * first sample in FIFO. (not documented) */ 1457 cs4280_clear_fifos(sc); 1458 1459 #if 0 1460 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1461 BA0WRITE4(sc, CS4280_SERBSP, 0); 1462 #endif 1463 1464 /* Configure the serial port */ 1465 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1466 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1467 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1468 1469 /* Wait for CODEC ready */ 1470 n = 0; 1471 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1472 delay(125); 1473 if (++n > 1000) { 1474 printf("%s: codec ready timeout\n", 1475 sc->sc_dev.dv_xname); 1476 return(1); 1477 } 1478 } 1479 1480 /* Assert valid frame signal */ 1481 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1482 1483 /* Wait for valid AC97 input slot */ 1484 n = 0; 1485 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1486 (ACISV_ISV3 | ACISV_ISV4)) { 1487 delay(1000); 1488 if (++n > 1000) { 1489 printf("AC97 inputs slot ready timeout\n"); 1490 return(1); 1491 } 1492 } 1493 1494 /* Set AC97 output slot valid signals */ 1495 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1496 1497 /* reset the processor */ 1498 cs4280_reset(sc); 1499 return (0); 1500 } 1501 1502 int 1503 cs4280_init2(struct cs4280_softc *sc, int init) 1504 { 1505 int n; 1506 u_int32_t mem; 1507 1508 /* Download the image to the processor */ 1509 if (cs4280_download_image(sc) != 0) { 1510 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1511 return(1); 1512 } 1513 1514 /* Save playback parameter and then write zero. 1515 * this ensures that DMA doesn't immediately occur upon 1516 * starting the processor core 1517 */ 1518 mem = BA1READ4(sc, CS4280_PCTL); 1519 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1520 cs4280_halt_output(sc); 1521 1522 /* Save capture parameter and then write zero. 1523 * this ensures that DMA doesn't immediately occur upon 1524 * starting the processor core 1525 */ 1526 mem = BA1READ4(sc, CS4280_CCTL); 1527 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1528 cs4280_halt_input(sc); 1529 1530 /* MSH: need to power up ADC and DAC? */ 1531 1532 /* Processor Startup Procedure */ 1533 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1534 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1535 1536 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1537 n = 0; 1538 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1539 delay(10); 1540 if (++n > 1000) { 1541 printf("SPCR 1->0 transition timeout\n"); 1542 return(1); 1543 } 1544 } 1545 1546 n = 0; 1547 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1548 delay(10); 1549 if (++n > 1000) { 1550 printf("SPCS 0->1 transition timeout\n"); 1551 return(1); 1552 } 1553 } 1554 /* Processor is now running !!! */ 1555 1556 /* Setup volume */ 1557 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1558 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1559 1560 /* Interrupt enable */ 1561 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1562 1563 /* playback interrupt enable */ 1564 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1565 mem |= PFIE_PI_ENABLE; 1566 BA1WRITE4(sc, CS4280_PFIE, mem); 1567 /* capture interrupt enable */ 1568 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1569 mem |= CIE_CI_ENABLE; 1570 BA1WRITE4(sc, CS4280_CIE, mem); 1571 1572 #if NMIDI > 0 1573 /* Reset midi port */ 1574 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1575 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1576 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1577 /* midi interrupt enable */ 1578 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1579 BA0WRITE4(sc, CS4280_MIDCR, mem); 1580 #endif 1581 return(0); 1582 } 1583 1584 int 1585 cs4280_activate(struct device *self, int act) 1586 { 1587 struct cs4280_softc *sc = (struct cs4280_softc *)self; 1588 int rv = 0; 1589 1590 switch (act) { 1591 case DVACT_SUSPEND: 1592 /* should I powerdown here ? */ 1593 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1594 break; 1595 case DVACT_RESUME: 1596 cs4280_close(sc); 1597 cs4280_init(sc, 0); 1598 cs4280_init2(sc, 0); 1599 ac97_resume(&sc->host_if, sc->codec_if); 1600 rv = config_activate_children(self, act); 1601 break; 1602 default: 1603 rv = config_activate_children(self, act); 1604 break; 1605 } 1606 return (rv); 1607 } 1608 1609 void 1610 cs4280_clear_fifos(struct cs4280_softc *sc) 1611 { 1612 int pd = 0, cnt, n; 1613 u_int32_t mem; 1614 1615 /* 1616 * If device power down, power up the device and keep power down 1617 * state. 1618 */ 1619 mem = BA0READ4(sc, CS4280_CLKCR1); 1620 if (!(mem & CLKCR1_SWCE)) { 1621 printf("cs4280_clear_fifo: power down found.\n"); 1622 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1623 pd = 1; 1624 } 1625 BA0WRITE4(sc, CS4280_SERBWP, 0); 1626 for (cnt = 0; cnt < 256; cnt++) { 1627 n = 0; 1628 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1629 delay(1000); 1630 if (++n > 1000) { 1631 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1632 break; 1633 } 1634 } 1635 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1636 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1637 } 1638 if (pd) 1639 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1640 } 1641 1642 #if NMIDI > 0 1643 int 1644 cs4280_midi_open(void *addr, int flags, void (*iintr)(void, int), 1645 void (*ointr)(void *), void *arg) 1646 { 1647 struct cs4280_softc *sc = addr; 1648 u_int32_t mem; 1649 1650 DPRINTF(("midi_open\n")); 1651 sc->sc_iintr = iintr; 1652 sc->sc_ointr = ointr; 1653 sc->sc_arg = arg; 1654 1655 /* midi interrupt enable */ 1656 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1657 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1658 BA0WRITE4(sc, CS4280_MIDCR, mem); 1659 #ifdef CS4280_DEBUG 1660 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1661 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1662 return(EINVAL); 1663 } 1664 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1665 #endif 1666 return (0); 1667 } 1668 1669 void 1670 cs4280_midi_close(void *addr) 1671 { 1672 struct cs4280_softc *sc = addr; 1673 u_int32_t mem; 1674 1675 DPRINTF(("midi_close\n")); 1676 mem = BA0READ4(sc, CS4280_MIDCR); 1677 mem &= ~MIDCR_MASK; 1678 BA0WRITE4(sc, CS4280_MIDCR, mem); 1679 1680 sc->sc_iintr = 0; 1681 sc->sc_ointr = 0; 1682 } 1683 1684 int 1685 cs4280_midi_output(void *addr, int d) 1686 { 1687 struct cs4280_softc *sc = addr; 1688 u_int32_t mem; 1689 int x; 1690 1691 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1692 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1693 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1694 mem |= d & MIDWP_MASK; 1695 DPRINTFN(5,("midi_output d=0x%08x",d)); 1696 BA0WRITE4(sc, CS4280_MIDWP, mem); 1697 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1698 DPRINTF(("Bad write data: %d %d", 1699 mem, BA0READ4(sc, CS4280_MIDWP))); 1700 return(EIO); 1701 } 1702 return (0); 1703 } 1704 delay(MIDI_BUSY_DELAY); 1705 } 1706 return (EIO); 1707 } 1708 1709 void 1710 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1711 { 1712 mi->name = "CS4280 MIDI UART"; 1713 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1714 } 1715 1716 #endif 1717