1 /* $OpenBSD: cs4280.c,v 1.51 2016/12/26 17:38:14 jca Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/cs4280reg.h> 78 79 #include <sys/audioio.h> 80 #include <dev/audio_if.h> 81 82 #include <dev/ic/ac97.h> 83 84 #include <machine/bus.h> 85 86 #define CSCC_PCI_BA0 0x10 87 #define CSCC_PCI_BA1 0x14 88 89 struct cs4280_dma { 90 bus_dmamap_t map; 91 caddr_t addr; /* real dma buffer */ 92 caddr_t dum; /* dummy buffer for audio driver */ 93 bus_dma_segment_t segs[1]; 94 int nsegs; 95 size_t size; 96 struct cs4280_dma *next; 97 }; 98 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 99 #define BUFADDR(p) ((void *)((p)->dum)) 100 #define KERNADDR(p) ((void *)((p)->addr)) 101 102 /* 103 * Software state 104 */ 105 struct cs4280_softc { 106 struct device sc_dev; 107 108 pci_intr_handle_t * sc_ih; 109 110 /* I/O (BA0) */ 111 bus_space_tag_t ba0t; 112 bus_space_handle_t ba0h; 113 114 /* BA1 */ 115 bus_space_tag_t ba1t; 116 bus_space_handle_t ba1h; 117 118 /* DMA */ 119 bus_dma_tag_t sc_dmatag; 120 struct cs4280_dma *sc_dmas; 121 122 void (*sc_pintr)(void *); /* dma completion intr handler */ 123 void *sc_parg; /* arg for sc_intr() */ 124 char *sc_ps, *sc_pe, *sc_pn; 125 int sc_pcount; 126 int sc_pi; 127 struct cs4280_dma *sc_pdma; 128 char *sc_pbuf; 129 #ifdef DIAGNOSTIC 130 char sc_prun; 131 #endif 132 133 void (*sc_rintr)(void *); /* dma completion intr handler */ 134 void *sc_rarg; /* arg for sc_intr() */ 135 char *sc_rs, *sc_re, *sc_rn; 136 int sc_rcount; 137 int sc_ri; 138 struct cs4280_dma *sc_rdma; 139 char *sc_rbuf; 140 int sc_rparam; /* record format */ 141 #ifdef DIAGNOSTIC 142 char sc_rrun; 143 #endif 144 145 #if NMIDI > 0 146 void (*sc_iintr)(void *, int); /* midi input ready handler */ 147 void (*sc_ointr)(void *); /* midi output ready handler */ 148 void *sc_arg; 149 #endif 150 151 u_int32_t pctl; 152 u_int32_t cctl; 153 154 struct ac97_codec_if *codec_if; 155 struct ac97_host_if host_if; 156 157 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 158 }; 159 160 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 161 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 162 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 163 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 164 165 int cs4280_match(struct device *, void *, void *); 166 void cs4280_attach(struct device *, struct device *, void *); 167 int cs4280_activate(struct device *, int); 168 void cs4280_attachhook(struct device *); 169 int cs4280_intr(void *); 170 void cs4280_reset(void *); 171 int cs4280_download_image(struct cs4280_softc *); 172 173 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 174 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t, 175 struct cs4280_dma *); 176 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *); 177 178 #ifdef CS4280_DEBUG 179 int cs4280_check_images(struct cs4280_softc *); 180 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 181 u_int32_t); 182 #endif 183 184 struct cfdriver clcs_cd = { 185 NULL, "clcs", DV_DULL 186 }; 187 188 struct cfattach clcs_ca = { 189 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach, NULL, 190 cs4280_activate 191 }; 192 193 int cs4280_init(struct cs4280_softc *, int); 194 int cs4280_init2(struct cs4280_softc *, int); 195 int cs4280_open(void *, int); 196 void cs4280_close(void *); 197 198 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 199 int cs4280_round_blocksize(void *, int); 200 201 int cs4280_halt_output(void *); 202 int cs4280_halt_input(void *); 203 204 int cs4280_mixer_set_port(void *, mixer_ctrl_t *); 205 int cs4280_mixer_get_port(void *, mixer_ctrl_t *); 206 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip); 207 void *cs4280_malloc(void *, int, size_t, int, int); 208 void cs4280_free(void *, void *, int); 209 size_t cs4280_round_buffersize(void *, int, size_t); 210 int cs4280_get_props(void *); 211 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 212 void *, struct audio_params *); 213 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 214 void *, struct audio_params *); 215 216 217 void cs4280_set_dac_rate(struct cs4280_softc *, int ); 218 void cs4280_set_adc_rate(struct cs4280_softc *, int ); 219 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *, 220 char *); 221 int cs4280_src_wait(struct cs4280_softc *); 222 int cs4280_attach_codec(void *sc, struct ac97_codec_if *); 223 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d); 224 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d); 225 void cs4280_reset_codec(void *sc); 226 227 void cs4280_clear_fifos(struct cs4280_softc *); 228 229 #if NMIDI > 0 230 void cs4280_midi_close(void *); 231 void cs4280_midi_getinfo(void *, struct midi_info *); 232 int cs4280_midi_open(void *, int, void (*)(void *, int), 233 void (*)(void *), void *); 234 int cs4280_midi_output(void *, int); 235 #endif 236 237 struct audio_hw_if cs4280_hw_if = { 238 cs4280_open, 239 cs4280_close, 240 cs4280_set_params, 241 cs4280_round_blocksize, 242 NULL, 243 NULL, 244 NULL, 245 NULL, 246 NULL, 247 cs4280_halt_output, 248 cs4280_halt_input, 249 NULL, 250 NULL, 251 cs4280_mixer_set_port, 252 cs4280_mixer_get_port, 253 cs4280_query_devinfo, 254 cs4280_malloc, 255 cs4280_free, 256 cs4280_round_buffersize, 257 cs4280_get_props, 258 cs4280_trigger_output, 259 cs4280_trigger_input 260 }; 261 262 #if NMIDI > 0 263 struct midi_hw_if cs4280_midi_hw_if = { 264 cs4280_midi_open, 265 cs4280_midi_close, 266 cs4280_midi_output, 267 0, /* flush */ 268 cs4280_midi_getinfo, 269 0, /* ioctl */ 270 }; 271 #endif 272 273 274 const struct pci_matchid cs4280_devices[] = { 275 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, 276 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, 277 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 }, 278 }; 279 280 int 281 cs4280_match(struct device *parent, void *ma, void *aux) 282 { 283 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, 284 nitems(cs4280_devices))); 285 } 286 287 int 288 cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data) 289 { 290 struct cs4280_softc *sc = sc_; 291 int n; 292 293 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 294 /* 295 * Make sure that there is not data sitting around from a preivous 296 * uncompleted access. 297 */ 298 BA0READ4(sc, CS4280_ACSDA); 299 300 /* Set up AC97 control registers. */ 301 BA0WRITE4(sc, CS4280_ACCAD, add); 302 BA0WRITE4(sc, CS4280_ACCDA, 0); 303 BA0WRITE4(sc, CS4280_ACCTL, 304 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 305 306 if (cs4280_src_wait(sc) < 0) { 307 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 308 sc->sc_dev.dv_xname, add); 309 return (1); 310 } 311 312 /* wait for valid status bit is active */ 313 n = 0; 314 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 315 delay(1); 316 while (++n > 1000) { 317 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 318 sc->sc_dev.dv_xname, add); 319 return (1); 320 } 321 } 322 *data = BA0READ4(sc, CS4280_ACSDA); 323 DPRINTFN(5,("data=0x%04x\n", *data)); 324 return (0); 325 } 326 327 int 328 cs4280_write_codec(void *sc_, u_int8_t add, u_int16_t data) 329 { 330 struct cs4280_softc *sc = sc_; 331 332 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 333 BA0WRITE4(sc, CS4280_ACCAD, add); 334 BA0WRITE4(sc, CS4280_ACCDA, data); 335 BA0WRITE4(sc, CS4280_ACCTL, 336 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 337 338 if (cs4280_src_wait(sc) < 0) { 339 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 340 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 341 return (1); 342 } 343 return (0); 344 } 345 346 int 347 cs4280_src_wait(struct cs4280_softc *sc) 348 { 349 int n; 350 351 n = 0; 352 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 353 delay(1000); 354 if (++n > 1000) 355 return (-1); 356 } 357 return (0); 358 } 359 360 361 void 362 cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) 363 { 364 /* calculate capture rate: 365 * 366 * capture_coefficient_increment = -round(rate*128*65536/48000; 367 * capture_phase_increment = floor(48000*65536*1024/rate); 368 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 369 * cy = floor(cx/200); 370 * capture_sample_rate_correction = cx - 200*cy; 371 * capture_delay = ceil(24*48000/rate); 372 * capture_num_triplets = floor(65536*rate/24000); 373 * capture_group_length = 24000/GCD(rate, 24000); 374 * where GCD means "Greatest Common Divisor". 375 * 376 * capture_coefficient_increment, capture_phase_increment and 377 * capture_num_triplets are 32-bit signed quantities. 378 * capture_sample_rate_correction and capture_group_length are 379 * 16-bit signed quantities. 380 * capture_delay is a 14-bit unsigned quantity. 381 */ 382 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 383 u_int16_t csrc, cgl, cdlay; 384 385 /* XXX 386 * Even though, embedded_audio_spec says capture rate range 11025 to 387 * 48000, dhwiface.cpp says, 388 * 389 * "We can only decimate by up to a factor of 1/9th the hardware rate. 390 * Return an error if an attempt is made to stray outside that limit." 391 * 392 * so assume range as 48000/9 to 48000 393 */ 394 395 if (rate < 8000) 396 rate = 8000; 397 if (rate > 48000) 398 rate = 48000; 399 400 cx = rate << 16; 401 cci = cx / 48000; 402 cx -= cci * 48000; 403 cx <<= 7; 404 cci <<= 7; 405 cci += cx / 48000; 406 cci = - cci; 407 408 cx = 48000 << 16; 409 cpi = cx / rate; 410 cx -= cpi * rate; 411 cx <<= 10; 412 cpi <<= 10; 413 cy = cx / rate; 414 cpi += cy; 415 cx -= cy * rate; 416 417 cy = cx / 200; 418 csrc = cx - 200*cy; 419 420 cdlay = ((48000 * 24) + rate - 1) / rate; 421 #if 0 422 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 423 #endif 424 425 cnt = rate << 16; 426 cnt /= 24000; 427 428 cgl = 1; 429 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 430 if (((rate / tmp1) * tmp1) != rate) 431 cgl *= 2; 432 } 433 if (((rate / 3) * 3) != rate) 434 cgl *= 3; 435 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 436 if (((rate / tmp1) * tmp1) != rate) 437 cgl *= 5; 438 } 439 #if 0 440 /* XXX what manual says */ 441 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 442 tmp1 |= csrc<<16; 443 BA1WRITE4(sc, CS4280_CSRC, tmp1); 444 #else 445 /* suggested by cs461x.c (ALSA driver) */ 446 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 447 #endif 448 449 #if 0 450 /* I am confused. The sample rate calculation section says 451 * cci *is* 32-bit signed quantity but in the parameter description 452 * section, CCI only assigned 16bit. 453 * I believe size of the variable. 454 */ 455 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 456 tmp1 |= cci<<16; 457 BA1WRITE4(sc, CS4280_CCI, tmp1); 458 #else 459 BA1WRITE4(sc, CS4280_CCI, cci); 460 #endif 461 462 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 463 tmp1 |= cdlay <<18; 464 BA1WRITE4(sc, CS4280_CD, tmp1); 465 466 BA1WRITE4(sc, CS4280_CPI, cpi); 467 468 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 469 tmp1 |= cgl; 470 BA1WRITE4(sc, CS4280_CGL, tmp1); 471 472 BA1WRITE4(sc, CS4280_CNT, cnt); 473 474 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 475 tmp1 |= cgl; 476 BA1WRITE4(sc, CS4280_CGC, tmp1); 477 } 478 479 void 480 cs4280_set_dac_rate(struct cs4280_softc *sc, int rate) 481 { 482 /* 483 * playback rate may range from 8000Hz to 48000Hz 484 * 485 * play_phase_increment = floor(rate*65536*1024/48000) 486 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 487 * py=floor(px/200) 488 * play_sample_rate_correction = px - 200*py 489 * 490 * play_phase_increment is a 32bit signed quantity. 491 * play_sample_rate_correction is a 16bit signed quantity. 492 */ 493 int32_t ppi; 494 int16_t psrc; 495 u_int32_t px, py; 496 497 if (rate < 8000) 498 rate = 8000; 499 if (rate > 48000) 500 rate = 48000; 501 px = rate << 16; 502 ppi = px/48000; 503 px -= ppi*48000; 504 ppi <<= 10; 505 px <<= 10; 506 py = px / 48000; 507 ppi += py; 508 px -= py*48000; 509 py = px/200; 510 px -= py*200; 511 psrc = px; 512 #if 0 513 /* what manual says */ 514 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 515 BA1WRITE4(sc, CS4280_PSRC, 516 ( ((psrc<<16) & PSRC_MASK) | px )); 517 #else 518 /* suggested by cs461x.c (ALSA driver) */ 519 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 520 #endif 521 BA1WRITE4(sc, CS4280_PPI, ppi); 522 } 523 524 void 525 cs4280_attachhook(struct device *self) 526 { 527 struct cs4280_softc *sc = (struct cs4280_softc *)self; 528 mixer_ctrl_t ctl; 529 530 /* Initialization */ 531 if (cs4280_init2(sc, 1) != 0) 532 return; 533 534 printf("%s: firmware loaded\n", sc->sc_dev.dv_xname); 535 536 /* Turn mute off of DAC, CD and master volumes by default */ 537 ctl.type = AUDIO_MIXER_ENUM; 538 ctl.un.ord = 0; /* off */ 539 540 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 541 AudioNmaster, AudioNmute); 542 cs4280_mixer_set_port(sc, &ctl); 543 544 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 545 AudioNdac, AudioNmute); 546 cs4280_mixer_set_port(sc, &ctl); 547 548 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 549 AudioNcd, AudioNmute); 550 cs4280_mixer_set_port(sc, &ctl); 551 552 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 553 554 #if NMIDI > 0 555 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 556 #endif 557 } 558 559 void 560 cs4280_attach(struct device *parent, struct device *self, void *aux) 561 { 562 struct cs4280_softc *sc = (struct cs4280_softc *) self; 563 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 564 pci_chipset_tag_t pc = pa->pa_pc; 565 char const *intrstr; 566 pci_intr_handle_t ih; 567 u_int32_t mem; 568 569 /* Map I/O register */ 570 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 571 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 572 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 573 printf(": can't map BA0 space\n"); 574 return; 575 } 576 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 577 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 578 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 579 printf(": can't map BA1 space\n"); 580 return; 581 } 582 583 sc->sc_dmatag = pa->pa_dmat; 584 585 /* Get out of power save mode if needed. */ 586 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 587 588 /* LATENCY_TIMER setting */ 589 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 590 if ( PCI_LATTIMER(mem) < 32 ) { 591 mem &= 0xffff00ff; 592 mem |= 0x00002000; 593 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 594 } 595 596 /* Map and establish the interrupt. */ 597 if (pci_intr_map(pa, &ih)) { 598 printf(": couldn't map interrupt\n"); 599 return; 600 } 601 intrstr = pci_intr_string(pc, ih); 602 603 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO | IPL_MPSAFE, 604 cs4280_intr, sc, sc->sc_dev.dv_xname); 605 if (sc->sc_ih == NULL) { 606 printf(": couldn't establish interrupt"); 607 if (intrstr != NULL) 608 printf(" at %s", intrstr); 609 printf("\n"); 610 return; 611 } 612 printf(": %s\n", intrstr); 613 614 /* Initialization */ 615 if (cs4280_init(sc, 1) != 0) 616 return; 617 618 config_mountroot(self, cs4280_attachhook); 619 620 /* AC 97 attachement */ 621 sc->host_if.arg = sc; 622 sc->host_if.attach = cs4280_attach_codec; 623 sc->host_if.read = cs4280_read_codec; 624 sc->host_if.write = cs4280_write_codec; 625 sc->host_if.reset = cs4280_reset_codec; 626 627 if (ac97_attach(&sc->host_if) != 0) { 628 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 629 return; 630 } 631 } 632 633 int 634 cs4280_intr(void *p) 635 { 636 /* 637 * XXX 638 * 639 * Since CS4280 has only 4kB dma buffer and 640 * interrupt occurs every 2kB block, I create dummy buffer 641 * which returns to audio driver and actual dma buffer 642 * using in DMA transfer. 643 * 644 * 645 * ring buffer in audio.c is pointed by BUFADDR 646 * <------ ring buffer size == 64kB ------> 647 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 648 * |= = = =|= = = =|= = = =|= = = =|= = = =| 649 * | | | | | | <- call audio_intp every 650 * sc->sc_[pr]_count time. 651 * 652 * actual dma buffer is pointed by KERNADDR 653 * <-> dma buffer size = 4kB 654 * |= =| 655 * 656 * 657 */ 658 struct cs4280_softc *sc = p; 659 u_int32_t intr, mem; 660 char * empty_dma; 661 int handled = 0; 662 663 mtx_enter(&audio_lock); 664 /* grab interrupt register then clear it */ 665 intr = BA0READ4(sc, CS4280_HISR); 666 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 667 668 /* Playback Interrupt */ 669 if (intr & HISR_PINT) { 670 handled = 1; 671 mem = BA1READ4(sc, CS4280_PFIE); 672 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 673 if (sc->sc_pintr) { 674 if ((sc->sc_pi%sc->sc_pcount) == 0) 675 sc->sc_pintr(sc->sc_parg); 676 } else { 677 printf("unexpected play intr\n"); 678 } 679 /* copy buffer */ 680 ++sc->sc_pi; 681 empty_dma = sc->sc_pdma->addr; 682 if (sc->sc_pi&1) 683 empty_dma += CS4280_ICHUNK; 684 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 685 sc->sc_pn += CS4280_ICHUNK; 686 if (sc->sc_pn >= sc->sc_pe) 687 sc->sc_pn = sc->sc_ps; 688 BA1WRITE4(sc, CS4280_PFIE, mem); 689 } 690 /* Capture Interrupt */ 691 if (intr & HISR_CINT) { 692 int i; 693 int16_t rdata; 694 695 handled = 1; 696 mem = BA1READ4(sc, CS4280_CIE); 697 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 698 ++sc->sc_ri; 699 empty_dma = sc->sc_rdma->addr; 700 if ((sc->sc_ri&1) == 0) 701 empty_dma += CS4280_ICHUNK; 702 703 /* 704 * XXX 705 * I think this audio data conversion should be 706 * happened in upper layer, but I put this here 707 * since there is no conversion function available. 708 */ 709 switch(sc->sc_rparam) { 710 case CF_16BIT_STEREO: 711 /* just copy it */ 712 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 713 sc->sc_rn += CS4280_ICHUNK; 714 break; 715 case CF_16BIT_MONO: 716 for (i = 0; i < 512; i++) { 717 rdata = *((int16_t *)empty_dma)>>1; 718 empty_dma += 2; 719 rdata += *((int16_t *)empty_dma)>>1; 720 empty_dma += 2; 721 *((int16_t *)sc->sc_rn) = rdata; 722 sc->sc_rn += 2; 723 } 724 break; 725 case CF_8BIT_STEREO: 726 for (i = 0; i < 512; i++) { 727 rdata = *((int16_t*)empty_dma); 728 empty_dma += 2; 729 *sc->sc_rn++ = rdata >> 8; 730 rdata = *((int16_t*)empty_dma); 731 empty_dma += 2; 732 *sc->sc_rn++ = rdata >> 8; 733 } 734 break; 735 case CF_8BIT_MONO: 736 for (i = 0; i < 512; i++) { 737 rdata = *((int16_t*)empty_dma) >>1; 738 empty_dma += 2; 739 rdata += *((int16_t*)empty_dma) >>1; 740 empty_dma += 2; 741 *sc->sc_rn++ = rdata >>8; 742 } 743 break; 744 default: 745 /* Should not reach here */ 746 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 747 } 748 if (sc->sc_rn >= sc->sc_re) 749 sc->sc_rn = sc->sc_rs; 750 BA1WRITE4(sc, CS4280_CIE, mem); 751 if (sc->sc_rintr) { 752 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 753 sc->sc_rintr(sc->sc_rarg); 754 } else { 755 printf("unexpected record intr\n"); 756 } 757 } 758 759 #if NMIDI > 0 760 /* Midi port Interrupt */ 761 if (intr & HISR_MIDI) { 762 int data; 763 764 handled = 1; 765 DPRINTF(("i: %d: ", 766 BA0READ4(sc, CS4280_MIDSR))); 767 /* Read the received data */ 768 while ((sc->sc_iintr != NULL) && 769 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 770 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 771 DPRINTF(("r:%x\n",data)); 772 sc->sc_iintr(sc->sc_arg, data); 773 } 774 775 /* Write the data */ 776 #if 1 777 /* XXX: 778 * It seems "Transmit Buffer Full" never activate until EOI 779 * is delivered. Shall I throw EOI top of this routine ? 780 */ 781 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 782 DPRINTF(("w: ")); 783 if (sc->sc_ointr != NULL) 784 sc->sc_ointr(sc->sc_arg); 785 } 786 #else 787 while ((sc->sc_ointr != NULL) && 788 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 789 DPRINTF(("w: ")); 790 sc->sc_ointr(sc->sc_arg); 791 } 792 #endif 793 DPRINTF(("\n")); 794 } 795 #endif 796 mtx_leave(&audio_lock); 797 return handled; 798 } 799 800 801 /* Download Proceessor Code and Data image */ 802 803 int 804 cs4280_download(struct cs4280_softc *sc, const u_int32_t *src, u_int32_t offset, 805 u_int32_t len) 806 { 807 u_int32_t ctr; 808 809 #ifdef CS4280_DEBUG 810 u_int32_t con, data; 811 u_int8_t c0,c1,c2,c3; 812 #endif 813 if ((offset&3) || (len&3)) 814 return (-1); 815 816 len /= sizeof(u_int32_t); 817 for (ctr = 0; ctr < len; ctr++) { 818 /* XXX: 819 * I cannot confirm this is the right thing or not 820 * on BIG-ENDIAN machines. 821 */ 822 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 823 #ifdef CS4280_DEBUG 824 data = htole32(*(src+ctr)); 825 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 826 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 827 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 828 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 829 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 830 if (data != con ) { 831 printf("0x%06x: write=0x%08x read=0x%08x\n", 832 offset+ctr*4, data, con); 833 return (-1); 834 } 835 #endif 836 } 837 return (0); 838 } 839 840 struct BA1struct *BA1Struct; 841 842 int 843 cs4280_download_image(struct cs4280_softc *sc) 844 { 845 int idx, err = 0; 846 u_int32_t offset = 0; 847 static u_char *cs4280_firmware; 848 static size_t cs4280_firmwarelen; 849 850 if (cs4280_firmware == NULL) { 851 err = loadfirmware("cs4280", &cs4280_firmware, 852 &cs4280_firmwarelen); 853 if (err) 854 return (err); 855 } 856 857 BA1Struct = (struct BA1struct *)cs4280_firmware; 858 859 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 860 err = cs4280_download(sc, &BA1Struct->map[offset], 861 BA1Struct->memory[idx].offset, BA1Struct->memory[idx].size); 862 if (err != 0) { 863 printf("%s: load_image failed at %d\n", 864 sc->sc_dev.dv_xname, idx); 865 return (-1); 866 } 867 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 868 } 869 return (err); 870 } 871 872 #ifdef CS4280_DEBUG 873 int 874 cs4280_checkimage(struct cs4280_softc *sc, u_int32_t *src, u_int32_t offset, 875 u_int32_t len) 876 { 877 u_int32_t ctr, data; 878 int err = 0; 879 880 if ((offset&3) || (len&3)) 881 return -1; 882 883 len /= sizeof(u_int32_t); 884 for (ctr = 0; ctr < len; ctr++) { 885 /* I cannot confirm this is the right thing 886 * on BIG-ENDIAN machines 887 */ 888 data = BA1READ4(sc, offset+ctr*4); 889 if (data != htole32(*(src+ctr))) { 890 printf("0x%06x: 0x%08x(0x%08x)\n", 891 offset+ctr*4, data, *(src+ctr)); 892 *(src+ctr) = data; 893 ++err; 894 } 895 } 896 return (err); 897 } 898 899 int 900 cs4280_check_images(struct cs4280_softc *sc) 901 { 902 int idx, err; 903 u_int32_t offset = 0; 904 905 err = 0; 906 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 907 for (idx = 0; idx < 1; ++idx) { 908 err = cs4280_checkimage(sc, &BA1Struct->map[offset], 909 BA1Struct->memory[idx].offset, 910 BA1Struct->memory[idx].size); 911 if (err != 0) { 912 printf("%s: check_image failed at %d\n", 913 sc->sc_dev.dv_xname, idx); 914 } 915 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 916 } 917 return (err); 918 } 919 920 #endif 921 922 int 923 cs4280_attach_codec(void *sc_, struct ac97_codec_if *codec_if) 924 { 925 struct cs4280_softc *sc = sc_; 926 927 sc->codec_if = codec_if; 928 return (0); 929 } 930 931 void 932 cs4280_reset_codec(void *sc_) 933 { 934 struct cs4280_softc *sc = sc_; 935 int n; 936 937 /* Reset codec */ 938 BA0WRITE4(sc, CS4280_ACCTL, 0); 939 delay(100); /* delay 100us */ 940 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 941 942 /* 943 * It looks like we do the following procedure, too 944 */ 945 946 /* Enable AC-link sync generation */ 947 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 948 delay(50*1000); /* XXX delay 50ms */ 949 950 /* Assert valid frame signal */ 951 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 952 953 /* Wait for valid AC97 input slot */ 954 n = 0; 955 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 956 delay(1000); 957 if (++n > 1000) { 958 printf("reset_codec: AC97 inputs slot ready timeout\n"); 959 return; 960 } 961 } 962 } 963 964 965 /* Processor Soft Reset */ 966 void 967 cs4280_reset(void *sc_) 968 { 969 struct cs4280_softc *sc = sc_; 970 971 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 972 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 973 delay(100); 974 /* Clear RSTSP bit in SPCR */ 975 BA1WRITE4(sc, CS4280_SPCR, 0); 976 /* enable DMA reqest */ 977 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 978 } 979 980 int 981 cs4280_open(void *addr, int flags) 982 { 983 return (0); 984 } 985 986 void 987 cs4280_close(void *addr) 988 { 989 struct cs4280_softc *sc = addr; 990 991 /* XXX: already called in audio_close() */ 992 cs4280_halt_output(sc); 993 cs4280_halt_input(sc); 994 995 sc->sc_pintr = 0; 996 sc->sc_rintr = 0; 997 } 998 999 int 1000 cs4280_set_params(void *addr, int setmode, int usemode, 1001 struct audio_params *play, struct audio_params *rec) 1002 { 1003 struct cs4280_softc *sc = addr; 1004 struct audio_params *p; 1005 int mode; 1006 1007 for (mode = AUMODE_RECORD; mode != -1; 1008 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1009 if ((setmode & mode) == 0) 1010 continue; 1011 1012 p = mode == AUMODE_PLAY ? play : rec; 1013 if (p == play) { 1014 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1015 p->sample_rate, p->precision, p->channels)); 1016 } else { 1017 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1018 p->sample_rate, p->precision, p->channels)); 1019 } 1020 /* play back data format may be 8- or 16-bit and 1021 * either stereo or mono. 1022 * playback rate may range from 8000Hz to 48000Hz 1023 * 1024 * capture data format must be 16bit stereo 1025 * and sample rate range from 11025Hz to 48000Hz. 1026 * 1027 * XXX: it looks like to work with 8000Hz, 1028 * although data sheets say lower limit is 1029 * 11025 Hz. 1030 */ 1031 if (p->sample_rate < 8000) 1032 p->sample_rate = 8000; 1033 if (p->sample_rate > 48000) 1034 p->sample_rate = 48000; 1035 if (p->precision > 16) 1036 p->precision = 16; 1037 if (p->channels > 2) 1038 p->channels = 2; 1039 1040 /* capturing data is slinear */ 1041 switch (p->encoding) { 1042 case AUDIO_ENCODING_SLINEAR_LE: 1043 break; 1044 default: 1045 return (EINVAL); 1046 } 1047 p->bps = AUDIO_BPS(p->precision); 1048 p->msb = 1; 1049 } 1050 1051 /* set sample rate */ 1052 cs4280_set_dac_rate(sc, play->sample_rate); 1053 cs4280_set_adc_rate(sc, rec->sample_rate); 1054 return (0); 1055 } 1056 1057 int 1058 cs4280_round_blocksize(void *hdl, int blk) 1059 { 1060 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1061 } 1062 1063 size_t 1064 cs4280_round_buffersize(void *addr, int direction, size_t size) 1065 { 1066 /* although real dma buffer size is 4KB, 1067 * let the audio.c driver use a larger buffer. 1068 * ( suggested by Lennart Augustsson. ) 1069 */ 1070 return (size); 1071 } 1072 1073 int 1074 cs4280_get_props(void *hdl) 1075 { 1076 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1077 #ifdef notyet 1078 /* XXX 1079 * How can I mmap ? 1080 */ 1081 AUDIO_PROP_MMAP 1082 #endif 1083 1084 } 1085 1086 int 1087 cs4280_mixer_get_port(void *addr, mixer_ctrl_t *cp) 1088 { 1089 struct cs4280_softc *sc = addr; 1090 1091 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1092 } 1093 1094 int 1095 cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip) 1096 { 1097 struct cs4280_softc *sc = addr; 1098 1099 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1100 } 1101 1102 int 1103 cs4280_get_portnum_by_name(struct cs4280_softc *sc, char *class, char *device, 1104 char *qualifier) 1105 { 1106 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1107 device, qualifier)); 1108 } 1109 1110 int 1111 cs4280_halt_output(void *addr) 1112 { 1113 struct cs4280_softc *sc = addr; 1114 u_int32_t mem; 1115 1116 mtx_enter(&audio_lock); 1117 mem = BA1READ4(sc, CS4280_PCTL); 1118 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1119 #ifdef DIAGNOSTIC 1120 sc->sc_prun = 0; 1121 #endif 1122 mtx_leave(&audio_lock); 1123 return (0); 1124 } 1125 1126 int 1127 cs4280_halt_input(void *addr) 1128 { 1129 struct cs4280_softc *sc = addr; 1130 u_int32_t mem; 1131 1132 mtx_enter(&audio_lock); 1133 mem = BA1READ4(sc, CS4280_CCTL); 1134 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1135 #ifdef DIAGNOSTIC 1136 sc->sc_rrun = 0; 1137 #endif 1138 mtx_leave(&audio_lock); 1139 return (0); 1140 } 1141 1142 int 1143 cs4280_mixer_set_port(void *addr, mixer_ctrl_t *cp) 1144 { 1145 struct cs4280_softc *sc = addr; 1146 int val; 1147 1148 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1149 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1150 return (val); 1151 } 1152 1153 1154 int 1155 cs4280_freemem(struct cs4280_softc *sc, struct cs4280_dma *p) 1156 { 1157 bus_dmamap_unload(sc->sc_dmatag, p->map); 1158 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1159 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1160 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1161 return (0); 1162 } 1163 1164 int 1165 cs4280_allocmem(struct cs4280_softc *sc, size_t size, size_t align, 1166 struct cs4280_dma *p) 1167 { 1168 int error; 1169 1170 /* XXX */ 1171 p->size = size; 1172 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1173 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1174 &p->nsegs, BUS_DMA_NOWAIT); 1175 if (error) { 1176 printf("%s: unable to allocate dma, error=%d\n", 1177 sc->sc_dev.dv_xname, error); 1178 return (error); 1179 } 1180 1181 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1182 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1183 if (error) { 1184 printf("%s: unable to map dma, error=%d\n", 1185 sc->sc_dev.dv_xname, error); 1186 goto free; 1187 } 1188 1189 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1190 0, BUS_DMA_NOWAIT, &p->map); 1191 if (error) { 1192 printf("%s: unable to create dma map, error=%d\n", 1193 sc->sc_dev.dv_xname, error); 1194 goto unmap; 1195 } 1196 1197 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1198 BUS_DMA_NOWAIT); 1199 if (error) { 1200 printf("%s: unable to load dma map, error=%d\n", 1201 sc->sc_dev.dv_xname, error); 1202 goto destroy; 1203 } 1204 return (0); 1205 1206 destroy: 1207 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1208 unmap: 1209 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1210 free: 1211 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1212 return (error); 1213 } 1214 1215 1216 void * 1217 cs4280_malloc(void *addr, int direction, size_t size, int pool, int flags) 1218 { 1219 struct cs4280_softc *sc = addr; 1220 struct cs4280_dma *p; 1221 caddr_t q; 1222 int error; 1223 1224 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1225 q = malloc(size, pool, flags); 1226 if (!q) 1227 return (0); 1228 p = malloc(sizeof(*p), pool, flags); 1229 if (!p) { 1230 free(q,pool, 0); 1231 return (0); 1232 } 1233 /* 1234 * cs4280 has fixed 4kB buffer 1235 */ 1236 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1237 1238 if (error) { 1239 free(q, pool, 0); 1240 free(p, pool, 0); 1241 return (0); 1242 } 1243 1244 p->next = sc->sc_dmas; 1245 sc->sc_dmas = p; 1246 p->dum = q; /* return to audio driver */ 1247 1248 return (p->dum); 1249 } 1250 1251 void 1252 cs4280_free(void *addr, void *ptr, int pool) 1253 { 1254 struct cs4280_softc *sc = addr; 1255 struct cs4280_dma **pp, *p; 1256 1257 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1258 if (BUFADDR(p) == ptr) { 1259 cs4280_freemem(sc, p); 1260 *pp = p->next; 1261 free(p->dum, pool, 0); 1262 free(p, pool, 0); 1263 return; 1264 } 1265 } 1266 } 1267 1268 int 1269 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 1270 void (*intr)(void *), void *arg, struct audio_params *param) 1271 { 1272 struct cs4280_softc *sc = addr; 1273 u_int32_t pfie, pctl, mem, pdtc; 1274 struct cs4280_dma *p; 1275 1276 #ifdef DIAGNOSTIC 1277 if (sc->sc_prun) 1278 printf("cs4280_trigger_output: already running\n"); 1279 sc->sc_prun = 1; 1280 #endif 1281 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1282 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1283 sc->sc_pintr = intr; 1284 sc->sc_parg = arg; 1285 1286 /* stop playback DMA */ 1287 mem = BA1READ4(sc, CS4280_PCTL); 1288 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1289 1290 /* setup PDTC */ 1291 pdtc = BA1READ4(sc, CS4280_PDTC); 1292 pdtc &= ~PDTC_MASK; 1293 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1294 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1295 1296 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 1297 param->precision, param->channels, 1298 param->encoding)); 1299 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1300 ; 1301 if (p == NULL) { 1302 printf("cs4280_trigger_output: bad addr %p\n", start); 1303 return (EINVAL); 1304 } 1305 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1306 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1307 "4kB align\n", DMAADDR(p)); 1308 return (EINVAL); 1309 } 1310 1311 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1312 sc->sc_ps = (char *)start; 1313 sc->sc_pe = (char *)end; 1314 sc->sc_pdma = p; 1315 sc->sc_pbuf = KERNADDR(p); 1316 sc->sc_pi = 0; 1317 sc->sc_pn = sc->sc_ps; 1318 if (blksize >= CS4280_DCHUNK) { 1319 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1320 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1321 ++sc->sc_pi; 1322 } else { 1323 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1324 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1325 } 1326 1327 /* initiate playback dma */ 1328 mtx_enter(&audio_lock); 1329 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1330 1331 /* set PFIE */ 1332 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1333 1334 if (param->precision == 8) 1335 pfie |= PFIE_8BIT; 1336 if (param->channels == 1) 1337 pfie |= PFIE_MONO; 1338 1339 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1340 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1341 pfie |= PFIE_SWAPPED; 1342 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1343 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1344 pfie |= PFIE_UNSIGNED; 1345 1346 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1347 1348 cs4280_set_dac_rate(sc, param->sample_rate); 1349 1350 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1351 pctl |= sc->pctl; 1352 BA1WRITE4(sc, CS4280_PCTL, pctl); 1353 mtx_leave(&audio_lock); 1354 return (0); 1355 } 1356 1357 int 1358 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 1359 void (*intr)(void *), void *arg, struct audio_params *param) 1360 { 1361 struct cs4280_softc *sc = addr; 1362 u_int32_t cctl, cie; 1363 struct cs4280_dma *p; 1364 1365 #ifdef DIAGNOSTIC 1366 if (sc->sc_rrun) 1367 printf("cs4280_trigger_input: already running\n"); 1368 sc->sc_rrun = 1; 1369 #endif 1370 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1371 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1372 sc->sc_rintr = intr; 1373 sc->sc_rarg = arg; 1374 1375 sc->sc_ri = 0; 1376 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1377 sc->sc_rs = (char *)start; 1378 sc->sc_re = (char *)end; 1379 sc->sc_rn = sc->sc_rs; 1380 1381 /* setup format information for internal converter */ 1382 sc->sc_rparam = 0; 1383 if (param->precision == 8) { 1384 sc->sc_rparam += CF_8BIT; 1385 sc->sc_rcount <<= 1; 1386 } 1387 if (param->channels == 1) { 1388 sc->sc_rparam += CF_MONO; 1389 sc->sc_rcount <<= 1; 1390 } 1391 1392 /* stop capture DMA */ 1393 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1394 BA1WRITE4(sc, CS4280_CCTL, cctl); 1395 1396 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1397 ; 1398 if (!p) { 1399 printf("cs4280_trigger_input: bad addr %p\n", start); 1400 return (EINVAL); 1401 } 1402 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1403 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1404 "4kB align\n", DMAADDR(p)); 1405 return (EINVAL); 1406 } 1407 sc->sc_rdma = p; 1408 sc->sc_rbuf = KERNADDR(p); 1409 1410 /* initiate capture dma */ 1411 mtx_enter(&audio_lock); 1412 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1413 1414 /* set CIE */ 1415 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1416 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1417 1418 cs4280_set_adc_rate(sc, param->sample_rate); 1419 1420 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1421 cctl |= sc->cctl; 1422 BA1WRITE4(sc, CS4280_CCTL, cctl); 1423 mtx_leave(&audio_lock); 1424 return (0); 1425 } 1426 1427 1428 int 1429 cs4280_init(struct cs4280_softc *sc, int init) 1430 { 1431 int n; 1432 u_int32_t mem; 1433 1434 /* Start PLL out in known state */ 1435 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1436 /* Start serial ports out in known state */ 1437 BA0WRITE4(sc, CS4280_SERMC1, 0); 1438 1439 /* Specify type of CODEC */ 1440 /* XXX should no be here */ 1441 #define SERACC_CODEC_TYPE_1_03 1442 #ifdef SERACC_CODEC_TYPE_1_03 1443 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1444 #else 1445 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1446 #endif 1447 1448 /* Reset codec */ 1449 BA0WRITE4(sc, CS4280_ACCTL, 0); 1450 delay(100); /* delay 100us */ 1451 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1452 1453 /* Enable AC-link sync generation */ 1454 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1455 delay(50*1000); /* delay 50ms */ 1456 1457 /* Set the serial port timing configuration */ 1458 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1459 1460 /* Setup clock control */ 1461 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1462 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1463 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1464 1465 /* Power up the PLL */ 1466 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1467 delay(50*1000); /* delay 50ms */ 1468 1469 /* Turn on clock */ 1470 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1471 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1472 1473 /* Set the serial port FIFO pointer to the 1474 * first sample in FIFO. (not documented) */ 1475 cs4280_clear_fifos(sc); 1476 1477 #if 0 1478 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1479 BA0WRITE4(sc, CS4280_SERBSP, 0); 1480 #endif 1481 1482 /* Configure the serial port */ 1483 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1484 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1485 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1486 1487 /* Wait for CODEC ready */ 1488 n = 0; 1489 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1490 delay(125); 1491 if (++n > 1000) { 1492 printf("%s: codec ready timeout\n", 1493 sc->sc_dev.dv_xname); 1494 return(1); 1495 } 1496 } 1497 1498 /* Assert valid frame signal */ 1499 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1500 1501 /* Wait for valid AC97 input slot */ 1502 n = 0; 1503 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1504 (ACISV_ISV3 | ACISV_ISV4)) { 1505 delay(1000); 1506 if (++n > 1000) { 1507 printf("AC97 inputs slot ready timeout\n"); 1508 return(1); 1509 } 1510 } 1511 1512 /* Set AC97 output slot valid signals */ 1513 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1514 1515 /* reset the processor */ 1516 cs4280_reset(sc); 1517 return (0); 1518 } 1519 1520 int 1521 cs4280_init2(struct cs4280_softc *sc, int init) 1522 { 1523 int n; 1524 u_int32_t mem; 1525 1526 /* Download the image to the processor */ 1527 if (cs4280_download_image(sc) != 0) { 1528 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1529 return(1); 1530 } 1531 1532 /* Save playback parameter and then write zero. 1533 * this ensures that DMA doesn't immediately occur upon 1534 * starting the processor core 1535 */ 1536 mem = BA1READ4(sc, CS4280_PCTL); 1537 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1538 cs4280_halt_output(sc); 1539 1540 /* Save capture parameter and then write zero. 1541 * this ensures that DMA doesn't immediately occur upon 1542 * starting the processor core 1543 */ 1544 mem = BA1READ4(sc, CS4280_CCTL); 1545 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1546 cs4280_halt_input(sc); 1547 1548 /* MSH: need to power up ADC and DAC? */ 1549 1550 /* Processor Startup Procedure */ 1551 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1552 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1553 1554 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1555 n = 0; 1556 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1557 delay(10); 1558 if (++n > 1000) { 1559 printf("SPCR 1->0 transition timeout\n"); 1560 return(1); 1561 } 1562 } 1563 1564 n = 0; 1565 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1566 delay(10); 1567 if (++n > 1000) { 1568 printf("SPCS 0->1 transition timeout\n"); 1569 return(1); 1570 } 1571 } 1572 /* Processor is now running !!! */ 1573 1574 /* Setup volume */ 1575 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1576 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1577 1578 /* Interrupt enable */ 1579 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1580 1581 /* playback interrupt enable */ 1582 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1583 mem |= PFIE_PI_ENABLE; 1584 BA1WRITE4(sc, CS4280_PFIE, mem); 1585 /* capture interrupt enable */ 1586 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1587 mem |= CIE_CI_ENABLE; 1588 BA1WRITE4(sc, CS4280_CIE, mem); 1589 1590 #if NMIDI > 0 1591 /* Reset midi port */ 1592 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1593 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1594 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1595 /* midi interrupt enable */ 1596 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1597 BA0WRITE4(sc, CS4280_MIDCR, mem); 1598 #endif 1599 return(0); 1600 } 1601 1602 int 1603 cs4280_activate(struct device *self, int act) 1604 { 1605 struct cs4280_softc *sc = (struct cs4280_softc *)self; 1606 int rv = 0; 1607 1608 switch (act) { 1609 case DVACT_SUSPEND: 1610 /* should I powerdown here ? */ 1611 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1612 break; 1613 case DVACT_RESUME: 1614 cs4280_close(sc); 1615 cs4280_init(sc, 0); 1616 cs4280_init2(sc, 0); 1617 ac97_resume(&sc->host_if, sc->codec_if); 1618 rv = config_activate_children(self, act); 1619 break; 1620 default: 1621 rv = config_activate_children(self, act); 1622 break; 1623 } 1624 return (rv); 1625 } 1626 1627 void 1628 cs4280_clear_fifos(struct cs4280_softc *sc) 1629 { 1630 int pd = 0, cnt, n; 1631 u_int32_t mem; 1632 1633 /* 1634 * If device power down, power up the device and keep power down 1635 * state. 1636 */ 1637 mem = BA0READ4(sc, CS4280_CLKCR1); 1638 if (!(mem & CLKCR1_SWCE)) { 1639 printf("cs4280_clear_fifo: power down found.\n"); 1640 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1641 pd = 1; 1642 } 1643 BA0WRITE4(sc, CS4280_SERBWP, 0); 1644 for (cnt = 0; cnt < 256; cnt++) { 1645 n = 0; 1646 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1647 delay(1000); 1648 if (++n > 1000) { 1649 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1650 break; 1651 } 1652 } 1653 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1654 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1655 } 1656 if (pd) 1657 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1658 } 1659 1660 #if NMIDI > 0 1661 int 1662 cs4280_midi_open(void *addr, int flags, void (*iintr)(void, int), 1663 void (*ointr)(void *), void *arg) 1664 { 1665 struct cs4280_softc *sc = addr; 1666 u_int32_t mem; 1667 1668 DPRINTF(("midi_open\n")); 1669 sc->sc_iintr = iintr; 1670 sc->sc_ointr = ointr; 1671 sc->sc_arg = arg; 1672 1673 /* midi interrupt enable */ 1674 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1675 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1676 BA0WRITE4(sc, CS4280_MIDCR, mem); 1677 #ifdef CS4280_DEBUG 1678 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1679 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1680 return(EINVAL); 1681 } 1682 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1683 #endif 1684 return (0); 1685 } 1686 1687 void 1688 cs4280_midi_close(void *addr) 1689 { 1690 struct cs4280_softc *sc = addr; 1691 u_int32_t mem; 1692 1693 DPRINTF(("midi_close\n")); 1694 mem = BA0READ4(sc, CS4280_MIDCR); 1695 mem &= ~MIDCR_MASK; 1696 BA0WRITE4(sc, CS4280_MIDCR, mem); 1697 1698 sc->sc_iintr = 0; 1699 sc->sc_ointr = 0; 1700 } 1701 1702 int 1703 cs4280_midi_output(void *addr, int d) 1704 { 1705 struct cs4280_softc *sc = addr; 1706 u_int32_t mem; 1707 int x; 1708 1709 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1710 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1711 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1712 mem |= d & MIDWP_MASK; 1713 DPRINTFN(5,("midi_output d=0x%08x",d)); 1714 BA0WRITE4(sc, CS4280_MIDWP, mem); 1715 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1716 DPRINTF(("Bad write data: %d %d", 1717 mem, BA0READ4(sc, CS4280_MIDWP))); 1718 return(EIO); 1719 } 1720 return (0); 1721 } 1722 delay(MIDI_BUSY_DELAY); 1723 } 1724 return (EIO); 1725 } 1726 1727 void 1728 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1729 { 1730 mi->name = "CS4280 MIDI UART"; 1731 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1732 } 1733 1734 #endif 1735