1 /* $OpenBSD: cs4280.c,v 1.31 2008/05/29 02:10:01 jakemsr Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/cs4280reg.h> 78 79 #include <sys/audioio.h> 80 #include <dev/audio_if.h> 81 #include <dev/midi_if.h> 82 #include <dev/mulaw.h> 83 #include <dev/auconv.h> 84 85 #include <dev/ic/ac97.h> 86 87 #include <machine/bus.h> 88 89 #define CSCC_PCI_BA0 0x10 90 #define CSCC_PCI_BA1 0x14 91 92 struct cs4280_dma { 93 bus_dmamap_t map; 94 caddr_t addr; /* real dma buffer */ 95 caddr_t dum; /* dummy buffer for audio driver */ 96 bus_dma_segment_t segs[1]; 97 int nsegs; 98 size_t size; 99 struct cs4280_dma *next; 100 }; 101 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 102 #define BUFADDR(p) ((void *)((p)->dum)) 103 #define KERNADDR(p) ((void *)((p)->addr)) 104 105 /* 106 * Software state 107 */ 108 struct cs4280_softc { 109 struct device sc_dev; 110 111 pci_intr_handle_t * sc_ih; 112 113 /* I/O (BA0) */ 114 bus_space_tag_t ba0t; 115 bus_space_handle_t ba0h; 116 117 /* BA1 */ 118 bus_space_tag_t ba1t; 119 bus_space_handle_t ba1h; 120 121 /* DMA */ 122 bus_dma_tag_t sc_dmatag; 123 struct cs4280_dma *sc_dmas; 124 125 void (*sc_pintr)(void *); /* dma completion intr handler */ 126 void *sc_parg; /* arg for sc_intr() */ 127 char *sc_ps, *sc_pe, *sc_pn; 128 int sc_pcount; 129 int sc_pi; 130 struct cs4280_dma *sc_pdma; 131 char *sc_pbuf; 132 #ifdef DIAGNOSTIC 133 char sc_prun; 134 #endif 135 136 void (*sc_rintr)(void *); /* dma completion intr handler */ 137 void *sc_rarg; /* arg for sc_intr() */ 138 char *sc_rs, *sc_re, *sc_rn; 139 int sc_rcount; 140 int sc_ri; 141 struct cs4280_dma *sc_rdma; 142 char *sc_rbuf; 143 int sc_rparam; /* record format */ 144 #ifdef DIAGNOSTIC 145 char sc_rrun; 146 #endif 147 148 #if NMIDI > 0 149 void (*sc_iintr)(void *, int); /* midi input ready handler */ 150 void (*sc_ointr)(void *); /* midi output ready handler */ 151 void *sc_arg; 152 #endif 153 154 u_int32_t pctl; 155 u_int32_t cctl; 156 157 struct ac97_codec_if *codec_if; 158 struct ac97_host_if host_if; 159 160 char sc_suspend; 161 void *sc_powerhook; /* Power Hook */ 162 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 163 }; 164 165 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 166 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 167 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 168 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 169 170 int cs4280_match(struct device *, void *, void *); 171 void cs4280_attach(struct device *, struct device *, void *); 172 void cs4280_attachhook(void *xsc); 173 int cs4280_intr(void *); 174 void cs4280_reset(void *); 175 int cs4280_download_image(struct cs4280_softc *); 176 177 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 178 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t, 179 struct cs4280_dma *); 180 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *); 181 182 #ifdef CS4280_DEBUG 183 int cs4280_check_images(struct cs4280_softc *); 184 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 185 u_int32_t); 186 #endif 187 188 struct cfdriver clcs_cd = { 189 NULL, "clcs", DV_DULL 190 }; 191 192 struct cfattach clcs_ca = { 193 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach 194 }; 195 196 int cs4280_init(struct cs4280_softc *, int); 197 int cs4280_init2(struct cs4280_softc *, int); 198 int cs4280_open(void *, int); 199 void cs4280_close(void *); 200 201 int cs4280_query_encoding(void *, struct audio_encoding *); 202 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 203 int cs4280_round_blocksize(void *, int); 204 void cs4280_get_default_params(void *, int, struct audio_params *); 205 206 int cs4280_halt_output(void *); 207 int cs4280_halt_input(void *); 208 209 int cs4280_getdev(void *, struct audio_device *); 210 211 int cs4280_mixer_set_port(void *, mixer_ctrl_t *); 212 int cs4280_mixer_get_port(void *, mixer_ctrl_t *); 213 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip); 214 void *cs4280_malloc(void *, int, size_t, int, int); 215 void cs4280_free(void *, void *, int); 216 size_t cs4280_round_buffersize(void *, int, size_t); 217 paddr_t cs4280_mappage(void *, void *, off_t, int); 218 int cs4280_get_props(void *); 219 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 220 void *, struct audio_params *); 221 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *); 223 224 225 void cs4280_set_dac_rate(struct cs4280_softc *, int ); 226 void cs4280_set_adc_rate(struct cs4280_softc *, int ); 227 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *, 228 char *); 229 int cs4280_src_wait(struct cs4280_softc *); 230 int cs4280_attach_codec(void *sc, struct ac97_codec_if *); 231 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d); 232 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d); 233 void cs4280_reset_codec(void *sc); 234 235 void cs4280_power(int, void *); 236 237 void cs4280_clear_fifos(struct cs4280_softc *); 238 239 #if NMIDI > 0 240 void cs4280_midi_close(void *); 241 void cs4280_midi_getinfo(void *, struct midi_info *); 242 int cs4280_midi_open(void *, int, void (*)(void *, int), 243 void (*)(void *), void *); 244 int cs4280_midi_output(void *, int); 245 #endif 246 247 struct audio_hw_if cs4280_hw_if = { 248 cs4280_open, 249 cs4280_close, 250 NULL, 251 cs4280_query_encoding, 252 cs4280_set_params, 253 cs4280_round_blocksize, 254 NULL, 255 NULL, 256 NULL, 257 NULL, 258 NULL, 259 cs4280_halt_output, 260 cs4280_halt_input, 261 NULL, 262 cs4280_getdev, 263 NULL, 264 cs4280_mixer_set_port, 265 cs4280_mixer_get_port, 266 cs4280_query_devinfo, 267 cs4280_malloc, 268 cs4280_free, 269 cs4280_round_buffersize, 270 0, /* cs4280_mappage, */ 271 cs4280_get_props, 272 cs4280_trigger_output, 273 cs4280_trigger_input, 274 cs4280_get_default_params 275 }; 276 277 #if NMIDI > 0 278 struct midi_hw_if cs4280_midi_hw_if = { 279 cs4280_midi_open, 280 cs4280_midi_close, 281 cs4280_midi_output, 282 0, /* flush */ 283 cs4280_midi_getinfo, 284 0, /* ioctl */ 285 }; 286 #endif 287 288 289 290 struct audio_device cs4280_device = { 291 "CS4280", 292 "", 293 "cs4280" 294 }; 295 296 const struct pci_matchid cs4280_devices[] = { 297 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, 298 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, 299 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 }, 300 }; 301 302 int 303 cs4280_match(parent, ma, aux) 304 struct device *parent; 305 void *ma; 306 void *aux; 307 { 308 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, 309 sizeof(cs4280_devices)/sizeof(cs4280_devices[0]))); 310 } 311 312 int 313 cs4280_read_codec(sc_, add, data) 314 void *sc_; 315 u_int8_t add; 316 u_int16_t *data; 317 { 318 struct cs4280_softc *sc = sc_; 319 int n; 320 321 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 322 /* 323 * Make sure that there is not data sitting around from a preivous 324 * uncompleted access. 325 */ 326 BA0READ4(sc, CS4280_ACSDA); 327 328 /* Set up AC97 control registers. */ 329 BA0WRITE4(sc, CS4280_ACCAD, add); 330 BA0WRITE4(sc, CS4280_ACCDA, 0); 331 BA0WRITE4(sc, CS4280_ACCTL, 332 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 333 334 if (cs4280_src_wait(sc) < 0) { 335 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 336 sc->sc_dev.dv_xname, add); 337 return (1); 338 } 339 340 /* wait for valid status bit is active */ 341 n = 0; 342 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 343 delay(1); 344 while (++n > 1000) { 345 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 346 sc->sc_dev.dv_xname, add); 347 return (1); 348 } 349 } 350 *data = BA0READ4(sc, CS4280_ACSDA); 351 DPRINTFN(5,("data=0x%04x\n", *data)); 352 return (0); 353 } 354 355 int 356 cs4280_write_codec(sc_, add, data) 357 void *sc_; 358 u_int8_t add; 359 u_int16_t data; 360 { 361 struct cs4280_softc *sc = sc_; 362 363 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 364 BA0WRITE4(sc, CS4280_ACCAD, add); 365 BA0WRITE4(sc, CS4280_ACCDA, data); 366 BA0WRITE4(sc, CS4280_ACCTL, 367 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 368 369 if (cs4280_src_wait(sc) < 0) { 370 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 371 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 372 return (1); 373 } 374 return (0); 375 } 376 377 int 378 cs4280_src_wait(sc) 379 struct cs4280_softc *sc; 380 { 381 int n; 382 383 n = 0; 384 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 385 delay(1000); 386 if (++n > 1000) 387 return (-1); 388 } 389 return (0); 390 } 391 392 393 void 394 cs4280_set_adc_rate(sc, rate) 395 struct cs4280_softc *sc; 396 int rate; 397 { 398 /* calculate capture rate: 399 * 400 * capture_coefficient_increment = -round(rate*128*65536/48000; 401 * capture_phase_increment = floor(48000*65536*1024/rate); 402 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 403 * cy = floor(cx/200); 404 * capture_sample_rate_correction = cx - 200*cy; 405 * capture_delay = ceil(24*48000/rate); 406 * capture_num_triplets = floor(65536*rate/24000); 407 * capture_group_length = 24000/GCD(rate, 24000); 408 * where GCD means "Greatest Common Divisor". 409 * 410 * capture_coefficient_increment, capture_phase_increment and 411 * capture_num_triplets are 32-bit signed quantities. 412 * capture_sample_rate_correction and capture_group_length are 413 * 16-bit signed quantities. 414 * capture_delay is a 14-bit unsigned quantity. 415 */ 416 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 417 u_int16_t csrc, cgl, cdlay; 418 419 /* XXX 420 * Even though, embedded_audio_spec says capture rate range 11025 to 421 * 48000, dhwiface.cpp says, 422 * 423 * "We can only decimate by up to a factor of 1/9th the hardware rate. 424 * Return an error if an attempt is made to stray outside that limit." 425 * 426 * so assume range as 48000/9 to 48000 427 */ 428 429 if (rate < 8000) 430 rate = 8000; 431 if (rate > 48000) 432 rate = 48000; 433 434 cx = rate << 16; 435 cci = cx / 48000; 436 cx -= cci * 48000; 437 cx <<= 7; 438 cci <<= 7; 439 cci += cx / 48000; 440 cci = - cci; 441 442 cx = 48000 << 16; 443 cpi = cx / rate; 444 cx -= cpi * rate; 445 cx <<= 10; 446 cpi <<= 10; 447 cy = cx / rate; 448 cpi += cy; 449 cx -= cy * rate; 450 451 cy = cx / 200; 452 csrc = cx - 200*cy; 453 454 cdlay = ((48000 * 24) + rate - 1) / rate; 455 #if 0 456 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 457 #endif 458 459 cnt = rate << 16; 460 cnt /= 24000; 461 462 cgl = 1; 463 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 464 if (((rate / tmp1) * tmp1) != rate) 465 cgl *= 2; 466 } 467 if (((rate / 3) * 3) != rate) 468 cgl *= 3; 469 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 470 if (((rate / tmp1) * tmp1) != rate) 471 cgl *= 5; 472 } 473 #if 0 474 /* XXX what manual says */ 475 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 476 tmp1 |= csrc<<16; 477 BA1WRITE4(sc, CS4280_CSRC, tmp1); 478 #else 479 /* suggested by cs461x.c (ALSA driver) */ 480 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 481 #endif 482 483 #if 0 484 /* I am confused. The sample rate calculation section says 485 * cci *is* 32-bit signed quantity but in the parameter description 486 * section, CCI only assigned 16bit. 487 * I believe size of the variable. 488 */ 489 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 490 tmp1 |= cci<<16; 491 BA1WRITE4(sc, CS4280_CCI, tmp1); 492 #else 493 BA1WRITE4(sc, CS4280_CCI, cci); 494 #endif 495 496 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 497 tmp1 |= cdlay <<18; 498 BA1WRITE4(sc, CS4280_CD, tmp1); 499 500 BA1WRITE4(sc, CS4280_CPI, cpi); 501 502 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 503 tmp1 |= cgl; 504 BA1WRITE4(sc, CS4280_CGL, tmp1); 505 506 BA1WRITE4(sc, CS4280_CNT, cnt); 507 508 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 509 tmp1 |= cgl; 510 BA1WRITE4(sc, CS4280_CGC, tmp1); 511 } 512 513 void 514 cs4280_set_dac_rate(sc, rate) 515 struct cs4280_softc *sc; 516 int rate; 517 { 518 /* 519 * playback rate may range from 8000Hz to 48000Hz 520 * 521 * play_phase_increment = floor(rate*65536*1024/48000) 522 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 523 * py=floor(px/200) 524 * play_sample_rate_correction = px - 200*py 525 * 526 * play_phase_increment is a 32bit signed quantity. 527 * play_sample_rate_correction is a 16bit signed quantity. 528 */ 529 int32_t ppi; 530 int16_t psrc; 531 u_int32_t px, py; 532 533 if (rate < 8000) 534 rate = 8000; 535 if (rate > 48000) 536 rate = 48000; 537 px = rate << 16; 538 ppi = px/48000; 539 px -= ppi*48000; 540 ppi <<= 10; 541 px <<= 10; 542 py = px / 48000; 543 ppi += py; 544 px -= py*48000; 545 py = px/200; 546 px -= py*200; 547 psrc = px; 548 #if 0 549 /* what manual says */ 550 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 551 BA1WRITE4(sc, CS4280_PSRC, 552 ( ((psrc<<16) & PSRC_MASK) | px )); 553 #else 554 /* suggested by cs461x.c (ALSA driver) */ 555 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 556 #endif 557 BA1WRITE4(sc, CS4280_PPI, ppi); 558 } 559 560 void 561 cs4280_attachhook(void *xsc) 562 { 563 struct cs4280_softc *sc = xsc; 564 mixer_ctrl_t ctl; 565 566 /* Initialization */ 567 if (cs4280_init2(sc, 1) != 0) 568 return; 569 570 printf("%s: firmware loaded\n", sc->sc_dev.dv_xname); 571 572 /* Turn mute off of DAC, CD and master volumes by default */ 573 ctl.type = AUDIO_MIXER_ENUM; 574 ctl.un.ord = 0; /* off */ 575 576 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 577 AudioNmaster, AudioNmute); 578 cs4280_mixer_set_port(sc, &ctl); 579 580 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 581 AudioNdac, AudioNmute); 582 cs4280_mixer_set_port(sc, &ctl); 583 584 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 585 AudioNcd, AudioNmute); 586 cs4280_mixer_set_port(sc, &ctl); 587 588 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 589 590 #if NMIDI > 0 591 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 592 #endif 593 sc->sc_suspend = PWR_RESUME; 594 sc->sc_powerhook = powerhook_establish(cs4280_power, sc); 595 } 596 597 void 598 cs4280_attach(parent, self, aux) 599 struct device *parent; 600 struct device *self; 601 void *aux; 602 { 603 struct cs4280_softc *sc = (struct cs4280_softc *) self; 604 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 605 pci_chipset_tag_t pc = pa->pa_pc; 606 char const *intrstr; 607 pci_intr_handle_t ih; 608 u_int32_t mem; 609 610 /* Map I/O register */ 611 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 612 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 613 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 614 printf(": can't map BA0 space\n"); 615 return; 616 } 617 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 618 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 619 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 620 printf(": can't map BA1 space\n"); 621 return; 622 } 623 624 sc->sc_dmatag = pa->pa_dmat; 625 626 /* Get out of power save mode if needed. */ 627 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 628 629 /* LATENCY_TIMER setting */ 630 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 631 if ( PCI_LATTIMER(mem) < 32 ) { 632 mem &= 0xffff00ff; 633 mem |= 0x00002000; 634 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 635 } 636 637 /* Map and establish the interrupt. */ 638 if (pci_intr_map(pa, &ih)) { 639 printf(": couldn't map interrupt\n"); 640 return; 641 } 642 intrstr = pci_intr_string(pc, ih); 643 644 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc, 645 sc->sc_dev.dv_xname); 646 if (sc->sc_ih == NULL) { 647 printf(": couldn't establish interrupt"); 648 if (intrstr != NULL) 649 printf(" at %s", intrstr); 650 printf("\n"); 651 return; 652 } 653 printf(": %s\n", intrstr); 654 655 /* Initialization */ 656 if (cs4280_init(sc, 1) != 0) 657 return; 658 659 mountroothook_establish(cs4280_attachhook, sc); 660 661 /* AC 97 attachement */ 662 sc->host_if.arg = sc; 663 sc->host_if.attach = cs4280_attach_codec; 664 sc->host_if.read = cs4280_read_codec; 665 sc->host_if.write = cs4280_write_codec; 666 sc->host_if.reset = cs4280_reset_codec; 667 668 if (ac97_attach(&sc->host_if) != 0) { 669 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 670 return; 671 } 672 } 673 674 int 675 cs4280_intr(p) 676 void *p; 677 { 678 /* 679 * XXX 680 * 681 * Since CS4280 has only 4kB dma buffer and 682 * interrupt occurs every 2kB block, I create dummy buffer 683 * which returns to audio driver and actual dma buffer 684 * using in DMA transfer. 685 * 686 * 687 * ring buffer in audio.c is pointed by BUFADDR 688 * <------ ring buffer size == 64kB ------> 689 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 690 * |= = = =|= = = =|= = = =|= = = =|= = = =| 691 * | | | | | | <- call audio_intp every 692 * sc->sc_[pr]_count time. 693 * 694 * actual dma buffer is pointed by KERNADDR 695 * <-> dma buffer size = 4kB 696 * |= =| 697 * 698 * 699 */ 700 struct cs4280_softc *sc = p; 701 u_int32_t intr, mem; 702 char * empty_dma; 703 int handled = 0; 704 705 /* grab interrupt register then clear it */ 706 intr = BA0READ4(sc, CS4280_HISR); 707 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 708 709 /* Playback Interrupt */ 710 if (intr & HISR_PINT) { 711 handled = 1; 712 mem = BA1READ4(sc, CS4280_PFIE); 713 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 714 if (sc->sc_pintr) { 715 if ((sc->sc_pi%sc->sc_pcount) == 0) 716 sc->sc_pintr(sc->sc_parg); 717 } else { 718 printf("unexpected play intr\n"); 719 } 720 /* copy buffer */ 721 ++sc->sc_pi; 722 empty_dma = sc->sc_pdma->addr; 723 if (sc->sc_pi&1) 724 empty_dma += CS4280_ICHUNK; 725 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 726 sc->sc_pn += CS4280_ICHUNK; 727 if (sc->sc_pn >= sc->sc_pe) 728 sc->sc_pn = sc->sc_ps; 729 BA1WRITE4(sc, CS4280_PFIE, mem); 730 } 731 /* Capture Interrupt */ 732 if (intr & HISR_CINT) { 733 int i; 734 int16_t rdata; 735 736 handled = 1; 737 mem = BA1READ4(sc, CS4280_CIE); 738 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 739 ++sc->sc_ri; 740 empty_dma = sc->sc_rdma->addr; 741 if ((sc->sc_ri&1) == 0) 742 empty_dma += CS4280_ICHUNK; 743 744 /* 745 * XXX 746 * I think this audio data conversion should be 747 * happend in upper layer, but I put this here 748 * since there is no conversion function available. 749 */ 750 switch(sc->sc_rparam) { 751 case CF_16BIT_STEREO: 752 /* just copy it */ 753 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 754 sc->sc_rn += CS4280_ICHUNK; 755 break; 756 case CF_16BIT_MONO: 757 for (i = 0; i < 512; i++) { 758 rdata = *((int16_t *)empty_dma)++>>1; 759 rdata += *((int16_t *)empty_dma)++>>1; 760 *((int16_t *)sc->sc_rn)++ = rdata; 761 } 762 break; 763 case CF_8BIT_STEREO: 764 for (i = 0; i < 512; i++) { 765 rdata = *((int16_t*)empty_dma)++; 766 *sc->sc_rn++ = rdata >> 8; 767 rdata = *((int16_t*)empty_dma)++; 768 *sc->sc_rn++ = rdata >> 8; 769 } 770 break; 771 case CF_8BIT_MONO: 772 for (i = 0; i < 512; i++) { 773 rdata = *((int16_t*)empty_dma)++ >>1; 774 rdata += *((int16_t*)empty_dma)++ >>1; 775 *sc->sc_rn++ = rdata >>8; 776 } 777 break; 778 default: 779 /* Should not reach here */ 780 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 781 } 782 if (sc->sc_rn >= sc->sc_re) 783 sc->sc_rn = sc->sc_rs; 784 BA1WRITE4(sc, CS4280_CIE, mem); 785 if (sc->sc_rintr) { 786 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 787 sc->sc_rintr(sc->sc_rarg); 788 } else { 789 printf("unexpected record intr\n"); 790 } 791 } 792 793 #if NMIDI > 0 794 /* Midi port Interrupt */ 795 if (intr & HISR_MIDI) { 796 int data; 797 798 handled = 1; 799 DPRINTF(("i: %d: ", 800 BA0READ4(sc, CS4280_MIDSR))); 801 /* Read the received data */ 802 while ((sc->sc_iintr != NULL) && 803 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 804 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 805 DPRINTF(("r:%x\n",data)); 806 sc->sc_iintr(sc->sc_arg, data); 807 } 808 809 /* Write the data */ 810 #if 1 811 /* XXX: 812 * It seems "Transmit Buffer Full" never activate until EOI 813 * is delivered. Shall I throw EOI top of this routine ? 814 */ 815 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 816 DPRINTF(("w: ")); 817 if (sc->sc_ointr != NULL) 818 sc->sc_ointr(sc->sc_arg); 819 } 820 #else 821 while ((sc->sc_ointr != NULL) && 822 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 823 DPRINTF(("w: ")); 824 sc->sc_ointr(sc->sc_arg); 825 } 826 #endif 827 DPRINTF(("\n")); 828 } 829 #endif 830 831 return handled; 832 } 833 834 835 /* Download Proceessor Code and Data image */ 836 837 int 838 cs4280_download(sc, src, offset, len) 839 struct cs4280_softc *sc; 840 const u_int32_t *src; 841 u_int32_t offset, len; 842 { 843 u_int32_t ctr; 844 845 #ifdef CS4280_DEBUG 846 u_int32_t con, data; 847 u_int8_t c0,c1,c2,c3; 848 #endif 849 if ((offset&3) || (len&3)) 850 return (-1); 851 852 len /= sizeof(u_int32_t); 853 for (ctr = 0; ctr < len; ctr++) { 854 /* XXX: 855 * I cannot confirm this is the right thing or not 856 * on BIG-ENDIAN machines. 857 */ 858 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 859 #ifdef CS4280_DEBUG 860 data = htole32(*(src+ctr)); 861 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 862 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 863 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 864 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 865 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 866 if (data != con ) { 867 printf("0x%06x: write=0x%08x read=0x%08x\n", 868 offset+ctr*4, data, con); 869 return (-1); 870 } 871 #endif 872 } 873 return (0); 874 } 875 876 struct BA1struct *BA1Struct; 877 878 int 879 cs4280_download_image(sc) 880 struct cs4280_softc *sc; 881 { 882 int idx, err = 0; 883 u_int32_t offset = 0; 884 static u_char *cs4280_firmware; 885 static size_t cs4280_firmwarelen; 886 887 if (cs4280_firmware == NULL) { 888 err = loadfirmware("cs4280", &cs4280_firmware, 889 &cs4280_firmwarelen); 890 if (err) 891 return (err); 892 } 893 894 BA1Struct = (struct BA1struct *)cs4280_firmware; 895 896 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 897 err = cs4280_download(sc, &BA1Struct->map[offset], 898 BA1Struct->memory[idx].offset, BA1Struct->memory[idx].size); 899 if (err != 0) { 900 printf("%s: load_image failed at %d\n", 901 sc->sc_dev.dv_xname, idx); 902 return (-1); 903 } 904 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 905 } 906 return (err); 907 } 908 909 #ifdef CS4280_DEBUG 910 int 911 cs4280_checkimage(sc, src, offset, len) 912 struct cs4280_softc *sc; 913 u_int32_t *src; 914 u_int32_t offset, len; 915 { 916 u_int32_t ctr, data; 917 int err = 0; 918 919 if ((offset&3) || (len&3)) 920 return -1; 921 922 len /= sizeof(u_int32_t); 923 for (ctr = 0; ctr < len; ctr++) { 924 /* I cannot confirm this is the right thing 925 * on BIG-ENDIAN machines 926 */ 927 data = BA1READ4(sc, offset+ctr*4); 928 if (data != htole32(*(src+ctr))) { 929 printf("0x%06x: 0x%08x(0x%08x)\n", 930 offset+ctr*4, data, *(src+ctr)); 931 *(src+ctr) = data; 932 ++err; 933 } 934 } 935 return (err); 936 } 937 938 int 939 cs4280_check_images(sc) 940 struct cs4280_softc *sc; 941 { 942 int idx, err; 943 u_int32_t offset = 0; 944 945 err = 0; 946 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 947 for (idx = 0; idx < 1; ++idx) { 948 err = cs4280_checkimage(sc, &BA1Struct->map[offset], 949 BA1Struct->memory[idx].offset, 950 BA1Struct->memory[idx].size); 951 if (err != 0) { 952 printf("%s: check_image failed at %d\n", 953 sc->sc_dev.dv_xname, idx); 954 } 955 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 956 } 957 return (err); 958 } 959 960 #endif 961 962 int 963 cs4280_attach_codec(sc_, codec_if) 964 void *sc_; 965 struct ac97_codec_if *codec_if; 966 { 967 struct cs4280_softc *sc = sc_; 968 969 sc->codec_if = codec_if; 970 return (0); 971 } 972 973 void 974 cs4280_reset_codec(sc_) 975 void *sc_; 976 { 977 struct cs4280_softc *sc = sc_; 978 int n; 979 980 /* Reset codec */ 981 BA0WRITE4(sc, CS4280_ACCTL, 0); 982 delay(100); /* delay 100us */ 983 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 984 985 /* 986 * It looks like we do the following procedure, too 987 */ 988 989 /* Enable AC-link sync generation */ 990 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 991 delay(50*1000); /* XXX delay 50ms */ 992 993 /* Assert valid frame signal */ 994 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 995 996 /* Wait for valid AC97 input slot */ 997 n = 0; 998 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 999 delay(1000); 1000 if (++n > 1000) { 1001 printf("reset_codec: AC97 inputs slot ready timeout\n"); 1002 return; 1003 } 1004 } 1005 } 1006 1007 1008 /* Processor Soft Reset */ 1009 void 1010 cs4280_reset(sc_) 1011 void *sc_; 1012 { 1013 struct cs4280_softc *sc = sc_; 1014 1015 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 1016 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 1017 delay(100); 1018 /* Clear RSTSP bit in SPCR */ 1019 BA1WRITE4(sc, CS4280_SPCR, 0); 1020 /* enable DMA reqest */ 1021 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 1022 } 1023 1024 int 1025 cs4280_open(addr, flags) 1026 void *addr; 1027 int flags; 1028 { 1029 return (0); 1030 } 1031 1032 void 1033 cs4280_close(addr) 1034 void *addr; 1035 { 1036 struct cs4280_softc *sc = addr; 1037 1038 cs4280_halt_output(sc); 1039 cs4280_halt_input(sc); 1040 1041 sc->sc_pintr = 0; 1042 sc->sc_rintr = 0; 1043 } 1044 1045 int 1046 cs4280_query_encoding(addr, fp) 1047 void *addr; 1048 struct audio_encoding *fp; 1049 { 1050 switch (fp->index) { 1051 case 0: 1052 strlcpy(fp->name, AudioEulinear, sizeof fp->name); 1053 fp->encoding = AUDIO_ENCODING_ULINEAR; 1054 fp->precision = 8; 1055 fp->flags = 0; 1056 break; 1057 case 1: 1058 strlcpy(fp->name, AudioEmulaw, sizeof fp->name); 1059 fp->encoding = AUDIO_ENCODING_ULAW; 1060 fp->precision = 8; 1061 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1062 break; 1063 case 2: 1064 strlcpy(fp->name, AudioEalaw, sizeof fp->name); 1065 fp->encoding = AUDIO_ENCODING_ALAW; 1066 fp->precision = 8; 1067 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1068 break; 1069 case 3: 1070 strlcpy(fp->name, AudioEslinear, sizeof fp->name); 1071 fp->encoding = AUDIO_ENCODING_SLINEAR; 1072 fp->precision = 8; 1073 fp->flags = 0; 1074 break; 1075 case 4: 1076 strlcpy(fp->name, AudioEslinear_le, sizeof fp->name); 1077 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1078 fp->precision = 16; 1079 fp->flags = 0; 1080 break; 1081 case 5: 1082 strlcpy(fp->name, AudioEulinear_le, sizeof fp->name); 1083 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1084 fp->precision = 16; 1085 fp->flags = 0; 1086 break; 1087 case 6: 1088 strlcpy(fp->name, AudioEslinear_be, sizeof fp->name); 1089 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1090 fp->precision = 16; 1091 fp->flags = 0; 1092 break; 1093 case 7: 1094 strlcpy(fp->name, AudioEulinear_be, sizeof fp->name); 1095 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1096 fp->precision = 16; 1097 fp->flags = 0; 1098 break; 1099 default: 1100 return (EINVAL); 1101 } 1102 return (0); 1103 } 1104 1105 int 1106 cs4280_set_params(addr, setmode, usemode, play, rec) 1107 void *addr; 1108 int setmode, usemode; 1109 struct audio_params *play, *rec; 1110 { 1111 struct cs4280_softc *sc = addr; 1112 struct audio_params *p; 1113 int mode; 1114 1115 for (mode = AUMODE_RECORD; mode != -1; 1116 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1117 if ((setmode & mode) == 0) 1118 continue; 1119 1120 p = mode == AUMODE_PLAY ? play : rec; 1121 1122 if (p == play) { 1123 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1124 p->sample_rate, p->precision, p->channels)); 1125 /* play back data format may be 8- or 16-bit and 1126 * either stereo or mono. 1127 * playback rate may range from 8000Hz to 48000Hz 1128 */ 1129 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1130 (p->precision != 8 && p->precision != 16) || 1131 (p->channels != 1 && p->channels != 2) ) { 1132 return (EINVAL); 1133 } 1134 } else { 1135 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1136 p->sample_rate, p->precision, p->channels)); 1137 /* capture data format must be 16bit stereo 1138 * and sample rate range from 11025Hz to 48000Hz. 1139 * 1140 * XXX: it looks like to work with 8000Hz, 1141 * although data sheets say lower limit is 1142 * 11025 Hz. 1143 */ 1144 1145 if (p->sample_rate < 8000 || p->sample_rate > 48000 || 1146 (p->precision != 8 && p->precision != 16) || 1147 (p->channels != 1 && p->channels != 2) ) { 1148 return (EINVAL); 1149 } 1150 } 1151 p->factor = 1; 1152 p->sw_code = 0; 1153 1154 /* capturing data is slinear */ 1155 switch (p->encoding) { 1156 case AUDIO_ENCODING_SLINEAR_BE: 1157 if (mode == AUMODE_RECORD) { 1158 if (p->precision == 16) 1159 p->sw_code = swap_bytes; 1160 } 1161 break; 1162 case AUDIO_ENCODING_SLINEAR_LE: 1163 break; 1164 case AUDIO_ENCODING_ULINEAR_BE: 1165 if (mode == AUMODE_RECORD) { 1166 if (p->precision == 16) 1167 p->sw_code = change_sign16_swap_bytes_le; 1168 else 1169 p->sw_code = change_sign8; 1170 } 1171 break; 1172 case AUDIO_ENCODING_ULINEAR_LE: 1173 if (mode == AUMODE_RECORD) { 1174 if (p->precision == 16) 1175 p->sw_code = change_sign16_le; 1176 else 1177 p->sw_code = change_sign8; 1178 } 1179 break; 1180 case AUDIO_ENCODING_ULAW: 1181 if (mode == AUMODE_PLAY) { 1182 p->factor = 2; 1183 p->sw_code = mulaw_to_slinear16_le; 1184 } else { 1185 p->sw_code = slinear8_to_mulaw; 1186 } 1187 break; 1188 case AUDIO_ENCODING_ALAW: 1189 if (mode == AUMODE_PLAY) { 1190 p->factor = 2; 1191 p->sw_code = alaw_to_slinear16_le; 1192 } else { 1193 p->sw_code = slinear8_to_alaw; 1194 } 1195 break; 1196 default: 1197 return (EINVAL); 1198 } 1199 } 1200 1201 /* set sample rate */ 1202 cs4280_set_dac_rate(sc, play->sample_rate); 1203 cs4280_set_adc_rate(sc, rec->sample_rate); 1204 return (0); 1205 } 1206 1207 int 1208 cs4280_round_blocksize(hdl, blk) 1209 void *hdl; 1210 int blk; 1211 { 1212 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1213 } 1214 1215 size_t 1216 cs4280_round_buffersize(addr, direction, size) 1217 void *addr; 1218 int direction; 1219 size_t size; 1220 { 1221 /* although real dma buffer size is 4KB, 1222 * let the audio.c driver use a larger buffer. 1223 * ( suggested by Lennart Augustsson. ) 1224 */ 1225 return (size); 1226 } 1227 1228 void 1229 cs4280_get_default_params(void *addr, int mode, struct audio_params *params) 1230 { 1231 ac97_get_default_params(params); 1232 } 1233 1234 int 1235 cs4280_get_props(hdl) 1236 void *hdl; 1237 { 1238 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1239 #ifdef notyet 1240 /* XXX 1241 * How can I mmap ? 1242 */ 1243 AUDIO_PROP_MMAP 1244 #endif 1245 1246 } 1247 1248 int 1249 cs4280_mixer_get_port(addr, cp) 1250 void *addr; 1251 mixer_ctrl_t *cp; 1252 { 1253 struct cs4280_softc *sc = addr; 1254 1255 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1256 } 1257 1258 paddr_t 1259 cs4280_mappage(addr, mem, off, prot) 1260 void *addr; 1261 void *mem; 1262 off_t off; 1263 int prot; 1264 { 1265 struct cs4280_softc *sc = addr; 1266 struct cs4280_dma *p; 1267 1268 if (off < 0) 1269 return (-1); 1270 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1271 ; 1272 if (!p) { 1273 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1274 return (-1); 1275 } 1276 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1277 off, prot, BUS_DMA_WAITOK)); 1278 } 1279 1280 1281 int 1282 cs4280_query_devinfo(addr, dip) 1283 void *addr; 1284 mixer_devinfo_t *dip; 1285 { 1286 struct cs4280_softc *sc = addr; 1287 1288 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1289 } 1290 1291 int 1292 cs4280_get_portnum_by_name(sc, class, device, qualifier) 1293 struct cs4280_softc *sc; 1294 char *class, *device, *qualifier; 1295 { 1296 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1297 device, qualifier)); 1298 } 1299 1300 int 1301 cs4280_halt_output(addr) 1302 void *addr; 1303 { 1304 struct cs4280_softc *sc = addr; 1305 u_int32_t mem; 1306 1307 mem = BA1READ4(sc, CS4280_PCTL); 1308 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1309 #ifdef DIAGNOSTIC 1310 sc->sc_prun = 0; 1311 #endif 1312 return (0); 1313 } 1314 1315 int 1316 cs4280_halt_input(addr) 1317 void *addr; 1318 { 1319 struct cs4280_softc *sc = addr; 1320 u_int32_t mem; 1321 1322 mem = BA1READ4(sc, CS4280_CCTL); 1323 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1324 #ifdef DIAGNOSTIC 1325 sc->sc_rrun = 0; 1326 #endif 1327 return (0); 1328 } 1329 1330 int 1331 cs4280_getdev(addr, retp) 1332 void *addr; 1333 struct audio_device *retp; 1334 { 1335 *retp = cs4280_device; 1336 return (0); 1337 } 1338 1339 int 1340 cs4280_mixer_set_port(addr, cp) 1341 void *addr; 1342 mixer_ctrl_t *cp; 1343 { 1344 struct cs4280_softc *sc = addr; 1345 int val; 1346 1347 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1348 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1349 return (val); 1350 } 1351 1352 1353 int 1354 cs4280_freemem(sc, p) 1355 struct cs4280_softc *sc; 1356 struct cs4280_dma *p; 1357 { 1358 bus_dmamap_unload(sc->sc_dmatag, p->map); 1359 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1360 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1361 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1362 return (0); 1363 } 1364 1365 int 1366 cs4280_allocmem(sc, size, align, p) 1367 struct cs4280_softc *sc; 1368 size_t size; 1369 size_t align; 1370 struct cs4280_dma *p; 1371 { 1372 int error; 1373 1374 /* XXX */ 1375 p->size = size; 1376 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1377 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1378 &p->nsegs, BUS_DMA_NOWAIT); 1379 if (error) { 1380 printf("%s: unable to allocate dma, error=%d\n", 1381 sc->sc_dev.dv_xname, error); 1382 return (error); 1383 } 1384 1385 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1386 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1387 if (error) { 1388 printf("%s: unable to map dma, error=%d\n", 1389 sc->sc_dev.dv_xname, error); 1390 goto free; 1391 } 1392 1393 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1394 0, BUS_DMA_NOWAIT, &p->map); 1395 if (error) { 1396 printf("%s: unable to create dma map, error=%d\n", 1397 sc->sc_dev.dv_xname, error); 1398 goto unmap; 1399 } 1400 1401 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1402 BUS_DMA_NOWAIT); 1403 if (error) { 1404 printf("%s: unable to load dma map, error=%d\n", 1405 sc->sc_dev.dv_xname, error); 1406 goto destroy; 1407 } 1408 return (0); 1409 1410 destroy: 1411 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1412 unmap: 1413 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1414 free: 1415 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1416 return (error); 1417 } 1418 1419 1420 void * 1421 cs4280_malloc(addr, direction, size, pool, flags) 1422 void *addr; 1423 int direction; 1424 size_t size; 1425 int pool, flags; 1426 { 1427 struct cs4280_softc *sc = addr; 1428 struct cs4280_dma *p; 1429 caddr_t q; 1430 int error; 1431 1432 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1433 q = malloc(size, pool, flags); 1434 if (!q) 1435 return (0); 1436 p = malloc(sizeof(*p), pool, flags); 1437 if (!p) { 1438 free(q,pool); 1439 return (0); 1440 } 1441 /* 1442 * cs4280 has fixed 4kB buffer 1443 */ 1444 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1445 1446 if (error) { 1447 free(q, pool); 1448 free(p, pool); 1449 return (0); 1450 } 1451 1452 p->next = sc->sc_dmas; 1453 sc->sc_dmas = p; 1454 p->dum = q; /* return to audio driver */ 1455 1456 return (p->dum); 1457 } 1458 1459 void 1460 cs4280_free(addr, ptr, pool) 1461 void *addr; 1462 void *ptr; 1463 int pool; 1464 { 1465 struct cs4280_softc *sc = addr; 1466 struct cs4280_dma **pp, *p; 1467 1468 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1469 if (BUFADDR(p) == ptr) { 1470 cs4280_freemem(sc, p); 1471 *pp = p->next; 1472 free(p->dum, pool); 1473 free(p, pool); 1474 return; 1475 } 1476 } 1477 } 1478 1479 int 1480 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param) 1481 void *addr; 1482 void *start, *end; 1483 int blksize; 1484 void (*intr)(void *); 1485 void *arg; 1486 struct audio_params *param; 1487 { 1488 struct cs4280_softc *sc = addr; 1489 u_int32_t pfie, pctl, mem, pdtc; 1490 struct cs4280_dma *p; 1491 1492 #ifdef DIAGNOSTIC 1493 if (sc->sc_prun) 1494 printf("cs4280_trigger_output: already running\n"); 1495 sc->sc_prun = 1; 1496 #endif 1497 1498 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1499 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1500 sc->sc_pintr = intr; 1501 sc->sc_parg = arg; 1502 1503 /* stop playback DMA */ 1504 mem = BA1READ4(sc, CS4280_PCTL); 1505 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1506 1507 /* setup PDTC */ 1508 pdtc = BA1READ4(sc, CS4280_PDTC); 1509 pdtc &= ~PDTC_MASK; 1510 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1511 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1512 1513 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1514 param->precision, param->factor, param->channels, 1515 param->encoding)); 1516 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1517 ; 1518 if (p == NULL) { 1519 printf("cs4280_trigger_output: bad addr %p\n", start); 1520 return (EINVAL); 1521 } 1522 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1523 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1524 "4kB align\n", DMAADDR(p)); 1525 return (EINVAL); 1526 } 1527 1528 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1529 sc->sc_ps = (char *)start; 1530 sc->sc_pe = (char *)end; 1531 sc->sc_pdma = p; 1532 sc->sc_pbuf = KERNADDR(p); 1533 sc->sc_pi = 0; 1534 sc->sc_pn = sc->sc_ps; 1535 if (blksize >= CS4280_DCHUNK) { 1536 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1537 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1538 ++sc->sc_pi; 1539 } else { 1540 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1541 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1542 } 1543 1544 /* initiate playback dma */ 1545 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1546 1547 /* set PFIE */ 1548 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1549 1550 if (param->precision * param->factor == 8) 1551 pfie |= PFIE_8BIT; 1552 if (param->channels == 1) 1553 pfie |= PFIE_MONO; 1554 1555 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1556 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1557 pfie |= PFIE_SWAPPED; 1558 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1559 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1560 pfie |= PFIE_UNSIGNED; 1561 1562 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1563 1564 cs4280_set_dac_rate(sc, param->sample_rate); 1565 1566 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1567 pctl |= sc->pctl; 1568 BA1WRITE4(sc, CS4280_PCTL, pctl); 1569 return (0); 1570 } 1571 1572 int 1573 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param) 1574 void *addr; 1575 void *start, *end; 1576 int blksize; 1577 void (*intr)(void *); 1578 void *arg; 1579 struct audio_params *param; 1580 { 1581 struct cs4280_softc *sc = addr; 1582 u_int32_t cctl, cie; 1583 struct cs4280_dma *p; 1584 1585 #ifdef DIAGNOSTIC 1586 if (sc->sc_rrun) 1587 printf("cs4280_trigger_input: already running\n"); 1588 sc->sc_rrun = 1; 1589 #endif 1590 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1591 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1592 sc->sc_rintr = intr; 1593 sc->sc_rarg = arg; 1594 1595 sc->sc_ri = 0; 1596 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1597 sc->sc_rs = (char *)start; 1598 sc->sc_re = (char *)end; 1599 sc->sc_rn = sc->sc_rs; 1600 1601 /* setup format information for internal converter */ 1602 sc->sc_rparam = 0; 1603 if (param->precision == 8) { 1604 sc->sc_rparam += CF_8BIT; 1605 sc->sc_rcount <<= 1; 1606 } 1607 if (param->channels == 1) { 1608 sc->sc_rparam += CF_MONO; 1609 sc->sc_rcount <<= 1; 1610 } 1611 1612 /* stop capture DMA */ 1613 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1614 BA1WRITE4(sc, CS4280_CCTL, cctl); 1615 1616 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1617 ; 1618 if (!p) { 1619 printf("cs4280_trigger_input: bad addr %p\n", start); 1620 return (EINVAL); 1621 } 1622 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1623 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1624 "4kB align\n", DMAADDR(p)); 1625 return (EINVAL); 1626 } 1627 sc->sc_rdma = p; 1628 sc->sc_rbuf = KERNADDR(p); 1629 1630 /* initiate capture dma */ 1631 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1632 1633 /* set CIE */ 1634 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1635 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1636 1637 cs4280_set_adc_rate(sc, param->sample_rate); 1638 1639 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1640 cctl |= sc->cctl; 1641 BA1WRITE4(sc, CS4280_CCTL, cctl); 1642 return (0); 1643 } 1644 1645 1646 int 1647 cs4280_init(sc, init) 1648 struct cs4280_softc *sc; 1649 int init; 1650 { 1651 int n; 1652 u_int32_t mem; 1653 1654 /* Start PLL out in known state */ 1655 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1656 /* Start serial ports out in known state */ 1657 BA0WRITE4(sc, CS4280_SERMC1, 0); 1658 1659 /* Specify type of CODEC */ 1660 /* XXX should no be here */ 1661 #define SERACC_CODEC_TYPE_1_03 1662 #ifdef SERACC_CODEC_TYPE_1_03 1663 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1664 #else 1665 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1666 #endif 1667 1668 /* Reset codec */ 1669 BA0WRITE4(sc, CS4280_ACCTL, 0); 1670 delay(100); /* delay 100us */ 1671 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1672 1673 /* Enable AC-link sync generation */ 1674 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1675 delay(50*1000); /* delay 50ms */ 1676 1677 /* Set the serial port timing configuration */ 1678 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1679 1680 /* Setup clock control */ 1681 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1682 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1683 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1684 1685 /* Power up the PLL */ 1686 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1687 delay(50*1000); /* delay 50ms */ 1688 1689 /* Turn on clock */ 1690 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1691 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1692 1693 /* Set the serial port FIFO pointer to the 1694 * first sample in FIFO. (not documented) */ 1695 cs4280_clear_fifos(sc); 1696 1697 #if 0 1698 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1699 BA0WRITE4(sc, CS4280_SERBSP, 0); 1700 #endif 1701 1702 /* Configure the serial port */ 1703 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1704 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1705 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1706 1707 /* Wait for CODEC ready */ 1708 n = 0; 1709 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1710 delay(125); 1711 if (++n > 1000) { 1712 printf("%s: codec ready timeout\n", 1713 sc->sc_dev.dv_xname); 1714 return(1); 1715 } 1716 } 1717 1718 /* Assert valid frame signal */ 1719 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1720 1721 /* Wait for valid AC97 input slot */ 1722 n = 0; 1723 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1724 (ACISV_ISV3 | ACISV_ISV4)) { 1725 delay(1000); 1726 if (++n > 1000) { 1727 printf("AC97 inputs slot ready timeout\n"); 1728 return(1); 1729 } 1730 } 1731 1732 /* Set AC97 output slot valid signals */ 1733 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1734 1735 /* reset the processor */ 1736 cs4280_reset(sc); 1737 return (0); 1738 } 1739 1740 int 1741 cs4280_init2(sc, init) 1742 struct cs4280_softc *sc; 1743 int init; 1744 { 1745 int n; 1746 u_int32_t mem; 1747 1748 /* Download the image to the processor */ 1749 if (cs4280_download_image(sc) != 0) { 1750 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1751 return(1); 1752 } 1753 1754 /* Save playback parameter and then write zero. 1755 * this ensures that DMA doesn't immediately occur upon 1756 * starting the processor core 1757 */ 1758 mem = BA1READ4(sc, CS4280_PCTL); 1759 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1760 cs4280_halt_output(sc); 1761 1762 /* Save capture parameter and then write zero. 1763 * this ensures that DMA doesn't immediately occur upon 1764 * starting the processor core 1765 */ 1766 mem = BA1READ4(sc, CS4280_CCTL); 1767 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1768 cs4280_halt_input(sc); 1769 1770 /* MSH: need to power up ADC and DAC? */ 1771 1772 /* Processor Startup Procedure */ 1773 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1774 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1775 1776 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1777 n = 0; 1778 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1779 delay(10); 1780 if (++n > 1000) { 1781 printf("SPCR 1->0 transition timeout\n"); 1782 return(1); 1783 } 1784 } 1785 1786 n = 0; 1787 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1788 delay(10); 1789 if (++n > 1000) { 1790 printf("SPCS 0->1 transition timeout\n"); 1791 return(1); 1792 } 1793 } 1794 /* Processor is now running !!! */ 1795 1796 /* Setup volume */ 1797 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1798 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1799 1800 /* Interrupt enable */ 1801 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1802 1803 /* playback interrupt enable */ 1804 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1805 mem |= PFIE_PI_ENABLE; 1806 BA1WRITE4(sc, CS4280_PFIE, mem); 1807 /* capture interrupt enable */ 1808 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1809 mem |= CIE_CI_ENABLE; 1810 BA1WRITE4(sc, CS4280_CIE, mem); 1811 1812 #if NMIDI > 0 1813 /* Reset midi port */ 1814 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1815 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1816 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1817 /* midi interrupt enable */ 1818 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1819 BA0WRITE4(sc, CS4280_MIDCR, mem); 1820 #endif 1821 return(0); 1822 } 1823 1824 void 1825 cs4280_power(why, v) 1826 int why; 1827 void *v; 1828 { 1829 struct cs4280_softc *sc = (struct cs4280_softc *)v; 1830 int i; 1831 1832 DPRINTF(("%s: cs4280_power why=%d\n", 1833 sc->sc_dev.dv_xname, why)); 1834 if (why != PWR_RESUME) { 1835 sc->sc_suspend = why; 1836 1837 cs4280_halt_output(sc); 1838 cs4280_halt_input(sc); 1839 /* Save AC97 registers */ 1840 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1841 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1842 continue; 1843 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]); 1844 } 1845 /* should I powerdown here ? */ 1846 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1847 } else { 1848 if (sc->sc_suspend == PWR_RESUME) { 1849 printf("cs4280_power: odd, resume without suspend.\n"); 1850 sc->sc_suspend = why; 1851 return; 1852 } 1853 sc->sc_suspend = why; 1854 cs4280_init(sc, 0); 1855 cs4280_init2(sc, 0); 1856 cs4280_reset_codec(sc); 1857 1858 /* restore ac97 registers */ 1859 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) { 1860 if(i == 0x04) /* AC97_REG_MASTER_TONE */ 1861 continue; 1862 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]); 1863 } 1864 } 1865 } 1866 1867 void 1868 cs4280_clear_fifos(sc) 1869 struct cs4280_softc *sc; 1870 { 1871 int pd = 0, cnt, n; 1872 u_int32_t mem; 1873 1874 /* 1875 * If device power down, power up the device and keep power down 1876 * state. 1877 */ 1878 mem = BA0READ4(sc, CS4280_CLKCR1); 1879 if (!(mem & CLKCR1_SWCE)) { 1880 printf("cs4280_clear_fifo: power down found.\n"); 1881 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1882 pd = 1; 1883 } 1884 BA0WRITE4(sc, CS4280_SERBWP, 0); 1885 for (cnt = 0; cnt < 256; cnt++) { 1886 n = 0; 1887 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1888 delay(1000); 1889 if (++n > 1000) { 1890 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1891 break; 1892 } 1893 } 1894 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1895 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1896 } 1897 if (pd) 1898 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1899 } 1900 1901 #if NMIDI > 0 1902 int 1903 cs4280_midi_open(addr, flags, iintr, ointr, arg) 1904 void *addr; 1905 int flags; 1906 void (*iintr)(void *, int); 1907 void (*ointr)(void *); 1908 void *arg; 1909 { 1910 struct cs4280_softc *sc = addr; 1911 u_int32_t mem; 1912 1913 DPRINTF(("midi_open\n")); 1914 sc->sc_iintr = iintr; 1915 sc->sc_ointr = ointr; 1916 sc->sc_arg = arg; 1917 1918 /* midi interrupt enable */ 1919 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1920 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1921 BA0WRITE4(sc, CS4280_MIDCR, mem); 1922 #ifdef CS4280_DEBUG 1923 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1924 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1925 return(EINVAL); 1926 } 1927 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1928 #endif 1929 return (0); 1930 } 1931 1932 void 1933 cs4280_midi_close(addr) 1934 void *addr; 1935 { 1936 struct cs4280_softc *sc = addr; 1937 u_int32_t mem; 1938 1939 DPRINTF(("midi_close\n")); 1940 mem = BA0READ4(sc, CS4280_MIDCR); 1941 mem &= ~MIDCR_MASK; 1942 BA0WRITE4(sc, CS4280_MIDCR, mem); 1943 1944 sc->sc_iintr = 0; 1945 sc->sc_ointr = 0; 1946 } 1947 1948 int 1949 cs4280_midi_output(addr, d) 1950 void *addr; 1951 int d; 1952 { 1953 struct cs4280_softc *sc = addr; 1954 u_int32_t mem; 1955 int x; 1956 1957 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1958 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1959 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1960 mem |= d & MIDWP_MASK; 1961 DPRINTFN(5,("midi_output d=0x%08x",d)); 1962 BA0WRITE4(sc, CS4280_MIDWP, mem); 1963 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1964 DPRINTF(("Bad write data: %d %d", 1965 mem, BA0READ4(sc, CS4280_MIDWP))); 1966 return(EIO); 1967 } 1968 return (0); 1969 } 1970 delay(MIDI_BUSY_DELAY); 1971 } 1972 return (EIO); 1973 } 1974 1975 void 1976 cs4280_midi_getinfo(addr, mi) 1977 void *addr; 1978 struct midi_info *mi; 1979 { 1980 mi->name = "CS4280 MIDI UART"; 1981 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1982 } 1983 1984 #endif 1985