1 /* $OpenBSD: cs4280.c,v 1.41 2012/01/11 16:22:33 dhill Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/cs4280reg.h> 78 79 #include <sys/audioio.h> 80 #include <dev/audio_if.h> 81 #include <dev/midi_if.h> 82 #include <dev/mulaw.h> 83 #include <dev/auconv.h> 84 85 #include <dev/ic/ac97.h> 86 87 #include <machine/bus.h> 88 89 #define CSCC_PCI_BA0 0x10 90 #define CSCC_PCI_BA1 0x14 91 92 struct cs4280_dma { 93 bus_dmamap_t map; 94 caddr_t addr; /* real dma buffer */ 95 caddr_t dum; /* dummy buffer for audio driver */ 96 bus_dma_segment_t segs[1]; 97 int nsegs; 98 size_t size; 99 struct cs4280_dma *next; 100 }; 101 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 102 #define BUFADDR(p) ((void *)((p)->dum)) 103 #define KERNADDR(p) ((void *)((p)->addr)) 104 105 /* 106 * Software state 107 */ 108 struct cs4280_softc { 109 struct device sc_dev; 110 111 pci_intr_handle_t * sc_ih; 112 113 /* I/O (BA0) */ 114 bus_space_tag_t ba0t; 115 bus_space_handle_t ba0h; 116 117 /* BA1 */ 118 bus_space_tag_t ba1t; 119 bus_space_handle_t ba1h; 120 121 /* DMA */ 122 bus_dma_tag_t sc_dmatag; 123 struct cs4280_dma *sc_dmas; 124 125 void (*sc_pintr)(void *); /* dma completion intr handler */ 126 void *sc_parg; /* arg for sc_intr() */ 127 char *sc_ps, *sc_pe, *sc_pn; 128 int sc_pcount; 129 int sc_pi; 130 struct cs4280_dma *sc_pdma; 131 char *sc_pbuf; 132 #ifdef DIAGNOSTIC 133 char sc_prun; 134 #endif 135 136 void (*sc_rintr)(void *); /* dma completion intr handler */ 137 void *sc_rarg; /* arg for sc_intr() */ 138 char *sc_rs, *sc_re, *sc_rn; 139 int sc_rcount; 140 int sc_ri; 141 struct cs4280_dma *sc_rdma; 142 char *sc_rbuf; 143 int sc_rparam; /* record format */ 144 #ifdef DIAGNOSTIC 145 char sc_rrun; 146 #endif 147 148 #if NMIDI > 0 149 void (*sc_iintr)(void *, int); /* midi input ready handler */ 150 void (*sc_ointr)(void *); /* midi output ready handler */ 151 void *sc_arg; 152 #endif 153 154 u_int32_t pctl; 155 u_int32_t cctl; 156 157 struct ac97_codec_if *codec_if; 158 struct ac97_host_if host_if; 159 160 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 161 }; 162 163 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 164 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 165 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 166 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 167 168 int cs4280_match(struct device *, void *, void *); 169 void cs4280_attach(struct device *, struct device *, void *); 170 int cs4280_activate(struct device *, int); 171 void cs4280_attachhook(void *xsc); 172 int cs4280_intr(void *); 173 void cs4280_reset(void *); 174 int cs4280_download_image(struct cs4280_softc *); 175 176 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 177 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t, 178 struct cs4280_dma *); 179 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *); 180 181 #ifdef CS4280_DEBUG 182 int cs4280_check_images(struct cs4280_softc *); 183 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 184 u_int32_t); 185 #endif 186 187 struct cfdriver clcs_cd = { 188 NULL, "clcs", DV_DULL 189 }; 190 191 struct cfattach clcs_ca = { 192 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach, NULL, 193 cs4280_activate 194 }; 195 196 int cs4280_init(struct cs4280_softc *, int); 197 int cs4280_init2(struct cs4280_softc *, int); 198 int cs4280_open(void *, int); 199 void cs4280_close(void *); 200 201 int cs4280_query_encoding(void *, struct audio_encoding *); 202 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 203 int cs4280_round_blocksize(void *, int); 204 void cs4280_get_default_params(void *, int, struct audio_params *); 205 206 int cs4280_halt_output(void *); 207 int cs4280_halt_input(void *); 208 209 int cs4280_getdev(void *, struct audio_device *); 210 211 int cs4280_mixer_set_port(void *, mixer_ctrl_t *); 212 int cs4280_mixer_get_port(void *, mixer_ctrl_t *); 213 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip); 214 void *cs4280_malloc(void *, int, size_t, int, int); 215 void cs4280_free(void *, void *, int); 216 size_t cs4280_round_buffersize(void *, int, size_t); 217 paddr_t cs4280_mappage(void *, void *, off_t, int); 218 int cs4280_get_props(void *); 219 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 220 void *, struct audio_params *); 221 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 222 void *, struct audio_params *); 223 224 225 void cs4280_set_dac_rate(struct cs4280_softc *, int ); 226 void cs4280_set_adc_rate(struct cs4280_softc *, int ); 227 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *, 228 char *); 229 int cs4280_src_wait(struct cs4280_softc *); 230 int cs4280_attach_codec(void *sc, struct ac97_codec_if *); 231 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d); 232 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d); 233 void cs4280_reset_codec(void *sc); 234 235 void cs4280_clear_fifos(struct cs4280_softc *); 236 237 #if NMIDI > 0 238 void cs4280_midi_close(void *); 239 void cs4280_midi_getinfo(void *, struct midi_info *); 240 int cs4280_midi_open(void *, int, void (*)(void *, int), 241 void (*)(void *), void *); 242 int cs4280_midi_output(void *, int); 243 #endif 244 245 struct audio_hw_if cs4280_hw_if = { 246 cs4280_open, 247 cs4280_close, 248 NULL, 249 cs4280_query_encoding, 250 cs4280_set_params, 251 cs4280_round_blocksize, 252 NULL, 253 NULL, 254 NULL, 255 NULL, 256 NULL, 257 cs4280_halt_output, 258 cs4280_halt_input, 259 NULL, 260 cs4280_getdev, 261 NULL, 262 cs4280_mixer_set_port, 263 cs4280_mixer_get_port, 264 cs4280_query_devinfo, 265 cs4280_malloc, 266 cs4280_free, 267 cs4280_round_buffersize, 268 0, /* cs4280_mappage, */ 269 cs4280_get_props, 270 cs4280_trigger_output, 271 cs4280_trigger_input, 272 cs4280_get_default_params 273 }; 274 275 #if NMIDI > 0 276 struct midi_hw_if cs4280_midi_hw_if = { 277 cs4280_midi_open, 278 cs4280_midi_close, 279 cs4280_midi_output, 280 0, /* flush */ 281 cs4280_midi_getinfo, 282 0, /* ioctl */ 283 }; 284 #endif 285 286 287 288 struct audio_device cs4280_device = { 289 "CS4280", 290 "", 291 "cs4280" 292 }; 293 294 const struct pci_matchid cs4280_devices[] = { 295 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, 296 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, 297 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 }, 298 }; 299 300 int 301 cs4280_match(struct device *parent, void *ma, void *aux) 302 { 303 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, 304 nitems(cs4280_devices))); 305 } 306 307 int 308 cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data) 309 { 310 struct cs4280_softc *sc = sc_; 311 int n; 312 313 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 314 /* 315 * Make sure that there is not data sitting around from a preivous 316 * uncompleted access. 317 */ 318 BA0READ4(sc, CS4280_ACSDA); 319 320 /* Set up AC97 control registers. */ 321 BA0WRITE4(sc, CS4280_ACCAD, add); 322 BA0WRITE4(sc, CS4280_ACCDA, 0); 323 BA0WRITE4(sc, CS4280_ACCTL, 324 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 325 326 if (cs4280_src_wait(sc) < 0) { 327 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 328 sc->sc_dev.dv_xname, add); 329 return (1); 330 } 331 332 /* wait for valid status bit is active */ 333 n = 0; 334 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 335 delay(1); 336 while (++n > 1000) { 337 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 338 sc->sc_dev.dv_xname, add); 339 return (1); 340 } 341 } 342 *data = BA0READ4(sc, CS4280_ACSDA); 343 DPRINTFN(5,("data=0x%04x\n", *data)); 344 return (0); 345 } 346 347 int 348 cs4280_write_codec(void *sc_, u_int8_t add, u_int16_t data) 349 { 350 struct cs4280_softc *sc = sc_; 351 352 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 353 BA0WRITE4(sc, CS4280_ACCAD, add); 354 BA0WRITE4(sc, CS4280_ACCDA, data); 355 BA0WRITE4(sc, CS4280_ACCTL, 356 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 357 358 if (cs4280_src_wait(sc) < 0) { 359 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 360 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 361 return (1); 362 } 363 return (0); 364 } 365 366 int 367 cs4280_src_wait(struct cs4280_softc *sc) 368 { 369 int n; 370 371 n = 0; 372 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 373 delay(1000); 374 if (++n > 1000) 375 return (-1); 376 } 377 return (0); 378 } 379 380 381 void 382 cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) 383 { 384 /* calculate capture rate: 385 * 386 * capture_coefficient_increment = -round(rate*128*65536/48000; 387 * capture_phase_increment = floor(48000*65536*1024/rate); 388 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 389 * cy = floor(cx/200); 390 * capture_sample_rate_correction = cx - 200*cy; 391 * capture_delay = ceil(24*48000/rate); 392 * capture_num_triplets = floor(65536*rate/24000); 393 * capture_group_length = 24000/GCD(rate, 24000); 394 * where GCD means "Greatest Common Divisor". 395 * 396 * capture_coefficient_increment, capture_phase_increment and 397 * capture_num_triplets are 32-bit signed quantities. 398 * capture_sample_rate_correction and capture_group_length are 399 * 16-bit signed quantities. 400 * capture_delay is a 14-bit unsigned quantity. 401 */ 402 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 403 u_int16_t csrc, cgl, cdlay; 404 405 /* XXX 406 * Even though, embedded_audio_spec says capture rate range 11025 to 407 * 48000, dhwiface.cpp says, 408 * 409 * "We can only decimate by up to a factor of 1/9th the hardware rate. 410 * Return an error if an attempt is made to stray outside that limit." 411 * 412 * so assume range as 48000/9 to 48000 413 */ 414 415 if (rate < 8000) 416 rate = 8000; 417 if (rate > 48000) 418 rate = 48000; 419 420 cx = rate << 16; 421 cci = cx / 48000; 422 cx -= cci * 48000; 423 cx <<= 7; 424 cci <<= 7; 425 cci += cx / 48000; 426 cci = - cci; 427 428 cx = 48000 << 16; 429 cpi = cx / rate; 430 cx -= cpi * rate; 431 cx <<= 10; 432 cpi <<= 10; 433 cy = cx / rate; 434 cpi += cy; 435 cx -= cy * rate; 436 437 cy = cx / 200; 438 csrc = cx - 200*cy; 439 440 cdlay = ((48000 * 24) + rate - 1) / rate; 441 #if 0 442 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 443 #endif 444 445 cnt = rate << 16; 446 cnt /= 24000; 447 448 cgl = 1; 449 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 450 if (((rate / tmp1) * tmp1) != rate) 451 cgl *= 2; 452 } 453 if (((rate / 3) * 3) != rate) 454 cgl *= 3; 455 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 456 if (((rate / tmp1) * tmp1) != rate) 457 cgl *= 5; 458 } 459 #if 0 460 /* XXX what manual says */ 461 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 462 tmp1 |= csrc<<16; 463 BA1WRITE4(sc, CS4280_CSRC, tmp1); 464 #else 465 /* suggested by cs461x.c (ALSA driver) */ 466 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 467 #endif 468 469 #if 0 470 /* I am confused. The sample rate calculation section says 471 * cci *is* 32-bit signed quantity but in the parameter description 472 * section, CCI only assigned 16bit. 473 * I believe size of the variable. 474 */ 475 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 476 tmp1 |= cci<<16; 477 BA1WRITE4(sc, CS4280_CCI, tmp1); 478 #else 479 BA1WRITE4(sc, CS4280_CCI, cci); 480 #endif 481 482 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 483 tmp1 |= cdlay <<18; 484 BA1WRITE4(sc, CS4280_CD, tmp1); 485 486 BA1WRITE4(sc, CS4280_CPI, cpi); 487 488 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 489 tmp1 |= cgl; 490 BA1WRITE4(sc, CS4280_CGL, tmp1); 491 492 BA1WRITE4(sc, CS4280_CNT, cnt); 493 494 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 495 tmp1 |= cgl; 496 BA1WRITE4(sc, CS4280_CGC, tmp1); 497 } 498 499 void 500 cs4280_set_dac_rate(struct cs4280_softc *sc, int rate) 501 { 502 /* 503 * playback rate may range from 8000Hz to 48000Hz 504 * 505 * play_phase_increment = floor(rate*65536*1024/48000) 506 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 507 * py=floor(px/200) 508 * play_sample_rate_correction = px - 200*py 509 * 510 * play_phase_increment is a 32bit signed quantity. 511 * play_sample_rate_correction is a 16bit signed quantity. 512 */ 513 int32_t ppi; 514 int16_t psrc; 515 u_int32_t px, py; 516 517 if (rate < 8000) 518 rate = 8000; 519 if (rate > 48000) 520 rate = 48000; 521 px = rate << 16; 522 ppi = px/48000; 523 px -= ppi*48000; 524 ppi <<= 10; 525 px <<= 10; 526 py = px / 48000; 527 ppi += py; 528 px -= py*48000; 529 py = px/200; 530 px -= py*200; 531 psrc = px; 532 #if 0 533 /* what manual says */ 534 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 535 BA1WRITE4(sc, CS4280_PSRC, 536 ( ((psrc<<16) & PSRC_MASK) | px )); 537 #else 538 /* suggested by cs461x.c (ALSA driver) */ 539 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 540 #endif 541 BA1WRITE4(sc, CS4280_PPI, ppi); 542 } 543 544 void 545 cs4280_attachhook(void *xsc) 546 { 547 struct cs4280_softc *sc = xsc; 548 mixer_ctrl_t ctl; 549 550 /* Initialization */ 551 if (cs4280_init2(sc, 1) != 0) 552 return; 553 554 printf("%s: firmware loaded\n", sc->sc_dev.dv_xname); 555 556 /* Turn mute off of DAC, CD and master volumes by default */ 557 ctl.type = AUDIO_MIXER_ENUM; 558 ctl.un.ord = 0; /* off */ 559 560 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 561 AudioNmaster, AudioNmute); 562 cs4280_mixer_set_port(sc, &ctl); 563 564 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 565 AudioNdac, AudioNmute); 566 cs4280_mixer_set_port(sc, &ctl); 567 568 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 569 AudioNcd, AudioNmute); 570 cs4280_mixer_set_port(sc, &ctl); 571 572 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev); 573 574 #if NMIDI > 0 575 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 576 #endif 577 } 578 579 void 580 cs4280_attach(struct device *parent, struct device *self, void *aux) 581 { 582 struct cs4280_softc *sc = (struct cs4280_softc *) self; 583 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 584 pci_chipset_tag_t pc = pa->pa_pc; 585 char const *intrstr; 586 pci_intr_handle_t ih; 587 u_int32_t mem; 588 589 /* Map I/O register */ 590 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 591 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 592 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 593 printf(": can't map BA0 space\n"); 594 return; 595 } 596 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 597 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 598 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 599 printf(": can't map BA1 space\n"); 600 return; 601 } 602 603 sc->sc_dmatag = pa->pa_dmat; 604 605 /* Get out of power save mode if needed. */ 606 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 607 608 /* LATENCY_TIMER setting */ 609 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 610 if ( PCI_LATTIMER(mem) < 32 ) { 611 mem &= 0xffff00ff; 612 mem |= 0x00002000; 613 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 614 } 615 616 /* Map and establish the interrupt. */ 617 if (pci_intr_map(pa, &ih)) { 618 printf(": couldn't map interrupt\n"); 619 return; 620 } 621 intrstr = pci_intr_string(pc, ih); 622 623 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc, 624 sc->sc_dev.dv_xname); 625 if (sc->sc_ih == NULL) { 626 printf(": couldn't establish interrupt"); 627 if (intrstr != NULL) 628 printf(" at %s", intrstr); 629 printf("\n"); 630 return; 631 } 632 printf(": %s\n", intrstr); 633 634 /* Initialization */ 635 if (cs4280_init(sc, 1) != 0) 636 return; 637 638 mountroothook_establish(cs4280_attachhook, sc); 639 640 /* AC 97 attachement */ 641 sc->host_if.arg = sc; 642 sc->host_if.attach = cs4280_attach_codec; 643 sc->host_if.read = cs4280_read_codec; 644 sc->host_if.write = cs4280_write_codec; 645 sc->host_if.reset = cs4280_reset_codec; 646 647 if (ac97_attach(&sc->host_if) != 0) { 648 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 649 return; 650 } 651 } 652 653 int 654 cs4280_intr(void *p) 655 { 656 /* 657 * XXX 658 * 659 * Since CS4280 has only 4kB dma buffer and 660 * interrupt occurs every 2kB block, I create dummy buffer 661 * which returns to audio driver and actual dma buffer 662 * using in DMA transfer. 663 * 664 * 665 * ring buffer in audio.c is pointed by BUFADDR 666 * <------ ring buffer size == 64kB ------> 667 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 668 * |= = = =|= = = =|= = = =|= = = =|= = = =| 669 * | | | | | | <- call audio_intp every 670 * sc->sc_[pr]_count time. 671 * 672 * actual dma buffer is pointed by KERNADDR 673 * <-> dma buffer size = 4kB 674 * |= =| 675 * 676 * 677 */ 678 struct cs4280_softc *sc = p; 679 u_int32_t intr, mem; 680 char * empty_dma; 681 int handled = 0; 682 683 /* grab interrupt register then clear it */ 684 intr = BA0READ4(sc, CS4280_HISR); 685 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 686 687 /* Playback Interrupt */ 688 if (intr & HISR_PINT) { 689 handled = 1; 690 mem = BA1READ4(sc, CS4280_PFIE); 691 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 692 if (sc->sc_pintr) { 693 if ((sc->sc_pi%sc->sc_pcount) == 0) 694 sc->sc_pintr(sc->sc_parg); 695 } else { 696 printf("unexpected play intr\n"); 697 } 698 /* copy buffer */ 699 ++sc->sc_pi; 700 empty_dma = sc->sc_pdma->addr; 701 if (sc->sc_pi&1) 702 empty_dma += CS4280_ICHUNK; 703 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 704 sc->sc_pn += CS4280_ICHUNK; 705 if (sc->sc_pn >= sc->sc_pe) 706 sc->sc_pn = sc->sc_ps; 707 BA1WRITE4(sc, CS4280_PFIE, mem); 708 } 709 /* Capture Interrupt */ 710 if (intr & HISR_CINT) { 711 int i; 712 int16_t rdata; 713 714 handled = 1; 715 mem = BA1READ4(sc, CS4280_CIE); 716 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 717 ++sc->sc_ri; 718 empty_dma = sc->sc_rdma->addr; 719 if ((sc->sc_ri&1) == 0) 720 empty_dma += CS4280_ICHUNK; 721 722 /* 723 * XXX 724 * I think this audio data conversion should be 725 * happend in upper layer, but I put this here 726 * since there is no conversion function available. 727 */ 728 switch(sc->sc_rparam) { 729 case CF_16BIT_STEREO: 730 /* just copy it */ 731 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 732 sc->sc_rn += CS4280_ICHUNK; 733 break; 734 case CF_16BIT_MONO: 735 for (i = 0; i < 512; i++) { 736 rdata = *((int16_t *)empty_dma)>>1; 737 empty_dma += 2; 738 rdata += *((int16_t *)empty_dma)>>1; 739 empty_dma += 2; 740 *((int16_t *)sc->sc_rn) = rdata; 741 sc->sc_rn += 2; 742 } 743 break; 744 case CF_8BIT_STEREO: 745 for (i = 0; i < 512; i++) { 746 rdata = *((int16_t*)empty_dma); 747 empty_dma += 2; 748 *sc->sc_rn++ = rdata >> 8; 749 rdata = *((int16_t*)empty_dma); 750 empty_dma += 2; 751 *sc->sc_rn++ = rdata >> 8; 752 } 753 break; 754 case CF_8BIT_MONO: 755 for (i = 0; i < 512; i++) { 756 rdata = *((int16_t*)empty_dma) >>1; 757 empty_dma += 2; 758 rdata += *((int16_t*)empty_dma) >>1; 759 empty_dma += 2; 760 *sc->sc_rn++ = rdata >>8; 761 } 762 break; 763 default: 764 /* Should not reach here */ 765 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 766 } 767 if (sc->sc_rn >= sc->sc_re) 768 sc->sc_rn = sc->sc_rs; 769 BA1WRITE4(sc, CS4280_CIE, mem); 770 if (sc->sc_rintr) { 771 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 772 sc->sc_rintr(sc->sc_rarg); 773 } else { 774 printf("unexpected record intr\n"); 775 } 776 } 777 778 #if NMIDI > 0 779 /* Midi port Interrupt */ 780 if (intr & HISR_MIDI) { 781 int data; 782 783 handled = 1; 784 DPRINTF(("i: %d: ", 785 BA0READ4(sc, CS4280_MIDSR))); 786 /* Read the received data */ 787 while ((sc->sc_iintr != NULL) && 788 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 789 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 790 DPRINTF(("r:%x\n",data)); 791 sc->sc_iintr(sc->sc_arg, data); 792 } 793 794 /* Write the data */ 795 #if 1 796 /* XXX: 797 * It seems "Transmit Buffer Full" never activate until EOI 798 * is delivered. Shall I throw EOI top of this routine ? 799 */ 800 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 801 DPRINTF(("w: ")); 802 if (sc->sc_ointr != NULL) 803 sc->sc_ointr(sc->sc_arg); 804 } 805 #else 806 while ((sc->sc_ointr != NULL) && 807 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 808 DPRINTF(("w: ")); 809 sc->sc_ointr(sc->sc_arg); 810 } 811 #endif 812 DPRINTF(("\n")); 813 } 814 #endif 815 816 return handled; 817 } 818 819 820 /* Download Proceessor Code and Data image */ 821 822 int 823 cs4280_download(struct cs4280_softc *sc, const u_int32_t *src, u_int32_t offset, 824 u_int32_t len) 825 { 826 u_int32_t ctr; 827 828 #ifdef CS4280_DEBUG 829 u_int32_t con, data; 830 u_int8_t c0,c1,c2,c3; 831 #endif 832 if ((offset&3) || (len&3)) 833 return (-1); 834 835 len /= sizeof(u_int32_t); 836 for (ctr = 0; ctr < len; ctr++) { 837 /* XXX: 838 * I cannot confirm this is the right thing or not 839 * on BIG-ENDIAN machines. 840 */ 841 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 842 #ifdef CS4280_DEBUG 843 data = htole32(*(src+ctr)); 844 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 845 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 846 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 847 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 848 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 849 if (data != con ) { 850 printf("0x%06x: write=0x%08x read=0x%08x\n", 851 offset+ctr*4, data, con); 852 return (-1); 853 } 854 #endif 855 } 856 return (0); 857 } 858 859 struct BA1struct *BA1Struct; 860 861 int 862 cs4280_download_image(struct cs4280_softc *sc) 863 { 864 int idx, err = 0; 865 u_int32_t offset = 0; 866 static u_char *cs4280_firmware; 867 static size_t cs4280_firmwarelen; 868 869 if (cs4280_firmware == NULL) { 870 err = loadfirmware("cs4280", &cs4280_firmware, 871 &cs4280_firmwarelen); 872 if (err) 873 return (err); 874 } 875 876 BA1Struct = (struct BA1struct *)cs4280_firmware; 877 878 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 879 err = cs4280_download(sc, &BA1Struct->map[offset], 880 BA1Struct->memory[idx].offset, BA1Struct->memory[idx].size); 881 if (err != 0) { 882 printf("%s: load_image failed at %d\n", 883 sc->sc_dev.dv_xname, idx); 884 return (-1); 885 } 886 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 887 } 888 return (err); 889 } 890 891 #ifdef CS4280_DEBUG 892 int 893 cs4280_checkimage(struct cs4280_softc *sc, u_int32_t *src, u_int32_t offset, 894 u_int32_t len) 895 { 896 u_int32_t ctr, data; 897 int err = 0; 898 899 if ((offset&3) || (len&3)) 900 return -1; 901 902 len /= sizeof(u_int32_t); 903 for (ctr = 0; ctr < len; ctr++) { 904 /* I cannot confirm this is the right thing 905 * on BIG-ENDIAN machines 906 */ 907 data = BA1READ4(sc, offset+ctr*4); 908 if (data != htole32(*(src+ctr))) { 909 printf("0x%06x: 0x%08x(0x%08x)\n", 910 offset+ctr*4, data, *(src+ctr)); 911 *(src+ctr) = data; 912 ++err; 913 } 914 } 915 return (err); 916 } 917 918 int 919 cs4280_check_images(struct cs4280_softc *sc) 920 { 921 int idx, err; 922 u_int32_t offset = 0; 923 924 err = 0; 925 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 926 for (idx = 0; idx < 1; ++idx) { 927 err = cs4280_checkimage(sc, &BA1Struct->map[offset], 928 BA1Struct->memory[idx].offset, 929 BA1Struct->memory[idx].size); 930 if (err != 0) { 931 printf("%s: check_image failed at %d\n", 932 sc->sc_dev.dv_xname, idx); 933 } 934 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 935 } 936 return (err); 937 } 938 939 #endif 940 941 int 942 cs4280_attach_codec(void *sc_, struct ac97_codec_if *codec_if) 943 { 944 struct cs4280_softc *sc = sc_; 945 946 sc->codec_if = codec_if; 947 return (0); 948 } 949 950 void 951 cs4280_reset_codec(void *sc_) 952 { 953 struct cs4280_softc *sc = sc_; 954 int n; 955 956 /* Reset codec */ 957 BA0WRITE4(sc, CS4280_ACCTL, 0); 958 delay(100); /* delay 100us */ 959 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 960 961 /* 962 * It looks like we do the following procedure, too 963 */ 964 965 /* Enable AC-link sync generation */ 966 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 967 delay(50*1000); /* XXX delay 50ms */ 968 969 /* Assert valid frame signal */ 970 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 971 972 /* Wait for valid AC97 input slot */ 973 n = 0; 974 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 975 delay(1000); 976 if (++n > 1000) { 977 printf("reset_codec: AC97 inputs slot ready timeout\n"); 978 return; 979 } 980 } 981 } 982 983 984 /* Processor Soft Reset */ 985 void 986 cs4280_reset(void *sc_) 987 { 988 struct cs4280_softc *sc = sc_; 989 990 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 991 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 992 delay(100); 993 /* Clear RSTSP bit in SPCR */ 994 BA1WRITE4(sc, CS4280_SPCR, 0); 995 /* enable DMA reqest */ 996 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 997 } 998 999 int 1000 cs4280_open(void *addr, int flags) 1001 { 1002 return (0); 1003 } 1004 1005 void 1006 cs4280_close(void *addr) 1007 { 1008 struct cs4280_softc *sc = addr; 1009 1010 cs4280_halt_output(sc); 1011 cs4280_halt_input(sc); 1012 1013 sc->sc_pintr = 0; 1014 sc->sc_rintr = 0; 1015 } 1016 1017 int 1018 cs4280_query_encoding(void *addr, struct audio_encoding *fp) 1019 { 1020 switch (fp->index) { 1021 case 0: 1022 strlcpy(fp->name, AudioEulinear, sizeof fp->name); 1023 fp->encoding = AUDIO_ENCODING_ULINEAR; 1024 fp->precision = 8; 1025 fp->flags = 0; 1026 break; 1027 case 1: 1028 strlcpy(fp->name, AudioEmulaw, sizeof fp->name); 1029 fp->encoding = AUDIO_ENCODING_ULAW; 1030 fp->precision = 8; 1031 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1032 break; 1033 case 2: 1034 strlcpy(fp->name, AudioEalaw, sizeof fp->name); 1035 fp->encoding = AUDIO_ENCODING_ALAW; 1036 fp->precision = 8; 1037 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 1038 break; 1039 case 3: 1040 strlcpy(fp->name, AudioEslinear, sizeof fp->name); 1041 fp->encoding = AUDIO_ENCODING_SLINEAR; 1042 fp->precision = 8; 1043 fp->flags = 0; 1044 break; 1045 case 4: 1046 strlcpy(fp->name, AudioEslinear_le, sizeof fp->name); 1047 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 1048 fp->precision = 16; 1049 fp->flags = 0; 1050 break; 1051 case 5: 1052 strlcpy(fp->name, AudioEulinear_le, sizeof fp->name); 1053 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 1054 fp->precision = 16; 1055 fp->flags = 0; 1056 break; 1057 case 6: 1058 strlcpy(fp->name, AudioEslinear_be, sizeof fp->name); 1059 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 1060 fp->precision = 16; 1061 fp->flags = 0; 1062 break; 1063 case 7: 1064 strlcpy(fp->name, AudioEulinear_be, sizeof fp->name); 1065 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 1066 fp->precision = 16; 1067 fp->flags = 0; 1068 break; 1069 default: 1070 return (EINVAL); 1071 } 1072 fp->bps = AUDIO_BPS(fp->precision); 1073 fp->msb = 1; 1074 1075 return (0); 1076 } 1077 1078 int 1079 cs4280_set_params(void *addr, int setmode, int usemode, 1080 struct audio_params *play, struct audio_params *rec) 1081 { 1082 struct cs4280_softc *sc = addr; 1083 struct audio_params *p; 1084 int mode; 1085 1086 for (mode = AUMODE_RECORD; mode != -1; 1087 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 1088 if ((setmode & mode) == 0) 1089 continue; 1090 1091 p = mode == AUMODE_PLAY ? play : rec; 1092 if (p == play) { 1093 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1094 p->sample_rate, p->precision, p->channels)); 1095 } else { 1096 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1097 p->sample_rate, p->precision, p->channels)); 1098 } 1099 /* play back data format may be 8- or 16-bit and 1100 * either stereo or mono. 1101 * playback rate may range from 8000Hz to 48000Hz 1102 * 1103 * capture data format must be 16bit stereo 1104 * and sample rate range from 11025Hz to 48000Hz. 1105 * 1106 * XXX: it looks like to work with 8000Hz, 1107 * although data sheets say lower limit is 1108 * 11025 Hz. 1109 */ 1110 if (p->sample_rate < 8000) 1111 p->sample_rate = 8000; 1112 if (p->sample_rate > 48000) 1113 p->sample_rate = 48000; 1114 if (p->precision > 16) 1115 p->precision = 16; 1116 if (p->channels > 2) 1117 p->channels = 2; 1118 p->factor = 1; 1119 p->sw_code = 0; 1120 1121 /* capturing data is slinear */ 1122 switch (p->encoding) { 1123 case AUDIO_ENCODING_SLINEAR_BE: 1124 if (mode == AUMODE_RECORD) { 1125 if (p->precision == 16) 1126 p->sw_code = swap_bytes; 1127 } 1128 break; 1129 case AUDIO_ENCODING_SLINEAR_LE: 1130 break; 1131 case AUDIO_ENCODING_ULINEAR_BE: 1132 if (mode == AUMODE_RECORD) { 1133 if (p->precision == 16) 1134 p->sw_code = change_sign16_swap_bytes_le; 1135 else 1136 p->sw_code = change_sign8; 1137 } 1138 break; 1139 case AUDIO_ENCODING_ULINEAR_LE: 1140 if (mode == AUMODE_RECORD) { 1141 if (p->precision == 16) 1142 p->sw_code = change_sign16_le; 1143 else 1144 p->sw_code = change_sign8; 1145 } 1146 break; 1147 case AUDIO_ENCODING_ULAW: 1148 if (mode == AUMODE_PLAY) { 1149 p->factor = 2; 1150 p->sw_code = mulaw_to_slinear16_le; 1151 } else { 1152 p->sw_code = slinear8_to_mulaw; 1153 } 1154 break; 1155 case AUDIO_ENCODING_ALAW: 1156 if (mode == AUMODE_PLAY) { 1157 p->factor = 2; 1158 p->sw_code = alaw_to_slinear16_le; 1159 } else { 1160 p->sw_code = slinear8_to_alaw; 1161 } 1162 break; 1163 default: 1164 return (EINVAL); 1165 } 1166 p->bps = AUDIO_BPS(p->precision); 1167 p->msb = 1; 1168 } 1169 1170 /* set sample rate */ 1171 cs4280_set_dac_rate(sc, play->sample_rate); 1172 cs4280_set_adc_rate(sc, rec->sample_rate); 1173 return (0); 1174 } 1175 1176 int 1177 cs4280_round_blocksize(void *hdl, int blk) 1178 { 1179 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1180 } 1181 1182 size_t 1183 cs4280_round_buffersize(void *addr, int direction, size_t size) 1184 { 1185 /* although real dma buffer size is 4KB, 1186 * let the audio.c driver use a larger buffer. 1187 * ( suggested by Lennart Augustsson. ) 1188 */ 1189 return (size); 1190 } 1191 1192 void 1193 cs4280_get_default_params(void *addr, int mode, struct audio_params *params) 1194 { 1195 ac97_get_default_params(params); 1196 } 1197 1198 int 1199 cs4280_get_props(void *hdl) 1200 { 1201 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX); 1202 #ifdef notyet 1203 /* XXX 1204 * How can I mmap ? 1205 */ 1206 AUDIO_PROP_MMAP 1207 #endif 1208 1209 } 1210 1211 int 1212 cs4280_mixer_get_port(void *addr, mixer_ctrl_t *cp) 1213 { 1214 struct cs4280_softc *sc = addr; 1215 1216 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1217 } 1218 1219 paddr_t 1220 cs4280_mappage(void *addr, void *mem, off_t off, int prot) 1221 { 1222 struct cs4280_softc *sc = addr; 1223 struct cs4280_dma *p; 1224 1225 if (off < 0) 1226 return (-1); 1227 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next) 1228 ; 1229 if (!p) { 1230 DPRINTF(("cs4280_mappage: bad buffer address\n")); 1231 return (-1); 1232 } 1233 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs, 1234 off, prot, BUS_DMA_WAITOK)); 1235 } 1236 1237 1238 int 1239 cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip) 1240 { 1241 struct cs4280_softc *sc = addr; 1242 1243 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1244 } 1245 1246 int 1247 cs4280_get_portnum_by_name(struct cs4280_softc *sc, char *class, char *device, 1248 char *qualifier) 1249 { 1250 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1251 device, qualifier)); 1252 } 1253 1254 int 1255 cs4280_halt_output(void *addr) 1256 { 1257 struct cs4280_softc *sc = addr; 1258 u_int32_t mem; 1259 1260 mem = BA1READ4(sc, CS4280_PCTL); 1261 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1262 #ifdef DIAGNOSTIC 1263 sc->sc_prun = 0; 1264 #endif 1265 return (0); 1266 } 1267 1268 int 1269 cs4280_halt_input(void *addr) 1270 { 1271 struct cs4280_softc *sc = addr; 1272 u_int32_t mem; 1273 1274 mem = BA1READ4(sc, CS4280_CCTL); 1275 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1276 #ifdef DIAGNOSTIC 1277 sc->sc_rrun = 0; 1278 #endif 1279 return (0); 1280 } 1281 1282 int 1283 cs4280_getdev(void *addr, struct audio_device *retp) 1284 { 1285 *retp = cs4280_device; 1286 return (0); 1287 } 1288 1289 int 1290 cs4280_mixer_set_port(void *addr, mixer_ctrl_t *cp) 1291 { 1292 struct cs4280_softc *sc = addr; 1293 int val; 1294 1295 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1296 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1297 return (val); 1298 } 1299 1300 1301 int 1302 cs4280_freemem(struct cs4280_softc *sc, struct cs4280_dma *p) 1303 { 1304 bus_dmamap_unload(sc->sc_dmatag, p->map); 1305 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1306 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1307 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1308 return (0); 1309 } 1310 1311 int 1312 cs4280_allocmem(struct cs4280_softc *sc, size_t size, size_t align, 1313 struct cs4280_dma *p) 1314 { 1315 int error; 1316 1317 /* XXX */ 1318 p->size = size; 1319 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1320 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1321 &p->nsegs, BUS_DMA_NOWAIT); 1322 if (error) { 1323 printf("%s: unable to allocate dma, error=%d\n", 1324 sc->sc_dev.dv_xname, error); 1325 return (error); 1326 } 1327 1328 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1329 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1330 if (error) { 1331 printf("%s: unable to map dma, error=%d\n", 1332 sc->sc_dev.dv_xname, error); 1333 goto free; 1334 } 1335 1336 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1337 0, BUS_DMA_NOWAIT, &p->map); 1338 if (error) { 1339 printf("%s: unable to create dma map, error=%d\n", 1340 sc->sc_dev.dv_xname, error); 1341 goto unmap; 1342 } 1343 1344 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1345 BUS_DMA_NOWAIT); 1346 if (error) { 1347 printf("%s: unable to load dma map, error=%d\n", 1348 sc->sc_dev.dv_xname, error); 1349 goto destroy; 1350 } 1351 return (0); 1352 1353 destroy: 1354 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1355 unmap: 1356 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1357 free: 1358 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1359 return (error); 1360 } 1361 1362 1363 void * 1364 cs4280_malloc(void *addr, int direction, size_t size, int pool, int flags) 1365 { 1366 struct cs4280_softc *sc = addr; 1367 struct cs4280_dma *p; 1368 caddr_t q; 1369 int error; 1370 1371 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1372 q = malloc(size, pool, flags); 1373 if (!q) 1374 return (0); 1375 p = malloc(sizeof(*p), pool, flags); 1376 if (!p) { 1377 free(q,pool); 1378 return (0); 1379 } 1380 /* 1381 * cs4280 has fixed 4kB buffer 1382 */ 1383 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1384 1385 if (error) { 1386 free(q, pool); 1387 free(p, pool); 1388 return (0); 1389 } 1390 1391 p->next = sc->sc_dmas; 1392 sc->sc_dmas = p; 1393 p->dum = q; /* return to audio driver */ 1394 1395 return (p->dum); 1396 } 1397 1398 void 1399 cs4280_free(void *addr, void *ptr, int pool) 1400 { 1401 struct cs4280_softc *sc = addr; 1402 struct cs4280_dma **pp, *p; 1403 1404 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1405 if (BUFADDR(p) == ptr) { 1406 cs4280_freemem(sc, p); 1407 *pp = p->next; 1408 free(p->dum, pool); 1409 free(p, pool); 1410 return; 1411 } 1412 } 1413 } 1414 1415 int 1416 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 1417 void (*intr)(void *), void *arg, struct audio_params *param) 1418 { 1419 struct cs4280_softc *sc = addr; 1420 u_int32_t pfie, pctl, mem, pdtc; 1421 struct cs4280_dma *p; 1422 1423 #ifdef DIAGNOSTIC 1424 if (sc->sc_prun) 1425 printf("cs4280_trigger_output: already running\n"); 1426 sc->sc_prun = 1; 1427 #endif 1428 1429 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1430 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1431 sc->sc_pintr = intr; 1432 sc->sc_parg = arg; 1433 1434 /* stop playback DMA */ 1435 mem = BA1READ4(sc, CS4280_PCTL); 1436 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1437 1438 /* setup PDTC */ 1439 pdtc = BA1READ4(sc, CS4280_PDTC); 1440 pdtc &= ~PDTC_MASK; 1441 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1442 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1443 1444 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n", 1445 param->precision, param->factor, param->channels, 1446 param->encoding)); 1447 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1448 ; 1449 if (p == NULL) { 1450 printf("cs4280_trigger_output: bad addr %p\n", start); 1451 return (EINVAL); 1452 } 1453 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1454 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1455 "4kB align\n", DMAADDR(p)); 1456 return (EINVAL); 1457 } 1458 1459 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1460 sc->sc_ps = (char *)start; 1461 sc->sc_pe = (char *)end; 1462 sc->sc_pdma = p; 1463 sc->sc_pbuf = KERNADDR(p); 1464 sc->sc_pi = 0; 1465 sc->sc_pn = sc->sc_ps; 1466 if (blksize >= CS4280_DCHUNK) { 1467 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1468 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1469 ++sc->sc_pi; 1470 } else { 1471 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1472 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1473 } 1474 1475 /* initiate playback dma */ 1476 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1477 1478 /* set PFIE */ 1479 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1480 1481 if (param->precision * param->factor == 8) 1482 pfie |= PFIE_8BIT; 1483 if (param->channels == 1) 1484 pfie |= PFIE_MONO; 1485 1486 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1487 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1488 pfie |= PFIE_SWAPPED; 1489 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1490 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1491 pfie |= PFIE_UNSIGNED; 1492 1493 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1494 1495 cs4280_set_dac_rate(sc, param->sample_rate); 1496 1497 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1498 pctl |= sc->pctl; 1499 BA1WRITE4(sc, CS4280_PCTL, pctl); 1500 return (0); 1501 } 1502 1503 int 1504 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 1505 void (*intr)(void *), void *arg, struct audio_params *param) 1506 { 1507 struct cs4280_softc *sc = addr; 1508 u_int32_t cctl, cie; 1509 struct cs4280_dma *p; 1510 1511 #ifdef DIAGNOSTIC 1512 if (sc->sc_rrun) 1513 printf("cs4280_trigger_input: already running\n"); 1514 sc->sc_rrun = 1; 1515 #endif 1516 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1517 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1518 sc->sc_rintr = intr; 1519 sc->sc_rarg = arg; 1520 1521 sc->sc_ri = 0; 1522 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1523 sc->sc_rs = (char *)start; 1524 sc->sc_re = (char *)end; 1525 sc->sc_rn = sc->sc_rs; 1526 1527 /* setup format information for internal converter */ 1528 sc->sc_rparam = 0; 1529 if (param->precision == 8) { 1530 sc->sc_rparam += CF_8BIT; 1531 sc->sc_rcount <<= 1; 1532 } 1533 if (param->channels == 1) { 1534 sc->sc_rparam += CF_MONO; 1535 sc->sc_rcount <<= 1; 1536 } 1537 1538 /* stop capture DMA */ 1539 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1540 BA1WRITE4(sc, CS4280_CCTL, cctl); 1541 1542 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1543 ; 1544 if (!p) { 1545 printf("cs4280_trigger_input: bad addr %p\n", start); 1546 return (EINVAL); 1547 } 1548 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1549 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1550 "4kB align\n", DMAADDR(p)); 1551 return (EINVAL); 1552 } 1553 sc->sc_rdma = p; 1554 sc->sc_rbuf = KERNADDR(p); 1555 1556 /* initiate capture dma */ 1557 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1558 1559 /* set CIE */ 1560 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1561 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1562 1563 cs4280_set_adc_rate(sc, param->sample_rate); 1564 1565 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1566 cctl |= sc->cctl; 1567 BA1WRITE4(sc, CS4280_CCTL, cctl); 1568 return (0); 1569 } 1570 1571 1572 int 1573 cs4280_init(struct cs4280_softc *sc, int init) 1574 { 1575 int n; 1576 u_int32_t mem; 1577 1578 /* Start PLL out in known state */ 1579 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1580 /* Start serial ports out in known state */ 1581 BA0WRITE4(sc, CS4280_SERMC1, 0); 1582 1583 /* Specify type of CODEC */ 1584 /* XXX should no be here */ 1585 #define SERACC_CODEC_TYPE_1_03 1586 #ifdef SERACC_CODEC_TYPE_1_03 1587 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1588 #else 1589 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1590 #endif 1591 1592 /* Reset codec */ 1593 BA0WRITE4(sc, CS4280_ACCTL, 0); 1594 delay(100); /* delay 100us */ 1595 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1596 1597 /* Enable AC-link sync generation */ 1598 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1599 delay(50*1000); /* delay 50ms */ 1600 1601 /* Set the serial port timing configuration */ 1602 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1603 1604 /* Setup clock control */ 1605 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1606 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1607 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1608 1609 /* Power up the PLL */ 1610 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1611 delay(50*1000); /* delay 50ms */ 1612 1613 /* Turn on clock */ 1614 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1615 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1616 1617 /* Set the serial port FIFO pointer to the 1618 * first sample in FIFO. (not documented) */ 1619 cs4280_clear_fifos(sc); 1620 1621 #if 0 1622 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1623 BA0WRITE4(sc, CS4280_SERBSP, 0); 1624 #endif 1625 1626 /* Configure the serial port */ 1627 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1628 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1629 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1630 1631 /* Wait for CODEC ready */ 1632 n = 0; 1633 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1634 delay(125); 1635 if (++n > 1000) { 1636 printf("%s: codec ready timeout\n", 1637 sc->sc_dev.dv_xname); 1638 return(1); 1639 } 1640 } 1641 1642 /* Assert valid frame signal */ 1643 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1644 1645 /* Wait for valid AC97 input slot */ 1646 n = 0; 1647 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1648 (ACISV_ISV3 | ACISV_ISV4)) { 1649 delay(1000); 1650 if (++n > 1000) { 1651 printf("AC97 inputs slot ready timeout\n"); 1652 return(1); 1653 } 1654 } 1655 1656 /* Set AC97 output slot valid signals */ 1657 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1658 1659 /* reset the processor */ 1660 cs4280_reset(sc); 1661 return (0); 1662 } 1663 1664 int 1665 cs4280_init2(struct cs4280_softc *sc, int init) 1666 { 1667 int n; 1668 u_int32_t mem; 1669 1670 /* Download the image to the processor */ 1671 if (cs4280_download_image(sc) != 0) { 1672 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1673 return(1); 1674 } 1675 1676 /* Save playback parameter and then write zero. 1677 * this ensures that DMA doesn't immediately occur upon 1678 * starting the processor core 1679 */ 1680 mem = BA1READ4(sc, CS4280_PCTL); 1681 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1682 cs4280_halt_output(sc); 1683 1684 /* Save capture parameter and then write zero. 1685 * this ensures that DMA doesn't immediately occur upon 1686 * starting the processor core 1687 */ 1688 mem = BA1READ4(sc, CS4280_CCTL); 1689 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1690 cs4280_halt_input(sc); 1691 1692 /* MSH: need to power up ADC and DAC? */ 1693 1694 /* Processor Startup Procedure */ 1695 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1696 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1697 1698 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1699 n = 0; 1700 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1701 delay(10); 1702 if (++n > 1000) { 1703 printf("SPCR 1->0 transition timeout\n"); 1704 return(1); 1705 } 1706 } 1707 1708 n = 0; 1709 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1710 delay(10); 1711 if (++n > 1000) { 1712 printf("SPCS 0->1 transition timeout\n"); 1713 return(1); 1714 } 1715 } 1716 /* Processor is now running !!! */ 1717 1718 /* Setup volume */ 1719 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1720 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1721 1722 /* Interrupt enable */ 1723 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1724 1725 /* playback interrupt enable */ 1726 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1727 mem |= PFIE_PI_ENABLE; 1728 BA1WRITE4(sc, CS4280_PFIE, mem); 1729 /* capture interrupt enable */ 1730 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1731 mem |= CIE_CI_ENABLE; 1732 BA1WRITE4(sc, CS4280_CIE, mem); 1733 1734 #if NMIDI > 0 1735 /* Reset midi port */ 1736 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1737 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1738 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1739 /* midi interrupt enable */ 1740 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1741 BA0WRITE4(sc, CS4280_MIDCR, mem); 1742 #endif 1743 return(0); 1744 } 1745 1746 int 1747 cs4280_activate(struct device *self, int act) 1748 { 1749 struct cs4280_softc *sc = (struct cs4280_softc *)self; 1750 int rv = 0; 1751 1752 switch (act) { 1753 case DVACT_QUIESCE: 1754 rv = config_activate_children(self, act); 1755 break; 1756 case DVACT_SUSPEND: 1757 /* should I powerdown here ? */ 1758 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1759 break; 1760 case DVACT_RESUME: 1761 cs4280_close(sc); 1762 cs4280_init(sc, 0); 1763 cs4280_init2(sc, 0); 1764 ac97_resume(&sc->host_if, sc->codec_if); 1765 rv = config_activate_children(self, act); 1766 break; 1767 case DVACT_DEACTIVATE: 1768 break; 1769 } 1770 return (rv); 1771 } 1772 1773 void 1774 cs4280_clear_fifos(struct cs4280_softc *sc) 1775 { 1776 int pd = 0, cnt, n; 1777 u_int32_t mem; 1778 1779 /* 1780 * If device power down, power up the device and keep power down 1781 * state. 1782 */ 1783 mem = BA0READ4(sc, CS4280_CLKCR1); 1784 if (!(mem & CLKCR1_SWCE)) { 1785 printf("cs4280_clear_fifo: power down found.\n"); 1786 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1787 pd = 1; 1788 } 1789 BA0WRITE4(sc, CS4280_SERBWP, 0); 1790 for (cnt = 0; cnt < 256; cnt++) { 1791 n = 0; 1792 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1793 delay(1000); 1794 if (++n > 1000) { 1795 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1796 break; 1797 } 1798 } 1799 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1800 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1801 } 1802 if (pd) 1803 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1804 } 1805 1806 #if NMIDI > 0 1807 int 1808 cs4280_midi_open(void *addr, int flags, void (*iintr)(void, int), 1809 void (*ointr)(void *), void *arg) 1810 { 1811 struct cs4280_softc *sc = addr; 1812 u_int32_t mem; 1813 1814 DPRINTF(("midi_open\n")); 1815 sc->sc_iintr = iintr; 1816 sc->sc_ointr = ointr; 1817 sc->sc_arg = arg; 1818 1819 /* midi interrupt enable */ 1820 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1821 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1822 BA0WRITE4(sc, CS4280_MIDCR, mem); 1823 #ifdef CS4280_DEBUG 1824 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1825 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1826 return(EINVAL); 1827 } 1828 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1829 #endif 1830 return (0); 1831 } 1832 1833 void 1834 cs4280_midi_close(void *addr) 1835 { 1836 struct cs4280_softc *sc = addr; 1837 u_int32_t mem; 1838 1839 DPRINTF(("midi_close\n")); 1840 mem = BA0READ4(sc, CS4280_MIDCR); 1841 mem &= ~MIDCR_MASK; 1842 BA0WRITE4(sc, CS4280_MIDCR, mem); 1843 1844 sc->sc_iintr = 0; 1845 sc->sc_ointr = 0; 1846 } 1847 1848 int 1849 cs4280_midi_output(void *addr, int d) 1850 { 1851 struct cs4280_softc *sc = addr; 1852 u_int32_t mem; 1853 int x; 1854 1855 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1856 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1857 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1858 mem |= d & MIDWP_MASK; 1859 DPRINTFN(5,("midi_output d=0x%08x",d)); 1860 BA0WRITE4(sc, CS4280_MIDWP, mem); 1861 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1862 DPRINTF(("Bad write data: %d %d", 1863 mem, BA0READ4(sc, CS4280_MIDWP))); 1864 return(EIO); 1865 } 1866 return (0); 1867 } 1868 delay(MIDI_BUSY_DELAY); 1869 } 1870 return (EIO); 1871 } 1872 1873 void 1874 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1875 { 1876 mi->name = "CS4280 MIDI UART"; 1877 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1878 } 1879 1880 #endif 1881