1 /* $OpenBSD: cs4280.c,v 1.60 2022/10/26 20:19:08 kn Exp $ */ 2 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */ 3 4 /* 5 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Tatoku Ogaito 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Cirrus Logic CS4280 (and maybe CS461x) driver. 36 * Data sheets can be found 37 * http://www.cirrus.com/ftp/pubs/4280.pdf 38 * http://www.cirrus.com/ftp/pubs/4297.pdf 39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf 40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc 41 */ 42 43 /* 44 * TODO 45 * Implement MIDI 46 * Joystick support 47 */ 48 49 #ifdef CS4280_DEBUG 50 #ifndef MIDI_READY 51 #define MIDI_READY 52 #endif /* ! MIDI_READY */ 53 #endif 54 55 #ifdef MIDI_READY 56 #include "midi.h" 57 #endif 58 59 #if defined(CS4280_DEBUG) 60 #define DPRINTF(x) if (cs4280debug) printf x 61 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x 62 int cs4280debug = 0; 63 #else 64 #define DPRINTF(x) 65 #define DPRINTFN(n,x) 66 #endif 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/fcntl.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 75 #include <dev/pci/pcidevs.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/cs4280reg.h> 78 79 #include <sys/audioio.h> 80 #include <dev/audio_if.h> 81 82 #include <dev/ic/ac97.h> 83 84 #include <machine/bus.h> 85 86 #define CSCC_PCI_BA0 0x10 87 #define CSCC_PCI_BA1 0x14 88 89 struct cs4280_dma { 90 bus_dmamap_t map; 91 caddr_t addr; /* real dma buffer */ 92 caddr_t dum; /* dummy buffer for audio driver */ 93 bus_dma_segment_t segs[1]; 94 int nsegs; 95 size_t size; 96 struct cs4280_dma *next; 97 }; 98 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr) 99 #define BUFADDR(p) ((void *)((p)->dum)) 100 #define KERNADDR(p) ((void *)((p)->addr)) 101 102 /* 103 * Software state 104 */ 105 struct cs4280_softc { 106 struct device sc_dev; 107 108 pci_intr_handle_t * sc_ih; 109 110 /* I/O (BA0) */ 111 bus_space_tag_t ba0t; 112 bus_space_handle_t ba0h; 113 114 /* BA1 */ 115 bus_space_tag_t ba1t; 116 bus_space_handle_t ba1h; 117 118 /* DMA */ 119 bus_dma_tag_t sc_dmatag; 120 struct cs4280_dma *sc_dmas; 121 122 void (*sc_pintr)(void *); /* dma completion intr handler */ 123 void *sc_parg; /* arg for sc_intr() */ 124 char *sc_ps, *sc_pe, *sc_pn; 125 int sc_pcount; 126 int sc_pi; 127 struct cs4280_dma *sc_pdma; 128 char *sc_pbuf; 129 #ifdef DIAGNOSTIC 130 char sc_prun; 131 #endif 132 133 void (*sc_rintr)(void *); /* dma completion intr handler */ 134 void *sc_rarg; /* arg for sc_intr() */ 135 char *sc_rs, *sc_re, *sc_rn; 136 int sc_rcount; 137 int sc_ri; 138 struct cs4280_dma *sc_rdma; 139 char *sc_rbuf; 140 int sc_rparam; /* record format */ 141 #ifdef DIAGNOSTIC 142 char sc_rrun; 143 #endif 144 145 #if NMIDI > 0 146 void (*sc_iintr)(void *, int); /* midi input ready handler */ 147 void (*sc_ointr)(void *); /* midi output ready handler */ 148 void *sc_arg; 149 #endif 150 151 u_int32_t pctl; 152 u_int32_t cctl; 153 154 struct ac97_codec_if *codec_if; 155 struct ac97_host_if host_if; 156 157 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ 158 }; 159 160 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) 161 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x)) 162 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r)) 163 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x)) 164 165 int cs4280_match(struct device *, void *, void *); 166 void cs4280_attach(struct device *, struct device *, void *); 167 int cs4280_activate(struct device *, int); 168 void cs4280_attachhook(struct device *); 169 int cs4280_intr(void *); 170 void cs4280_reset(void *); 171 int cs4280_download_image(struct cs4280_softc *); 172 173 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t); 174 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t, 175 struct cs4280_dma *); 176 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *); 177 178 #ifdef CS4280_DEBUG 179 int cs4280_check_images(struct cs4280_softc *); 180 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t, 181 u_int32_t); 182 #endif 183 184 struct cfdriver clcs_cd = { 185 NULL, "clcs", DV_DULL 186 }; 187 188 const struct cfattach clcs_ca = { 189 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach, NULL, 190 cs4280_activate 191 }; 192 193 int cs4280_init(struct cs4280_softc *, int); 194 int cs4280_init2(struct cs4280_softc *, int); 195 int cs4280_open(void *, int); 196 void cs4280_close(void *); 197 198 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *); 199 int cs4280_round_blocksize(void *, int); 200 201 int cs4280_halt_output(void *); 202 int cs4280_halt_input(void *); 203 204 int cs4280_mixer_set_port(void *, mixer_ctrl_t *); 205 int cs4280_mixer_get_port(void *, mixer_ctrl_t *); 206 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip); 207 void *cs4280_malloc(void *, int, size_t, int, int); 208 void cs4280_free(void *, void *, int); 209 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *), 210 void *, struct audio_params *); 211 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *), 212 void *, struct audio_params *); 213 214 215 void cs4280_set_dac_rate(struct cs4280_softc *, int ); 216 void cs4280_set_adc_rate(struct cs4280_softc *, int ); 217 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *, 218 char *); 219 int cs4280_src_wait(struct cs4280_softc *); 220 int cs4280_attach_codec(void *sc, struct ac97_codec_if *); 221 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d); 222 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d); 223 void cs4280_reset_codec(void *sc); 224 225 void cs4280_clear_fifos(struct cs4280_softc *); 226 227 #if NMIDI > 0 228 void cs4280_midi_close(void *); 229 void cs4280_midi_getinfo(void *, struct midi_info *); 230 int cs4280_midi_open(void *, int, void (*)(void *, int), 231 void (*)(void *), void *); 232 int cs4280_midi_output(void *, int); 233 #endif 234 235 const struct audio_hw_if cs4280_hw_if = { 236 .open = cs4280_open, 237 .close = cs4280_close, 238 .set_params = cs4280_set_params, 239 .round_blocksize = cs4280_round_blocksize, 240 .halt_output = cs4280_halt_output, 241 .halt_input = cs4280_halt_input, 242 .set_port = cs4280_mixer_set_port, 243 .get_port = cs4280_mixer_get_port, 244 .query_devinfo = cs4280_query_devinfo, 245 .allocm = cs4280_malloc, 246 .freem = cs4280_free, 247 .trigger_output = cs4280_trigger_output, 248 .trigger_input = cs4280_trigger_input, 249 }; 250 251 #if NMIDI > 0 252 const struct midi_hw_if cs4280_midi_hw_if = { 253 cs4280_midi_open, 254 cs4280_midi_close, 255 cs4280_midi_output, 256 0, /* flush */ 257 cs4280_midi_getinfo, 258 0, /* ioctl */ 259 }; 260 #endif 261 262 263 const struct pci_matchid cs4280_devices[] = { 264 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, 265 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, 266 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 }, 267 }; 268 269 int 270 cs4280_match(struct device *parent, void *ma, void *aux) 271 { 272 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, 273 nitems(cs4280_devices))); 274 } 275 276 int 277 cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data) 278 { 279 struct cs4280_softc *sc = sc_; 280 int n; 281 282 DPRINTFN(5,("read_codec: add=0x%02x ", add)); 283 /* 284 * Make sure that there is not data sitting around from a previous 285 * uncompleted access. 286 */ 287 BA0READ4(sc, CS4280_ACSDA); 288 289 /* Set up AC97 control registers. */ 290 BA0WRITE4(sc, CS4280_ACCAD, add); 291 BA0WRITE4(sc, CS4280_ACCDA, 0); 292 BA0WRITE4(sc, CS4280_ACCTL, 293 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); 294 295 if (cs4280_src_wait(sc) < 0) { 296 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n", 297 sc->sc_dev.dv_xname, add); 298 return (1); 299 } 300 301 /* wait for valid status bit is active */ 302 n = 0; 303 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { 304 delay(1); 305 while (++n > 1000) { 306 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", 307 sc->sc_dev.dv_xname, add); 308 return (1); 309 } 310 } 311 *data = BA0READ4(sc, CS4280_ACSDA); 312 DPRINTFN(5,("data=0x%04x\n", *data)); 313 return (0); 314 } 315 316 int 317 cs4280_write_codec(void *sc_, u_int8_t add, u_int16_t data) 318 { 319 struct cs4280_softc *sc = sc_; 320 321 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); 322 BA0WRITE4(sc, CS4280_ACCAD, add); 323 BA0WRITE4(sc, CS4280_ACCDA, data); 324 BA0WRITE4(sc, CS4280_ACCTL, 325 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); 326 327 if (cs4280_src_wait(sc) < 0) { 328 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data=" 329 "0x%04x\n", sc->sc_dev.dv_xname, add, data); 330 return (1); 331 } 332 return (0); 333 } 334 335 int 336 cs4280_src_wait(struct cs4280_softc *sc) 337 { 338 int n; 339 340 n = 0; 341 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) { 342 delay(1000); 343 if (++n > 1000) 344 return (-1); 345 } 346 return (0); 347 } 348 349 350 void 351 cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) 352 { 353 /* calculate capture rate: 354 * 355 * capture_coefficient_increment = -round(rate*128*65536/48000; 356 * capture_phase_increment = floor(48000*65536*1024/rate); 357 * cx = round(48000*65536*1024 - capture_phase_increment*rate); 358 * cy = floor(cx/200); 359 * capture_sample_rate_correction = cx - 200*cy; 360 * capture_delay = ceil(24*48000/rate); 361 * capture_num_triplets = floor(65536*rate/24000); 362 * capture_group_length = 24000/GCD(rate, 24000); 363 * where GCD means "Greatest Common Divisor". 364 * 365 * capture_coefficient_increment, capture_phase_increment and 366 * capture_num_triplets are 32-bit signed quantities. 367 * capture_sample_rate_correction and capture_group_length are 368 * 16-bit signed quantities. 369 * capture_delay is a 14-bit unsigned quantity. 370 */ 371 u_int32_t cci,cpi,cnt,cx,cy, tmp1; 372 u_int16_t csrc, cgl, cdlay; 373 374 /* XXX 375 * Even though, embedded_audio_spec says capture rate range 11025 to 376 * 48000, dhwiface.cpp says, 377 * 378 * "We can only decimate by up to a factor of 1/9th the hardware rate. 379 * Return an error if an attempt is made to stray outside that limit." 380 * 381 * so assume range as 48000/9 to 48000 382 */ 383 384 if (rate < 8000) 385 rate = 8000; 386 if (rate > 48000) 387 rate = 48000; 388 389 cx = rate << 16; 390 cci = cx / 48000; 391 cx -= cci * 48000; 392 cx <<= 7; 393 cci <<= 7; 394 cci += cx / 48000; 395 cci = - cci; 396 397 cx = 48000 << 16; 398 cpi = cx / rate; 399 cx -= cpi * rate; 400 cx <<= 10; 401 cpi <<= 10; 402 cy = cx / rate; 403 cpi += cy; 404 cx -= cy * rate; 405 406 cy = cx / 200; 407 csrc = cx - 200*cy; 408 409 cdlay = ((48000 * 24) + rate - 1) / rate; 410 #if 0 411 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */ 412 #endif 413 414 cnt = rate << 16; 415 cnt /= 24000; 416 417 cgl = 1; 418 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) { 419 if (((rate / tmp1) * tmp1) != rate) 420 cgl *= 2; 421 } 422 if (((rate / 3) * 3) != rate) 423 cgl *= 3; 424 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { 425 if (((rate / tmp1) * tmp1) != rate) 426 cgl *= 5; 427 } 428 #if 0 429 /* XXX what manual says */ 430 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK; 431 tmp1 |= csrc<<16; 432 BA1WRITE4(sc, CS4280_CSRC, tmp1); 433 #else 434 /* suggested by cs461x.c (ALSA driver) */ 435 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy)); 436 #endif 437 438 #if 0 439 /* I am confused. The sample rate calculation section says 440 * cci *is* 32-bit signed quantity but in the parameter description 441 * section, CCI only assigned 16bit. 442 * I believe size of the variable. 443 */ 444 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK; 445 tmp1 |= cci<<16; 446 BA1WRITE4(sc, CS4280_CCI, tmp1); 447 #else 448 BA1WRITE4(sc, CS4280_CCI, cci); 449 #endif 450 451 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; 452 tmp1 |= cdlay <<18; 453 BA1WRITE4(sc, CS4280_CD, tmp1); 454 455 BA1WRITE4(sc, CS4280_CPI, cpi); 456 457 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; 458 tmp1 |= cgl; 459 BA1WRITE4(sc, CS4280_CGL, tmp1); 460 461 BA1WRITE4(sc, CS4280_CNT, cnt); 462 463 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; 464 tmp1 |= cgl; 465 BA1WRITE4(sc, CS4280_CGC, tmp1); 466 } 467 468 void 469 cs4280_set_dac_rate(struct cs4280_softc *sc, int rate) 470 { 471 /* 472 * playback rate may range from 8000Hz to 48000Hz 473 * 474 * play_phase_increment = floor(rate*65536*1024/48000) 475 * px = round(rate*65536*1024 - play_phase_incremnt*48000) 476 * py=floor(px/200) 477 * play_sample_rate_correction = px - 200*py 478 * 479 * play_phase_increment is a 32bit signed quantity. 480 * play_sample_rate_correction is a 16bit signed quantity. 481 */ 482 int32_t ppi; 483 int16_t psrc; 484 u_int32_t px, py; 485 486 if (rate < 8000) 487 rate = 8000; 488 if (rate > 48000) 489 rate = 48000; 490 px = rate << 16; 491 ppi = px/48000; 492 px -= ppi*48000; 493 ppi <<= 10; 494 px <<= 10; 495 py = px / 48000; 496 ppi += py; 497 px -= py*48000; 498 py = px/200; 499 px -= py*200; 500 psrc = px; 501 #if 0 502 /* what manual says */ 503 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; 504 BA1WRITE4(sc, CS4280_PSRC, 505 ( ((psrc<<16) & PSRC_MASK) | px )); 506 #else 507 /* suggested by cs461x.c (ALSA driver) */ 508 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); 509 #endif 510 BA1WRITE4(sc, CS4280_PPI, ppi); 511 } 512 513 void 514 cs4280_attachhook(struct device *self) 515 { 516 struct cs4280_softc *sc = (struct cs4280_softc *)self; 517 mixer_ctrl_t ctl; 518 519 /* Initialization */ 520 if (cs4280_init2(sc, 1) != 0) 521 return; 522 523 printf("%s: firmware loaded\n", sc->sc_dev.dv_xname); 524 525 /* Turn mute off of DAC, CD and master volumes by default */ 526 ctl.type = AUDIO_MIXER_ENUM; 527 ctl.un.ord = 0; /* off */ 528 529 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs, 530 AudioNmaster, AudioNmute); 531 cs4280_mixer_set_port(sc, &ctl); 532 533 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 534 AudioNdac, AudioNmute); 535 cs4280_mixer_set_port(sc, &ctl); 536 537 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs, 538 AudioNcd, AudioNmute); 539 cs4280_mixer_set_port(sc, &ctl); 540 541 audio_attach_mi(&cs4280_hw_if, sc, NULL, &sc->sc_dev); 542 543 #if NMIDI > 0 544 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev); 545 #endif 546 } 547 548 void 549 cs4280_attach(struct device *parent, struct device *self, void *aux) 550 { 551 struct cs4280_softc *sc = (struct cs4280_softc *) self; 552 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 553 pci_chipset_tag_t pc = pa->pa_pc; 554 char const *intrstr; 555 pci_intr_handle_t ih; 556 u_int32_t mem; 557 558 /* Map I/O register */ 559 if (pci_mapreg_map(pa, CSCC_PCI_BA0, 560 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 561 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { 562 printf(": can't map BA0 space\n"); 563 return; 564 } 565 if (pci_mapreg_map(pa, CSCC_PCI_BA1, 566 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 567 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) { 568 printf(": can't map BA1 space\n"); 569 return; 570 } 571 572 sc->sc_dmatag = pa->pa_dmat; 573 574 /* Get out of power save mode if needed. */ 575 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 576 577 /* LATENCY_TIMER setting */ 578 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 579 if ( PCI_LATTIMER(mem) < 32 ) { 580 mem &= 0xffff00ff; 581 mem |= 0x00002000; 582 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); 583 } 584 585 /* Map and establish the interrupt. */ 586 if (pci_intr_map(pa, &ih)) { 587 printf(": couldn't map interrupt\n"); 588 return; 589 } 590 intrstr = pci_intr_string(pc, ih); 591 592 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO | IPL_MPSAFE, 593 cs4280_intr, sc, sc->sc_dev.dv_xname); 594 if (sc->sc_ih == NULL) { 595 printf(": couldn't establish interrupt"); 596 if (intrstr != NULL) 597 printf(" at %s", intrstr); 598 printf("\n"); 599 return; 600 } 601 printf(": %s\n", intrstr); 602 603 /* Initialization */ 604 if (cs4280_init(sc, 1) != 0) 605 return; 606 607 config_mountroot(self, cs4280_attachhook); 608 609 /* AC 97 attachment */ 610 sc->host_if.arg = sc; 611 sc->host_if.attach = cs4280_attach_codec; 612 sc->host_if.read = cs4280_read_codec; 613 sc->host_if.write = cs4280_write_codec; 614 sc->host_if.reset = cs4280_reset_codec; 615 616 if (ac97_attach(&sc->host_if) != 0) { 617 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname); 618 return; 619 } 620 } 621 622 int 623 cs4280_intr(void *p) 624 { 625 /* 626 * XXX 627 * 628 * Since CS4280 has only 4kB dma buffer and 629 * interrupt occurs every 2kB block, I create dummy buffer 630 * which returns to audio driver and actual dma buffer 631 * using in DMA transfer. 632 * 633 * 634 * ring buffer in audio.c is pointed by BUFADDR 635 * <------ ring buffer size == 64kB ------> 636 * <-----> blksize == 2048*(sc->sc_[pr]count) kB 637 * |= = = =|= = = =|= = = =|= = = =|= = = =| 638 * | | | | | | <- call audio_intp every 639 * sc->sc_[pr]_count time. 640 * 641 * actual dma buffer is pointed by KERNADDR 642 * <-> dma buffer size = 4kB 643 * |= =| 644 * 645 * 646 */ 647 struct cs4280_softc *sc = p; 648 u_int32_t intr, mem; 649 char * empty_dma; 650 int handled = 0; 651 652 mtx_enter(&audio_lock); 653 /* grab interrupt register then clear it */ 654 intr = BA0READ4(sc, CS4280_HISR); 655 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV); 656 657 /* Playback Interrupt */ 658 if (intr & HISR_PINT) { 659 handled = 1; 660 mem = BA1READ4(sc, CS4280_PFIE); 661 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE); 662 if (sc->sc_pintr) { 663 if ((sc->sc_pi%sc->sc_pcount) == 0) 664 sc->sc_pintr(sc->sc_parg); 665 } else { 666 printf("unexpected play intr\n"); 667 } 668 /* copy buffer */ 669 ++sc->sc_pi; 670 empty_dma = sc->sc_pdma->addr; 671 if (sc->sc_pi&1) 672 empty_dma += CS4280_ICHUNK; 673 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK); 674 sc->sc_pn += CS4280_ICHUNK; 675 if (sc->sc_pn >= sc->sc_pe) 676 sc->sc_pn = sc->sc_ps; 677 BA1WRITE4(sc, CS4280_PFIE, mem); 678 } 679 /* Capture Interrupt */ 680 if (intr & HISR_CINT) { 681 int i; 682 int16_t rdata; 683 684 handled = 1; 685 mem = BA1READ4(sc, CS4280_CIE); 686 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE); 687 ++sc->sc_ri; 688 empty_dma = sc->sc_rdma->addr; 689 if ((sc->sc_ri&1) == 0) 690 empty_dma += CS4280_ICHUNK; 691 692 /* 693 * XXX 694 * I think this audio data conversion should be 695 * happened in upper layer, but I put this here 696 * since there is no conversion function available. 697 */ 698 switch(sc->sc_rparam) { 699 case CF_16BIT_STEREO: 700 /* just copy it */ 701 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK); 702 sc->sc_rn += CS4280_ICHUNK; 703 break; 704 case CF_16BIT_MONO: 705 for (i = 0; i < 512; i++) { 706 rdata = *((int16_t *)empty_dma)>>1; 707 empty_dma += 2; 708 rdata += *((int16_t *)empty_dma)>>1; 709 empty_dma += 2; 710 *((int16_t *)sc->sc_rn) = rdata; 711 sc->sc_rn += 2; 712 } 713 break; 714 case CF_8BIT_STEREO: 715 for (i = 0; i < 512; i++) { 716 rdata = *((int16_t*)empty_dma); 717 empty_dma += 2; 718 *sc->sc_rn++ = rdata >> 8; 719 rdata = *((int16_t*)empty_dma); 720 empty_dma += 2; 721 *sc->sc_rn++ = rdata >> 8; 722 } 723 break; 724 case CF_8BIT_MONO: 725 for (i = 0; i < 512; i++) { 726 rdata = *((int16_t*)empty_dma) >>1; 727 empty_dma += 2; 728 rdata += *((int16_t*)empty_dma) >>1; 729 empty_dma += 2; 730 *sc->sc_rn++ = rdata >>8; 731 } 732 break; 733 default: 734 /* Should not reach here */ 735 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam); 736 } 737 if (sc->sc_rn >= sc->sc_re) 738 sc->sc_rn = sc->sc_rs; 739 BA1WRITE4(sc, CS4280_CIE, mem); 740 if (sc->sc_rintr) { 741 if ((sc->sc_ri%(sc->sc_rcount)) == 0) 742 sc->sc_rintr(sc->sc_rarg); 743 } else { 744 printf("unexpected record intr\n"); 745 } 746 } 747 748 #if NMIDI > 0 749 /* Midi port Interrupt */ 750 if (intr & HISR_MIDI) { 751 int data; 752 753 handled = 1; 754 DPRINTF(("i: %d: ", 755 BA0READ4(sc, CS4280_MIDSR))); 756 /* Read the received data */ 757 while ((sc->sc_iintr != NULL) && 758 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) { 759 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK; 760 DPRINTF(("r:%x\n",data)); 761 sc->sc_iintr(sc->sc_arg, data); 762 } 763 764 /* Write the data */ 765 #if 1 766 /* XXX: 767 * It seems "Transmit Buffer Full" never activate until EOI 768 * is delivered. Shall I throw EOI top of this routine ? 769 */ 770 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 771 DPRINTF(("w: ")); 772 if (sc->sc_ointr != NULL) 773 sc->sc_ointr(sc->sc_arg); 774 } 775 #else 776 while ((sc->sc_ointr != NULL) && 777 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { 778 DPRINTF(("w: ")); 779 sc->sc_ointr(sc->sc_arg); 780 } 781 #endif 782 DPRINTF(("\n")); 783 } 784 #endif 785 mtx_leave(&audio_lock); 786 return handled; 787 } 788 789 790 /* Download Processor Code and Data image */ 791 792 int 793 cs4280_download(struct cs4280_softc *sc, const u_int32_t *src, u_int32_t offset, 794 u_int32_t len) 795 { 796 u_int32_t ctr; 797 798 #ifdef CS4280_DEBUG 799 u_int32_t con, data; 800 u_int8_t c0,c1,c2,c3; 801 #endif 802 if ((offset&3) || (len&3)) 803 return (-1); 804 805 len /= sizeof(u_int32_t); 806 for (ctr = 0; ctr < len; ctr++) { 807 /* XXX: 808 * I cannot confirm this is the right thing or not 809 * on BIG-ENDIAN machines. 810 */ 811 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr))); 812 #ifdef CS4280_DEBUG 813 data = htole32(*(src+ctr)); 814 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0); 815 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1); 816 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2); 817 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3); 818 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 ); 819 if (data != con ) { 820 printf("0x%06x: write=0x%08x read=0x%08x\n", 821 offset+ctr*4, data, con); 822 return (-1); 823 } 824 #endif 825 } 826 return (0); 827 } 828 829 struct BA1struct *BA1Struct; 830 831 int 832 cs4280_download_image(struct cs4280_softc *sc) 833 { 834 int idx, err = 0; 835 u_int32_t offset = 0; 836 static u_char *cs4280_firmware; 837 static size_t cs4280_firmwarelen; 838 839 if (cs4280_firmware == NULL) { 840 err = loadfirmware("cs4280", &cs4280_firmware, 841 &cs4280_firmwarelen); 842 if (err) 843 return (err); 844 } 845 846 BA1Struct = (struct BA1struct *)cs4280_firmware; 847 848 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) { 849 err = cs4280_download(sc, &BA1Struct->map[offset], 850 BA1Struct->memory[idx].offset, BA1Struct->memory[idx].size); 851 if (err != 0) { 852 printf("%s: load_image failed at %d\n", 853 sc->sc_dev.dv_xname, idx); 854 return (-1); 855 } 856 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 857 } 858 return (err); 859 } 860 861 #ifdef CS4280_DEBUG 862 int 863 cs4280_checkimage(struct cs4280_softc *sc, u_int32_t *src, u_int32_t offset, 864 u_int32_t len) 865 { 866 u_int32_t ctr, data; 867 int err = 0; 868 869 if ((offset&3) || (len&3)) 870 return -1; 871 872 len /= sizeof(u_int32_t); 873 for (ctr = 0; ctr < len; ctr++) { 874 /* I cannot confirm this is the right thing 875 * on BIG-ENDIAN machines 876 */ 877 data = BA1READ4(sc, offset+ctr*4); 878 if (data != htole32(*(src+ctr))) { 879 printf("0x%06x: 0x%08x(0x%08x)\n", 880 offset+ctr*4, data, *(src+ctr)); 881 *(src+ctr) = data; 882 ++err; 883 } 884 } 885 return (err); 886 } 887 888 int 889 cs4280_check_images(struct cs4280_softc *sc) 890 { 891 int idx, err; 892 u_int32_t offset = 0; 893 894 err = 0; 895 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */ 896 for (idx = 0; idx < 1; ++idx) { 897 err = cs4280_checkimage(sc, &BA1Struct->map[offset], 898 BA1Struct->memory[idx].offset, 899 BA1Struct->memory[idx].size); 900 if (err != 0) { 901 printf("%s: check_image failed at %d\n", 902 sc->sc_dev.dv_xname, idx); 903 } 904 offset += BA1Struct->memory[idx].size / sizeof(u_int32_t); 905 } 906 return (err); 907 } 908 909 #endif 910 911 int 912 cs4280_attach_codec(void *sc_, struct ac97_codec_if *codec_if) 913 { 914 struct cs4280_softc *sc = sc_; 915 916 sc->codec_if = codec_if; 917 return (0); 918 } 919 920 void 921 cs4280_reset_codec(void *sc_) 922 { 923 struct cs4280_softc *sc = sc_; 924 int n; 925 926 /* Reset codec */ 927 BA0WRITE4(sc, CS4280_ACCTL, 0); 928 delay(100); /* delay 100us */ 929 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 930 931 /* 932 * It looks like we do the following procedure, too 933 */ 934 935 /* Enable AC-link sync generation */ 936 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 937 delay(50*1000); /* XXX delay 50ms */ 938 939 /* Assert valid frame signal */ 940 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 941 942 /* Wait for valid AC97 input slot */ 943 n = 0; 944 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) { 945 delay(1000); 946 if (++n > 1000) { 947 printf("reset_codec: AC97 inputs slot ready timeout\n"); 948 return; 949 } 950 } 951 } 952 953 954 /* Processor Soft Reset */ 955 void 956 cs4280_reset(void *sc_) 957 { 958 struct cs4280_softc *sc = sc_; 959 960 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */ 961 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP); 962 delay(100); 963 /* Clear RSTSP bit in SPCR */ 964 BA1WRITE4(sc, CS4280_SPCR, 0); 965 /* enable DMA request */ 966 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN); 967 } 968 969 int 970 cs4280_open(void *addr, int flags) 971 { 972 return (0); 973 } 974 975 void 976 cs4280_close(void *addr) 977 { 978 struct cs4280_softc *sc = addr; 979 980 /* XXX: already called in audio_close() */ 981 cs4280_halt_output(sc); 982 cs4280_halt_input(sc); 983 984 sc->sc_pintr = 0; 985 sc->sc_rintr = 0; 986 } 987 988 int 989 cs4280_set_params(void *addr, int setmode, int usemode, 990 struct audio_params *play, struct audio_params *rec) 991 { 992 struct cs4280_softc *sc = addr; 993 struct audio_params *p; 994 int mode; 995 996 for (mode = AUMODE_RECORD; mode != -1; 997 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { 998 if ((setmode & mode) == 0) 999 continue; 1000 1001 p = mode == AUMODE_PLAY ? play : rec; 1002 if (p == play) { 1003 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", 1004 p->sample_rate, p->precision, p->channels)); 1005 } else { 1006 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n", 1007 p->sample_rate, p->precision, p->channels)); 1008 } 1009 /* play back data format may be 8- or 16-bit and 1010 * either stereo or mono. 1011 * playback rate may range from 8000Hz to 48000Hz 1012 * 1013 * capture data format must be 16bit stereo 1014 * and sample rate range from 11025Hz to 48000Hz. 1015 * 1016 * XXX: it looks like to work with 8000Hz, 1017 * although data sheets say lower limit is 1018 * 11025 Hz. 1019 */ 1020 if (p->sample_rate < 8000) 1021 p->sample_rate = 8000; 1022 if (p->sample_rate > 48000) 1023 p->sample_rate = 48000; 1024 if (p->precision > 16) 1025 p->precision = 16; 1026 if (p->channels > 2) 1027 p->channels = 2; 1028 1029 /* capturing data is slinear */ 1030 switch (p->encoding) { 1031 case AUDIO_ENCODING_SLINEAR_LE: 1032 break; 1033 default: 1034 return (EINVAL); 1035 } 1036 p->bps = AUDIO_BPS(p->precision); 1037 p->msb = 1; 1038 } 1039 1040 /* set sample rate */ 1041 cs4280_set_dac_rate(sc, play->sample_rate); 1042 cs4280_set_adc_rate(sc, rec->sample_rate); 1043 return (0); 1044 } 1045 1046 int 1047 cs4280_round_blocksize(void *hdl, int blk) 1048 { 1049 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK); 1050 } 1051 1052 int 1053 cs4280_mixer_get_port(void *addr, mixer_ctrl_t *cp) 1054 { 1055 struct cs4280_softc *sc = addr; 1056 1057 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); 1058 } 1059 1060 int 1061 cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip) 1062 { 1063 struct cs4280_softc *sc = addr; 1064 1065 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip)); 1066 } 1067 1068 int 1069 cs4280_get_portnum_by_name(struct cs4280_softc *sc, char *class, char *device, 1070 char *qualifier) 1071 { 1072 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class, 1073 device, qualifier)); 1074 } 1075 1076 int 1077 cs4280_halt_output(void *addr) 1078 { 1079 struct cs4280_softc *sc = addr; 1080 u_int32_t mem; 1081 1082 mtx_enter(&audio_lock); 1083 mem = BA1READ4(sc, CS4280_PCTL); 1084 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1085 #ifdef DIAGNOSTIC 1086 sc->sc_prun = 0; 1087 #endif 1088 mtx_leave(&audio_lock); 1089 return (0); 1090 } 1091 1092 int 1093 cs4280_halt_input(void *addr) 1094 { 1095 struct cs4280_softc *sc = addr; 1096 u_int32_t mem; 1097 1098 mtx_enter(&audio_lock); 1099 mem = BA1READ4(sc, CS4280_CCTL); 1100 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK); 1101 #ifdef DIAGNOSTIC 1102 sc->sc_rrun = 0; 1103 #endif 1104 mtx_leave(&audio_lock); 1105 return (0); 1106 } 1107 1108 int 1109 cs4280_mixer_set_port(void *addr, mixer_ctrl_t *cp) 1110 { 1111 struct cs4280_softc *sc = addr; 1112 int val; 1113 1114 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1115 DPRINTFN(3,("mixer_set_port: val=%d\n", val)); 1116 return (val); 1117 } 1118 1119 1120 int 1121 cs4280_freemem(struct cs4280_softc *sc, struct cs4280_dma *p) 1122 { 1123 bus_dmamap_unload(sc->sc_dmatag, p->map); 1124 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1125 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1126 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1127 return (0); 1128 } 1129 1130 int 1131 cs4280_allocmem(struct cs4280_softc *sc, size_t size, size_t align, 1132 struct cs4280_dma *p) 1133 { 1134 int error; 1135 1136 /* XXX */ 1137 p->size = size; 1138 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 1139 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 1140 &p->nsegs, BUS_DMA_NOWAIT); 1141 if (error) { 1142 printf("%s: unable to allocate dma, error=%d\n", 1143 sc->sc_dev.dv_xname, error); 1144 return (error); 1145 } 1146 1147 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 1148 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1149 if (error) { 1150 printf("%s: unable to map dma, error=%d\n", 1151 sc->sc_dev.dv_xname, error); 1152 goto free; 1153 } 1154 1155 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 1156 0, BUS_DMA_NOWAIT, &p->map); 1157 if (error) { 1158 printf("%s: unable to create dma map, error=%d\n", 1159 sc->sc_dev.dv_xname, error); 1160 goto unmap; 1161 } 1162 1163 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, 1164 BUS_DMA_NOWAIT); 1165 if (error) { 1166 printf("%s: unable to load dma map, error=%d\n", 1167 sc->sc_dev.dv_xname, error); 1168 goto destroy; 1169 } 1170 return (0); 1171 1172 destroy: 1173 bus_dmamap_destroy(sc->sc_dmatag, p->map); 1174 unmap: 1175 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size); 1176 free: 1177 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 1178 return (error); 1179 } 1180 1181 1182 void * 1183 cs4280_malloc(void *addr, int direction, size_t size, int pool, int flags) 1184 { 1185 struct cs4280_softc *sc = addr; 1186 struct cs4280_dma *p; 1187 caddr_t q; 1188 int error; 1189 1190 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); 1191 q = malloc(size, pool, flags); 1192 if (!q) 1193 return (0); 1194 p = malloc(sizeof(*p), pool, flags); 1195 if (!p) { 1196 free(q,pool, 0); 1197 return (0); 1198 } 1199 /* 1200 * cs4280 has fixed 4kB buffer 1201 */ 1202 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); 1203 1204 if (error) { 1205 free(q, pool, 0); 1206 free(p, pool, 0); 1207 return (0); 1208 } 1209 1210 p->next = sc->sc_dmas; 1211 sc->sc_dmas = p; 1212 p->dum = q; /* return to audio driver */ 1213 1214 return (p->dum); 1215 } 1216 1217 void 1218 cs4280_free(void *addr, void *ptr, int pool) 1219 { 1220 struct cs4280_softc *sc = addr; 1221 struct cs4280_dma **pp, *p; 1222 1223 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { 1224 if (BUFADDR(p) == ptr) { 1225 cs4280_freemem(sc, p); 1226 *pp = p->next; 1227 free(p->dum, pool, 0); 1228 free(p, pool, 0); 1229 return; 1230 } 1231 } 1232 } 1233 1234 int 1235 cs4280_trigger_output(void *addr, void *start, void *end, int blksize, 1236 void (*intr)(void *), void *arg, struct audio_params *param) 1237 { 1238 struct cs4280_softc *sc = addr; 1239 u_int32_t pfie, pctl, mem, pdtc; 1240 struct cs4280_dma *p; 1241 1242 #ifdef DIAGNOSTIC 1243 if (sc->sc_prun) 1244 printf("cs4280_trigger_output: already running\n"); 1245 sc->sc_prun = 1; 1246 #endif 1247 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p " 1248 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1249 sc->sc_pintr = intr; 1250 sc->sc_parg = arg; 1251 1252 /* stop playback DMA */ 1253 mem = BA1READ4(sc, CS4280_PCTL); 1254 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); 1255 1256 /* setup PDTC */ 1257 pdtc = BA1READ4(sc, CS4280_PDTC); 1258 pdtc &= ~PDTC_MASK; 1259 pdtc |= CS4280_MK_PDTC(param->precision * param->channels); 1260 BA1WRITE4(sc, CS4280_PDTC, pdtc); 1261 1262 DPRINTF(("param: precision=%d channels=%d encoding=%d\n", 1263 param->precision, param->channels, 1264 param->encoding)); 1265 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next) 1266 ; 1267 if (p == NULL) { 1268 printf("cs4280_trigger_output: bad addr %p\n", start); 1269 return (EINVAL); 1270 } 1271 if (DMAADDR(p) % CS4280_DALIGN != 0 ) { 1272 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start" 1273 "4kB align\n", DMAADDR(p)); 1274 return (EINVAL); 1275 } 1276 1277 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1278 sc->sc_ps = (char *)start; 1279 sc->sc_pe = (char *)end; 1280 sc->sc_pdma = p; 1281 sc->sc_pbuf = KERNADDR(p); 1282 sc->sc_pi = 0; 1283 sc->sc_pn = sc->sc_ps; 1284 if (blksize >= CS4280_DCHUNK) { 1285 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK; 1286 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK); 1287 ++sc->sc_pi; 1288 } else { 1289 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK; 1290 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK); 1291 } 1292 1293 /* initiate playback dma */ 1294 mtx_enter(&audio_lock); 1295 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p)); 1296 1297 /* set PFIE */ 1298 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK; 1299 1300 if (param->precision == 8) 1301 pfie |= PFIE_8BIT; 1302 if (param->channels == 1) 1303 pfie |= PFIE_MONO; 1304 1305 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1306 param->encoding == AUDIO_ENCODING_SLINEAR_BE) 1307 pfie |= PFIE_SWAPPED; 1308 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE || 1309 param->encoding == AUDIO_ENCODING_ULINEAR_LE) 1310 pfie |= PFIE_UNSIGNED; 1311 1312 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE); 1313 1314 cs4280_set_dac_rate(sc, param->sample_rate); 1315 1316 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK; 1317 pctl |= sc->pctl; 1318 BA1WRITE4(sc, CS4280_PCTL, pctl); 1319 mtx_leave(&audio_lock); 1320 return (0); 1321 } 1322 1323 int 1324 cs4280_trigger_input(void *addr, void *start, void *end, int blksize, 1325 void (*intr)(void *), void *arg, struct audio_params *param) 1326 { 1327 struct cs4280_softc *sc = addr; 1328 u_int32_t cctl, cie; 1329 struct cs4280_dma *p; 1330 1331 #ifdef DIAGNOSTIC 1332 if (sc->sc_rrun) 1333 printf("cs4280_trigger_input: already running\n"); 1334 sc->sc_rrun = 1; 1335 #endif 1336 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p " 1337 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); 1338 sc->sc_rintr = intr; 1339 sc->sc_rarg = arg; 1340 1341 sc->sc_ri = 0; 1342 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/ 1343 sc->sc_rs = (char *)start; 1344 sc->sc_re = (char *)end; 1345 sc->sc_rn = sc->sc_rs; 1346 1347 /* setup format information for internal converter */ 1348 sc->sc_rparam = 0; 1349 if (param->precision == 8) { 1350 sc->sc_rparam += CF_8BIT; 1351 sc->sc_rcount <<= 1; 1352 } 1353 if (param->channels == 1) { 1354 sc->sc_rparam += CF_MONO; 1355 sc->sc_rcount <<= 1; 1356 } 1357 1358 /* stop capture DMA */ 1359 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1360 BA1WRITE4(sc, CS4280_CCTL, cctl); 1361 1362 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) 1363 ; 1364 if (!p) { 1365 printf("cs4280_trigger_input: bad addr %p\n", start); 1366 return (EINVAL); 1367 } 1368 if (DMAADDR(p) % CS4280_DALIGN != 0) { 1369 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start" 1370 "4kB align\n", DMAADDR(p)); 1371 return (EINVAL); 1372 } 1373 sc->sc_rdma = p; 1374 sc->sc_rbuf = KERNADDR(p); 1375 1376 /* initiate capture dma */ 1377 mtx_enter(&audio_lock); 1378 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); 1379 1380 /* set CIE */ 1381 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1382 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE); 1383 1384 cs4280_set_adc_rate(sc, param->sample_rate); 1385 1386 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; 1387 cctl |= sc->cctl; 1388 BA1WRITE4(sc, CS4280_CCTL, cctl); 1389 mtx_leave(&audio_lock); 1390 return (0); 1391 } 1392 1393 1394 int 1395 cs4280_init(struct cs4280_softc *sc, int init) 1396 { 1397 int n; 1398 u_int32_t mem; 1399 1400 /* Start PLL out in known state */ 1401 BA0WRITE4(sc, CS4280_CLKCR1, 0); 1402 /* Start serial ports out in known state */ 1403 BA0WRITE4(sc, CS4280_SERMC1, 0); 1404 1405 /* Specify type of CODEC */ 1406 /* XXX should no be here */ 1407 #define SERACC_CODEC_TYPE_1_03 1408 #ifdef SERACC_CODEC_TYPE_1_03 1409 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */ 1410 #else 1411 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */ 1412 #endif 1413 1414 /* Reset codec */ 1415 BA0WRITE4(sc, CS4280_ACCTL, 0); 1416 delay(100); /* delay 100us */ 1417 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); 1418 1419 /* Enable AC-link sync generation */ 1420 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 1421 delay(50*1000); /* delay 50ms */ 1422 1423 /* Set the serial port timing configuration */ 1424 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); 1425 1426 /* Setup clock control */ 1427 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); 1428 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); 1429 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); 1430 1431 /* Power up the PLL */ 1432 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); 1433 delay(50*1000); /* delay 50ms */ 1434 1435 /* Turn on clock */ 1436 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; 1437 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1438 1439 /* Set the serial port FIFO pointer to the 1440 * first sample in FIFO. (not documented) */ 1441 cs4280_clear_fifos(sc); 1442 1443 #if 0 1444 /* Set the serial port FIFO pointer to the first sample in the FIFO */ 1445 BA0WRITE4(sc, CS4280_SERBSP, 0); 1446 #endif 1447 1448 /* Configure the serial port */ 1449 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); 1450 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); 1451 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); 1452 1453 /* Wait for CODEC ready */ 1454 n = 0; 1455 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { 1456 delay(125); 1457 if (++n > 1000) { 1458 printf("%s: codec ready timeout\n", 1459 sc->sc_dev.dv_xname); 1460 return(1); 1461 } 1462 } 1463 1464 /* Assert valid frame signal */ 1465 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 1466 1467 /* Wait for valid AC97 input slot */ 1468 n = 0; 1469 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) != 1470 (ACISV_ISV3 | ACISV_ISV4)) { 1471 delay(1000); 1472 if (++n > 1000) { 1473 printf("AC97 inputs slot ready timeout\n"); 1474 return(1); 1475 } 1476 } 1477 1478 /* Set AC97 output slot valid signals */ 1479 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 1480 1481 /* reset the processor */ 1482 cs4280_reset(sc); 1483 return (0); 1484 } 1485 1486 int 1487 cs4280_init2(struct cs4280_softc *sc, int init) 1488 { 1489 int n; 1490 u_int32_t mem; 1491 1492 /* Download the image to the processor */ 1493 if (cs4280_download_image(sc) != 0) { 1494 printf("%s: image download error\n", sc->sc_dev.dv_xname); 1495 return(1); 1496 } 1497 1498 /* Save playback parameter and then write zero. 1499 * this ensures that DMA doesn't immediately occur upon 1500 * starting the processor core 1501 */ 1502 mem = BA1READ4(sc, CS4280_PCTL); 1503 sc->pctl = mem & PCTL_MASK; /* save startup value */ 1504 cs4280_halt_output(sc); 1505 1506 /* Save capture parameter and then write zero. 1507 * this ensures that DMA doesn't immediately occur upon 1508 * starting the processor core 1509 */ 1510 mem = BA1READ4(sc, CS4280_CCTL); 1511 sc->cctl = mem & CCTL_MASK; /* save startup value */ 1512 cs4280_halt_input(sc); 1513 1514 /* MSH: need to power up ADC and DAC? */ 1515 1516 /* Processor Startup Procedure */ 1517 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV); 1518 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 1519 1520 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */ 1521 n = 0; 1522 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) { 1523 delay(10); 1524 if (++n > 1000) { 1525 printf("SPCR 1->0 transition timeout\n"); 1526 return(1); 1527 } 1528 } 1529 1530 n = 0; 1531 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { 1532 delay(10); 1533 if (++n > 1000) { 1534 printf("SPCS 0->1 transition timeout\n"); 1535 return(1); 1536 } 1537 } 1538 /* Processor is now running !!! */ 1539 1540 /* Setup volume */ 1541 BA1WRITE4(sc, CS4280_PVOL, 0x80008000); 1542 BA1WRITE4(sc, CS4280_CVOL, 0x80008000); 1543 1544 /* Interrupt enable */ 1545 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM); 1546 1547 /* playback interrupt enable */ 1548 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK; 1549 mem |= PFIE_PI_ENABLE; 1550 BA1WRITE4(sc, CS4280_PFIE, mem); 1551 /* capture interrupt enable */ 1552 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK; 1553 mem |= CIE_CI_ENABLE; 1554 BA1WRITE4(sc, CS4280_CIE, mem); 1555 1556 #if NMIDI > 0 1557 /* Reset midi port */ 1558 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1559 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST); 1560 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1561 /* midi interrupt enable */ 1562 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE; 1563 BA0WRITE4(sc, CS4280_MIDCR, mem); 1564 #endif 1565 return(0); 1566 } 1567 1568 int 1569 cs4280_activate(struct device *self, int act) 1570 { 1571 struct cs4280_softc *sc = (struct cs4280_softc *)self; 1572 int rv = 0; 1573 1574 switch (act) { 1575 case DVACT_SUSPEND: 1576 /* should I powerdown here ? */ 1577 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL); 1578 break; 1579 case DVACT_RESUME: 1580 cs4280_close(sc); 1581 cs4280_init(sc, 0); 1582 cs4280_init2(sc, 0); 1583 ac97_resume(&sc->host_if, sc->codec_if); 1584 rv = config_activate_children(self, act); 1585 break; 1586 default: 1587 rv = config_activate_children(self, act); 1588 break; 1589 } 1590 return (rv); 1591 } 1592 1593 void 1594 cs4280_clear_fifos(struct cs4280_softc *sc) 1595 { 1596 int pd = 0, cnt, n; 1597 u_int32_t mem; 1598 1599 /* 1600 * If device power down, power up the device and keep power down 1601 * state. 1602 */ 1603 mem = BA0READ4(sc, CS4280_CLKCR1); 1604 if (!(mem & CLKCR1_SWCE)) { 1605 printf("cs4280_clear_fifo: power down found.\n"); 1606 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE); 1607 pd = 1; 1608 } 1609 BA0WRITE4(sc, CS4280_SERBWP, 0); 1610 for (cnt = 0; cnt < 256; cnt++) { 1611 n = 0; 1612 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) { 1613 delay(1000); 1614 if (++n > 1000) { 1615 printf("clear_fifo: fist timeout cnt=%d\n", cnt); 1616 break; 1617 } 1618 } 1619 BA0WRITE4(sc, CS4280_SERBAD, cnt); 1620 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC); 1621 } 1622 if (pd) 1623 BA0WRITE4(sc, CS4280_CLKCR1, mem); 1624 } 1625 1626 #if NMIDI > 0 1627 int 1628 cs4280_midi_open(void *addr, int flags, void (*iintr)(void, int), 1629 void (*ointr)(void *), void *arg) 1630 { 1631 struct cs4280_softc *sc = addr; 1632 u_int32_t mem; 1633 1634 DPRINTF(("midi_open\n")); 1635 sc->sc_iintr = iintr; 1636 sc->sc_ointr = ointr; 1637 sc->sc_arg = arg; 1638 1639 /* midi interrupt enable */ 1640 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK; 1641 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB; 1642 BA0WRITE4(sc, CS4280_MIDCR, mem); 1643 #ifdef CS4280_DEBUG 1644 if (mem != BA0READ4(sc, CS4280_MIDCR)) { 1645 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR))); 1646 return(EINVAL); 1647 } 1648 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR))); 1649 #endif 1650 return (0); 1651 } 1652 1653 void 1654 cs4280_midi_close(void *addr) 1655 { 1656 struct cs4280_softc *sc = addr; 1657 u_int32_t mem; 1658 1659 DPRINTF(("midi_close\n")); 1660 mem = BA0READ4(sc, CS4280_MIDCR); 1661 mem &= ~MIDCR_MASK; 1662 BA0WRITE4(sc, CS4280_MIDCR, mem); 1663 1664 sc->sc_iintr = 0; 1665 sc->sc_ointr = 0; 1666 } 1667 1668 int 1669 cs4280_midi_output(void *addr, int d) 1670 { 1671 struct cs4280_softc *sc = addr; 1672 u_int32_t mem; 1673 int x; 1674 1675 for (x = 0; x != MIDI_BUSY_WAIT; x++) { 1676 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) { 1677 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK; 1678 mem |= d & MIDWP_MASK; 1679 DPRINTFN(5,("midi_output d=0x%08x",d)); 1680 BA0WRITE4(sc, CS4280_MIDWP, mem); 1681 if (mem != BA0READ4(sc, CS4280_MIDWP)) { 1682 DPRINTF(("Bad write data: %d %d", 1683 mem, BA0READ4(sc, CS4280_MIDWP))); 1684 return(EIO); 1685 } 1686 return (0); 1687 } 1688 delay(MIDI_BUSY_DELAY); 1689 } 1690 return (EIO); 1691 } 1692 1693 void 1694 cs4280_midi_getinfo(void *addr, struct midi_info *mi) 1695 { 1696 mi->name = "CS4280 MIDI UART"; 1697 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR; 1698 } 1699 1700 #endif 1701