1 /* $OpenBSD: cmpcireg.h,v 1.1 2000/04/27 02:19:41 millert Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Takuya SHIOZAKI 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* C-Media CMI8x38 Audio Chip Support */ 31 32 #ifndef _DEV_PCI_CMPCIREG_H_ 33 #define _DEV_PCI_CMPCIREG_H_ 34 35 /* 36 * PCI Configuration Registers 37 */ 38 39 #define CMPCI_PCI_IOBASEREG (PCI_MAPREG_START) 40 41 42 /* 43 * I/O Space 44 */ 45 46 #define CMPCI_REG_FUNC_0 0x00 47 # define CMPCI_REG_CH0_DIR 0x00000001 48 # define CMPCI_REG_CH1_DIR 0x00000002 49 # define CMPCI_REG_CH0_PAUSE 0x00000004 50 # define CMPCI_REG_CH1_PAUSE 0x00000008 51 # define CMPCI_REG_CH0_ENABLE 0x00010000 52 # define CMPCI_REG_CH1_ENABLE 0x00020000 53 # define CMPCI_REG_CH0_RESET 0x00040000 54 # define CMPCI_REG_CH1_RESET 0x00080000 55 56 #define CMPCI_REG_FUNC_1 0x04 57 # define CMPCI_REG_JOY_ENABLE 0x00000002 58 # define CMPCI_REG_UART_ENABLE 0x00000004 59 # define CMPCI_REG_LEGACY_ENABLE 0x00000008 60 # define CMPCI_REG_BREQ 0x00000010 61 # define CMPCI_REG_MCBINTR_ENABLE 0x00000020 62 # define CMPCI_REG_SPDIFOUT_DAC 0x00000040 63 # define CMPCI_REG_SPDIF_LOOP 0x00000080 64 # define CMPCI_REG_SPDIF0_ENABLE 0x00000100 65 # define CMPCI_REG_SPDIF1_ENABLE 0x00000200 66 # define CMPCI_REG_DAC_FS_SHIFT 10 67 # define CMPCI_REG_DAC_FS_MASK 0x00000007 68 # define CMPCI_REG_ADC_FS_SHIFT 13 69 # define CMPCI_REG_ADC_FS_MASK 0x00000007 70 71 #define CMPCI_REG_CHANNEL_FORMAT 0x08 72 # define CMPCI_REG_CH0_FORMAT_SHIFT 0 73 # define CMPCI_REG_CH0_FORMAT_MASK 0x00000003 74 # define CMPCI_REG_CH1_FORMAT_SHIFT 2 75 # define CMPCI_REG_CH1_FORMAT_MASK 0x00000003 76 # define CMPCI_REG_FORMAT_MONO 0x00000000 77 # define CMPCI_REG_FORMAT_STEREO 0x00000001 78 # define CMPCI_REG_FORMAT_8BIT 0x00000000 79 # define CMPCI_REG_FORMAT_16BIT 0x00000002 80 81 #define CMPCI_REG_INTR_CTRL 0x0c 82 # define CMPCI_REG_CH0_INTR_ENABLE 0x00010000 83 # define CMPCI_REG_CH1_INTR_ENABLE 0x00020000 84 # define CMPCI_REG_TDMA_INTR_ENABLE 0x00040000 85 86 #define CMPCI_REG_INTR_STATUS 0x10 87 # define CMPCI_REG_CH0_INTR 0x00000001 88 # define CMPCI_REG_CH1_INTR 0x00000002 89 # define CMPCI_REG_CH0_BUSY 0x00000004 90 # define CMPCI_REG_CH1_BUSY 0x00000008 91 # define CMPCI_REG_LEGACY_STEREO 0x00000010 92 # define CMPCI_REG_LEGACY_HDMA 0x00000020 93 # define CMPCI_REG_DMASTAT 0x00000040 94 # define CMPCI_REG_XDO46 0x00000080 95 # define CMPCI_REG_HTDMA_INTR 0x00004000 96 # define CMPCI_REG_LTDMA_INTR 0x00008000 97 # define CMPCI_REG_UART_INTR 0x00010000 98 # define CMPCI_REG_MCB_INTR 0x04000000 99 # define CMPCI_REG_VCO 0x08000000 100 # define CMPCI_REG_ANY_INTR 0x80000000 101 102 #define CMPCI_REG_LEGACY_CTRL 0x14 103 # define CMPCI_REG_LEGACY_SPDIF_ENABLE 0x00200000 104 # define CMPCI_REG_SPDIF_COPYRIGHT 0x00400000 105 # define CMPCI_REG_XSPDIF_ENABLE 0x00800000 106 # define CMPCI_REG_FMSEL_SHIFT 24 107 # define CMPCI_REG_FMSEL_MASK 0x00000003 108 # define CMPCI_REG_VSBSEL_SHIFT 26 109 # define CMPCI_REG_VSBSEL_MASK 0x00000003 110 # define CMPCI_REG_VMPUSEL_SHIFT 29 111 # define CMPCI_REG_VMPUSEL_MASK 0x00000003 112 113 #define CMPCI_REG_MISC 0x18 114 # define CMPCI_REG_SPDIF_48K 0x00008000 115 # define CMPCI_REG_FM_ENABLE 0x00080000 116 117 118 #define CMPCI_REG_SBDATA 0x22 119 #define CMPCI_REG_SBADDR 0x23 120 # define CMPCI_SB16_MIXER_RESET 0x00 121 # define CMPCI_SB16_MIXER_MASTER_L 0x30 122 # define CMPCI_SB16_MIXER_MASTER_R 0x31 123 # define CMPCI_SB16_MIXER_VOICE_L 0x32 124 # define CMPCI_SB16_MIXER_VOICE_R 0x33 125 # define CMPCI_SB16_MIXER_FM_L 0x34 126 # define CMPCI_SB16_MIXER_FM_R 0x35 127 # define CMPCI_SB16_MIXER_CDDA_L 0x36 128 # define CMPCI_SB16_MIXER_CDDA_R 0x37 129 # define CMPCI_SB16_MIXER_LINE_L 0x38 130 # define CMPCI_SB16_MIXER_LINE_R 0x39 131 # define CMPCI_SB16_MIXER_MIC 0x3A 132 # define CMPCI_SB16_MIXER_SPEAKER 0x3B 133 # define CMPCI_SB16_MIXER_OUTMIX 0x3C 134 # define CMPCI_SB16_SW_MIC 0x01 135 # define CMPCI_SB16_SW_CD_R 0x02 136 # define CMPCI_SB16_SW_CD_L 0x04 137 # define CMPCI_SB16_SW_CD (CMPCI_SB16_SW_CD_L|CMPCI_SB16_SW_CD_R) 138 # define CMPCI_SB16_SW_LINE_R 0x08 139 # define CMPCI_SB16_SW_LINE_L 0x10 140 # define CMPCI_SB16_SW_LINE (CMPCI_SB16_SW_LINE_L|CMPCI_SB16_SW_LINE_R) 141 # define CMPCI_SB16_SW_FM_R 0x20 142 # define CMPCI_SB16_SW_FM_L 0x40 143 # define CMPCI_SB16_SW_FM (CMPCI_SB16_SW_FM_L|CMPCI_SB16_SW_FM_R) 144 # define CMPCI_SB16_MIXER_ADCMIX_L 0x3D 145 # define CMPCI_SB16_MIXER_ADCMIX_R 0x3E 146 # define CMPCI_SB16_MIXER_FM_SRC_R 0x20 147 # define CMPCI_SB16_MIXER_LINE_SRC_R 0x08 148 # define CMPCI_SB16_MIXER_CD_SRC_R 0x02 149 # define CMPCI_SB16_MIXER_MIC_SRC 0x01 150 # define CMPCI_SB16_MIXER_SRC_R_TO_L(v) ((v) << 1) 151 152 # define CMPCI_SB16_MIXER_INGAIN_L 0x3F 153 # define CMPCI_SB16_MIXER_INGAIN_R 0x40 154 # define CMPCI_SB16_MIXER_OUTGAIN_L 0x41 155 # define CMPCI_SB16_MIXER_OUTGAIN_R 0x42 156 # define CMPCI_SB16_MIXER_AGC 0x43 157 # define CMPCI_SB16_MIXER_TREBLE_L 0x44 158 # define CMPCI_SB16_MIXER_TREBLE_R 0x45 159 # define CMPCI_SB16_MIXER_BASS_L 0x46 160 # define CMPCI_SB16_MIXER_BASS_R 0x47 161 # define CMPCI_SB16_MIXER_L_TO_R(addr) ((addr)+1) 162 163 # define CMPCI_ADJUST_MIC_GAIN(sc, x) cmpci_adjust((x), 0xf8) 164 # define CMPCI_ADJUST_GAIN(sc, x) cmpci_adjust((x), 0xf8) 165 # define CMPCI_ADJUST_2_GAIN(sc, x) cmpci_adjust((x), 0xc0) 166 167 #define CMPCI_REG_MPU_BASE 0x40 168 #define CMPCI_REG_MPU_SIZE 0x10 169 #define CMPCI_REG_FM_BASE 0x50 170 #define CMPCI_REG_FM_SIZE 0x10 171 172 #define CMPCI_REG_DMA0_BASE 0x80 173 #define CMPCI_REG_DMA0_BYTES 0x84 174 #define CMPCI_REG_DMA0_SAMPLES 0x86 175 #define CMPCI_REG_DMA1_BASE 0x88 176 #define CMPCI_REG_DMA1_BYTES 0x8C 177 #define CMPCI_REG_DMA1_SAMPLES 0x8E 178 179 180 /* sample rate */ 181 #define CMPCI_REG_RATE_5512 0 182 #define CMPCI_REG_RATE_11025 1 183 #define CMPCI_REG_RATE_22050 2 184 #define CMPCI_REG_RATE_44100 3 185 #define CMPCI_REG_RATE_8000 4 186 #define CMPCI_REG_RATE_16000 5 187 #define CMPCI_REG_RATE_32000 6 188 #define CMPCI_REG_RATE_48000 7 189 #define CMPCI_REG_NUMRATE 8 190 191 #endif /* _DEV_PCI_CMPCIREG_H_ */ 192