xref: /openbsd-src/sys/dev/pci/cac_pci.c (revision a28daedfc357b214be5c701aa8ba8adb29a7f1c2)
1 /*	$OpenBSD: cac_pci.c,v 1.13 2009/04/06 15:18:45 kettenis Exp $	*/
2 /*	$NetBSD: cac_pci.c,v 1.10 2001/01/10 16:48:04 ad Exp $	*/
3 
4 /*-
5  * Copyright (c) 2000 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Andrew Doran.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * PCI front-end for cac(4) driver.
35  */
36 
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/device.h>
41 #include <sys/queue.h>
42 
43 #include <machine/endian.h>
44 #include <machine/bus.h>
45 
46 #include <dev/pci/pcidevs.h>
47 #include <dev/pci/pcivar.h>
48 
49 #include <scsi/scsi_all.h>
50 #include <scsi/scsi_disk.h>
51 #include <scsi/scsiconf.h>
52 
53 #include <dev/ic/cacreg.h>
54 #include <dev/ic/cacvar.h>
55 
56 void	cac_pci_attach(struct device *, struct device *, void *);
57 const struct	cac_pci_type *cac_pci_findtype(struct pci_attach_args *);
58 int	cac_pci_match(struct device *, void *, void *);
59 
60 struct	cac_ccb *cac_pci_l0_completed(struct cac_softc *);
61 int	cac_pci_l0_fifo_full(struct cac_softc *);
62 void	cac_pci_l0_intr_enable(struct cac_softc *, int);
63 int	cac_pci_l0_intr_pending(struct cac_softc *);
64 void	cac_pci_l0_submit(struct cac_softc *, struct cac_ccb *);
65 
66 struct cfattach cac_pci_ca = {
67 	sizeof(struct cac_softc), cac_pci_match, cac_pci_attach
68 };
69 
70 static const struct cac_linkage cac_pci_l0 = {
71 	cac_pci_l0_completed,
72 	cac_pci_l0_fifo_full,
73 	cac_pci_l0_intr_enable,
74 	cac_pci_l0_intr_pending,
75 	cac_pci_l0_submit
76 };
77 
78 #define CT_STARTFW	0x01	/* Need to start controller firmware */
79 
80 static const
81 struct cac_pci_type {
82 	int	ct_subsysid;
83 	int	ct_flags;
84 	const struct	cac_linkage *ct_linkage;
85 	char	*ct_typestr;
86 } cac_pci_type[] = {
87 	{ 0x40300e11,	0,		&cac_l0,	"SMART-2/P" },
88 	{ 0x40310e11,	0,		&cac_l0,	"SMART-2SL" },
89 	{ 0x40320e11,	0,		&cac_l0,	"Smart Array 3200" },
90 	{ 0x40330e11,	0,		&cac_l0,	"Smart Array 3100ES" },
91 	{ 0x40340e11,	0,		&cac_l0,	"Smart Array 221" },
92 	{ 0x40400e11,	CT_STARTFW,	&cac_pci_l0,	"Integrated Array" },
93 	{ 0x40480e11,	CT_STARTFW,	&cac_pci_l0,	"RAID LC2" },
94 	{ 0x40500e11,	0,		&cac_pci_l0,	"Smart Array 4200" },
95 	{ 0x40510e11,	0,		&cac_pci_l0,	"Smart Array 4200ES" },
96 	{ 0x40580e11,	0,		&cac_pci_l0,	"Smart Array 431" },
97 };
98 
99 static const
100 struct cac_pci_product {
101 	u_short	cp_vendor;
102 	u_short	cp_product;
103 } cac_pci_product[] = {
104 	{ PCI_VENDOR_COMPAQ,	PCI_PRODUCT_COMPAQ_SMART2P },
105 	{ PCI_VENDOR_DEC,	PCI_PRODUCT_DEC_21554 },
106 	{ PCI_VENDOR_SYMBIOS,	PCI_PRODUCT_SYMBIOS_1510 },
107 };
108 
109 const struct cac_pci_type *
110 cac_pci_findtype(pa)
111 	struct pci_attach_args *pa;
112 {
113 	const struct cac_pci_type *ct;
114 	const struct cac_pci_product *cp;
115 	pcireg_t subsysid;
116 	int i;
117 
118 	cp = cac_pci_product;
119 	i = 0;
120 	while (i < sizeof(cac_pci_product) / sizeof(cac_pci_product[0])) {
121 		if (PCI_VENDOR(pa->pa_id) == cp->cp_vendor &&
122 		    PCI_PRODUCT(pa->pa_id) == cp->cp_product)
123 			break;
124 		cp++;
125 		i++;
126 	}
127 	if (i == sizeof(cac_pci_product) / sizeof(cac_pci_product[0]))
128 		return (NULL);
129 
130 	subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
131 	ct = cac_pci_type;
132 	i = 0;
133 	while (i < sizeof(cac_pci_type) / sizeof(cac_pci_type[0])) {
134 		if (subsysid == ct->ct_subsysid)
135 			break;
136 		ct++;
137 		i++;
138 	}
139 	if (i == sizeof(cac_pci_type) / sizeof(cac_pci_type[0]))
140 		return (NULL);
141 
142 	return (ct);
143 }
144 
145 int
146 cac_pci_match(parent, match, aux)
147 	struct device *parent;
148 	void *match, *aux;
149 {
150 
151 	return (cac_pci_findtype(aux) != NULL);
152 }
153 
154 void
155 cac_pci_attach(parent, self, aux)
156 	struct device *parent;
157 	struct device *self;
158 	void *aux;
159 {
160 	struct pci_attach_args *pa;
161 	const struct cac_pci_type *ct;
162 	struct cac_softc *sc;
163 	pci_chipset_tag_t pc;
164 	pci_intr_handle_t ih;
165 	const char *intrstr;
166 	pcireg_t reg;
167 	bus_size_t size;
168 	int memr, ior, i;
169 
170 	sc = (struct cac_softc *)self;
171 	pa = (struct pci_attach_args *)aux;
172 	pc = pa->pa_pc;
173 	ct = cac_pci_findtype(pa);
174 
175 	/*
176 	 * Map the PCI register window.
177 	 */
178 	memr = -1;
179 	ior = -1;
180 
181 	for (i = 0x10; i <= 0x14; i += 4) {
182 		reg = pci_conf_read(pa->pa_pc, pa->pa_tag, i);
183 
184 		if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) {
185 			if (ior == -1 && PCI_MAPREG_IO_SIZE(reg) != 0)
186 				ior = i;
187 		} else {
188 			if (memr == -1 && PCI_MAPREG_MEM_SIZE(reg) != 0)
189 				memr = i;
190 		}
191 	}
192 
193 	if (memr != -1) {
194 		if (pci_mapreg_map(pa, memr, PCI_MAPREG_TYPE_MEM, 0,
195 		    &sc->sc_iot, &sc->sc_ioh, NULL, &size, 0))
196 			memr = -1;
197 		else
198 			ior = -1;
199 	}
200 	if (ior != -1)
201 		if (pci_mapreg_map(pa, ior, PCI_MAPREG_TYPE_IO, 0,
202 		    &sc->sc_iot, &sc->sc_ioh, NULL, &size, 0))
203 			ior = -1;
204 	if (memr == -1 && ior == -1) {
205 		printf(": can't map i/o or memory space\n");
206 		return;
207 	}
208 
209 	sc->sc_dmat = pa->pa_dmat;
210 
211 	/* Map and establish the interrupt. */
212 	if (pci_intr_map(pa, &ih)) {
213 		printf(": can't map interrupt\n");
214 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
215 		return;
216 	}
217 	intrstr = pci_intr_string(pc, ih);
218 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, cac_intr,
219 	    sc, sc->sc_dv.dv_xname);
220 	if (sc->sc_ih == NULL) {
221 		printf(": can't establish interrupt");
222 		if (intrstr != NULL)
223 			printf(" at %s", intrstr);
224 		printf("\n");
225 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
226 		return;
227 	}
228 
229 	printf(": %s, %s\n", intrstr, ct->ct_typestr);
230 
231 	/* Now attach to the bus-independent code. */
232 	sc->sc_cl = ct->ct_linkage;
233 	cac_init(sc, (ct->ct_flags & CT_STARTFW) != 0);
234 }
235 
236 void
237 cac_pci_l0_submit(struct cac_softc *sc, struct cac_ccb *ccb)
238 {
239 
240 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0,
241 	    sc->sc_dmamap->dm_mapsize,
242 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
243 	cac_outl(sc, CAC_42REG_CMD_FIFO, ccb->ccb_paddr);
244 }
245 
246 struct cac_ccb *
247 cac_pci_l0_completed(struct cac_softc *sc)
248 {
249 	struct cac_ccb *ccb;
250 	u_int32_t off;
251 
252 	if ((off = cac_inl(sc, CAC_42REG_DONE_FIFO)) == 0xffffffffU)
253 		return (NULL);
254 
255 	cac_outl(sc, CAC_42REG_DONE_FIFO, 0);
256 	off = (off & ~3) - sc->sc_ccbs_paddr;
257 	ccb = (struct cac_ccb *)(sc->sc_ccbs + off);
258 
259 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0,
260 	    sc->sc_dmamap->dm_mapsize,
261 	    BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
262 
263 	return (ccb);
264 }
265 
266 int
267 cac_pci_l0_intr_pending(struct cac_softc *sc)
268 {
269 
270 	return ((cac_inl(sc, CAC_42REG_STATUS) & CAC_42_EXTINT) != 0);
271 }
272 
273 void
274 cac_pci_l0_intr_enable(struct cac_softc *sc, int state)
275 {
276 
277 	cac_outl(sc, CAC_42REG_INTR_MASK, (state ? 0 : 8));	/* XXX */
278 }
279 
280 int
281 cac_pci_l0_fifo_full(struct cac_softc *sc)
282 {
283 
284 	return (cac_inl(sc, CAC_42REG_CMD_FIFO) != 0);
285 }
286