1 /* $OpenBSD: auich.c,v 1.106 2016/09/19 06:46:44 ratchov Exp $ */ 2 3 /* 4 * Copyright (c) 2000,2001 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * AC'97 audio found on Intel 810/815/820/440MX chipsets. 31 * http://developer.intel.com/design/chipsets/datashts/290655.htm 32 * http://developer.intel.com/design/chipsets/manuals/298028.htm 33 * http://www.intel.com/design/chipsets/datashts/290714.htm 34 * http://www.intel.com/design/chipsets/datashts/290744.htm 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/device.h> 41 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pcivar.h> 44 45 #include <sys/audioio.h> 46 #include <dev/audio_if.h> 47 48 #include <machine/bus.h> 49 50 #include <dev/ic/ac97.h> 51 52 /* 12.1.10 NAMBAR - native audio mixer base address register */ 53 #define AUICH_NAMBAR 0x10 54 /* 12.1.11 NABMBAR - native audio bus mastering base address register */ 55 #define AUICH_NABMBAR 0x14 56 #define AUICH_CFG 0x41 57 #define AUICH_CFG_IOSE 0x01 58 /* ICH4/ICH5/ICH6/ICH7 native audio mixer BAR */ 59 #define AUICH_MMBAR 0x18 60 /* ICH4/ICH5/ICH6/ICH7 native bus mastering BAR */ 61 #define AUICH_MBBAR 0x1c 62 #define AUICH_S2CR 0x10000000 /* tertiary codec ready */ 63 64 /* table 12-3. native audio bus master control registers */ 65 #define AUICH_BDBAR 0x00 /* 8-byte aligned address */ 66 #define AUICH_CIV 0x04 /* 5 bits current index value */ 67 #define AUICH_LVI 0x05 /* 5 bits last valid index value */ 68 #define AUICH_LVI_MASK 0x1f 69 #define AUICH_STS 0x06 /* 16 bits status */ 70 #define AUICH_FIFOE 0x10 /* fifo error */ 71 #define AUICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */ 72 #define AUICH_LVBCI 0x04 /* r- last valid bci, wr ack */ 73 #define AUICH_CELV 0x02 /* current equals last valid */ 74 #define AUICH_DCH 0x01 /* dma halted */ 75 #define AUICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe" 76 #define AUICH_PICB 0x08 /* 16 bits */ 77 #define AUICH_PIV 0x0a /* 5 bits prefetched index value */ 78 #define AUICH_CTRL 0x0b /* control */ 79 #define AUICH_IOCE 0x10 /* int on completion enable */ 80 #define AUICH_FEIE 0x08 /* fifo error int enable */ 81 #define AUICH_LVBIE 0x04 /* last valid buf int enable */ 82 #define AUICH_RR 0x02 /* 1 - reset regs */ 83 #define AUICH_RPBM 0x01 /* 1 - run, 0 - pause */ 84 85 #define AUICH_PCMI 0x00 86 #define AUICH_PCMO 0x10 87 #define AUICH_MICI 0x20 88 89 #define AUICH_GCTRL 0x2c 90 #define AUICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */ 91 #define AUICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */ 92 #define AUICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */ 93 #define AUICH_POM16 0x000000 /* PCM out precision 16bit */ 94 #define AUICH_POM20 0x400000 /* PCM out precision 20bit */ 95 #define AUICH_PCM246_MASK 0x300000 96 #define AUICH_PCM2 0x000000 /* 2ch output */ 97 #define AUICH_PCM4 0x100000 /* 4ch output */ 98 #define AUICH_PCM6 0x200000 /* 6ch output */ 99 #define AUICH_SIS_PCM246_MASK 0x0000c0 /* SiS 7012 */ 100 #define AUICH_SIS_PCM2 0x000000 /* SiS 7012 2ch output */ 101 #define AUICH_SIS_PCM4 0x000040 /* SiS 7012 4ch output */ 102 #define AUICH_SIS_PCM6 0x000080 /* SiS 7012 6ch output */ 103 #define AUICH_S2RIE 0x40 /* int when tertiary codec resume */ 104 #define AUICH_SRIE 0x20 /* int when 2ndary codec resume */ 105 #define AUICH_PRIE 0x10 /* int when primary codec resume */ 106 #define AUICH_ACLSO 0x08 /* aclink shut off */ 107 #define AUICH_WRESET 0x04 /* warm reset */ 108 #define AUICH_CRESET 0x02 /* cold reset */ 109 #define AUICH_GIE 0x01 /* gpi int enable */ 110 #define AUICH_GSTS 0x30 111 #define AUICH_MD3 0x20000 /* pwr-dn semaphore for modem */ 112 #define AUICH_AD3 0x10000 /* pwr-dn semaphore for audio */ 113 #define AUICH_RCS 0x08000 /* read completion status */ 114 #define AUICH_B3S12 0x04000 /* bit 3 of slot 12 */ 115 #define AUICH_B2S12 0x02000 /* bit 2 of slot 12 */ 116 #define AUICH_B1S12 0x01000 /* bit 1 of slot 12 */ 117 #define AUICH_SRI 0x00800 /* secondary resume int */ 118 #define AUICH_PRI 0x00400 /* primary resume int */ 119 #define AUICH_SCR 0x00200 /* secondary codec ready */ 120 #define AUICH_PCR 0x00100 /* primary codec ready */ 121 #define AUICH_MINT 0x00080 /* mic in int */ 122 #define AUICH_POINT 0x00040 /* pcm out int */ 123 #define AUICH_PIINT 0x00020 /* pcm in int */ 124 #define AUICH_MOINT 0x00004 /* modem out int */ 125 #define AUICH_MIINT 0x00002 /* modem in int */ 126 #define AUICH_GSCI 0x00001 /* gpi status change */ 127 #define AUICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3" 128 #define AUICH_CAS 0x34 /* 1/8 bit */ 129 #define AUICH_SEMATIMO 1000 /* us */ 130 #define AUICH_RESETIMO 500000 /* us */ 131 132 #define ICH_SIS_NV_CTL 0x4c /* some SiS/NVIDIA register. From Linux */ 133 #define ICH_SIS_CTL_UNMUTE 0x01 /* un-mute the output */ 134 135 /* 136 * There are 32 buffer descriptors. Each can reference up to 2^16 16-bit 137 * samples. 138 */ 139 #define AUICH_DMALIST_MAX 32 140 #define AUICH_DMASEG_MAX (65536*2) 141 struct auich_dmalist { 142 u_int32_t base; 143 u_int32_t len; 144 #define AUICH_DMAF_IOC 0x80000000 /* 1-int on complete */ 145 #define AUICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 146 }; 147 148 #define AUICH_FIXED_RATE 48000 149 150 struct auich_dma { 151 bus_dmamap_t map; 152 caddr_t addr; 153 bus_dma_segment_t segs[1]; 154 int nsegs; 155 size_t size; 156 }; 157 158 struct auich_cdata { 159 struct auich_dmalist ic_dmalist_pcmo[AUICH_DMALIST_MAX]; 160 struct auich_dmalist ic_dmalist_pcmi[AUICH_DMALIST_MAX]; 161 struct auich_dmalist ic_dmalist_mici[AUICH_DMALIST_MAX]; 162 }; 163 164 #define AUICH_CDOFF(x) offsetof(struct auich_cdata, x) 165 #define AUICH_PCMO_OFF(x) AUICH_CDOFF(ic_dmalist_pcmo[(x)]) 166 #define AUICH_PCMI_OFF(x) AUICH_CDOFF(ic_dmalist_pcmi[(x)]) 167 #define AUICH_MICI_OFF(x) AUICH_CDOFF(ic_dmalist_mici[(x)]) 168 169 struct auich_softc { 170 struct device sc_dev; 171 void *sc_ih; 172 173 pcireg_t pci_id; 174 bus_space_tag_t iot; 175 bus_space_tag_t iot_mix; 176 bus_space_handle_t mix_ioh; 177 bus_space_handle_t aud_ioh; 178 bus_dma_tag_t dmat; 179 180 struct ac97_codec_if *codec_if; 181 struct ac97_host_if host_if; 182 int sc_spdif; 183 184 /* dma scatter-gather buffer lists */ 185 186 bus_dmamap_t sc_cddmamap; 187 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 188 189 struct auich_cdata *sc_cdata; 190 191 struct auich_ring { 192 int qptr; 193 struct auich_dmalist *dmalist; 194 195 uint32_t start, p, end; 196 int blksize; 197 198 void (*intr)(void *); 199 void *arg; 200 int running; 201 size_t size; 202 uint32_t ap; 203 } pcmo, pcmi, mici; 204 205 struct auich_dma *sc_pdma; /* play */ 206 struct auich_dma *sc_rdma; /* record */ 207 struct auich_dma *sc_cdma; /* calibrate */ 208 209 #ifdef AUICH_DEBUG 210 int pcmi_fifoe; 211 int pcmo_fifoe; 212 #endif 213 214 int suspend; 215 u_int16_t ext_ctrl; 216 int sc_sample_size; 217 int sc_sts_reg; 218 int sc_dmamap_flags; 219 int sc_ignore_codecready; 220 int flags; 221 int sc_ac97rate; 222 223 /* multi-channel control bits */ 224 int sc_pcm246_mask; 225 int sc_pcm2; 226 int sc_pcm4; 227 int sc_pcm6; 228 229 u_int last_rrate; 230 u_int last_prate; 231 u_int last_pchan; 232 }; 233 234 #ifdef AUICH_DEBUG 235 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 236 int auich_debug = 0x0002; 237 #define AUICH_DEBUG_CODECIO 0x0001 238 #define AUICH_DEBUG_DMA 0x0002 239 #define AUICH_DEBUG_INTR 0x0004 240 #else 241 #define DPRINTF(x,y) /* nothing */ 242 #endif 243 244 struct cfdriver auich_cd = { 245 NULL, "auich", DV_DULL 246 }; 247 248 int auich_match(struct device *, void *, void *); 249 void auich_attach(struct device *, struct device *, void *); 250 int auich_intr(void *); 251 252 int auich_activate(struct device *, int); 253 254 struct cfattach auich_ca = { 255 sizeof(struct auich_softc), auich_match, auich_attach, 256 NULL, auich_activate 257 }; 258 259 static const struct auich_devtype { 260 int vendor; 261 int product; 262 int options; 263 char name[8]; 264 } auich_devices[] = { 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_ACA, 0, "ESB" }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_ACA, 0, "ESB2" }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 0, "ICH" }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 0, "ICH0" }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 0, "ICH2" }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_ACA, 0, "ICH3" }, 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ACA, 0, "ICH4" }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_ACA, 0, "ICH5" }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_ACA, 0, "ICH6" }, 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_ACA, 0, "ICH7" }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 0, "440MX" }, 276 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_ACA, 0, "SiS7012" }, 277 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_ACA, 0, "nForce" }, 278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_ACA, 0, "nForce2" }, 279 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_ACA, 280 0, "nForce2" }, 281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_ACA, 0, "nForce3" }, 282 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_ACA, 283 0, "nForce3" }, 284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_AC, 0, "nForce4" }, 285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_AC97, 0, "MCP04" }, 286 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_ACA, 0, "MCP51" }, 287 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_ACA, 0, "AMD768" }, 288 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_8111_ACA, 0, "AMD8111" }, 289 }; 290 291 int auich_open(void *, int); 292 void auich_close(void *); 293 int auich_set_params(void *, int, int, struct audio_params *, 294 struct audio_params *); 295 int auich_round_blocksize(void *, int); 296 void auich_halt_pipe(struct auich_softc *, int, struct auich_ring *); 297 int auich_halt_output(void *); 298 int auich_halt_input(void *); 299 int auich_set_port(void *, mixer_ctrl_t *); 300 int auich_get_port(void *, mixer_ctrl_t *); 301 int auich_query_devinfo(void *, mixer_devinfo_t *); 302 void *auich_allocm(void *, int, size_t, int, int); 303 void auich_freem(void *, void *, int); 304 size_t auich_round_buffersize(void *, int, size_t); 305 int auich_get_props(void *); 306 void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 307 void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 308 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 309 void *, struct audio_params *); 310 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 311 void *, struct audio_params *); 312 int auich_alloc_cdata(struct auich_softc *); 313 int auich_allocmem(struct auich_softc *, size_t, size_t, struct auich_dma *); 314 int auich_freemem(struct auich_softc *, struct auich_dma *); 315 316 int auich_resume(struct auich_softc *); 317 318 struct audio_hw_if auich_hw_if = { 319 auich_open, 320 auich_close, 321 auich_set_params, 322 auich_round_blocksize, 323 NULL, /* commit_setting */ 324 NULL, /* init_output */ 325 NULL, /* init_input */ 326 NULL, /* start_output */ 327 NULL, /* start_input */ 328 auich_halt_output, 329 auich_halt_input, 330 NULL, /* speaker_ctl */ 331 NULL, /* getfd */ 332 auich_set_port, 333 auich_get_port, 334 auich_query_devinfo, 335 auich_allocm, 336 auich_freem, 337 auich_round_buffersize, 338 auich_get_props, 339 auich_trigger_output, 340 auich_trigger_input 341 }; 342 343 int auich_attach_codec(void *, struct ac97_codec_if *); 344 int auich_read_codec(void *, u_int8_t, u_int16_t *); 345 int auich_write_codec(void *, u_int8_t, u_int16_t); 346 void auich_reset_codec(void *); 347 enum ac97_host_flags auich_flags_codec(void *); 348 unsigned int auich_calibrate(struct auich_softc *); 349 void auich_spdif_event(void *, int); 350 351 int 352 auich_match(struct device *parent, void *match, void *aux) 353 { 354 struct pci_attach_args *pa = aux; 355 int i; 356 357 for (i = nitems(auich_devices); i--;) 358 if (PCI_VENDOR(pa->pa_id) == auich_devices[i].vendor && 359 PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 360 return 1; 361 362 return 0; 363 } 364 365 void 366 auich_attach(struct device *parent, struct device *self, void *aux) 367 { 368 struct auich_softc *sc = (struct auich_softc *)self; 369 struct pci_attach_args *pa = aux; 370 pci_intr_handle_t ih; 371 bus_size_t mix_size, aud_size; 372 pcireg_t csr; 373 const char *intrstr; 374 u_int32_t status; 375 int i; 376 377 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 378 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 379 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 380 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 381 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 382 /* 383 * Use native mode for ICH4/ICH5/ICH6/ICH7 384 */ 385 if (pci_mapreg_map(pa, AUICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 386 &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 387 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 388 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 389 csr | AUICH_CFG_IOSE); 390 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 391 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 392 printf(": can't map codec mem/io space\n"); 393 return; 394 } 395 } 396 397 if (pci_mapreg_map(pa, AUICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 398 &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 399 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 400 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 401 csr | AUICH_CFG_IOSE); 402 if (pci_mapreg_map(pa, AUICH_NABMBAR, 403 PCI_MAPREG_TYPE_IO, 0, &sc->iot, 404 &sc->aud_ioh, NULL, &aud_size, 0)) { 405 printf(": can't map device mem/io space\n"); 406 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 407 return; 408 } 409 } 410 } else { 411 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 412 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 413 printf(": can't map codec i/o space\n"); 414 return; 415 } 416 417 if (pci_mapreg_map(pa, AUICH_NABMBAR, PCI_MAPREG_TYPE_IO, 418 0, &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 419 printf(": can't map device i/o space\n"); 420 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 421 return; 422 } 423 } 424 sc->dmat = pa->pa_dmat; 425 sc->pci_id = pa->pa_id; 426 427 if (pci_intr_map(pa, &ih)) { 428 printf(": can't map interrupt\n"); 429 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 430 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 431 return; 432 } 433 intrstr = pci_intr_string(pa->pa_pc, ih); 434 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO | IPL_MPSAFE, 435 auich_intr, sc, sc->sc_dev.dv_xname); 436 if (!sc->sc_ih) { 437 printf(": can't establish interrupt"); 438 if (intrstr) 439 printf(" at %s", intrstr); 440 printf("\n"); 441 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 442 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 443 return; 444 } 445 446 for (i = nitems(auich_devices); i--;) 447 if (PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 448 break; 449 450 printf(": %s, %s\n", intrstr, auich_devices[i].name); 451 452 /* SiS 7012 needs special handling */ 453 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 454 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_7012_ACA) { 455 sc->sc_sts_reg = AUICH_PICB; 456 sc->sc_sample_size = 1; 457 sc->sc_pcm246_mask = AUICH_SIS_PCM246_MASK; 458 sc->sc_pcm2 = AUICH_SIS_PCM2; 459 sc->sc_pcm4 = AUICH_SIS_PCM4; 460 sc->sc_pcm6 = AUICH_SIS_PCM6; 461 /* un-mute output */ 462 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 463 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 464 ICH_SIS_CTL_UNMUTE); 465 } else { 466 sc->sc_sts_reg = AUICH_STS; 467 sc->sc_sample_size = 2; 468 sc->sc_pcm246_mask = AUICH_PCM246_MASK; 469 sc->sc_pcm2 = AUICH_PCM2; 470 sc->sc_pcm4 = AUICH_PCM4; 471 sc->sc_pcm6 = AUICH_PCM6; 472 } 473 474 /* Workaround for a 440MX B-stepping erratum */ 475 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 476 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 477 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_ACA) { 478 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 479 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 480 } 481 482 /* Set up DMA lists. */ 483 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 484 auich_alloc_cdata(sc); 485 486 DPRINTF(AUICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 487 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 488 489 /* Reset codec and AC'97 */ 490 auich_reset_codec(sc); 491 status = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 492 if (!(status & AUICH_PCR)) { /* reset failure */ 493 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 494 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 495 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 496 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 497 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 498 /* MSI 845G Max never return AUICH_PCR */ 499 sc->sc_ignore_codecready = 1; 500 } else { 501 printf("%s: reset failed!\n", sc->sc_dev.dv_xname); 502 return; 503 } 504 } 505 506 sc->host_if.arg = sc; 507 sc->host_if.attach = auich_attach_codec; 508 sc->host_if.read = auich_read_codec; 509 sc->host_if.write = auich_write_codec; 510 sc->host_if.reset = auich_reset_codec; 511 sc->host_if.flags = auich_flags_codec; 512 sc->host_if.spdif_event = auich_spdif_event; 513 if (sc->sc_dev.dv_cfdata->cf_flags & 0x0001) 514 sc->flags = AC97_HOST_SWAPPED_CHANNELS; 515 516 if (ac97_attach(&sc->host_if) != 0) { 517 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 518 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 519 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 520 return; 521 } 522 sc->codec_if->vtbl->unlock(sc->codec_if); 523 524 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 525 526 /* Watch for power changes */ 527 sc->suspend = DVACT_RESUME; 528 529 sc->sc_ac97rate = -1; 530 } 531 532 int 533 auich_activate(struct device *self, int act) 534 { 535 struct auich_softc *sc = (struct auich_softc *)self; 536 int rv = 0; 537 538 switch (act) { 539 case DVACT_RESUME: 540 auich_resume(sc); 541 rv = config_activate_children(self, act); 542 break; 543 default: 544 rv = config_activate_children(self, act); 545 break; 546 } 547 return (rv); 548 } 549 550 int 551 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 552 { 553 struct auich_softc *sc = v; 554 int i; 555 556 /* wait for an access semaphore */ 557 for (i = AUICH_SEMATIMO; i-- && 558 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 559 560 if (!sc->sc_ignore_codecready && i < 0) { 561 DPRINTF(AUICH_DEBUG_CODECIO, 562 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 563 return (-1); 564 } 565 566 *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg); 567 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: read_codec(%x, %x)\n", 568 sc->sc_dev.dv_xname, reg, *val)); 569 return (0); 570 } 571 572 int 573 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 574 { 575 struct auich_softc *sc = v; 576 int i; 577 578 /* wait for an access semaphore */ 579 for (i = AUICH_SEMATIMO; i-- && 580 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 581 582 if (sc->sc_ignore_codecready || i >= 0) { 583 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: write_codec(%x, %x)\n", 584 sc->sc_dev.dv_xname, reg, val)); 585 bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val); 586 return (0); 587 } else { 588 DPRINTF(AUICH_DEBUG_CODECIO, 589 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 590 return (-1); 591 } 592 } 593 594 int 595 auich_attach_codec(void *v, struct ac97_codec_if *cif) 596 { 597 struct auich_softc *sc = v; 598 599 sc->codec_if = cif; 600 return 0; 601 } 602 603 void 604 auich_reset_codec(void *v) 605 { 606 struct auich_softc *sc = v; 607 u_int32_t control; 608 int i; 609 610 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 611 control &= ~(AUICH_ACLSO | sc->sc_pcm246_mask); 612 control |= (control & AUICH_CRESET) ? AUICH_WRESET : AUICH_CRESET; 613 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 614 615 for (i = AUICH_RESETIMO; i-- && 616 !(bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS) & AUICH_PCR); 617 DELAY(1)); 618 619 if (i < 0) 620 DPRINTF(AUICH_DEBUG_CODECIO, 621 ("%s: reset_codec timeout\n", sc->sc_dev.dv_xname)); 622 } 623 624 enum ac97_host_flags 625 auich_flags_codec(void *v) 626 { 627 struct auich_softc *sc = v; 628 629 return (sc->flags); 630 } 631 632 void 633 auich_spdif_event(void *v, int flag) 634 { 635 struct auich_softc *sc = v; 636 sc->sc_spdif = flag; 637 } 638 639 int 640 auich_open(void *v, int flags) 641 { 642 struct auich_softc *sc = v; 643 644 if (sc->sc_ac97rate == -1) 645 sc->sc_ac97rate = auich_calibrate(sc); 646 647 sc->codec_if->vtbl->lock(sc->codec_if); 648 649 return 0; 650 } 651 652 void 653 auich_close(void *v) 654 { 655 struct auich_softc *sc = v; 656 657 sc->codec_if->vtbl->unlock(sc->codec_if); 658 } 659 660 int 661 auich_set_params(void *v, int setmode, int usemode, 662 struct audio_params *play, struct audio_params *rec) 663 { 664 struct auich_softc *sc = v; 665 struct ac97_codec_if *codec = sc->codec_if; 666 int error; 667 u_int orate; 668 u_int adj_rate; 669 u_int32_t control; 670 u_int16_t ext_id; 671 672 if (setmode & AUMODE_PLAY) { 673 /* only 16-bit 48kHz slinear_le if s/pdif enabled */ 674 if (sc->sc_spdif) { 675 play->sample_rate = 48000; 676 play->precision = 16; 677 play->encoding = AUDIO_ENCODING_SLINEAR_LE; 678 } 679 } 680 if (setmode & AUMODE_PLAY) { 681 play->precision = 16; 682 switch(play->encoding) { 683 case AUDIO_ENCODING_SLINEAR_LE: 684 if (play->channels > 6) 685 play->channels = 6; 686 if (play->channels > 1) 687 play->channels &= ~1; 688 switch (play->channels) { 689 case 1: 690 play->channels = 2; 691 break; 692 case 2: 693 break; 694 case 4: 695 ext_id = codec->vtbl->get_caps(codec); 696 if (!(ext_id & AC97_EXT_AUDIO_SDAC)) 697 play->channels = 2; 698 break; 699 case 6: 700 ext_id = codec->vtbl->get_caps(codec); 701 if ((ext_id & AC97_BITS_6CH) != 702 AC97_BITS_6CH) 703 play->channels = 2; 704 break; 705 default: 706 return (EINVAL); 707 } 708 break; 709 default: 710 return (EINVAL); 711 } 712 play->bps = AUDIO_BPS(play->precision); 713 play->msb = 1; 714 715 orate = adj_rate = play->sample_rate; 716 if (sc->sc_ac97rate != 0) 717 adj_rate = orate * AUICH_FIXED_RATE / sc->sc_ac97rate; 718 719 play->sample_rate = adj_rate; 720 sc->last_prate = play->sample_rate; 721 722 error = ac97_set_rate(sc->codec_if, 723 AC97_REG_PCM_LFE_DAC_RATE, &play->sample_rate); 724 if (error) 725 return (error); 726 727 play->sample_rate = adj_rate; 728 error = ac97_set_rate(sc->codec_if, 729 AC97_REG_PCM_SURR_DAC_RATE, &play->sample_rate); 730 if (error) 731 return (error); 732 733 play->sample_rate = adj_rate; 734 error = ac97_set_rate(sc->codec_if, 735 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate); 736 if (error) 737 return (error); 738 739 if (play->sample_rate == adj_rate) 740 play->sample_rate = orate; 741 742 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 743 control &= ~(sc->sc_pcm246_mask); 744 if (play->channels == 4) 745 control |= sc->sc_pcm4; 746 else if (play->channels == 6) 747 control |= sc->sc_pcm6; 748 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 749 750 sc->last_pchan = play->channels; 751 } 752 753 if (setmode & AUMODE_RECORD) { 754 rec->channels = 2; 755 rec->precision = 16; 756 rec->encoding = AUDIO_ENCODING_SLINEAR_LE; 757 rec->bps = AUDIO_BPS(rec->precision); 758 rec->msb = 1; 759 760 orate = rec->sample_rate; 761 if (sc->sc_ac97rate != 0) 762 rec->sample_rate = orate * AUICH_FIXED_RATE / 763 sc->sc_ac97rate; 764 sc->last_rrate = rec->sample_rate; 765 error = ac97_set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 766 &rec->sample_rate); 767 if (error) 768 return (error); 769 rec->sample_rate = orate; 770 } 771 772 return (0); 773 } 774 775 int 776 auich_round_blocksize(void *v, int blk) 777 { 778 return (blk + 0x3f) & ~0x3f; 779 } 780 781 782 void 783 auich_halt_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 784 { 785 int i; 786 uint32_t sts; 787 788 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 0); 789 790 /* wait for DMA halted and clear interrupt / event bits if needed */ 791 for (i = 0; i < 1000; i++) { 792 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 793 pipe + sc->sc_sts_reg); 794 if (sts & (AUICH_CELV | AUICH_LVBCI | AUICH_BCIS | AUICH_FIFOE)) 795 bus_space_write_2(sc->iot, sc->aud_ioh, 796 pipe + sc->sc_sts_reg, 797 AUICH_CELV | AUICH_LVBCI | 798 AUICH_BCIS | AUICH_FIFOE); 799 if (sts & AUICH_DCH) 800 break; 801 DELAY(100); 802 } 803 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, AUICH_RR); 804 805 if (i > 0) 806 DPRINTF(AUICH_DEBUG_DMA, 807 ("auich_halt_pipe: halt took %d cycles\n", i)); 808 809 ring->running = 0; 810 } 811 812 813 int 814 auich_halt_output(void *v) 815 { 816 struct auich_softc *sc = v; 817 818 DPRINTF(AUICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 819 820 mtx_enter(&audio_lock); 821 auich_halt_pipe(sc, AUICH_PCMO, &sc->pcmo); 822 823 sc->pcmo.intr = NULL; 824 mtx_leave(&audio_lock); 825 return 0; 826 } 827 828 int 829 auich_halt_input(void *v) 830 { 831 struct auich_softc *sc = v; 832 833 DPRINTF(AUICH_DEBUG_DMA, 834 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 835 836 /* XXX halt both unless known otherwise */ 837 mtx_enter(&audio_lock); 838 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 839 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 840 841 sc->pcmi.intr = NULL; 842 mtx_leave(&audio_lock); 843 return 0; 844 } 845 846 int 847 auich_set_port(void *v, mixer_ctrl_t *cp) 848 { 849 struct auich_softc *sc = v; 850 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 851 } 852 853 int 854 auich_get_port(void *v, mixer_ctrl_t *cp) 855 { 856 struct auich_softc *sc = v; 857 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 858 } 859 860 int 861 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 862 { 863 struct auich_softc *sc = v; 864 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 865 } 866 867 void * 868 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 869 { 870 struct auich_softc *sc = v; 871 struct auich_dma *p; 872 int error; 873 874 /* can only use 1 segment */ 875 if (size > AUICH_DMASEG_MAX) { 876 DPRINTF(AUICH_DEBUG_DMA, 877 ("%s: requested buffer size too large: %zd", \ 878 sc->sc_dev.dv_xname, size)); 879 return NULL; 880 } 881 882 p = malloc(sizeof(*p), pool, flags | M_ZERO); 883 if (!p) 884 return NULL; 885 886 error = auich_allocmem(sc, size, PAGE_SIZE, p); 887 if (error) { 888 free(p, pool, 0); 889 return NULL; 890 } 891 892 if (direction == AUMODE_PLAY) 893 sc->sc_pdma = p; 894 else if (direction == AUMODE_RECORD) 895 sc->sc_rdma = p; 896 else 897 sc->sc_cdma = p; 898 899 return p->addr; 900 } 901 902 void 903 auich_freem(void *v, void *ptr, int pool) 904 { 905 struct auich_softc *sc; 906 struct auich_dma *p; 907 908 sc = v; 909 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == ptr) 910 p = sc->sc_pdma; 911 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == ptr) 912 p = sc->sc_rdma; 913 else if (sc->sc_cdma != NULL && sc->sc_cdma->addr == ptr) 914 p = sc->sc_cdma; 915 else 916 return; 917 918 auich_freemem(sc, p); 919 free(p, pool, 0); 920 } 921 922 size_t 923 auich_round_buffersize(void *v, int direction, size_t size) 924 { 925 if (size > AUICH_DMALIST_MAX * AUICH_DMASEG_MAX) 926 size = AUICH_DMALIST_MAX * AUICH_DMASEG_MAX; 927 928 return size; 929 } 930 931 int 932 auich_get_props(void *v) 933 { 934 return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 935 } 936 937 int 938 auich_intr(void *v) 939 { 940 struct auich_softc *sc = v; 941 int ret = 0, sts, gsts; 942 943 mtx_enter(&audio_lock); 944 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 945 DPRINTF(AUICH_DEBUG_INTR, ("auich_intr: gsts=%b\n", gsts, AUICH_GSTS_BITS)); 946 947 if (gsts & AUICH_POINT) { 948 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 949 AUICH_PCMO + sc->sc_sts_reg); 950 DPRINTF(AUICH_DEBUG_INTR, 951 ("auich_intr: osts=%b\n", sts, AUICH_ISTS_BITS)); 952 953 #ifdef AUICH_DEBUG 954 if (sts & AUICH_FIFOE) { 955 printf("%s: in fifo underrun # %u civ=%u ctrl=0x%x sts=%b\n", 956 sc->sc_dev.dv_xname, sc->pcmo_fifoe++, 957 bus_space_read_1(sc->iot, sc->aud_ioh, 958 AUICH_PCMO + AUICH_CIV), 959 bus_space_read_1(sc->iot, sc->aud_ioh, 960 AUICH_PCMO + AUICH_CTRL), 961 bus_space_read_2(sc->iot, sc->aud_ioh, 962 AUICH_PCMO + sc->sc_sts_reg), 963 AUICH_ISTS_BITS); 964 } 965 #endif 966 967 if (sts & AUICH_BCIS) 968 auich_intr_pipe(sc, AUICH_PCMO, &sc->pcmo); 969 970 /* int ack */ 971 bus_space_write_2(sc->iot, sc->aud_ioh, 972 AUICH_PCMO + sc->sc_sts_reg, sts & 973 (AUICH_BCIS | AUICH_FIFOE)); 974 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_POINT); 975 ret++; 976 } 977 978 if (gsts & AUICH_PIINT) { 979 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 980 AUICH_PCMI + sc->sc_sts_reg); 981 DPRINTF(AUICH_DEBUG_INTR, 982 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 983 984 #ifdef AUICH_DEBUG 985 if (sts & AUICH_FIFOE) { 986 printf("%s: in fifo overrun # %u civ=%u ctrl=0x%x sts=%b\n", 987 sc->sc_dev.dv_xname, sc->pcmi_fifoe++, 988 bus_space_read_1(sc->iot, sc->aud_ioh, 989 AUICH_PCMI + AUICH_CIV), 990 bus_space_read_1(sc->iot, sc->aud_ioh, 991 AUICH_PCMI + AUICH_CTRL), 992 bus_space_read_2(sc->iot, sc->aud_ioh, 993 AUICH_PCMI + sc->sc_sts_reg), 994 AUICH_ISTS_BITS); 995 } 996 #endif 997 998 if (sts & AUICH_BCIS) 999 auich_intr_pipe(sc, AUICH_PCMI, &sc->pcmi); 1000 1001 /* int ack */ 1002 bus_space_write_2(sc->iot, sc->aud_ioh, 1003 AUICH_PCMI + sc->sc_sts_reg, sts & 1004 (AUICH_BCIS | AUICH_FIFOE)); 1005 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_PIINT); 1006 ret++; 1007 } 1008 1009 if (gsts & AUICH_MINT) { 1010 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1011 AUICH_MICI + sc->sc_sts_reg); 1012 DPRINTF(AUICH_DEBUG_INTR, 1013 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1014 #ifdef AUICH_DEBUG 1015 if (sts & AUICH_FIFOE) { 1016 printf("%s: in fifo overrun civ=%u ctrl=0x%x sts=%b\n", 1017 sc->sc_dev.dv_xname, 1018 bus_space_read_1(sc->iot, sc->aud_ioh, 1019 AUICH_MICI + AUICH_CIV), 1020 bus_space_read_1(sc->iot, sc->aud_ioh, 1021 AUICH_MICI + AUICH_CTRL), 1022 bus_space_read_2(sc->iot, sc->aud_ioh, 1023 AUICH_MICI + sc->sc_sts_reg), 1024 AUICH_ISTS_BITS); 1025 } 1026 #endif 1027 if (sts & AUICH_BCIS) 1028 auich_intr_pipe(sc, AUICH_MICI, &sc->mici); 1029 1030 /* int ack */ 1031 bus_space_write_2(sc->iot, sc->aud_ioh, 1032 AUICH_MICI + sc->sc_sts_reg, 1033 sts + (AUICH_BCIS | AUICH_FIFOE)); 1034 1035 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_MINT); 1036 ret++; 1037 } 1038 mtx_leave(&audio_lock); 1039 return ret; 1040 } 1041 1042 1043 void 1044 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1045 { 1046 int blksize, qptr, oqptr; 1047 struct auich_dmalist *q; 1048 1049 blksize = ring->blksize; 1050 qptr = oqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1051 1052 /* XXX remove this when no one reports problems */ 1053 if(oqptr >= AUICH_DMALIST_MAX) { 1054 printf("%s: Unexpected CIV: %d\n", sc->sc_dev.dv_xname, oqptr); 1055 qptr = oqptr = 0; 1056 } 1057 1058 do { 1059 q = &ring->dmalist[qptr]; 1060 q->base = ring->p; 1061 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1062 1063 DPRINTF(AUICH_DEBUG_INTR, 1064 ("auich_trigger_pipe: %p, %p = %x @ 0x%x qptr=%d\n", 1065 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1066 1067 ring->p += blksize; 1068 if (ring->p >= ring->end) 1069 ring->p = ring->start; 1070 1071 qptr = (qptr + 1) & AUICH_LVI_MASK; 1072 } while (qptr != oqptr); 1073 1074 ring->qptr = qptr; 1075 1076 DPRINTF(AUICH_DEBUG_DMA, 1077 ("auich_trigger_pipe: qptr=%d\n", qptr)); 1078 1079 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1080 (qptr - 1) & AUICH_LVI_MASK); 1081 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 1082 AUICH_IOCE | AUICH_FEIE | AUICH_RPBM); 1083 1084 ring->running = 1; 1085 } 1086 1087 void 1088 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1089 { 1090 int blksize, qptr, nqptr; 1091 struct auich_dmalist *q; 1092 1093 blksize = ring->blksize; 1094 qptr = ring->qptr; 1095 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1096 1097 while (qptr != nqptr) { 1098 q = &ring->dmalist[qptr]; 1099 q->base = ring->p; 1100 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1101 1102 DPRINTF(AUICH_DEBUG_INTR, 1103 ("auich_intr: %p, %p = %x @ 0x%x qptr=%d\n", 1104 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1105 1106 ring->p += blksize; 1107 if (ring->p >= ring->end) 1108 ring->p = ring->start; 1109 1110 qptr = (qptr + 1) & AUICH_LVI_MASK; 1111 if (ring->intr) 1112 ring->intr(ring->arg); 1113 else 1114 printf("auich_intr: got progress with intr==NULL\n"); 1115 1116 ring->ap += blksize; 1117 if (ring->ap >= ring->size) 1118 ring->ap = 0; 1119 } 1120 ring->qptr = qptr; 1121 1122 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1123 (qptr - 1) & AUICH_LVI_MASK); 1124 } 1125 1126 1127 int 1128 auich_trigger_output(void *v, void *start, void *end, int blksize, 1129 void (*intr)(void *), void *arg, struct audio_params *param) 1130 { 1131 struct auich_softc *sc = v; 1132 struct auich_dma *p; 1133 size_t size; 1134 #ifdef AUICH_DEBUG 1135 uint16_t sts; 1136 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1137 AUICH_PCMO + sc->sc_sts_reg); 1138 DPRINTF(AUICH_DEBUG_DMA, 1139 ("auich_trigger_output(%p, %p, %d, %p, %p, %p) sts=%b\n", 1140 start, end, blksize, intr, arg, param, sts, AUICH_ISTS_BITS)); 1141 #endif 1142 1143 if (sc->sc_pdma->addr == start) 1144 p = sc->sc_pdma; 1145 else 1146 return -1; 1147 1148 size = (size_t)((caddr_t)end - (caddr_t)start); 1149 sc->pcmo.size = size; 1150 sc->pcmo.intr = intr; 1151 sc->pcmo.arg = arg; 1152 1153 /* 1154 * The logic behind this is: 1155 * setup one buffer to play, then LVI dump out the rest 1156 * to the scatter-gather chain. 1157 */ 1158 sc->pcmo.start = p->segs->ds_addr; 1159 sc->pcmo.p = sc->pcmo.start; 1160 sc->pcmo.end = sc->pcmo.start + size; 1161 sc->pcmo.blksize = blksize; 1162 1163 mtx_enter(&audio_lock); 1164 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMO + AUICH_BDBAR, 1165 sc->sc_cddma + AUICH_PCMO_OFF(0)); 1166 auich_trigger_pipe(sc, AUICH_PCMO, &sc->pcmo); 1167 mtx_leave(&audio_lock); 1168 return 0; 1169 } 1170 1171 int 1172 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1173 void *v; 1174 void *start, *end; 1175 int blksize; 1176 void (*intr)(void *); 1177 void *arg; 1178 struct audio_params *param; 1179 { 1180 struct auich_softc *sc = v; 1181 struct auich_dma *p; 1182 size_t size; 1183 1184 #ifdef AUICH_DEBUG 1185 DPRINTF(AUICH_DEBUG_DMA, 1186 ("auich_trigger_input(%p, %p, %d, %p, %p, %p) sts=%b\n", 1187 start, end, blksize, intr, arg, param, 1188 bus_space_read_2(sc->iot, sc->aud_ioh, 1189 AUICH_PCMI + sc->sc_sts_reg), 1190 AUICH_ISTS_BITS)); 1191 #endif 1192 if (sc->sc_rdma->addr == start) 1193 p = sc->sc_rdma; 1194 else 1195 return -1; 1196 1197 size = (size_t)((caddr_t)end - (caddr_t)start); 1198 sc->pcmi.size = size; 1199 sc->pcmi.intr = intr; 1200 sc->pcmi.arg = arg; 1201 1202 /* 1203 * The logic behind this is: 1204 * setup one buffer to play, then LVI dump out the rest 1205 * to the scatter-gather chain. 1206 */ 1207 sc->pcmi.start = p->segs->ds_addr; 1208 sc->pcmi.p = sc->pcmi.start; 1209 sc->pcmi.end = sc->pcmi.start + size; 1210 sc->pcmi.blksize = blksize; 1211 mtx_enter(&audio_lock); 1212 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1213 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1214 auich_trigger_pipe(sc, AUICH_PCMI, &sc->pcmi); 1215 mtx_leave(&audio_lock); 1216 return 0; 1217 } 1218 1219 1220 int 1221 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1222 struct auich_dma *p) 1223 { 1224 int error; 1225 1226 p->size = size; 1227 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, p->segs, 1, 1228 &p->nsegs, BUS_DMA_NOWAIT); 1229 if (error) { 1230 DPRINTF(AUICH_DEBUG_DMA, 1231 ("%s: bus_dmamem_alloc failed: error %d\n", 1232 sc->sc_dev.dv_xname, error)); 1233 return error; 1234 } 1235 1236 error = bus_dmamem_map(sc->dmat, p->segs, 1, p->size, &p->addr, 1237 BUS_DMA_NOWAIT | sc->sc_dmamap_flags); 1238 if (error) { 1239 DPRINTF(AUICH_DEBUG_DMA, 1240 ("%s: bus_dmamem_map failed: error %d\n", 1241 sc->sc_dev.dv_xname, error)); 1242 goto free; 1243 } 1244 1245 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 0, 1246 BUS_DMA_NOWAIT, &p->map); 1247 if (error) { 1248 DPRINTF(AUICH_DEBUG_DMA, 1249 ("%s: bus_dmamap_create failed: error %d\n", 1250 sc->sc_dev.dv_xname, error)); 1251 goto unmap; 1252 } 1253 1254 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1255 BUS_DMA_NOWAIT); 1256 if (error) { 1257 DPRINTF(AUICH_DEBUG_DMA, 1258 ("%s: bus_dmamap_load failed: error %d\n", 1259 sc->sc_dev.dv_xname, error)); 1260 goto destroy; 1261 } 1262 return 0; 1263 1264 destroy: 1265 bus_dmamap_destroy(sc->dmat, p->map); 1266 unmap: 1267 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1268 free: 1269 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1270 return error; 1271 } 1272 1273 1274 int 1275 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1276 { 1277 bus_dmamap_unload(sc->dmat, p->map); 1278 bus_dmamap_destroy(sc->dmat, p->map); 1279 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1280 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1281 return 0; 1282 } 1283 1284 1285 1286 int 1287 auich_alloc_cdata(struct auich_softc *sc) 1288 { 1289 bus_dma_segment_t seg; 1290 int error, rseg; 1291 1292 /* 1293 * Allocate the control data structure, and create and load the 1294 * DMA map for it. 1295 */ 1296 if ((error = bus_dmamem_alloc(sc->dmat, sizeof(struct auich_cdata), 1297 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1298 printf("%s: unable to allocate control data, error = %d\n", 1299 sc->sc_dev.dv_xname, error); 1300 goto fail_0; 1301 } 1302 1303 if ((error = bus_dmamem_map(sc->dmat, &seg, 1, 1304 sizeof(struct auich_cdata), (caddr_t *) &sc->sc_cdata, 1305 sc->sc_dmamap_flags)) != 0) { 1306 printf("%s: unable to map control data, error = %d\n", 1307 sc->sc_dev.dv_xname, error); 1308 goto fail_1; 1309 } 1310 1311 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1312 sizeof(struct auich_cdata), 0, 0, &sc->sc_cddmamap)) != 0) { 1313 printf("%s: unable to create control data DMA map, " 1314 "error = %d\n", sc->sc_dev.dv_xname, error); 1315 goto fail_2; 1316 } 1317 1318 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, sc->sc_cdata, 1319 sizeof(struct auich_cdata), NULL, 0)) != 0) { 1320 printf("%s: unable tp load control data DMA map, " 1321 "error = %d\n", sc->sc_dev.dv_xname, error); 1322 goto fail_3; 1323 } 1324 1325 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1326 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1327 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1328 1329 return 0; 1330 1331 fail_3: 1332 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1333 fail_2: 1334 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1335 sizeof(struct auich_cdata)); 1336 fail_1: 1337 bus_dmamem_free(sc->dmat, &seg, rseg); 1338 fail_0: 1339 return error; 1340 } 1341 1342 int 1343 auich_resume(struct auich_softc *sc) 1344 { 1345 /* SiS 7012 needs special handling */ 1346 if (PCI_VENDOR(sc->pci_id) == PCI_VENDOR_SIS && 1347 PCI_PRODUCT(sc->pci_id) == PCI_PRODUCT_SIS_7012_ACA) { 1348 /* un-mute output */ 1349 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 1350 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 1351 ICH_SIS_CTL_UNMUTE); 1352 } 1353 1354 ac97_resume(&sc->host_if, sc->codec_if); 1355 1356 return (0); 1357 } 1358 1359 /* -------------------------------------------------------------------- */ 1360 /* Calibrate card (some boards are overclocked and need scaling) */ 1361 1362 unsigned int 1363 auich_calibrate(struct auich_softc *sc) 1364 { 1365 struct timeval t1, t2; 1366 u_int8_t civ, ociv; 1367 uint16_t sts, osts; 1368 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1369 void *temp_buffer; 1370 struct auich_dma *p; 1371 1372 ac97rate = AUICH_FIXED_RATE; 1373 /* 1374 * Grab audio from input for fixed interval and compare how 1375 * much we actually get with what we expect. Interval needs 1376 * to be sufficiently short that no interrupts are 1377 * generated. 1378 * XXX: Is this true? We don't request any interrupts, 1379 * so why should the chip issue any? 1380 */ 1381 1382 /* Setup a buffer */ 1383 bytes = 16000; 1384 temp_buffer = auich_allocm(sc, 0, bytes, M_DEVBUF, M_NOWAIT); 1385 if (temp_buffer == NULL) 1386 return (ac97rate); 1387 if (sc->sc_cdma->addr == temp_buffer) { 1388 p = sc->sc_cdma; 1389 } else { 1390 printf("auich_calibrate: bad address %p\n", temp_buffer); 1391 return (ac97rate); 1392 } 1393 1394 /* get current CIV (usually 0 after reboot) */ 1395 ociv = civ = bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CIV); 1396 sc->pcmi.dmalist[civ].base = p->map->dm_segs[0].ds_addr; 1397 sc->pcmi.dmalist[civ].len = bytes / sc->sc_sample_size; 1398 1399 1400 /* 1401 * our data format is stereo, 16 bit so each sample is 4 bytes. 1402 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1403 * we're going to start recording with interrupts disabled and measure 1404 * the time taken for one block to complete. we know the block size, 1405 * we know the time in microseconds, we calculate the sample rate: 1406 * 1407 * actual_rate [bps] = bytes / (time [s] * 4) 1408 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1409 * actual_rate [Hz] = (bytes * 250000) / time [us] 1410 */ 1411 1412 /* prepare */ 1413 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1414 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1415 /* we got only one valid sample, so set LVI to CIV 1416 * otherwise we provoke a AUICH_FIFOE FIFO error 1417 * which will confuse the chip later on. */ 1418 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_LVI, 1419 civ & AUICH_LVI_MASK); 1420 1421 /* start, but don't request any interupts */ 1422 microuptime(&t1); 1423 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CTRL, 1424 AUICH_RPBM); 1425 1426 /* XXX remove this sometime */ 1427 osts = bus_space_read_2(sc->iot, sc->aud_ioh, 1428 AUICH_PCMI + sc->sc_sts_reg); 1429 /* wait */ 1430 while(1) { 1431 microuptime(&t2); 1432 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1433 AUICH_PCMI + sc->sc_sts_reg); 1434 civ = bus_space_read_1(sc->iot, sc->aud_ioh, 1435 AUICH_PCMI + AUICH_CIV); 1436 1437 /* turn time delta into us */ 1438 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + 1439 t2.tv_usec - t1.tv_usec; 1440 1441 /* this should actually never happen because civ==lvi */ 1442 if ((civ & AUICH_LVI_MASK) != (ociv & AUICH_LVI_MASK)) { 1443 printf("%s: ac97 CIV progressed after %d us sts=%b civ=%u\n", 1444 sc->sc_dev.dv_xname, wait_us, sts, 1445 AUICH_ISTS_BITS, civ); 1446 ociv = civ; 1447 } 1448 /* normal completion */ 1449 if (sts & (AUICH_DCH | AUICH_CELV | AUICH_LVBCI)) 1450 break; 1451 /* 1452 * check for strange changes in STS - 1453 * XXX remove it when everythings fine 1454 */ 1455 if (sts != osts) { 1456 printf("%s: ac97 sts changed after %d us sts=%b civ=%u\n", 1457 sc->sc_dev.dv_xname, wait_us, sts, 1458 AUICH_ISTS_BITS, civ); 1459 osts = sts; 1460 } 1461 /* 1462 * timeout: we expect 83333 us for 48k sampling rate, 1463 * 600000 us will be enough even for 8k sampling rate 1464 */ 1465 if (wait_us > 600000) { 1466 printf("%s: ac97 link rate timed out %d us sts=%b civ=%u\n", 1467 sc->sc_dev.dv_xname, wait_us, sts, 1468 AUICH_ISTS_BITS, civ); 1469 /* reset and clean up*/ 1470 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1471 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1472 auich_freem(sc, temp_buffer, M_DEVBUF); 1473 /* return default sample rate */ 1474 return (ac97rate); 1475 } 1476 } 1477 1478 DPRINTF(AUICH_DEBUG_CODECIO, 1479 ("%s: ac97 link rate calibration took %d us sts=%b civ=%u\n", 1480 sc->sc_dev.dv_xname, wait_us, sts, AUICH_ISTS_BITS, civ)); 1481 1482 /* reset and clean up */ 1483 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1484 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1485 auich_freem(sc, temp_buffer, M_DEVBUF); 1486 1487 #ifdef AUICH_DEBUG 1488 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1489 AUICH_PCMI + sc->sc_sts_reg); 1490 civ = bus_space_read_4(sc->iot, sc->aud_ioh, 1491 AUICH_PCMI + AUICH_CIV); 1492 printf("%s: after calibration and reset sts=%b civ=%u\n", 1493 sc->sc_dev.dv_xname, sts, AUICH_ISTS_BITS, civ); 1494 #endif 1495 1496 /* now finally calculate measured samplerate */ 1497 actual_48k_rate = (bytes * 250000) / wait_us; 1498 1499 if (actual_48k_rate <= 48500) 1500 ac97rate = AUICH_FIXED_RATE; 1501 else 1502 ac97rate = actual_48k_rate; 1503 1504 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: measured ac97 link rate at %d Hz", 1505 sc->sc_dev.dv_xname, actual_48k_rate)); 1506 if (ac97rate != actual_48k_rate) 1507 DPRINTF(AUICH_DEBUG_CODECIO, (", will use %d Hz", ac97rate)); 1508 DPRINTF(AUICH_DEBUG_CODECIO, ("\n")); 1509 1510 return (ac97rate); 1511 } 1512