1 /* $OpenBSD: auich.c,v 1.95 2011/07/03 15:47:16 matthew Exp $ */ 2 3 /* 4 * Copyright (c) 2000,2001 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * AC'97 audio found on Intel 810/815/820/440MX chipsets. 31 * http://developer.intel.com/design/chipsets/datashts/290655.htm 32 * http://developer.intel.com/design/chipsets/manuals/298028.htm 33 * http://www.intel.com/design/chipsets/datashts/290714.htm 34 * http://www.intel.com/design/chipsets/datashts/290744.htm 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <sys/audioio.h> 47 #include <dev/audio_if.h> 48 #include <dev/mulaw.h> 49 #include <dev/auconv.h> 50 51 #include <machine/bus.h> 52 53 #include <dev/ic/ac97.h> 54 55 /* 12.1.10 NAMBAR - native audio mixer base address register */ 56 #define AUICH_NAMBAR 0x10 57 /* 12.1.11 NABMBAR - native audio bus mastering base address register */ 58 #define AUICH_NABMBAR 0x14 59 #define AUICH_CFG 0x41 60 #define AUICH_CFG_IOSE 0x01 61 /* ICH4/ICH5/ICH6/ICH7 native audio mixer BAR */ 62 #define AUICH_MMBAR 0x18 63 /* ICH4/ICH5/ICH6/ICH7 native bus mastering BAR */ 64 #define AUICH_MBBAR 0x1c 65 #define AUICH_S2CR 0x10000000 /* tertiary codec ready */ 66 67 /* table 12-3. native audio bus master control registers */ 68 #define AUICH_BDBAR 0x00 /* 8-byte aligned address */ 69 #define AUICH_CIV 0x04 /* 5 bits current index value */ 70 #define AUICH_LVI 0x05 /* 5 bits last valid index value */ 71 #define AUICH_LVI_MASK 0x1f 72 #define AUICH_STS 0x06 /* 16 bits status */ 73 #define AUICH_FIFOE 0x10 /* fifo error */ 74 #define AUICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */ 75 #define AUICH_LVBCI 0x04 /* r- last valid bci, wr ack */ 76 #define AUICH_CELV 0x02 /* current equals last valid */ 77 #define AUICH_DCH 0x01 /* dma halted */ 78 #define AUICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe" 79 #define AUICH_PICB 0x08 /* 16 bits */ 80 #define AUICH_PIV 0x0a /* 5 bits prefetched index value */ 81 #define AUICH_CTRL 0x0b /* control */ 82 #define AUICH_IOCE 0x10 /* int on completion enable */ 83 #define AUICH_FEIE 0x08 /* fifo error int enable */ 84 #define AUICH_LVBIE 0x04 /* last valid buf int enable */ 85 #define AUICH_RR 0x02 /* 1 - reset regs */ 86 #define AUICH_RPBM 0x01 /* 1 - run, 0 - pause */ 87 88 #define AUICH_PCMI 0x00 89 #define AUICH_PCMO 0x10 90 #define AUICH_MICI 0x20 91 92 #define AUICH_GCTRL 0x2c 93 #define AUICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */ 94 #define AUICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */ 95 #define AUICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */ 96 #define AUICH_POM16 0x000000 /* PCM out precision 16bit */ 97 #define AUICH_POM20 0x400000 /* PCM out precision 20bit */ 98 #define AUICH_PCM246_MASK 0x300000 99 #define AUICH_PCM2 0x000000 /* 2ch output */ 100 #define AUICH_PCM4 0x100000 /* 4ch output */ 101 #define AUICH_PCM6 0x200000 /* 6ch output */ 102 #define AUICH_SIS_PCM246_MASK 0x0000c0 /* SiS 7012 */ 103 #define AUICH_SIS_PCM2 0x000000 /* SiS 7012 2ch output */ 104 #define AUICH_SIS_PCM4 0x000040 /* SiS 7012 4ch output */ 105 #define AUICH_SIS_PCM6 0x000080 /* SiS 7012 6ch output */ 106 #define AUICH_S2RIE 0x40 /* int when tertiary codec resume */ 107 #define AUICH_SRIE 0x20 /* int when 2ndary codec resume */ 108 #define AUICH_PRIE 0x10 /* int when primary codec resume */ 109 #define AUICH_ACLSO 0x08 /* aclink shut off */ 110 #define AUICH_WRESET 0x04 /* warm reset */ 111 #define AUICH_CRESET 0x02 /* cold reset */ 112 #define AUICH_GIE 0x01 /* gpi int enable */ 113 #define AUICH_GSTS 0x30 114 #define AUICH_MD3 0x20000 /* pwr-dn semaphore for modem */ 115 #define AUICH_AD3 0x10000 /* pwr-dn semaphore for audio */ 116 #define AUICH_RCS 0x08000 /* read completion status */ 117 #define AUICH_B3S12 0x04000 /* bit 3 of slot 12 */ 118 #define AUICH_B2S12 0x02000 /* bit 2 of slot 12 */ 119 #define AUICH_B1S12 0x01000 /* bit 1 of slot 12 */ 120 #define AUICH_SRI 0x00800 /* secondary resume int */ 121 #define AUICH_PRI 0x00400 /* primary resume int */ 122 #define AUICH_SCR 0x00200 /* secondary codec ready */ 123 #define AUICH_PCR 0x00100 /* primary codec ready */ 124 #define AUICH_MINT 0x00080 /* mic in int */ 125 #define AUICH_POINT 0x00040 /* pcm out int */ 126 #define AUICH_PIINT 0x00020 /* pcm in int */ 127 #define AUICH_MOINT 0x00004 /* modem out int */ 128 #define AUICH_MIINT 0x00002 /* modem in int */ 129 #define AUICH_GSCI 0x00001 /* gpi status change */ 130 #define AUICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3" 131 #define AUICH_CAS 0x34 /* 1/8 bit */ 132 #define AUICH_SEMATIMO 1000 /* us */ 133 #define AUICH_RESETIMO 500000 /* us */ 134 135 #define ICH_SIS_NV_CTL 0x4c /* some SiS/NVIDIA register. From Linux */ 136 #define ICH_SIS_CTL_UNMUTE 0x01 /* un-mute the output */ 137 138 /* 139 * There are 32 buffer descriptors. Each can reference up to 2^16 16-bit 140 * samples. 141 */ 142 #define AUICH_DMALIST_MAX 32 143 #define AUICH_DMASEG_MAX (65536*2) 144 struct auich_dmalist { 145 u_int32_t base; 146 u_int32_t len; 147 #define AUICH_DMAF_IOC 0x80000000 /* 1-int on complete */ 148 #define AUICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 149 }; 150 151 #define AUICH_FIXED_RATE 48000 152 153 struct auich_dma { 154 bus_dmamap_t map; 155 caddr_t addr; 156 bus_dma_segment_t segs[1]; 157 int nsegs; 158 size_t size; 159 }; 160 161 struct auich_cdata { 162 struct auich_dmalist ic_dmalist_pcmo[AUICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_pcmi[AUICH_DMALIST_MAX]; 164 struct auich_dmalist ic_dmalist_mici[AUICH_DMALIST_MAX]; 165 }; 166 167 #define AUICH_CDOFF(x) offsetof(struct auich_cdata, x) 168 #define AUICH_PCMO_OFF(x) AUICH_CDOFF(ic_dmalist_pcmo[(x)]) 169 #define AUICH_PCMI_OFF(x) AUICH_CDOFF(ic_dmalist_pcmi[(x)]) 170 #define AUICH_MICI_OFF(x) AUICH_CDOFF(ic_dmalist_mici[(x)]) 171 172 struct auich_softc { 173 struct device sc_dev; 174 void *sc_ih; 175 176 audio_device_t sc_audev; 177 struct device *audiodev; 178 179 pcireg_t pci_id; 180 bus_space_tag_t iot; 181 bus_space_tag_t iot_mix; 182 bus_space_handle_t mix_ioh; 183 bus_space_handle_t aud_ioh; 184 bus_dma_tag_t dmat; 185 186 struct ac97_codec_if *codec_if; 187 struct ac97_host_if host_if; 188 int sc_spdif; 189 190 /* dma scatter-gather buffer lists */ 191 192 bus_dmamap_t sc_cddmamap; 193 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 194 195 struct auich_cdata *sc_cdata; 196 197 struct auich_ring { 198 int qptr; 199 struct auich_dmalist *dmalist; 200 201 uint32_t start, p, end; 202 int blksize; 203 204 void (*intr)(void *); 205 void *arg; 206 int running; 207 size_t size; 208 uint32_t ap; 209 } pcmo, pcmi, mici; 210 211 struct auich_dma *sc_pdma; /* play */ 212 struct auich_dma *sc_rdma; /* record */ 213 struct auich_dma *sc_cdma; /* calibrate */ 214 215 #ifdef AUICH_DEBUG 216 int pcmi_fifoe; 217 int pcmo_fifoe; 218 #endif 219 220 int suspend; 221 u_int16_t ext_ctrl; 222 int sc_sample_size; 223 int sc_sts_reg; 224 int sc_dmamap_flags; 225 int sc_ignore_codecready; 226 int flags; 227 int sc_ac97rate; 228 229 /* multi-channel control bits */ 230 int sc_pcm246_mask; 231 int sc_pcm2; 232 int sc_pcm4; 233 int sc_pcm6; 234 235 u_int last_rrate; 236 u_int last_prate; 237 u_int last_pchan; 238 }; 239 240 #ifdef AUICH_DEBUG 241 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 242 int auich_debug = 0x0002; 243 #define AUICH_DEBUG_CODECIO 0x0001 244 #define AUICH_DEBUG_DMA 0x0002 245 #define AUICH_DEBUG_INTR 0x0004 246 #else 247 #define DPRINTF(x,y) /* nothing */ 248 #endif 249 250 struct cfdriver auich_cd = { 251 NULL, "auich", DV_DULL 252 }; 253 254 int auich_match(struct device *, void *, void *); 255 void auich_attach(struct device *, struct device *, void *); 256 int auich_intr(void *); 257 258 int auich_activate(struct device *, int); 259 260 struct cfattach auich_ca = { 261 sizeof(struct auich_softc), auich_match, auich_attach, 262 NULL, auich_activate 263 }; 264 265 static const struct auich_devtype { 266 int vendor; 267 int product; 268 int options; 269 char name[8]; 270 } auich_devices[] = { 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_ACA, 0, "ESB" }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_ACA, 0, "ESB2" }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 0, "ICH" }, 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 0, "ICH0" }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 0, "ICH2" }, 276 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_ACA, 0, "ICH3" }, 277 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ACA, 0, "ICH4" }, 278 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_ACA, 0, "ICH5" }, 279 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_ACA, 0, "ICH6" }, 280 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_ACA, 0, "ICH7" }, 281 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 0, "440MX" }, 282 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_ACA, 0, "SiS7012" }, 283 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_ACA, 0, "nForce" }, 284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_ACA, 0, "nForce2" }, 285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_ACA, 286 0, "nForce2" }, 287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_ACA, 0, "nForce3" }, 288 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_ACA, 289 0, "nForce3" }, 290 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_AC, 0, "nForce4" }, 291 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_AC97, 0, "MCP04" }, 292 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_ACA, 0, "MCP51" }, 293 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_ACA, 0, "AMD768" }, 294 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_8111_ACA, 0, "AMD8111" }, 295 }; 296 297 int auich_open(void *, int); 298 void auich_close(void *); 299 int auich_query_encoding(void *, struct audio_encoding *); 300 int auich_set_params(void *, int, int, struct audio_params *, 301 struct audio_params *); 302 int auich_round_blocksize(void *, int); 303 void auich_halt_pipe(struct auich_softc *, int, struct auich_ring *); 304 int auich_halt_output(void *); 305 int auich_halt_input(void *); 306 int auich_getdev(void *, struct audio_device *); 307 int auich_set_port(void *, mixer_ctrl_t *); 308 int auich_get_port(void *, mixer_ctrl_t *); 309 int auich_query_devinfo(void *, mixer_devinfo_t *); 310 void *auich_allocm(void *, int, size_t, int, int); 311 void auich_freem(void *, void *, int); 312 size_t auich_round_buffersize(void *, int, size_t); 313 paddr_t auich_mappage(void *, void *, off_t, int); 314 int auich_get_props(void *); 315 void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 316 void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 317 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 318 void *, struct audio_params *); 319 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 320 void *, struct audio_params *); 321 int auich_alloc_cdata(struct auich_softc *); 322 int auich_allocmem(struct auich_softc *, size_t, size_t, struct auich_dma *); 323 int auich_freemem(struct auich_softc *, struct auich_dma *); 324 void auich_get_default_params(void *, int, struct audio_params *); 325 326 int auich_resume(struct auich_softc *); 327 328 struct audio_hw_if auich_hw_if = { 329 auich_open, 330 auich_close, 331 NULL, /* drain */ 332 auich_query_encoding, 333 auich_set_params, 334 auich_round_blocksize, 335 NULL, /* commit_setting */ 336 NULL, /* init_output */ 337 NULL, /* init_input */ 338 NULL, /* start_output */ 339 NULL, /* start_input */ 340 auich_halt_output, 341 auich_halt_input, 342 NULL, /* speaker_ctl */ 343 auich_getdev, 344 NULL, /* getfd */ 345 auich_set_port, 346 auich_get_port, 347 auich_query_devinfo, 348 auich_allocm, 349 auich_freem, 350 auich_round_buffersize, 351 auich_mappage, 352 auich_get_props, 353 auich_trigger_output, 354 auich_trigger_input, 355 auich_get_default_params 356 }; 357 358 int auich_attach_codec(void *, struct ac97_codec_if *); 359 int auich_read_codec(void *, u_int8_t, u_int16_t *); 360 int auich_write_codec(void *, u_int8_t, u_int16_t); 361 void auich_reset_codec(void *); 362 enum ac97_host_flags auich_flags_codec(void *); 363 unsigned int auich_calibrate(struct auich_softc *); 364 void auich_spdif_event(void *, int); 365 366 int 367 auich_match(parent, match, aux) 368 struct device *parent; 369 void *match; 370 void *aux; 371 { 372 struct pci_attach_args *pa = aux; 373 int i; 374 375 for (i = nitems(auich_devices); i--;) 376 if (PCI_VENDOR(pa->pa_id) == auich_devices[i].vendor && 377 PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 378 return 1; 379 380 return 0; 381 } 382 383 void 384 auich_attach(parent, self, aux) 385 struct device *parent, *self; 386 void *aux; 387 { 388 struct auich_softc *sc = (struct auich_softc *)self; 389 struct pci_attach_args *pa = aux; 390 pci_intr_handle_t ih; 391 bus_size_t mix_size, aud_size; 392 pcireg_t csr; 393 const char *intrstr; 394 u_int32_t status; 395 int i; 396 397 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 398 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 399 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 400 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 401 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 402 /* 403 * Use native mode for ICH4/ICH5/ICH6/ICH7 404 */ 405 if (pci_mapreg_map(pa, AUICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 406 &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 407 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 408 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 409 csr | AUICH_CFG_IOSE); 410 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 411 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 412 printf(": can't map codec mem/io space\n"); 413 return; 414 } 415 } 416 417 if (pci_mapreg_map(pa, AUICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 418 &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 419 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 420 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 421 csr | AUICH_CFG_IOSE); 422 if (pci_mapreg_map(pa, AUICH_NABMBAR, 423 PCI_MAPREG_TYPE_IO, 0, &sc->iot, 424 &sc->aud_ioh, NULL, &aud_size, 0)) { 425 printf(": can't map device mem/io space\n"); 426 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 427 return; 428 } 429 } 430 } else { 431 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 432 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 433 printf(": can't map codec i/o space\n"); 434 return; 435 } 436 437 if (pci_mapreg_map(pa, AUICH_NABMBAR, PCI_MAPREG_TYPE_IO, 438 0, &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 439 printf(": can't map device i/o space\n"); 440 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 441 return; 442 } 443 } 444 sc->dmat = pa->pa_dmat; 445 sc->pci_id = pa->pa_id; 446 447 if (pci_intr_map(pa, &ih)) { 448 printf(": can't map interrupt\n"); 449 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 450 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 451 return; 452 } 453 intrstr = pci_intr_string(pa->pa_pc, ih); 454 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, auich_intr, 455 sc, sc->sc_dev.dv_xname); 456 if (!sc->sc_ih) { 457 printf(": can't establish interrupt"); 458 if (intrstr) 459 printf(" at %s", intrstr); 460 printf("\n"); 461 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 462 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 463 return; 464 } 465 466 for (i = nitems(auich_devices); i--;) 467 if (PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 468 break; 469 470 snprintf(sc->sc_audev.name, sizeof sc->sc_audev.name, "%s AC97", 471 auich_devices[i].name); 472 snprintf(sc->sc_audev.version, sizeof sc->sc_audev.version, "0x%02x", 473 PCI_REVISION(pa->pa_class)); 474 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, 475 sizeof sc->sc_audev.config); 476 477 printf(": %s, %s\n", intrstr, sc->sc_audev.name); 478 479 /* SiS 7012 needs special handling */ 480 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 481 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_7012_ACA) { 482 sc->sc_sts_reg = AUICH_PICB; 483 sc->sc_sample_size = 1; 484 sc->sc_pcm246_mask = AUICH_SIS_PCM246_MASK; 485 sc->sc_pcm2 = AUICH_SIS_PCM2; 486 sc->sc_pcm4 = AUICH_SIS_PCM4; 487 sc->sc_pcm6 = AUICH_SIS_PCM6; 488 /* un-mute output */ 489 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 490 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 491 ICH_SIS_CTL_UNMUTE); 492 } else { 493 sc->sc_sts_reg = AUICH_STS; 494 sc->sc_sample_size = 2; 495 sc->sc_pcm246_mask = AUICH_PCM246_MASK; 496 sc->sc_pcm2 = AUICH_PCM2; 497 sc->sc_pcm4 = AUICH_PCM4; 498 sc->sc_pcm6 = AUICH_PCM6; 499 } 500 501 /* Workaround for a 440MX B-stepping erratum */ 502 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 503 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 504 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_ACA) { 505 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 506 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 507 } 508 509 /* Set up DMA lists. */ 510 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 511 auich_alloc_cdata(sc); 512 513 DPRINTF(AUICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 514 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 515 516 /* Reset codec and AC'97 */ 517 auich_reset_codec(sc); 518 status = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 519 if (!(status & AUICH_PCR)) { /* reset failure */ 520 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 521 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 522 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 523 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 524 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 525 /* MSI 845G Max never return AUICH_PCR */ 526 sc->sc_ignore_codecready = 1; 527 } else { 528 printf("%s: reset failed!\n", sc->sc_dev.dv_xname); 529 return; 530 } 531 } 532 533 sc->host_if.arg = sc; 534 sc->host_if.attach = auich_attach_codec; 535 sc->host_if.read = auich_read_codec; 536 sc->host_if.write = auich_write_codec; 537 sc->host_if.reset = auich_reset_codec; 538 sc->host_if.flags = auich_flags_codec; 539 sc->host_if.spdif_event = auich_spdif_event; 540 if (sc->sc_dev.dv_cfdata->cf_flags & 0x0001) 541 sc->flags = AC97_HOST_SWAPPED_CHANNELS; 542 543 if (ac97_attach(&sc->host_if) != 0) { 544 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 545 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 546 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 547 return; 548 } 549 sc->codec_if->vtbl->unlock(sc->codec_if); 550 551 sc->audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 552 553 /* Watch for power changes */ 554 sc->suspend = DVACT_RESUME; 555 556 sc->sc_ac97rate = -1; 557 } 558 559 int 560 auich_activate(struct device *self, int act) 561 { 562 struct auich_softc *sc = (struct auich_softc *)self; 563 int rv = 0; 564 565 switch (act) { 566 case DVACT_QUIESCE: 567 rv = config_activate_children(self, act); 568 break; 569 case DVACT_SUSPEND: 570 break; 571 case DVACT_RESUME: 572 auich_resume(sc); 573 rv = config_activate_children(self, act); 574 break; 575 case DVACT_DEACTIVATE: 576 if (sc->audiodev != NULL) 577 rv = config_deactivate(sc->audiodev); 578 break; 579 } 580 return (rv); 581 } 582 583 int 584 auich_read_codec(v, reg, val) 585 void *v; 586 u_int8_t reg; 587 u_int16_t *val; 588 { 589 struct auich_softc *sc = v; 590 int i; 591 592 /* wait for an access semaphore */ 593 for (i = AUICH_SEMATIMO; i-- && 594 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 595 596 if (!sc->sc_ignore_codecready && i < 0) { 597 DPRINTF(AUICH_DEBUG_CODECIO, 598 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 599 return (-1); 600 } 601 602 *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg); 603 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: read_codec(%x, %x)\n", 604 sc->sc_dev.dv_xname, reg, *val)); 605 return (0); 606 } 607 608 int 609 auich_write_codec(v, reg, val) 610 void *v; 611 u_int8_t reg; 612 u_int16_t val; 613 { 614 struct auich_softc *sc = v; 615 int i; 616 617 /* wait for an access semaphore */ 618 for (i = AUICH_SEMATIMO; i-- && 619 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 620 621 if (sc->sc_ignore_codecready || i >= 0) { 622 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: write_codec(%x, %x)\n", 623 sc->sc_dev.dv_xname, reg, val)); 624 bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val); 625 return (0); 626 } else { 627 DPRINTF(AUICH_DEBUG_CODECIO, 628 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 629 return (-1); 630 } 631 } 632 633 int 634 auich_attach_codec(v, cif) 635 void *v; 636 struct ac97_codec_if *cif; 637 { 638 struct auich_softc *sc = v; 639 640 sc->codec_if = cif; 641 return 0; 642 } 643 644 void 645 auich_reset_codec(v) 646 void *v; 647 { 648 struct auich_softc *sc = v; 649 u_int32_t control; 650 int i; 651 652 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 653 control &= ~(AUICH_ACLSO | sc->sc_pcm246_mask); 654 control |= (control & AUICH_CRESET) ? AUICH_WRESET : AUICH_CRESET; 655 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 656 657 for (i = AUICH_RESETIMO; i-- && 658 !(bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS) & AUICH_PCR); 659 DELAY(1)); 660 661 if (i < 0) 662 DPRINTF(AUICH_DEBUG_CODECIO, 663 ("%s: reset_codec timeout\n", sc->sc_dev.dv_xname)); 664 } 665 666 enum ac97_host_flags 667 auich_flags_codec(void *v) 668 { 669 struct auich_softc *sc = v; 670 671 return (sc->flags); 672 } 673 674 void 675 auich_spdif_event(void *v, int flag) 676 { 677 struct auich_softc *sc = v; 678 sc->sc_spdif = flag; 679 } 680 681 int 682 auich_open(v, flags) 683 void *v; 684 int flags; 685 { 686 struct auich_softc *sc = v; 687 688 if (sc->sc_ac97rate == -1) 689 sc->sc_ac97rate = auich_calibrate(sc); 690 691 sc->codec_if->vtbl->lock(sc->codec_if); 692 693 return 0; 694 } 695 696 void 697 auich_close(v) 698 void *v; 699 { 700 struct auich_softc *sc = v; 701 702 sc->codec_if->vtbl->unlock(sc->codec_if); 703 } 704 705 void 706 auich_get_default_params(void *addr, int mode, struct audio_params *params) 707 { 708 ac97_get_default_params(params); 709 } 710 711 int 712 auich_query_encoding(v, aep) 713 void *v; 714 struct audio_encoding *aep; 715 { 716 struct auich_softc *sc = v; 717 if (sc->sc_spdif) { 718 switch (aep->index) { 719 case 0: 720 strlcpy(aep->name, AudioEslinear_le, sizeof aep->name); 721 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 722 aep->precision = 16; 723 aep->flags = 0; 724 aep->bps = 2; 725 aep->msb = 1; 726 return (0); 727 default: 728 return (EINVAL); 729 } 730 } else { 731 switch (aep->index) { 732 case 0: 733 strlcpy(aep->name, AudioEulinear, sizeof aep->name); 734 aep->encoding = AUDIO_ENCODING_ULINEAR; 735 aep->precision = 8; 736 aep->flags = 0; 737 break; 738 case 1: 739 strlcpy(aep->name, AudioEmulaw, sizeof aep->name); 740 aep->encoding = AUDIO_ENCODING_ULAW; 741 aep->precision = 8; 742 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 743 break; 744 case 2: 745 strlcpy(aep->name, AudioEalaw, sizeof aep->name); 746 aep->encoding = AUDIO_ENCODING_ALAW; 747 aep->precision = 8; 748 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 749 break; 750 case 3: 751 strlcpy(aep->name, AudioEslinear, sizeof aep->name); 752 aep->encoding = AUDIO_ENCODING_SLINEAR; 753 aep->precision = 8; 754 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 755 break; 756 case 4: 757 strlcpy(aep->name, AudioEslinear_le, sizeof aep->name); 758 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 759 aep->precision = 16; 760 aep->flags = 0; 761 break; 762 case 5: 763 strlcpy(aep->name, AudioEulinear_le, sizeof aep->name); 764 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 765 aep->precision = 16; 766 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 767 break; 768 case 6: 769 strlcpy(aep->name, AudioEslinear_be, sizeof aep->name); 770 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 771 aep->precision = 16; 772 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 773 break; 774 case 7: 775 strlcpy(aep->name, AudioEulinear_be, sizeof aep->name); 776 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 777 aep->precision = 16; 778 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 779 break; 780 default: 781 return (EINVAL); 782 } 783 aep->bps = AUDIO_BPS(aep->precision); 784 aep->msb = 1; 785 return (0); 786 } 787 } 788 789 int 790 auich_set_params(v, setmode, usemode, play, rec) 791 void *v; 792 int setmode, usemode; 793 struct audio_params *play, *rec; 794 { 795 struct auich_softc *sc = v; 796 struct ac97_codec_if *codec = sc->codec_if; 797 int error; 798 u_int orate; 799 u_int adj_rate; 800 u_int32_t control; 801 u_int16_t ext_id; 802 803 if (setmode & AUMODE_PLAY) { 804 /* only 16-bit 48kHz slinear_le if s/pdif enabled */ 805 if (sc->sc_spdif) { 806 play->sample_rate = 48000; 807 play->precision = 16; 808 play->encoding = AUDIO_ENCODING_SLINEAR_LE; 809 } 810 } 811 if (setmode & AUMODE_PLAY) { 812 play->factor = 1; 813 play->sw_code = NULL; 814 if (play->precision > 16) 815 play->precision = 16; 816 switch(play->encoding) { 817 case AUDIO_ENCODING_ULAW: 818 if (play->channels > 2) 819 play->channels = 2; 820 switch (play->channels) { 821 case 1: 822 play->factor = 4; 823 play->sw_code = mulaw_to_slinear16_le_mts; 824 break; 825 case 2: 826 play->factor = 2; 827 play->sw_code = mulaw_to_slinear16_le; 828 break; 829 default: 830 return (EINVAL); 831 } 832 break; 833 case AUDIO_ENCODING_SLINEAR_LE: 834 switch (play->precision) { 835 case 8: 836 if (play->channels > 2) 837 play->channels = 2; 838 switch (play->channels) { 839 case 1: 840 play->factor = 4; 841 play->sw_code = linear8_to_linear16_le_mts; 842 break; 843 case 2: 844 play->factor = 2; 845 play->sw_code = linear8_to_linear16_le; 846 break; 847 default: 848 return (EINVAL); 849 } 850 break; 851 case 16: 852 if (play->channels > 6) 853 play->channels = 6; 854 if (play->channels > 1) 855 play->channels &= ~1; 856 switch (play->channels) { 857 case 1: 858 play->factor = 2; 859 play->sw_code = noswap_bytes_mts; 860 break; 861 case 2: 862 break; 863 case 4: 864 ext_id = codec->vtbl->get_caps(codec); 865 if (!(ext_id & AC97_EXT_AUDIO_SDAC)) 866 play->channels = 2; 867 break; 868 case 6: 869 ext_id = codec->vtbl->get_caps(codec); 870 if ((ext_id & AC97_BITS_6CH) != 871 AC97_BITS_6CH) 872 play->channels = 2; 873 break; 874 default: 875 return (EINVAL); 876 } 877 break; 878 } 879 break; 880 case AUDIO_ENCODING_ULINEAR_LE: 881 if (play->channels > 2) 882 play->channels = 2; 883 switch (play->precision) { 884 case 8: 885 switch (play->channels) { 886 case 1: 887 play->factor = 4; 888 play->sw_code = ulinear8_to_linear16_le_mts; 889 break; 890 case 2: 891 play->factor = 2; 892 play->sw_code = ulinear8_to_linear16_le; 893 break; 894 default: 895 return (EINVAL); 896 } 897 break; 898 case 16: 899 switch (play->channels) { 900 case 1: 901 play->factor = 2; 902 play->sw_code = change_sign16_le_mts; 903 break; 904 case 2: 905 play->sw_code = change_sign16_le; 906 break; 907 default: 908 return (EINVAL); 909 } 910 break; 911 default: 912 return (EINVAL); 913 } 914 break; 915 case AUDIO_ENCODING_ALAW: 916 if (play->channels > 2) 917 play->channels = 2; 918 switch (play->channels) { 919 case 1: 920 play->factor = 4; 921 play->sw_code = alaw_to_slinear16_le_mts; 922 break; 923 case 2: 924 play->factor = 2; 925 play->sw_code = alaw_to_slinear16_le; 926 break; 927 default: 928 return (EINVAL); 929 } 930 break; 931 case AUDIO_ENCODING_SLINEAR_BE: 932 if (play->channels > 2) 933 play->channels = 2; 934 switch (play->precision) { 935 case 8: 936 switch (play->channels) { 937 case 1: 938 play->factor = 4; 939 play->sw_code = linear8_to_linear16_le_mts; 940 break; 941 case 2: 942 play->factor = 2; 943 play->sw_code = linear8_to_linear16_le; 944 break; 945 default: 946 return (EINVAL); 947 } 948 break; 949 case 16: 950 switch (play->channels) { 951 case 1: 952 play->factor = 2; 953 play->sw_code = swap_bytes_mts; 954 break; 955 case 2: 956 play->sw_code = swap_bytes; 957 break; 958 default: 959 return (EINVAL); 960 } 961 break; 962 default: 963 return (EINVAL); 964 } 965 break; 966 case AUDIO_ENCODING_ULINEAR_BE: 967 if (play->channels > 2) 968 play->channels = 2; 969 switch (play->precision) { 970 case 8: 971 switch (play->channels) { 972 case 1: 973 play->factor = 4; 974 play->sw_code = ulinear8_to_linear16_le_mts; 975 break; 976 case 2: 977 play->factor = 2; 978 play->sw_code = ulinear8_to_linear16_le; 979 break; 980 default: 981 return (EINVAL); 982 } 983 break; 984 case 16: 985 switch (play->channels) { 986 case 1: 987 play->factor = 2; 988 play->sw_code = swap_bytes_change_sign16_le_mts; 989 break; 990 case 2: 991 play->sw_code = swap_bytes_change_sign16_le; 992 break; 993 default: 994 return (EINVAL); 995 } 996 break; 997 default: 998 return (EINVAL); 999 } 1000 break; 1001 default: 1002 return (EINVAL); 1003 } 1004 play->bps = AUDIO_BPS(play->precision); 1005 play->msb = 1; 1006 1007 orate = adj_rate = play->sample_rate; 1008 if (sc->sc_ac97rate != 0) 1009 adj_rate = orate * AUICH_FIXED_RATE / sc->sc_ac97rate; 1010 1011 play->sample_rate = adj_rate; 1012 sc->last_prate = play->sample_rate; 1013 1014 error = ac97_set_rate(sc->codec_if, 1015 AC97_REG_PCM_LFE_DAC_RATE, &play->sample_rate); 1016 if (error) 1017 return (error); 1018 1019 play->sample_rate = adj_rate; 1020 error = ac97_set_rate(sc->codec_if, 1021 AC97_REG_PCM_SURR_DAC_RATE, &play->sample_rate); 1022 if (error) 1023 return (error); 1024 1025 play->sample_rate = adj_rate; 1026 error = ac97_set_rate(sc->codec_if, 1027 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate); 1028 if (error) 1029 return (error); 1030 1031 if (play->sample_rate == adj_rate) 1032 play->sample_rate = orate; 1033 1034 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 1035 control &= ~(sc->sc_pcm246_mask); 1036 if (play->channels == 4) 1037 control |= sc->sc_pcm4; 1038 else if (play->channels == 6) 1039 control |= sc->sc_pcm6; 1040 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 1041 1042 sc->last_pchan = play->channels; 1043 } 1044 1045 if (setmode & AUMODE_RECORD) { 1046 rec->factor = 1; 1047 rec->sw_code = 0; 1048 if (rec->channels > 2) 1049 rec->channels = 2; 1050 if (rec->precision > 16) 1051 rec->precision = 16; 1052 switch(rec->encoding) { 1053 case AUDIO_ENCODING_ULAW: 1054 switch (rec->channels) { 1055 case 1: 1056 rec->sw_code = slinear16_to_mulaw_le_stm; 1057 rec->factor = 4; 1058 break; 1059 case 2: 1060 rec->sw_code = slinear16_to_mulaw_le; 1061 rec->factor = 2; 1062 break; 1063 } 1064 break; 1065 case AUDIO_ENCODING_ALAW: 1066 switch (rec->channels) { 1067 case 1: 1068 rec->sw_code = slinear16_to_alaw_le_stm; 1069 rec->factor = 4; 1070 break; 1071 case 2: 1072 rec->sw_code = slinear16_to_alaw_le; 1073 rec->factor = 2; 1074 break; 1075 } 1076 break; 1077 case AUDIO_ENCODING_SLINEAR_LE: 1078 switch (rec->precision) { 1079 case 8: 1080 switch (rec->channels) { 1081 case 1: 1082 rec->sw_code = linear16_to_linear8_le_stm; 1083 rec->factor = 4; 1084 break; 1085 case 2: 1086 rec->sw_code = linear16_to_linear8_le; 1087 rec->factor = 2; 1088 break; 1089 } 1090 break; 1091 case 16: 1092 switch (rec->channels) { 1093 case 1: 1094 rec->sw_code = linear16_decimator; 1095 rec->factor = 2; 1096 break; 1097 case 2: 1098 break; 1099 } 1100 break; 1101 default: 1102 return (EINVAL); 1103 } 1104 break; 1105 case AUDIO_ENCODING_ULINEAR_LE: 1106 switch (rec->precision) { 1107 case 8: 1108 switch (rec->channels) { 1109 case 1: 1110 rec->sw_code = linear16_to_ulinear8_le_stm; 1111 rec->factor = 4; 1112 break; 1113 case 2: 1114 rec->sw_code = linear16_to_ulinear8_le; 1115 rec->factor = 2; 1116 break; 1117 } 1118 break; 1119 case 16: 1120 switch (rec->channels) { 1121 case 1: 1122 rec->sw_code = change_sign16_le_stm; 1123 rec->factor = 2; 1124 break; 1125 case 2: 1126 rec->sw_code = change_sign16_le; 1127 break; 1128 } 1129 break; 1130 default: 1131 return (EINVAL); 1132 } 1133 break; 1134 case AUDIO_ENCODING_SLINEAR_BE: 1135 switch (rec->precision) { 1136 case 8: 1137 switch (rec->channels) { 1138 case 1: 1139 rec->sw_code = linear16_to_linear8_le_stm; 1140 rec->factor = 4; 1141 break; 1142 case 2: 1143 rec->sw_code = linear16_to_linear8_le; 1144 rec->factor = 2; 1145 break; 1146 } 1147 break; 1148 case 16: 1149 switch (rec->channels) { 1150 case 1: 1151 rec->sw_code = swap_bytes_stm; 1152 rec->factor = 2; 1153 break; 1154 case 2: 1155 rec->sw_code = swap_bytes; 1156 break; 1157 } 1158 break; 1159 default: 1160 return (EINVAL); 1161 } 1162 break; 1163 case AUDIO_ENCODING_ULINEAR_BE: 1164 switch (rec->precision) { 1165 case 8: 1166 switch (rec->channels) { 1167 case 1: 1168 rec->sw_code = linear16_to_ulinear8_le_stm; 1169 rec->factor = 4; 1170 break; 1171 case 2: 1172 rec->sw_code = linear16_to_ulinear8_le; 1173 rec->factor = 2; 1174 break; 1175 } 1176 break; 1177 case 16: 1178 switch (rec->channels) { 1179 case 1: 1180 rec->sw_code = change_sign16_swap_bytes_le_stm; 1181 rec->factor = 2; 1182 break; 1183 case 2: 1184 rec->sw_code = change_sign16_swap_bytes_le; 1185 break; 1186 } 1187 break; 1188 default: 1189 return (EINVAL); 1190 } 1191 break; 1192 default: 1193 return (EINVAL); 1194 } 1195 rec->bps = AUDIO_BPS(rec->precision); 1196 rec->msb = 1; 1197 1198 orate = rec->sample_rate; 1199 if (sc->sc_ac97rate != 0) 1200 rec->sample_rate = orate * AUICH_FIXED_RATE / 1201 sc->sc_ac97rate; 1202 sc->last_rrate = rec->sample_rate; 1203 error = ac97_set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1204 &rec->sample_rate); 1205 if (error) 1206 return (error); 1207 rec->sample_rate = orate; 1208 } 1209 1210 return (0); 1211 } 1212 1213 int 1214 auich_round_blocksize(v, blk) 1215 void *v; 1216 int blk; 1217 { 1218 return (blk + 0x3f) & ~0x3f; 1219 } 1220 1221 1222 void 1223 auich_halt_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1224 { 1225 int i; 1226 uint32_t sts; 1227 1228 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 0); 1229 1230 /* wait for DMA halted and clear interrupt / event bits if needed */ 1231 for (i = 0; i < 1000; i++) { 1232 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1233 pipe + sc->sc_sts_reg); 1234 if (sts & (AUICH_CELV | AUICH_LVBCI | AUICH_BCIS | AUICH_FIFOE)) 1235 bus_space_write_2(sc->iot, sc->aud_ioh, 1236 pipe + sc->sc_sts_reg, 1237 AUICH_CELV | AUICH_LVBCI | 1238 AUICH_BCIS | AUICH_FIFOE); 1239 if (sts & AUICH_DCH) 1240 break; 1241 DELAY(100); 1242 } 1243 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, AUICH_RR); 1244 1245 if (i > 0) 1246 DPRINTF(AUICH_DEBUG_DMA, 1247 ("auich_halt_pipe: halt took %d cycles\n", i)); 1248 1249 ring->running = 0; 1250 } 1251 1252 1253 int 1254 auich_halt_output(v) 1255 void *v; 1256 { 1257 struct auich_softc *sc = v; 1258 1259 DPRINTF(AUICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1260 1261 auich_halt_pipe(sc, AUICH_PCMO, &sc->pcmo); 1262 1263 sc->pcmo.intr = NULL; 1264 1265 return 0; 1266 } 1267 1268 int 1269 auich_halt_input(v) 1270 void *v; 1271 { 1272 struct auich_softc *sc = v; 1273 1274 DPRINTF(AUICH_DEBUG_DMA, 1275 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1276 1277 /* XXX halt both unless known otherwise */ 1278 1279 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1280 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1281 1282 sc->pcmi.intr = NULL; 1283 1284 return 0; 1285 } 1286 1287 int 1288 auich_getdev(v, adp) 1289 void *v; 1290 struct audio_device *adp; 1291 { 1292 struct auich_softc *sc = v; 1293 *adp = sc->sc_audev; 1294 return 0; 1295 } 1296 1297 int 1298 auich_set_port(v, cp) 1299 void *v; 1300 mixer_ctrl_t *cp; 1301 { 1302 struct auich_softc *sc = v; 1303 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1304 } 1305 1306 int 1307 auich_get_port(v, cp) 1308 void *v; 1309 mixer_ctrl_t *cp; 1310 { 1311 struct auich_softc *sc = v; 1312 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1313 } 1314 1315 int 1316 auich_query_devinfo(v, dp) 1317 void *v; 1318 mixer_devinfo_t *dp; 1319 { 1320 struct auich_softc *sc = v; 1321 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1322 } 1323 1324 void * 1325 auich_allocm(v, direction, size, pool, flags) 1326 void *v; 1327 int direction; 1328 size_t size; 1329 int pool, flags; 1330 { 1331 struct auich_softc *sc = v; 1332 struct auich_dma *p; 1333 int error; 1334 1335 /* can only use 1 segment */ 1336 if (size > AUICH_DMASEG_MAX) { 1337 DPRINTF(AUICH_DEBUG_DMA, 1338 ("%s: requested buffer size too large: %d", \ 1339 sc->sc_dev.dv_xname, size)); 1340 return NULL; 1341 } 1342 1343 p = malloc(sizeof(*p), pool, flags | M_ZERO); 1344 if (!p) 1345 return NULL; 1346 1347 error = auich_allocmem(sc, size, PAGE_SIZE, p); 1348 if (error) { 1349 free(p, pool); 1350 return NULL; 1351 } 1352 1353 if (direction == AUMODE_PLAY) 1354 sc->sc_pdma = p; 1355 else if (direction == AUMODE_RECORD) 1356 sc->sc_rdma = p; 1357 else 1358 sc->sc_cdma = p; 1359 1360 return p->addr; 1361 } 1362 1363 void 1364 auich_freem(void *v, void *ptr, int pool) 1365 { 1366 struct auich_softc *sc; 1367 struct auich_dma *p; 1368 1369 sc = v; 1370 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == ptr) 1371 p = sc->sc_pdma; 1372 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == ptr) 1373 p = sc->sc_rdma; 1374 else if (sc->sc_cdma != NULL && sc->sc_cdma->addr == ptr) 1375 p = sc->sc_cdma; 1376 else 1377 return; 1378 1379 auich_freemem(sc, p); 1380 free(p, pool); 1381 } 1382 1383 size_t 1384 auich_round_buffersize(v, direction, size) 1385 void *v; 1386 int direction; 1387 size_t size; 1388 { 1389 if (size > AUICH_DMALIST_MAX * AUICH_DMASEG_MAX) 1390 size = AUICH_DMALIST_MAX * AUICH_DMASEG_MAX; 1391 1392 return size; 1393 } 1394 1395 paddr_t 1396 auich_mappage(v, mem, off, prot) 1397 void *v; 1398 void *mem; 1399 off_t off; 1400 int prot; 1401 { 1402 struct auich_softc *sc = v; 1403 struct auich_dma *p; 1404 1405 if (off < 0) 1406 return -1; 1407 1408 p = NULL; 1409 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == mem) 1410 p = sc->sc_pdma; 1411 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == mem) 1412 p = sc->sc_rdma; 1413 else 1414 return -1; 1415 1416 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1417 off, prot, BUS_DMA_WAITOK); 1418 } 1419 1420 int 1421 auich_get_props(v) 1422 void *v; 1423 { 1424 return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1425 } 1426 1427 int 1428 auich_intr(v) 1429 void *v; 1430 { 1431 struct auich_softc *sc = v; 1432 int ret = 0, sts, gsts; 1433 1434 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 1435 DPRINTF(AUICH_DEBUG_INTR, ("auich_intr: gsts=%b\n", gsts, AUICH_GSTS_BITS)); 1436 1437 if (gsts & AUICH_POINT) { 1438 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1439 AUICH_PCMO + sc->sc_sts_reg); 1440 DPRINTF(AUICH_DEBUG_INTR, 1441 ("auich_intr: osts=%b\n", sts, AUICH_ISTS_BITS)); 1442 1443 #ifdef AUICH_DEBUG 1444 if (sts & AUICH_FIFOE) { 1445 printf("%s: in fifo underrun # %u civ=%u ctrl=0x%x sts=%b\n", 1446 sc->sc_dev.dv_xname, sc->pcmo_fifoe++, 1447 bus_space_read_1(sc->iot, sc->aud_ioh, 1448 AUICH_PCMO + AUICH_CIV), 1449 bus_space_read_1(sc->iot, sc->aud_ioh, 1450 AUICH_PCMO + AUICH_CTRL), 1451 bus_space_read_2(sc->iot, sc->aud_ioh, 1452 AUICH_PCMO + sc->sc_sts_reg), 1453 AUICH_ISTS_BITS); 1454 } 1455 #endif 1456 1457 if (sts & AUICH_BCIS) 1458 auich_intr_pipe(sc, AUICH_PCMO, &sc->pcmo); 1459 1460 /* int ack */ 1461 bus_space_write_2(sc->iot, sc->aud_ioh, 1462 AUICH_PCMO + sc->sc_sts_reg, sts & 1463 (AUICH_BCIS | AUICH_FIFOE)); 1464 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_POINT); 1465 ret++; 1466 } 1467 1468 if (gsts & AUICH_PIINT) { 1469 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1470 AUICH_PCMI + sc->sc_sts_reg); 1471 DPRINTF(AUICH_DEBUG_INTR, 1472 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1473 1474 #ifdef AUICH_DEBUG 1475 if (sts & AUICH_FIFOE) { 1476 printf("%s: in fifo overrun civ=%u ctrl=0x%x sts=%b\n", 1477 sc->sc_dev.dv_xname, sc->pcmi_fifoe++, 1478 bus_space_read_1(sc->iot, sc->aud_ioh, 1479 AUICH_PCMI + AUICH_CIV), 1480 bus_space_read_1(sc->iot, sc->aud_ioh, 1481 AUICH_PCMI + AUICH_CTRL), 1482 bus_space_read_2(sc->iot, sc->aud_ioh, 1483 AUICH_PCMI + sc->sc_sts_reg), 1484 AUICH_ISTS_BITS); 1485 } 1486 #endif 1487 1488 if (sts & AUICH_BCIS) 1489 auich_intr_pipe(sc, AUICH_PCMI, &sc->pcmi); 1490 1491 /* int ack */ 1492 bus_space_write_2(sc->iot, sc->aud_ioh, 1493 AUICH_PCMI + sc->sc_sts_reg, sts & 1494 (AUICH_BCIS | AUICH_FIFOE)); 1495 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_PIINT); 1496 ret++; 1497 } 1498 1499 if (gsts & AUICH_MINT) { 1500 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1501 AUICH_MICI + sc->sc_sts_reg); 1502 DPRINTF(AUICH_DEBUG_INTR, 1503 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1504 #ifdef AUICH_DEBUG 1505 if (sts & AUICH_FIFOE) { 1506 printf("%s: in fifo overrun # %u civ=%u ctrl=0x%x sts=%b\n", 1507 sc->sc_dev.dv_xname, 1508 bus_space_read_1(sc->iot, sc->aud_ioh, 1509 AUICH_MICI + AUICH_CIV), 1510 bus_space_read_1(sc->iot, sc->aud_ioh, 1511 AUICH_MICI + AUICH_CTRL), 1512 bus_space_read_2(sc->iot, sc->aud_ioh, 1513 AUICH_MICI + sc->sc_sts_reg), 1514 AUICH_ISTS_BITS); 1515 } 1516 #endif 1517 if (sts & AUICH_BCIS) 1518 auich_intr_pipe(sc, AUICH_MICI, &sc->mici); 1519 1520 /* int ack */ 1521 bus_space_write_2(sc->iot, sc->aud_ioh, 1522 AUICH_MICI + sc->sc_sts_reg, 1523 sts + (AUICH_BCIS | AUICH_FIFOE)); 1524 1525 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_MINT); 1526 ret++; 1527 } 1528 1529 return ret; 1530 } 1531 1532 1533 void 1534 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1535 { 1536 int blksize, qptr, oqptr; 1537 struct auich_dmalist *q; 1538 1539 blksize = ring->blksize; 1540 qptr = oqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1541 1542 /* XXX remove this when no one reports problems */ 1543 if(oqptr >= AUICH_DMALIST_MAX) { 1544 printf("%s: Unexpected CIV: %d\n", sc->sc_dev.dv_xname, oqptr); 1545 qptr = oqptr = 0; 1546 } 1547 1548 do { 1549 q = &ring->dmalist[qptr]; 1550 q->base = ring->p; 1551 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1552 1553 DPRINTF(AUICH_DEBUG_INTR, 1554 ("auich_trigger_pipe: %p, %p = %x @ 0x%x qptr=%d\n", 1555 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1556 1557 ring->p += blksize; 1558 if (ring->p >= ring->end) 1559 ring->p = ring->start; 1560 1561 qptr = (qptr + 1) & AUICH_LVI_MASK; 1562 } while (qptr != oqptr); 1563 1564 ring->qptr = qptr; 1565 1566 DPRINTF(AUICH_DEBUG_DMA, 1567 ("auich_trigger_pipe: qptr=%d\n", qptr)); 1568 1569 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1570 (qptr - 1) & AUICH_LVI_MASK); 1571 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 1572 AUICH_IOCE | AUICH_FEIE | AUICH_RPBM); 1573 1574 ring->running = 1; 1575 } 1576 1577 void 1578 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1579 { 1580 int blksize, qptr, nqptr; 1581 struct auich_dmalist *q; 1582 1583 blksize = ring->blksize; 1584 qptr = ring->qptr; 1585 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1586 1587 while (qptr != nqptr) { 1588 q = &ring->dmalist[qptr]; 1589 q->base = ring->p; 1590 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1591 1592 DPRINTF(AUICH_DEBUG_INTR, 1593 ("auich_intr: %p, %p = %x @ 0x%x qptr=%d\n", 1594 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1595 1596 ring->p += blksize; 1597 if (ring->p >= ring->end) 1598 ring->p = ring->start; 1599 1600 qptr = (qptr + 1) & AUICH_LVI_MASK; 1601 if (ring->intr) 1602 ring->intr(ring->arg); 1603 else 1604 printf("auich_intr: got progress with intr==NULL\n"); 1605 1606 ring->ap += blksize; 1607 if (ring->ap >= ring->size) 1608 ring->ap = 0; 1609 } 1610 ring->qptr = qptr; 1611 1612 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1613 (qptr - 1) & AUICH_LVI_MASK); 1614 } 1615 1616 1617 int 1618 auich_trigger_output(v, start, end, blksize, intr, arg, param) 1619 void *v; 1620 void *start, *end; 1621 int blksize; 1622 void (*intr)(void *); 1623 void *arg; 1624 struct audio_params *param; 1625 { 1626 struct auich_softc *sc = v; 1627 struct auich_dma *p; 1628 size_t size; 1629 #ifdef AUICH_DEBUG 1630 uint16_t sts; 1631 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1632 AUICH_PCMO + sc->sc_sts_reg); 1633 DPRINTF(AUICH_DEBUG_DMA, 1634 ("auich_trigger_output(%x, %x, %d, %p, %p, %p) sts=%b\n", 1635 start, end, blksize, intr, arg, param, sts, AUICH_ISTS_BITS)); 1636 #endif 1637 1638 if (sc->sc_pdma->addr == start) 1639 p = sc->sc_pdma; 1640 else 1641 return -1; 1642 1643 size = (size_t)((caddr_t)end - (caddr_t)start); 1644 sc->pcmo.size = size; 1645 sc->pcmo.intr = intr; 1646 sc->pcmo.arg = arg; 1647 1648 /* 1649 * The logic behind this is: 1650 * setup one buffer to play, then LVI dump out the rest 1651 * to the scatter-gather chain. 1652 */ 1653 sc->pcmo.start = p->segs->ds_addr; 1654 sc->pcmo.p = sc->pcmo.start; 1655 sc->pcmo.end = sc->pcmo.start + size; 1656 sc->pcmo.blksize = blksize; 1657 1658 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMO + AUICH_BDBAR, 1659 sc->sc_cddma + AUICH_PCMO_OFF(0)); 1660 auich_trigger_pipe(sc, AUICH_PCMO, &sc->pcmo); 1661 1662 return 0; 1663 } 1664 1665 int 1666 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1667 void *v; 1668 void *start, *end; 1669 int blksize; 1670 void (*intr)(void *); 1671 void *arg; 1672 struct audio_params *param; 1673 { 1674 struct auich_softc *sc = v; 1675 struct auich_dma *p; 1676 size_t size; 1677 1678 #ifdef AUICH_DEBUG 1679 DPRINTF(AUICH_DEBUG_DMA, 1680 ("auich_trigger_input(%x, %x, %d, %p, %p, %p) sts=%b\n", 1681 start, end, blksize, intr, arg, param, 1682 bus_space_read_2(sc->iot, sc->aud_ioh, 1683 AUICH_PCMI + sc->sc_sts_reg), 1684 AUICH_ISTS_BITS)); 1685 #endif 1686 if (sc->sc_rdma->addr == start) 1687 p = sc->sc_rdma; 1688 else 1689 return -1; 1690 1691 size = (size_t)((caddr_t)end - (caddr_t)start); 1692 sc->pcmi.size = size; 1693 sc->pcmi.intr = intr; 1694 sc->pcmi.arg = arg; 1695 1696 /* 1697 * The logic behind this is: 1698 * setup one buffer to play, then LVI dump out the rest 1699 * to the scatter-gather chain. 1700 */ 1701 sc->pcmi.start = p->segs->ds_addr; 1702 sc->pcmi.p = sc->pcmi.start; 1703 sc->pcmi.end = sc->pcmi.start + size; 1704 sc->pcmi.blksize = blksize; 1705 1706 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1707 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1708 auich_trigger_pipe(sc, AUICH_PCMI, &sc->pcmi); 1709 1710 return 0; 1711 } 1712 1713 1714 int 1715 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1716 struct auich_dma *p) 1717 { 1718 int error; 1719 1720 p->size = size; 1721 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, p->segs, 1, 1722 &p->nsegs, BUS_DMA_NOWAIT); 1723 if (error) { 1724 DPRINTF(AUICH_DEBUG_DMA, 1725 ("%s: bus_dmamem_alloc failed: error %d\n", 1726 sc->sc_dev.dv_xname, error)); 1727 return error; 1728 } 1729 1730 error = bus_dmamem_map(sc->dmat, p->segs, 1, p->size, &p->addr, 1731 BUS_DMA_NOWAIT | sc->sc_dmamap_flags); 1732 if (error) { 1733 DPRINTF(AUICH_DEBUG_DMA, 1734 ("%s: bus_dmamem_map failed: error %d\n", 1735 sc->sc_dev.dv_xname, error)); 1736 goto free; 1737 } 1738 1739 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 0, 1740 BUS_DMA_NOWAIT, &p->map); 1741 if (error) { 1742 DPRINTF(AUICH_DEBUG_DMA, 1743 ("%s: bus_dmamap_create failed: error %d\n", 1744 sc->sc_dev.dv_xname, error)); 1745 goto unmap; 1746 } 1747 1748 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1749 BUS_DMA_NOWAIT); 1750 if (error) { 1751 DPRINTF(AUICH_DEBUG_DMA, 1752 ("%s: bus_dmamap_load failed: error %d\n", 1753 sc->sc_dev.dv_xname, error)); 1754 goto destroy; 1755 } 1756 return 0; 1757 1758 destroy: 1759 bus_dmamap_destroy(sc->dmat, p->map); 1760 unmap: 1761 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1762 free: 1763 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1764 return error; 1765 } 1766 1767 1768 int 1769 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1770 { 1771 bus_dmamap_unload(sc->dmat, p->map); 1772 bus_dmamap_destroy(sc->dmat, p->map); 1773 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1774 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1775 return 0; 1776 } 1777 1778 1779 1780 int 1781 auich_alloc_cdata(struct auich_softc *sc) 1782 { 1783 bus_dma_segment_t seg; 1784 int error, rseg; 1785 1786 /* 1787 * Allocate the control data structure, and create and load the 1788 * DMA map for it. 1789 */ 1790 if ((error = bus_dmamem_alloc(sc->dmat, sizeof(struct auich_cdata), 1791 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1792 printf("%s: unable to allocate control data, error = %d\n", 1793 sc->sc_dev.dv_xname, error); 1794 goto fail_0; 1795 } 1796 1797 if ((error = bus_dmamem_map(sc->dmat, &seg, 1, 1798 sizeof(struct auich_cdata), (caddr_t *) &sc->sc_cdata, 1799 sc->sc_dmamap_flags)) != 0) { 1800 printf("%s: unable to map control data, error = %d\n", 1801 sc->sc_dev.dv_xname, error); 1802 goto fail_1; 1803 } 1804 1805 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1806 sizeof(struct auich_cdata), 0, 0, &sc->sc_cddmamap)) != 0) { 1807 printf("%s: unable to create control data DMA map, " 1808 "error = %d\n", sc->sc_dev.dv_xname, error); 1809 goto fail_2; 1810 } 1811 1812 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, sc->sc_cdata, 1813 sizeof(struct auich_cdata), NULL, 0)) != 0) { 1814 printf("%s: unable tp load control data DMA map, " 1815 "error = %d\n", sc->sc_dev.dv_xname, error); 1816 goto fail_3; 1817 } 1818 1819 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1820 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1821 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1822 1823 return 0; 1824 1825 fail_3: 1826 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1827 fail_2: 1828 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1829 sizeof(struct auich_cdata)); 1830 fail_1: 1831 bus_dmamem_free(sc->dmat, &seg, rseg); 1832 fail_0: 1833 return error; 1834 } 1835 1836 int 1837 auich_resume(struct auich_softc *sc) 1838 { 1839 /* SiS 7012 needs special handling */ 1840 if (PCI_VENDOR(sc->pci_id) == PCI_VENDOR_SIS && 1841 PCI_PRODUCT(sc->pci_id) == PCI_PRODUCT_SIS_7012_ACA) { 1842 /* un-mute output */ 1843 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 1844 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 1845 ICH_SIS_CTL_UNMUTE); 1846 } 1847 1848 ac97_resume(&sc->host_if, sc->codec_if); 1849 1850 return (0); 1851 } 1852 1853 /* -------------------------------------------------------------------- */ 1854 /* Calibrate card (some boards are overclocked and need scaling) */ 1855 1856 unsigned int 1857 auich_calibrate(struct auich_softc *sc) 1858 { 1859 struct timeval t1, t2; 1860 u_int8_t civ, ociv; 1861 uint16_t sts, osts; 1862 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1863 void *temp_buffer; 1864 struct auich_dma *p; 1865 1866 ac97rate = AUICH_FIXED_RATE; 1867 /* 1868 * Grab audio from input for fixed interval and compare how 1869 * much we actually get with what we expect. Interval needs 1870 * to be sufficiently short that no interrupts are 1871 * generated. 1872 * XXX: Is this true? We don't request any interrupts, 1873 * so why should the chip issue any? 1874 */ 1875 1876 /* Setup a buffer */ 1877 bytes = 16000; 1878 temp_buffer = auich_allocm(sc, 0, bytes, M_DEVBUF, M_NOWAIT); 1879 if (temp_buffer == NULL) 1880 return (ac97rate); 1881 if (sc->sc_cdma->addr == temp_buffer) { 1882 p = sc->sc_cdma; 1883 } else { 1884 printf("auich_calibrate: bad address %p\n", temp_buffer); 1885 return (ac97rate); 1886 } 1887 1888 /* get current CIV (usually 0 after reboot) */ 1889 ociv = civ = bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CIV); 1890 sc->pcmi.dmalist[civ].base = p->map->dm_segs[0].ds_addr; 1891 sc->pcmi.dmalist[civ].len = bytes / sc->sc_sample_size; 1892 1893 1894 /* 1895 * our data format is stereo, 16 bit so each sample is 4 bytes. 1896 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1897 * we're going to start recording with interrupts disabled and measure 1898 * the time taken for one block to complete. we know the block size, 1899 * we know the time in microseconds, we calculate the sample rate: 1900 * 1901 * actual_rate [bps] = bytes / (time [s] * 4) 1902 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1903 * actual_rate [Hz] = (bytes * 250000) / time [us] 1904 */ 1905 1906 /* prepare */ 1907 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1908 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1909 /* we got only one valid sample, so set LVI to CIV 1910 * otherwise we provoke a AUICH_FIFOE FIFO error 1911 * which will confuse the chip later on. */ 1912 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_LVI, 1913 civ & AUICH_LVI_MASK); 1914 1915 /* start, but don't request any interupts */ 1916 microuptime(&t1); 1917 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CTRL, 1918 AUICH_RPBM); 1919 1920 /* XXX remove this sometime */ 1921 osts = bus_space_read_2(sc->iot, sc->aud_ioh, 1922 AUICH_PCMI + sc->sc_sts_reg); 1923 /* wait */ 1924 while(1) { 1925 microuptime(&t2); 1926 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1927 AUICH_PCMI + sc->sc_sts_reg); 1928 civ = bus_space_read_1(sc->iot, sc->aud_ioh, 1929 AUICH_PCMI + AUICH_CIV); 1930 1931 /* turn time delta into us */ 1932 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + 1933 t2.tv_usec - t1.tv_usec; 1934 1935 /* this should actually never happen because civ==lvi */ 1936 if ((civ & AUICH_LVI_MASK) != (ociv & AUICH_LVI_MASK)) { 1937 printf("%s: ac97 CIV progressed after %d us sts=%b civ=%u\n", 1938 sc->sc_dev.dv_xname, wait_us, sts, 1939 AUICH_ISTS_BITS, civ); 1940 ociv = civ; 1941 } 1942 /* normal completion */ 1943 if (sts & (AUICH_DCH | AUICH_CELV | AUICH_LVBCI)) 1944 break; 1945 /* 1946 * check for strange changes in STS - 1947 * XXX remove it when everythings fine 1948 */ 1949 if (sts != osts) { 1950 printf("%s: ac97 sts changed after %d us sts=%b civ=%u\n", 1951 sc->sc_dev.dv_xname, wait_us, sts, 1952 AUICH_ISTS_BITS, civ); 1953 osts = sts; 1954 } 1955 /* 1956 * timeout: we expect 83333 us for 48k sampling rate, 1957 * 600000 us will be enough even for 8k sampling rate 1958 */ 1959 if (wait_us > 600000) { 1960 printf("%s: ac97 link rate timed out %d us sts=%b civ=%u\n", 1961 sc->sc_dev.dv_xname, wait_us, sts, 1962 AUICH_ISTS_BITS, civ); 1963 /* reset and clean up*/ 1964 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1965 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1966 auich_freem(sc, temp_buffer, M_DEVBUF); 1967 /* return default sample rate */ 1968 return (ac97rate); 1969 } 1970 } 1971 1972 DPRINTF(AUICH_DEBUG_CODECIO, 1973 ("%s: ac97 link rate calibration took %d us sts=%b civ=%u\n", 1974 sc->sc_dev.dv_xname, wait_us, sts, AUICH_ISTS_BITS, civ)); 1975 1976 /* reset and clean up */ 1977 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1978 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1979 auich_freem(sc, temp_buffer, M_DEVBUF); 1980 1981 #ifdef AUICH_DEBUG 1982 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1983 AUICH_PCMI + sc->sc_sts_reg); 1984 civ = bus_space_read_4(sc->iot, sc->aud_ioh, 1985 AUICH_PCMI + AUICH_CIV); 1986 printf("%s: after calibration and reset sts=%b civ=%u\n", 1987 sc->sc_dev.dv_xname, sts, AUICH_ISTS_BITS, civ); 1988 #endif 1989 1990 /* now finally calculate measured samplerate */ 1991 actual_48k_rate = (bytes * 250000) / wait_us; 1992 1993 if (actual_48k_rate <= 48500) 1994 ac97rate = AUICH_FIXED_RATE; 1995 else 1996 ac97rate = actual_48k_rate; 1997 1998 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: measured ac97 link rate at %d Hz", 1999 sc->sc_dev.dv_xname, actual_48k_rate)); 2000 if (ac97rate != actual_48k_rate) 2001 DPRINTF(AUICH_DEBUG_CODECIO, (", will use %d Hz", ac97rate)); 2002 DPRINTF(AUICH_DEBUG_CODECIO, ("\n")); 2003 2004 return (ac97rate); 2005 } 2006