1 /* $OpenBSD: auich.c,v 1.112 2019/08/22 09:47:29 miko Exp $ */ 2 3 /* 4 * Copyright (c) 2000,2001 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * AC'97 audio found on Intel 810/815/820/440MX chipsets. 31 * http://developer.intel.com/design/chipsets/datashts/290655.htm 32 * http://developer.intel.com/design/chipsets/manuals/298028.htm 33 * http://www.intel.com/design/chipsets/datashts/290714.htm 34 * http://www.intel.com/design/chipsets/datashts/290744.htm 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/device.h> 41 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pcivar.h> 44 45 #include <sys/audioio.h> 46 #include <dev/audio_if.h> 47 48 #include <machine/bus.h> 49 50 #include <dev/ic/ac97.h> 51 52 /* 12.1.10 NAMBAR - native audio mixer base address register */ 53 #define AUICH_NAMBAR 0x10 54 /* 12.1.11 NABMBAR - native audio bus mastering base address register */ 55 #define AUICH_NABMBAR 0x14 56 #define AUICH_CFG 0x41 57 #define AUICH_CFG_IOSE 0x01 58 /* ICH4/ICH5/ICH6/ICH7 native audio mixer BAR */ 59 #define AUICH_MMBAR 0x18 60 /* ICH4/ICH5/ICH6/ICH7 native bus mastering BAR */ 61 #define AUICH_MBBAR 0x1c 62 #define AUICH_S2CR 0x10000000 /* tertiary codec ready */ 63 64 /* table 12-3. native audio bus master control registers */ 65 #define AUICH_BDBAR 0x00 /* 8-byte aligned address */ 66 #define AUICH_CIV 0x04 /* 5 bits current index value */ 67 #define AUICH_LVI 0x05 /* 5 bits last valid index value */ 68 #define AUICH_LVI_MASK 0x1f 69 #define AUICH_STS 0x06 /* 16 bits status */ 70 #define AUICH_FIFOE 0x10 /* fifo error */ 71 #define AUICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */ 72 #define AUICH_LVBCI 0x04 /* r- last valid bci, wr ack */ 73 #define AUICH_CELV 0x02 /* current equals last valid */ 74 #define AUICH_DCH 0x01 /* dma halted */ 75 #define AUICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe" 76 #define AUICH_PICB 0x08 /* 16 bits */ 77 #define AUICH_PIV 0x0a /* 5 bits prefetched index value */ 78 #define AUICH_CTRL 0x0b /* control */ 79 #define AUICH_IOCE 0x10 /* int on completion enable */ 80 #define AUICH_FEIE 0x08 /* fifo error int enable */ 81 #define AUICH_LVBIE 0x04 /* last valid buf int enable */ 82 #define AUICH_RR 0x02 /* 1 - reset regs */ 83 #define AUICH_RPBM 0x01 /* 1 - run, 0 - pause */ 84 85 #define AUICH_PCMI 0x00 86 #define AUICH_PCMO 0x10 87 #define AUICH_MICI 0x20 88 89 #define AUICH_GCTRL 0x2c 90 #define AUICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */ 91 #define AUICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */ 92 #define AUICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */ 93 #define AUICH_POM16 0x000000 /* PCM out precision 16bit */ 94 #define AUICH_POM20 0x400000 /* PCM out precision 20bit */ 95 #define AUICH_PCM246_MASK 0x300000 96 #define AUICH_PCM2 0x000000 /* 2ch output */ 97 #define AUICH_PCM4 0x100000 /* 4ch output */ 98 #define AUICH_PCM6 0x200000 /* 6ch output */ 99 #define AUICH_SIS_PCM246_MASK 0x0000c0 /* SiS 7012 */ 100 #define AUICH_SIS_PCM2 0x000000 /* SiS 7012 2ch output */ 101 #define AUICH_SIS_PCM4 0x000040 /* SiS 7012 4ch output */ 102 #define AUICH_SIS_PCM6 0x000080 /* SiS 7012 6ch output */ 103 #define AUICH_S2RIE 0x40 /* int when tertiary codec resume */ 104 #define AUICH_SRIE 0x20 /* int when 2ndary codec resume */ 105 #define AUICH_PRIE 0x10 /* int when primary codec resume */ 106 #define AUICH_ACLSO 0x08 /* aclink shut off */ 107 #define AUICH_WRESET 0x04 /* warm reset */ 108 #define AUICH_CRESET 0x02 /* cold reset */ 109 #define AUICH_GIE 0x01 /* gpi int enable */ 110 #define AUICH_GSTS 0x30 111 #define AUICH_MD3 0x20000 /* pwr-dn semaphore for modem */ 112 #define AUICH_AD3 0x10000 /* pwr-dn semaphore for audio */ 113 #define AUICH_RCS 0x08000 /* read completion status */ 114 #define AUICH_B3S12 0x04000 /* bit 3 of slot 12 */ 115 #define AUICH_B2S12 0x02000 /* bit 2 of slot 12 */ 116 #define AUICH_B1S12 0x01000 /* bit 1 of slot 12 */ 117 #define AUICH_SRI 0x00800 /* secondary resume int */ 118 #define AUICH_PRI 0x00400 /* primary resume int */ 119 #define AUICH_SCR 0x00200 /* secondary codec ready */ 120 #define AUICH_PCR 0x00100 /* primary codec ready */ 121 #define AUICH_MINT 0x00080 /* mic in int */ 122 #define AUICH_POINT 0x00040 /* pcm out int */ 123 #define AUICH_PIINT 0x00020 /* pcm in int */ 124 #define AUICH_MOINT 0x00004 /* modem out int */ 125 #define AUICH_MIINT 0x00002 /* modem in int */ 126 #define AUICH_GSCI 0x00001 /* gpi status change */ 127 #define AUICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3" 128 #define AUICH_CAS 0x34 /* 1/8 bit */ 129 #define AUICH_SEMATIMO 1000 /* us */ 130 #define AUICH_RESETIMO 500000 /* us */ 131 132 #define ICH_SIS_NV_CTL 0x4c /* some SiS/NVIDIA register. From Linux */ 133 #define ICH_SIS_CTL_UNMUTE 0x01 /* un-mute the output */ 134 135 /* 136 * There are 32 buffer descriptors. Each can reference up to 2^16 16-bit 137 * samples. 138 */ 139 #define AUICH_DMALIST_MAX 32 140 #define AUICH_DMASEG_MAX (65536*2) 141 struct auich_dmalist { 142 u_int32_t base; 143 u_int32_t len; 144 #define AUICH_DMAF_IOC 0x80000000 /* 1-int on complete */ 145 #define AUICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 146 }; 147 148 #define AUICH_FIXED_RATE 48000 149 150 struct auich_dma { 151 bus_dmamap_t map; 152 caddr_t addr; 153 bus_dma_segment_t segs[1]; 154 int nsegs; 155 size_t size; 156 }; 157 158 struct auich_cdata { 159 struct auich_dmalist ic_dmalist_pcmo[AUICH_DMALIST_MAX]; 160 struct auich_dmalist ic_dmalist_pcmi[AUICH_DMALIST_MAX]; 161 struct auich_dmalist ic_dmalist_mici[AUICH_DMALIST_MAX]; 162 }; 163 164 #define AUICH_CDOFF(x) offsetof(struct auich_cdata, x) 165 #define AUICH_PCMO_OFF(x) AUICH_CDOFF(ic_dmalist_pcmo[(x)]) 166 #define AUICH_PCMI_OFF(x) AUICH_CDOFF(ic_dmalist_pcmi[(x)]) 167 #define AUICH_MICI_OFF(x) AUICH_CDOFF(ic_dmalist_mici[(x)]) 168 169 struct auich_softc { 170 struct device sc_dev; 171 void *sc_ih; 172 173 pcireg_t pci_id; 174 bus_space_tag_t iot; 175 bus_space_tag_t iot_mix; 176 bus_space_handle_t mix_ioh; 177 bus_space_handle_t aud_ioh; 178 bus_dma_tag_t dmat; 179 180 struct ac97_codec_if *codec_if; 181 struct ac97_host_if host_if; 182 int sc_spdif; 183 184 /* dma scatter-gather buffer lists */ 185 186 bus_dmamap_t sc_cddmamap; 187 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 188 189 struct auich_cdata *sc_cdata; 190 191 struct auich_ring { 192 int qptr; 193 struct auich_dmalist *dmalist; 194 195 uint32_t start, p, end; 196 int blksize; 197 198 void (*intr)(void *); 199 void *arg; 200 int running; 201 size_t size; 202 uint32_t ap; 203 } pcmo, pcmi, mici; 204 205 struct auich_dma *sc_pdma; /* play */ 206 struct auich_dma *sc_rdma; /* record */ 207 struct auich_dma *sc_cdma; /* calibrate */ 208 209 #ifdef AUICH_DEBUG 210 int pcmi_fifoe; 211 int pcmo_fifoe; 212 #endif 213 214 int suspend; 215 u_int16_t ext_ctrl; 216 int sc_sample_size; 217 int sc_sts_reg; 218 int sc_dmamap_flags; 219 int sc_ignore_codecready; 220 int flags; 221 int sc_ac97rate; 222 223 /* multi-channel control bits */ 224 int sc_pcm246_mask; 225 int sc_pcm2; 226 int sc_pcm4; 227 int sc_pcm6; 228 229 u_int last_rrate; 230 u_int last_prate; 231 u_int last_pchan; 232 }; 233 234 #ifdef AUICH_DEBUG 235 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 236 int auich_debug = 0x0002; 237 #define AUICH_DEBUG_CODECIO 0x0001 238 #define AUICH_DEBUG_DMA 0x0002 239 #define AUICH_DEBUG_INTR 0x0004 240 #else 241 #define DPRINTF(x,y) /* nothing */ 242 #endif 243 244 struct cfdriver auich_cd = { 245 NULL, "auich", DV_DULL 246 }; 247 248 int auich_match(struct device *, void *, void *); 249 void auich_attach(struct device *, struct device *, void *); 250 int auich_intr(void *); 251 252 int auich_activate(struct device *, int); 253 254 struct cfattach auich_ca = { 255 sizeof(struct auich_softc), auich_match, auich_attach, 256 NULL, auich_activate 257 }; 258 259 static const struct auich_devtype { 260 int vendor; 261 int product; 262 int options; 263 char name[8]; 264 } auich_devices[] = { 265 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_ACA, 0, "ESB" }, 266 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_ACA, 0, "ESB2" }, 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 0, "ICH" }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 0, "ICH0" }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 0, "ICH2" }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_ACA, 0, "ICH3" }, 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ACA, 0, "ICH4" }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_ACA, 0, "ICH5" }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_ACA, 0, "ICH6" }, 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_ACA, 0, "ICH7" }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 0, "440MX" }, 276 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_ACA, 0, "SiS7012" }, 277 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_ACA, 0, "nForce" }, 278 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_ACA, 0, "nForce2" }, 279 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_ACA, 280 0, "nForce2" }, 281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_ACA, 0, "nForce3" }, 282 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_ACA, 283 0, "nForce3" }, 284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_AC, 0, "nForce4" }, 285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_AC97, 0, "MCP04" }, 286 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_ACA, 0, "MCP51" }, 287 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_ACA, 0, "AMD768" }, 288 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_8111_ACA, 0, "AMD8111" }, 289 }; 290 291 int auich_open(void *, int); 292 void auich_close(void *); 293 int auich_set_params(void *, int, int, struct audio_params *, 294 struct audio_params *); 295 int auich_round_blocksize(void *, int); 296 void auich_halt_pipe(struct auich_softc *, int, struct auich_ring *); 297 int auich_halt_output(void *); 298 int auich_halt_input(void *); 299 int auich_set_port(void *, mixer_ctrl_t *); 300 int auich_get_port(void *, mixer_ctrl_t *); 301 int auich_query_devinfo(void *, mixer_devinfo_t *); 302 void *auich_allocm(void *, int, size_t, int, int); 303 void auich_freem(void *, void *, int); 304 size_t auich_round_buffersize(void *, int, size_t); 305 int auich_get_props(void *); 306 void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 307 void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 308 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 309 void *, struct audio_params *); 310 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 311 void *, struct audio_params *); 312 int auich_alloc_cdata(struct auich_softc *); 313 int auich_allocmem(struct auich_softc *, size_t, size_t, struct auich_dma *); 314 void auich_freemem(struct auich_softc *, struct auich_dma *); 315 316 void auich_resume(struct auich_softc *); 317 318 struct audio_hw_if auich_hw_if = { 319 auich_open, 320 auich_close, 321 auich_set_params, 322 auich_round_blocksize, 323 NULL, /* commit_setting */ 324 NULL, /* init_output */ 325 NULL, /* init_input */ 326 NULL, /* start_output */ 327 NULL, /* start_input */ 328 auich_halt_output, 329 auich_halt_input, 330 NULL, /* speaker_ctl */ 331 NULL, /* getfd */ 332 auich_set_port, 333 auich_get_port, 334 auich_query_devinfo, 335 auich_allocm, 336 auich_freem, 337 auich_round_buffersize, 338 auich_get_props, 339 auich_trigger_output, 340 auich_trigger_input 341 }; 342 343 int auich_attach_codec(void *, struct ac97_codec_if *); 344 int auich_read_codec(void *, u_int8_t, u_int16_t *); 345 int auich_write_codec(void *, u_int8_t, u_int16_t); 346 void auich_reset_codec(void *); 347 enum ac97_host_flags auich_flags_codec(void *); 348 unsigned int auich_calibrate(struct auich_softc *); 349 void auich_spdif_event(void *, int); 350 351 int 352 auich_match(struct device *parent, void *match, void *aux) 353 { 354 struct pci_attach_args *pa = aux; 355 int i; 356 357 for (i = nitems(auich_devices); i--;) 358 if (PCI_VENDOR(pa->pa_id) == auich_devices[i].vendor && 359 PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 360 return 1; 361 362 return 0; 363 } 364 365 void 366 auich_attach(struct device *parent, struct device *self, void *aux) 367 { 368 struct auich_softc *sc = (struct auich_softc *)self; 369 struct pci_attach_args *pa = aux; 370 pci_intr_handle_t ih; 371 bus_size_t mix_size, aud_size; 372 pcireg_t csr; 373 const char *intrstr; 374 u_int32_t status; 375 int i; 376 377 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 378 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 379 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 380 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 381 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 382 /* 383 * Use native mode for ICH4/ICH5/ICH6/ICH7 384 */ 385 if (pci_mapreg_map(pa, AUICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 386 &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 387 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 388 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 389 csr | AUICH_CFG_IOSE); 390 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 391 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 392 printf(": can't map codec mem/io space\n"); 393 return; 394 } 395 } 396 397 if (pci_mapreg_map(pa, AUICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 398 &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 399 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 400 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 401 csr | AUICH_CFG_IOSE); 402 if (pci_mapreg_map(pa, AUICH_NABMBAR, 403 PCI_MAPREG_TYPE_IO, 0, &sc->iot, 404 &sc->aud_ioh, NULL, &aud_size, 0)) { 405 printf(": can't map device mem/io space\n"); 406 goto fail_unmap_mix; 407 } 408 } 409 } else { 410 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 411 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 412 printf(": can't map codec i/o space\n"); 413 return; 414 } 415 416 if (pci_mapreg_map(pa, AUICH_NABMBAR, PCI_MAPREG_TYPE_IO, 417 0, &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 418 printf(": can't map device i/o space\n"); 419 goto fail_unmap_mix; 420 } 421 } 422 sc->dmat = pa->pa_dmat; 423 sc->pci_id = pa->pa_id; 424 425 if (pci_intr_map(pa, &ih)) { 426 printf(": can't map interrupt\n"); 427 goto fail_unmap; 428 } 429 intrstr = pci_intr_string(pa->pa_pc, ih); 430 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO | IPL_MPSAFE, 431 auich_intr, sc, sc->sc_dev.dv_xname); 432 if (!sc->sc_ih) { 433 printf(": can't establish interrupt"); 434 if (intrstr) 435 printf(" at %s", intrstr); 436 printf("\n"); 437 goto fail_unmap; 438 } 439 440 for (i = nitems(auich_devices); i--;) 441 if (PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 442 break; 443 444 printf(": %s, %s\n", intrstr, auich_devices[i].name); 445 446 /* SiS 7012 needs special handling */ 447 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 448 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_7012_ACA) { 449 sc->sc_sts_reg = AUICH_PICB; 450 sc->sc_sample_size = 1; 451 sc->sc_pcm246_mask = AUICH_SIS_PCM246_MASK; 452 sc->sc_pcm2 = AUICH_SIS_PCM2; 453 sc->sc_pcm4 = AUICH_SIS_PCM4; 454 sc->sc_pcm6 = AUICH_SIS_PCM6; 455 /* un-mute output */ 456 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 457 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 458 ICH_SIS_CTL_UNMUTE); 459 } else { 460 sc->sc_sts_reg = AUICH_STS; 461 sc->sc_sample_size = 2; 462 sc->sc_pcm246_mask = AUICH_PCM246_MASK; 463 sc->sc_pcm2 = AUICH_PCM2; 464 sc->sc_pcm4 = AUICH_PCM4; 465 sc->sc_pcm6 = AUICH_PCM6; 466 } 467 468 /* Workaround for a 440MX B-stepping erratum */ 469 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 470 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 471 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_ACA) { 472 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 473 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 474 } 475 476 /* Set up DMA lists. */ 477 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 478 if (auich_alloc_cdata(sc) != 0) 479 goto fail_disestablish_intr; 480 481 DPRINTF(AUICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 482 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 483 484 /* Reset codec and AC'97 */ 485 auich_reset_codec(sc); 486 status = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 487 if (!(status & AUICH_PCR)) { /* reset failure */ 488 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 489 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 490 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 491 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 492 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 493 /* MSI 845G Max never return AUICH_PCR */ 494 sc->sc_ignore_codecready = 1; 495 } else { 496 printf("%s: reset failed!\n", sc->sc_dev.dv_xname); 497 return; 498 } 499 } 500 501 sc->host_if.arg = sc; 502 sc->host_if.attach = auich_attach_codec; 503 sc->host_if.read = auich_read_codec; 504 sc->host_if.write = auich_write_codec; 505 sc->host_if.reset = auich_reset_codec; 506 sc->host_if.flags = auich_flags_codec; 507 sc->host_if.spdif_event = auich_spdif_event; 508 if (sc->sc_dev.dv_cfdata->cf_flags & 0x0001) 509 sc->flags = AC97_HOST_SWAPPED_CHANNELS; 510 511 if (ac97_attach(&sc->host_if) != 0) 512 goto fail_disestablish_intr; 513 sc->codec_if->vtbl->unlock(sc->codec_if); 514 515 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 516 517 /* Watch for power changes */ 518 sc->suspend = DVACT_RESUME; 519 520 sc->sc_ac97rate = -1; 521 return; 522 523 fail_disestablish_intr: 524 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 525 fail_unmap: 526 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 527 fail_unmap_mix: 528 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 529 } 530 531 int 532 auich_activate(struct device *self, int act) 533 { 534 struct auich_softc *sc = (struct auich_softc *)self; 535 536 switch (act) { 537 case DVACT_RESUME: 538 auich_resume(sc); 539 break; 540 default: 541 break; 542 } 543 return (config_activate_children(self, act)); 544 } 545 546 int 547 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 548 { 549 struct auich_softc *sc = v; 550 int i; 551 552 /* wait for an access semaphore */ 553 for (i = AUICH_SEMATIMO; i-- && 554 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 555 556 if (!sc->sc_ignore_codecready && i < 0) { 557 DPRINTF(AUICH_DEBUG_CODECIO, 558 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 559 return (-1); 560 } 561 562 *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg); 563 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: read_codec(%x, %x)\n", 564 sc->sc_dev.dv_xname, reg, *val)); 565 return (0); 566 } 567 568 int 569 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 570 { 571 struct auich_softc *sc = v; 572 int i; 573 574 /* wait for an access semaphore */ 575 for (i = AUICH_SEMATIMO; i-- && 576 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 577 578 if (sc->sc_ignore_codecready || i >= 0) { 579 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: write_codec(%x, %x)\n", 580 sc->sc_dev.dv_xname, reg, val)); 581 bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val); 582 return (0); 583 } else { 584 DPRINTF(AUICH_DEBUG_CODECIO, 585 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 586 return (-1); 587 } 588 } 589 590 int 591 auich_attach_codec(void *v, struct ac97_codec_if *cif) 592 { 593 struct auich_softc *sc = v; 594 595 sc->codec_if = cif; 596 return 0; 597 } 598 599 void 600 auich_reset_codec(void *v) 601 { 602 struct auich_softc *sc = v; 603 u_int32_t control; 604 int i; 605 606 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 607 control &= ~(AUICH_ACLSO | sc->sc_pcm246_mask); 608 control |= (control & AUICH_CRESET) ? AUICH_WRESET : AUICH_CRESET; 609 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 610 611 for (i = AUICH_RESETIMO; i-- && 612 !(bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS) & AUICH_PCR); 613 DELAY(1)); 614 615 if (i < 0) 616 DPRINTF(AUICH_DEBUG_CODECIO, 617 ("%s: reset_codec timeout\n", sc->sc_dev.dv_xname)); 618 } 619 620 enum ac97_host_flags 621 auich_flags_codec(void *v) 622 { 623 struct auich_softc *sc = v; 624 625 return (sc->flags); 626 } 627 628 void 629 auich_spdif_event(void *v, int flag) 630 { 631 struct auich_softc *sc = v; 632 sc->sc_spdif = flag; 633 } 634 635 int 636 auich_open(void *v, int flags) 637 { 638 struct auich_softc *sc = v; 639 640 if (sc->sc_ac97rate == -1) 641 sc->sc_ac97rate = auich_calibrate(sc); 642 643 sc->codec_if->vtbl->lock(sc->codec_if); 644 645 return 0; 646 } 647 648 void 649 auich_close(void *v) 650 { 651 struct auich_softc *sc = v; 652 653 sc->codec_if->vtbl->unlock(sc->codec_if); 654 } 655 656 int 657 auich_set_params(void *v, int setmode, int usemode, 658 struct audio_params *play, struct audio_params *rec) 659 { 660 struct auich_softc *sc = v; 661 struct ac97_codec_if *codec = sc->codec_if; 662 int error; 663 u_int orate; 664 u_int adj_rate; 665 u_int32_t control; 666 u_int16_t ext_id; 667 668 if (setmode & AUMODE_PLAY) { 669 /* only 16-bit 48kHz slinear_le if s/pdif enabled */ 670 if (sc->sc_spdif) { 671 play->sample_rate = 48000; 672 play->precision = 16; 673 play->encoding = AUDIO_ENCODING_SLINEAR_LE; 674 } 675 } 676 if (setmode & AUMODE_PLAY) { 677 play->precision = 16; 678 switch(play->encoding) { 679 case AUDIO_ENCODING_SLINEAR_LE: 680 if (play->channels > 6) 681 play->channels = 6; 682 if (play->channels > 1) 683 play->channels &= ~1; 684 switch (play->channels) { 685 case 1: 686 play->channels = 2; 687 break; 688 case 2: 689 break; 690 case 4: 691 ext_id = codec->vtbl->get_caps(codec); 692 if (!(ext_id & AC97_EXT_AUDIO_SDAC)) 693 play->channels = 2; 694 break; 695 case 6: 696 ext_id = codec->vtbl->get_caps(codec); 697 if ((ext_id & AC97_BITS_6CH) != 698 AC97_BITS_6CH) 699 play->channels = 2; 700 break; 701 default: 702 return (EINVAL); 703 } 704 break; 705 default: 706 return (EINVAL); 707 } 708 play->bps = AUDIO_BPS(play->precision); 709 play->msb = 1; 710 711 orate = adj_rate = play->sample_rate; 712 if (sc->sc_ac97rate != 0) 713 adj_rate = orate * AUICH_FIXED_RATE / sc->sc_ac97rate; 714 715 play->sample_rate = adj_rate; 716 sc->last_prate = play->sample_rate; 717 718 error = ac97_set_rate(sc->codec_if, 719 AC97_REG_PCM_LFE_DAC_RATE, &play->sample_rate); 720 if (error) 721 return (error); 722 723 play->sample_rate = adj_rate; 724 error = ac97_set_rate(sc->codec_if, 725 AC97_REG_PCM_SURR_DAC_RATE, &play->sample_rate); 726 if (error) 727 return (error); 728 729 play->sample_rate = adj_rate; 730 error = ac97_set_rate(sc->codec_if, 731 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate); 732 if (error) 733 return (error); 734 735 if (play->sample_rate == adj_rate) 736 play->sample_rate = orate; 737 738 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 739 control &= ~(sc->sc_pcm246_mask); 740 if (play->channels == 4) 741 control |= sc->sc_pcm4; 742 else if (play->channels == 6) 743 control |= sc->sc_pcm6; 744 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 745 746 sc->last_pchan = play->channels; 747 } 748 749 if (setmode & AUMODE_RECORD) { 750 rec->channels = 2; 751 rec->precision = 16; 752 rec->encoding = AUDIO_ENCODING_SLINEAR_LE; 753 rec->bps = AUDIO_BPS(rec->precision); 754 rec->msb = 1; 755 756 orate = rec->sample_rate; 757 if (sc->sc_ac97rate != 0) 758 rec->sample_rate = orate * AUICH_FIXED_RATE / 759 sc->sc_ac97rate; 760 sc->last_rrate = rec->sample_rate; 761 error = ac97_set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 762 &rec->sample_rate); 763 if (error) 764 return (error); 765 rec->sample_rate = orate; 766 } 767 768 return (0); 769 } 770 771 int 772 auich_round_blocksize(void *v, int blk) 773 { 774 return (blk + 0x3f) & ~0x3f; 775 } 776 777 778 void 779 auich_halt_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 780 { 781 int i; 782 uint32_t sts; 783 784 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 0); 785 786 /* wait for DMA halted and clear interrupt / event bits if needed */ 787 for (i = 0; i < 1000; i++) { 788 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 789 pipe + sc->sc_sts_reg); 790 if (sts & (AUICH_CELV | AUICH_LVBCI | AUICH_BCIS | AUICH_FIFOE)) 791 bus_space_write_2(sc->iot, sc->aud_ioh, 792 pipe + sc->sc_sts_reg, 793 AUICH_CELV | AUICH_LVBCI | 794 AUICH_BCIS | AUICH_FIFOE); 795 if (sts & AUICH_DCH) 796 break; 797 DELAY(100); 798 } 799 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, AUICH_RR); 800 801 if (i > 0) 802 DPRINTF(AUICH_DEBUG_DMA, 803 ("auich_halt_pipe: halt took %d cycles\n", i)); 804 805 ring->running = 0; 806 } 807 808 809 int 810 auich_halt_output(void *v) 811 { 812 struct auich_softc *sc = v; 813 814 DPRINTF(AUICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 815 816 mtx_enter(&audio_lock); 817 auich_halt_pipe(sc, AUICH_PCMO, &sc->pcmo); 818 819 sc->pcmo.intr = NULL; 820 mtx_leave(&audio_lock); 821 return 0; 822 } 823 824 int 825 auich_halt_input(void *v) 826 { 827 struct auich_softc *sc = v; 828 829 DPRINTF(AUICH_DEBUG_DMA, 830 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 831 832 /* XXX halt both unless known otherwise */ 833 mtx_enter(&audio_lock); 834 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 835 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 836 837 sc->pcmi.intr = NULL; 838 mtx_leave(&audio_lock); 839 return 0; 840 } 841 842 int 843 auich_set_port(void *v, mixer_ctrl_t *cp) 844 { 845 struct auich_softc *sc = v; 846 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 847 } 848 849 int 850 auich_get_port(void *v, mixer_ctrl_t *cp) 851 { 852 struct auich_softc *sc = v; 853 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 854 } 855 856 int 857 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 858 { 859 struct auich_softc *sc = v; 860 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 861 } 862 863 void * 864 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 865 { 866 struct auich_softc *sc = v; 867 struct auich_dma *p; 868 int error; 869 870 /* can only use 1 segment */ 871 if (size > AUICH_DMASEG_MAX) { 872 DPRINTF(AUICH_DEBUG_DMA, 873 ("%s: requested buffer size too large: %zd", \ 874 sc->sc_dev.dv_xname, size)); 875 return NULL; 876 } 877 878 p = malloc(sizeof(*p), pool, flags | M_ZERO); 879 if (!p) 880 return NULL; 881 882 error = auich_allocmem(sc, size, PAGE_SIZE, p); 883 if (error) { 884 free(p, pool, sizeof(*p)); 885 return NULL; 886 } 887 888 if (direction == AUMODE_PLAY) 889 sc->sc_pdma = p; 890 else if (direction == AUMODE_RECORD) 891 sc->sc_rdma = p; 892 else 893 sc->sc_cdma = p; 894 895 return p->addr; 896 } 897 898 void 899 auich_freem(void *v, void *ptr, int pool) 900 { 901 struct auich_softc *sc; 902 struct auich_dma *p; 903 904 sc = v; 905 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == ptr) 906 p = sc->sc_pdma; 907 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == ptr) 908 p = sc->sc_rdma; 909 else if (sc->sc_cdma != NULL && sc->sc_cdma->addr == ptr) 910 p = sc->sc_cdma; 911 else 912 return; 913 914 auich_freemem(sc, p); 915 free(p, pool, sizeof(*p)); 916 } 917 918 size_t 919 auich_round_buffersize(void *v, int direction, size_t size) 920 { 921 if (size > AUICH_DMALIST_MAX * AUICH_DMASEG_MAX) 922 size = AUICH_DMALIST_MAX * AUICH_DMASEG_MAX; 923 924 return size; 925 } 926 927 int 928 auich_get_props(void *v) 929 { 930 return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 931 } 932 933 int 934 auich_intr(void *v) 935 { 936 struct auich_softc *sc = v; 937 int ret = 0, sts, gsts; 938 939 mtx_enter(&audio_lock); 940 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 941 DPRINTF(AUICH_DEBUG_INTR, ("auich_intr: gsts=%b\n", gsts, AUICH_GSTS_BITS)); 942 943 if (gsts & AUICH_POINT) { 944 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 945 AUICH_PCMO + sc->sc_sts_reg); 946 DPRINTF(AUICH_DEBUG_INTR, 947 ("auich_intr: osts=%b\n", sts, AUICH_ISTS_BITS)); 948 949 #ifdef AUICH_DEBUG 950 if (sts & AUICH_FIFOE) { 951 printf("%s: in fifo underrun # %u civ=%u ctrl=0x%x sts=%b\n", 952 sc->sc_dev.dv_xname, sc->pcmo_fifoe++, 953 bus_space_read_1(sc->iot, sc->aud_ioh, 954 AUICH_PCMO + AUICH_CIV), 955 bus_space_read_1(sc->iot, sc->aud_ioh, 956 AUICH_PCMO + AUICH_CTRL), 957 bus_space_read_2(sc->iot, sc->aud_ioh, 958 AUICH_PCMO + sc->sc_sts_reg), 959 AUICH_ISTS_BITS); 960 } 961 #endif 962 963 if (sts & AUICH_BCIS) 964 auich_intr_pipe(sc, AUICH_PCMO, &sc->pcmo); 965 966 /* int ack */ 967 bus_space_write_2(sc->iot, sc->aud_ioh, 968 AUICH_PCMO + sc->sc_sts_reg, sts & 969 (AUICH_BCIS | AUICH_FIFOE)); 970 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_POINT); 971 ret++; 972 } 973 974 if (gsts & AUICH_PIINT) { 975 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 976 AUICH_PCMI + sc->sc_sts_reg); 977 DPRINTF(AUICH_DEBUG_INTR, 978 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 979 980 #ifdef AUICH_DEBUG 981 if (sts & AUICH_FIFOE) { 982 printf("%s: in fifo overrun # %u civ=%u ctrl=0x%x sts=%b\n", 983 sc->sc_dev.dv_xname, sc->pcmi_fifoe++, 984 bus_space_read_1(sc->iot, sc->aud_ioh, 985 AUICH_PCMI + AUICH_CIV), 986 bus_space_read_1(sc->iot, sc->aud_ioh, 987 AUICH_PCMI + AUICH_CTRL), 988 bus_space_read_2(sc->iot, sc->aud_ioh, 989 AUICH_PCMI + sc->sc_sts_reg), 990 AUICH_ISTS_BITS); 991 } 992 #endif 993 994 if (sts & AUICH_BCIS) 995 auich_intr_pipe(sc, AUICH_PCMI, &sc->pcmi); 996 997 /* int ack */ 998 bus_space_write_2(sc->iot, sc->aud_ioh, 999 AUICH_PCMI + sc->sc_sts_reg, sts & 1000 (AUICH_BCIS | AUICH_FIFOE)); 1001 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_PIINT); 1002 ret++; 1003 } 1004 1005 if (gsts & AUICH_MINT) { 1006 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1007 AUICH_MICI + sc->sc_sts_reg); 1008 DPRINTF(AUICH_DEBUG_INTR, 1009 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1010 #ifdef AUICH_DEBUG 1011 if (sts & AUICH_FIFOE) { 1012 printf("%s: in fifo overrun civ=%u ctrl=0x%x sts=%b\n", 1013 sc->sc_dev.dv_xname, 1014 bus_space_read_1(sc->iot, sc->aud_ioh, 1015 AUICH_MICI + AUICH_CIV), 1016 bus_space_read_1(sc->iot, sc->aud_ioh, 1017 AUICH_MICI + AUICH_CTRL), 1018 bus_space_read_2(sc->iot, sc->aud_ioh, 1019 AUICH_MICI + sc->sc_sts_reg), 1020 AUICH_ISTS_BITS); 1021 } 1022 #endif 1023 if (sts & AUICH_BCIS) 1024 auich_intr_pipe(sc, AUICH_MICI, &sc->mici); 1025 1026 /* int ack */ 1027 bus_space_write_2(sc->iot, sc->aud_ioh, 1028 AUICH_MICI + sc->sc_sts_reg, 1029 sts + (AUICH_BCIS | AUICH_FIFOE)); 1030 1031 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_MINT); 1032 ret++; 1033 } 1034 mtx_leave(&audio_lock); 1035 return ret; 1036 } 1037 1038 1039 void 1040 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1041 { 1042 int blksize, qptr, oqptr; 1043 struct auich_dmalist *q; 1044 1045 blksize = ring->blksize; 1046 qptr = oqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1047 1048 /* XXX remove this when no one reports problems */ 1049 if(oqptr >= AUICH_DMALIST_MAX) { 1050 printf("%s: Unexpected CIV: %d\n", sc->sc_dev.dv_xname, oqptr); 1051 qptr = oqptr = 0; 1052 } 1053 1054 do { 1055 q = &ring->dmalist[qptr]; 1056 q->base = ring->p; 1057 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1058 1059 DPRINTF(AUICH_DEBUG_INTR, 1060 ("auich_trigger_pipe: %p, %p = %x @ 0x%x qptr=%d\n", 1061 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1062 1063 ring->p += blksize; 1064 if (ring->p >= ring->end) 1065 ring->p = ring->start; 1066 1067 qptr = (qptr + 1) & AUICH_LVI_MASK; 1068 } while (qptr != oqptr); 1069 1070 ring->qptr = qptr; 1071 1072 DPRINTF(AUICH_DEBUG_DMA, 1073 ("auich_trigger_pipe: qptr=%d\n", qptr)); 1074 1075 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1076 (qptr - 1) & AUICH_LVI_MASK); 1077 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 1078 AUICH_IOCE | AUICH_FEIE | AUICH_RPBM); 1079 1080 ring->running = 1; 1081 } 1082 1083 void 1084 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1085 { 1086 int blksize, qptr, nqptr; 1087 struct auich_dmalist *q; 1088 1089 blksize = ring->blksize; 1090 qptr = ring->qptr; 1091 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1092 1093 while (qptr != nqptr) { 1094 q = &ring->dmalist[qptr]; 1095 q->base = ring->p; 1096 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1097 1098 DPRINTF(AUICH_DEBUG_INTR, 1099 ("auich_intr: %p, %p = %x @ 0x%x qptr=%d\n", 1100 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1101 1102 ring->p += blksize; 1103 if (ring->p >= ring->end) 1104 ring->p = ring->start; 1105 1106 qptr = (qptr + 1) & AUICH_LVI_MASK; 1107 if (ring->intr) 1108 ring->intr(ring->arg); 1109 else 1110 printf("auich_intr: got progress with intr==NULL\n"); 1111 1112 ring->ap += blksize; 1113 if (ring->ap >= ring->size) 1114 ring->ap = 0; 1115 } 1116 ring->qptr = qptr; 1117 1118 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1119 (qptr - 1) & AUICH_LVI_MASK); 1120 } 1121 1122 1123 int 1124 auich_trigger_output(void *v, void *start, void *end, int blksize, 1125 void (*intr)(void *), void *arg, struct audio_params *param) 1126 { 1127 struct auich_softc *sc = v; 1128 struct auich_dma *p; 1129 size_t size; 1130 #ifdef AUICH_DEBUG 1131 uint16_t sts; 1132 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1133 AUICH_PCMO + sc->sc_sts_reg); 1134 DPRINTF(AUICH_DEBUG_DMA, 1135 ("auich_trigger_output(%p, %p, %d, %p, %p, %p) sts=%b\n", 1136 start, end, blksize, intr, arg, param, sts, AUICH_ISTS_BITS)); 1137 #endif 1138 1139 if (sc->sc_pdma->addr == start) 1140 p = sc->sc_pdma; 1141 else 1142 return -1; 1143 1144 size = (size_t)((caddr_t)end - (caddr_t)start); 1145 sc->pcmo.size = size; 1146 sc->pcmo.intr = intr; 1147 sc->pcmo.arg = arg; 1148 1149 /* 1150 * The logic behind this is: 1151 * setup one buffer to play, then LVI dump out the rest 1152 * to the scatter-gather chain. 1153 */ 1154 sc->pcmo.start = p->segs->ds_addr; 1155 sc->pcmo.p = sc->pcmo.start; 1156 sc->pcmo.end = sc->pcmo.start + size; 1157 sc->pcmo.blksize = blksize; 1158 1159 mtx_enter(&audio_lock); 1160 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMO + AUICH_BDBAR, 1161 sc->sc_cddma + AUICH_PCMO_OFF(0)); 1162 auich_trigger_pipe(sc, AUICH_PCMO, &sc->pcmo); 1163 mtx_leave(&audio_lock); 1164 return 0; 1165 } 1166 1167 int 1168 auich_trigger_input(void *v, void *start, void *end, int blksize, 1169 void (*intr)(void *), void *arg, struct audio_params *param) 1170 { 1171 struct auich_softc *sc = v; 1172 struct auich_dma *p; 1173 size_t size; 1174 1175 DPRINTF(AUICH_DEBUG_DMA, 1176 ("auich_trigger_input(%p, %p, %d, %p, %p, %p) sts=%b\n", 1177 start, end, blksize, intr, arg, param, 1178 bus_space_read_2(sc->iot, sc->aud_ioh, 1179 AUICH_PCMI + sc->sc_sts_reg), 1180 AUICH_ISTS_BITS)); 1181 1182 if (sc->sc_rdma->addr == start) 1183 p = sc->sc_rdma; 1184 else 1185 return -1; 1186 1187 size = (size_t)((caddr_t)end - (caddr_t)start); 1188 sc->pcmi.size = size; 1189 sc->pcmi.intr = intr; 1190 sc->pcmi.arg = arg; 1191 1192 /* 1193 * The logic behind this is: 1194 * setup one buffer to play, then LVI dump out the rest 1195 * to the scatter-gather chain. 1196 */ 1197 sc->pcmi.start = p->segs->ds_addr; 1198 sc->pcmi.p = sc->pcmi.start; 1199 sc->pcmi.end = sc->pcmi.start + size; 1200 sc->pcmi.blksize = blksize; 1201 mtx_enter(&audio_lock); 1202 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1203 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1204 auich_trigger_pipe(sc, AUICH_PCMI, &sc->pcmi); 1205 mtx_leave(&audio_lock); 1206 return 0; 1207 } 1208 1209 1210 int 1211 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1212 struct auich_dma *p) 1213 { 1214 int error; 1215 1216 p->size = size; 1217 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, p->segs, 1, 1218 &p->nsegs, BUS_DMA_NOWAIT); 1219 if (error) { 1220 DPRINTF(AUICH_DEBUG_DMA, 1221 ("%s: bus_dmamem_alloc failed: error %d\n", 1222 sc->sc_dev.dv_xname, error)); 1223 return error; 1224 } 1225 1226 error = bus_dmamem_map(sc->dmat, p->segs, 1, p->size, &p->addr, 1227 BUS_DMA_NOWAIT | sc->sc_dmamap_flags); 1228 if (error) { 1229 DPRINTF(AUICH_DEBUG_DMA, 1230 ("%s: bus_dmamem_map failed: error %d\n", 1231 sc->sc_dev.dv_xname, error)); 1232 goto free; 1233 } 1234 1235 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 0, 1236 BUS_DMA_NOWAIT, &p->map); 1237 if (error) { 1238 DPRINTF(AUICH_DEBUG_DMA, 1239 ("%s: bus_dmamap_create failed: error %d\n", 1240 sc->sc_dev.dv_xname, error)); 1241 goto unmap; 1242 } 1243 1244 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1245 BUS_DMA_NOWAIT); 1246 if (error) { 1247 DPRINTF(AUICH_DEBUG_DMA, 1248 ("%s: bus_dmamap_load failed: error %d\n", 1249 sc->sc_dev.dv_xname, error)); 1250 goto destroy; 1251 } 1252 return 0; 1253 1254 destroy: 1255 bus_dmamap_destroy(sc->dmat, p->map); 1256 unmap: 1257 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1258 free: 1259 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1260 return error; 1261 } 1262 1263 1264 void 1265 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1266 { 1267 bus_dmamap_unload(sc->dmat, p->map); 1268 bus_dmamap_destroy(sc->dmat, p->map); 1269 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1270 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1271 } 1272 1273 1274 1275 int 1276 auich_alloc_cdata(struct auich_softc *sc) 1277 { 1278 bus_dma_segment_t seg; 1279 int error, rseg; 1280 1281 /* 1282 * Allocate the control data structure, and create and load the 1283 * DMA map for it. 1284 */ 1285 if ((error = bus_dmamem_alloc(sc->dmat, sizeof(struct auich_cdata), 1286 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1287 printf("%s: unable to allocate control data, error = %d\n", 1288 sc->sc_dev.dv_xname, error); 1289 goto fail_0; 1290 } 1291 1292 if ((error = bus_dmamem_map(sc->dmat, &seg, 1, 1293 sizeof(struct auich_cdata), (caddr_t *) &sc->sc_cdata, 1294 sc->sc_dmamap_flags)) != 0) { 1295 printf("%s: unable to map control data, error = %d\n", 1296 sc->sc_dev.dv_xname, error); 1297 goto fail_1; 1298 } 1299 1300 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1301 sizeof(struct auich_cdata), 0, 0, &sc->sc_cddmamap)) != 0) { 1302 printf("%s: unable to create control data DMA map, " 1303 "error = %d\n", sc->sc_dev.dv_xname, error); 1304 goto fail_2; 1305 } 1306 1307 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, sc->sc_cdata, 1308 sizeof(struct auich_cdata), NULL, 0)) != 0) { 1309 printf("%s: unable to load control data DMA map, " 1310 "error = %d\n", sc->sc_dev.dv_xname, error); 1311 goto fail_3; 1312 } 1313 1314 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1315 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1316 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1317 1318 return 0; 1319 1320 fail_3: 1321 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1322 fail_2: 1323 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1324 sizeof(struct auich_cdata)); 1325 fail_1: 1326 bus_dmamem_free(sc->dmat, &seg, rseg); 1327 fail_0: 1328 return error; 1329 } 1330 1331 void 1332 auich_resume(struct auich_softc *sc) 1333 { 1334 /* SiS 7012 needs special handling */ 1335 if (PCI_VENDOR(sc->pci_id) == PCI_VENDOR_SIS && 1336 PCI_PRODUCT(sc->pci_id) == PCI_PRODUCT_SIS_7012_ACA) { 1337 /* un-mute output */ 1338 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 1339 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 1340 ICH_SIS_CTL_UNMUTE); 1341 } 1342 1343 ac97_resume(&sc->host_if, sc->codec_if); 1344 } 1345 1346 /* -------------------------------------------------------------------- */ 1347 /* Calibrate card (some boards are overclocked and need scaling) */ 1348 1349 unsigned int 1350 auich_calibrate(struct auich_softc *sc) 1351 { 1352 struct timeval t1, t2; 1353 u_int8_t civ, ociv; 1354 uint16_t sts, osts; 1355 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1356 void *temp_buffer; 1357 struct auich_dma *p; 1358 1359 ac97rate = AUICH_FIXED_RATE; 1360 /* 1361 * Grab audio from input for fixed interval and compare how 1362 * much we actually get with what we expect. Interval needs 1363 * to be sufficiently short that no interrupts are 1364 * generated. 1365 * XXX: Is this true? We don't request any interrupts, 1366 * so why should the chip issue any? 1367 */ 1368 1369 /* Setup a buffer */ 1370 bytes = 16000; 1371 temp_buffer = auich_allocm(sc, 0, bytes, M_DEVBUF, M_NOWAIT); 1372 if (temp_buffer == NULL) 1373 return (ac97rate); 1374 if (sc->sc_cdma->addr == temp_buffer) { 1375 p = sc->sc_cdma; 1376 } else { 1377 printf("auich_calibrate: bad address %p\n", temp_buffer); 1378 return (ac97rate); 1379 } 1380 1381 /* get current CIV (usually 0 after reboot) */ 1382 ociv = civ = bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CIV); 1383 sc->pcmi.dmalist[civ].base = p->map->dm_segs[0].ds_addr; 1384 sc->pcmi.dmalist[civ].len = bytes / sc->sc_sample_size; 1385 1386 1387 /* 1388 * our data format is stereo, 16 bit so each sample is 4 bytes. 1389 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1390 * we're going to start recording with interrupts disabled and measure 1391 * the time taken for one block to complete. we know the block size, 1392 * we know the time in microseconds, we calculate the sample rate: 1393 * 1394 * actual_rate [bps] = bytes / (time [s] * 4) 1395 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1396 * actual_rate [Hz] = (bytes * 250000) / time [us] 1397 */ 1398 1399 /* prepare */ 1400 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1401 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1402 /* we got only one valid sample, so set LVI to CIV 1403 * otherwise we provoke a AUICH_FIFOE FIFO error 1404 * which will confuse the chip later on. */ 1405 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_LVI, 1406 civ & AUICH_LVI_MASK); 1407 1408 /* start, but don't request any interupts */ 1409 microuptime(&t1); 1410 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CTRL, 1411 AUICH_RPBM); 1412 1413 /* XXX remove this sometime */ 1414 osts = bus_space_read_2(sc->iot, sc->aud_ioh, 1415 AUICH_PCMI + sc->sc_sts_reg); 1416 /* wait */ 1417 while(1) { 1418 microuptime(&t2); 1419 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1420 AUICH_PCMI + sc->sc_sts_reg); 1421 civ = bus_space_read_1(sc->iot, sc->aud_ioh, 1422 AUICH_PCMI + AUICH_CIV); 1423 1424 /* turn time delta into us */ 1425 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + 1426 t2.tv_usec - t1.tv_usec; 1427 1428 /* this should actually never happen because civ==lvi */ 1429 if ((civ & AUICH_LVI_MASK) != (ociv & AUICH_LVI_MASK)) { 1430 printf("%s: ac97 CIV progressed after %d us sts=%b civ=%u\n", 1431 sc->sc_dev.dv_xname, wait_us, sts, 1432 AUICH_ISTS_BITS, civ); 1433 ociv = civ; 1434 } 1435 /* normal completion */ 1436 if (sts & (AUICH_DCH | AUICH_CELV | AUICH_LVBCI)) 1437 break; 1438 /* 1439 * check for strange changes in STS - 1440 * XXX remove it when everythings fine 1441 */ 1442 if (sts != osts) { 1443 printf("%s: ac97 sts changed after %d us sts=%b civ=%u\n", 1444 sc->sc_dev.dv_xname, wait_us, sts, 1445 AUICH_ISTS_BITS, civ); 1446 osts = sts; 1447 } 1448 /* 1449 * timeout: we expect 83333 us for 48k sampling rate, 1450 * 600000 us will be enough even for 8k sampling rate 1451 */ 1452 if (wait_us > 600000) { 1453 printf("%s: ac97 link rate timed out %d us sts=%b civ=%u\n", 1454 sc->sc_dev.dv_xname, wait_us, sts, 1455 AUICH_ISTS_BITS, civ); 1456 /* reset and clean up*/ 1457 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1458 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1459 auich_freem(sc, temp_buffer, M_DEVBUF); 1460 /* return default sample rate */ 1461 return (ac97rate); 1462 } 1463 } 1464 1465 DPRINTF(AUICH_DEBUG_CODECIO, 1466 ("%s: ac97 link rate calibration took %d us sts=%b civ=%u\n", 1467 sc->sc_dev.dv_xname, wait_us, sts, AUICH_ISTS_BITS, civ)); 1468 1469 /* reset and clean up */ 1470 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1471 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1472 auich_freem(sc, temp_buffer, M_DEVBUF); 1473 1474 #ifdef AUICH_DEBUG 1475 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1476 AUICH_PCMI + sc->sc_sts_reg); 1477 civ = bus_space_read_4(sc->iot, sc->aud_ioh, 1478 AUICH_PCMI + AUICH_CIV); 1479 printf("%s: after calibration and reset sts=%b civ=%u\n", 1480 sc->sc_dev.dv_xname, sts, AUICH_ISTS_BITS, civ); 1481 #endif 1482 1483 /* now finally calculate measured samplerate */ 1484 actual_48k_rate = (bytes * 250000) / wait_us; 1485 1486 if (actual_48k_rate <= 48500) 1487 ac97rate = AUICH_FIXED_RATE; 1488 else 1489 ac97rate = actual_48k_rate; 1490 1491 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: measured ac97 link rate at %d Hz", 1492 sc->sc_dev.dv_xname, actual_48k_rate)); 1493 if (ac97rate != actual_48k_rate) 1494 DPRINTF(AUICH_DEBUG_CODECIO, (", will use %d Hz", ac97rate)); 1495 DPRINTF(AUICH_DEBUG_CODECIO, ("\n")); 1496 1497 return (ac97rate); 1498 } 1499