1 /* $OpenBSD: auich.c,v 1.101 2014/07/12 18:48:51 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 2000,2001 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * AC'97 audio found on Intel 810/815/820/440MX chipsets. 31 * http://developer.intel.com/design/chipsets/datashts/290655.htm 32 * http://developer.intel.com/design/chipsets/manuals/298028.htm 33 * http://www.intel.com/design/chipsets/datashts/290714.htm 34 * http://www.intel.com/design/chipsets/datashts/290744.htm 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <sys/audioio.h> 47 #include <dev/audio_if.h> 48 #include <dev/mulaw.h> 49 #include <dev/auconv.h> 50 51 #include <machine/bus.h> 52 53 #include <dev/ic/ac97.h> 54 55 /* 12.1.10 NAMBAR - native audio mixer base address register */ 56 #define AUICH_NAMBAR 0x10 57 /* 12.1.11 NABMBAR - native audio bus mastering base address register */ 58 #define AUICH_NABMBAR 0x14 59 #define AUICH_CFG 0x41 60 #define AUICH_CFG_IOSE 0x01 61 /* ICH4/ICH5/ICH6/ICH7 native audio mixer BAR */ 62 #define AUICH_MMBAR 0x18 63 /* ICH4/ICH5/ICH6/ICH7 native bus mastering BAR */ 64 #define AUICH_MBBAR 0x1c 65 #define AUICH_S2CR 0x10000000 /* tertiary codec ready */ 66 67 /* table 12-3. native audio bus master control registers */ 68 #define AUICH_BDBAR 0x00 /* 8-byte aligned address */ 69 #define AUICH_CIV 0x04 /* 5 bits current index value */ 70 #define AUICH_LVI 0x05 /* 5 bits last valid index value */ 71 #define AUICH_LVI_MASK 0x1f 72 #define AUICH_STS 0x06 /* 16 bits status */ 73 #define AUICH_FIFOE 0x10 /* fifo error */ 74 #define AUICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */ 75 #define AUICH_LVBCI 0x04 /* r- last valid bci, wr ack */ 76 #define AUICH_CELV 0x02 /* current equals last valid */ 77 #define AUICH_DCH 0x01 /* dma halted */ 78 #define AUICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe" 79 #define AUICH_PICB 0x08 /* 16 bits */ 80 #define AUICH_PIV 0x0a /* 5 bits prefetched index value */ 81 #define AUICH_CTRL 0x0b /* control */ 82 #define AUICH_IOCE 0x10 /* int on completion enable */ 83 #define AUICH_FEIE 0x08 /* fifo error int enable */ 84 #define AUICH_LVBIE 0x04 /* last valid buf int enable */ 85 #define AUICH_RR 0x02 /* 1 - reset regs */ 86 #define AUICH_RPBM 0x01 /* 1 - run, 0 - pause */ 87 88 #define AUICH_PCMI 0x00 89 #define AUICH_PCMO 0x10 90 #define AUICH_MICI 0x20 91 92 #define AUICH_GCTRL 0x2c 93 #define AUICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */ 94 #define AUICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */ 95 #define AUICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */ 96 #define AUICH_POM16 0x000000 /* PCM out precision 16bit */ 97 #define AUICH_POM20 0x400000 /* PCM out precision 20bit */ 98 #define AUICH_PCM246_MASK 0x300000 99 #define AUICH_PCM2 0x000000 /* 2ch output */ 100 #define AUICH_PCM4 0x100000 /* 4ch output */ 101 #define AUICH_PCM6 0x200000 /* 6ch output */ 102 #define AUICH_SIS_PCM246_MASK 0x0000c0 /* SiS 7012 */ 103 #define AUICH_SIS_PCM2 0x000000 /* SiS 7012 2ch output */ 104 #define AUICH_SIS_PCM4 0x000040 /* SiS 7012 4ch output */ 105 #define AUICH_SIS_PCM6 0x000080 /* SiS 7012 6ch output */ 106 #define AUICH_S2RIE 0x40 /* int when tertiary codec resume */ 107 #define AUICH_SRIE 0x20 /* int when 2ndary codec resume */ 108 #define AUICH_PRIE 0x10 /* int when primary codec resume */ 109 #define AUICH_ACLSO 0x08 /* aclink shut off */ 110 #define AUICH_WRESET 0x04 /* warm reset */ 111 #define AUICH_CRESET 0x02 /* cold reset */ 112 #define AUICH_GIE 0x01 /* gpi int enable */ 113 #define AUICH_GSTS 0x30 114 #define AUICH_MD3 0x20000 /* pwr-dn semaphore for modem */ 115 #define AUICH_AD3 0x10000 /* pwr-dn semaphore for audio */ 116 #define AUICH_RCS 0x08000 /* read completion status */ 117 #define AUICH_B3S12 0x04000 /* bit 3 of slot 12 */ 118 #define AUICH_B2S12 0x02000 /* bit 2 of slot 12 */ 119 #define AUICH_B1S12 0x01000 /* bit 1 of slot 12 */ 120 #define AUICH_SRI 0x00800 /* secondary resume int */ 121 #define AUICH_PRI 0x00400 /* primary resume int */ 122 #define AUICH_SCR 0x00200 /* secondary codec ready */ 123 #define AUICH_PCR 0x00100 /* primary codec ready */ 124 #define AUICH_MINT 0x00080 /* mic in int */ 125 #define AUICH_POINT 0x00040 /* pcm out int */ 126 #define AUICH_PIINT 0x00020 /* pcm in int */ 127 #define AUICH_MOINT 0x00004 /* modem out int */ 128 #define AUICH_MIINT 0x00002 /* modem in int */ 129 #define AUICH_GSCI 0x00001 /* gpi status change */ 130 #define AUICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3" 131 #define AUICH_CAS 0x34 /* 1/8 bit */ 132 #define AUICH_SEMATIMO 1000 /* us */ 133 #define AUICH_RESETIMO 500000 /* us */ 134 135 #define ICH_SIS_NV_CTL 0x4c /* some SiS/NVIDIA register. From Linux */ 136 #define ICH_SIS_CTL_UNMUTE 0x01 /* un-mute the output */ 137 138 /* 139 * There are 32 buffer descriptors. Each can reference up to 2^16 16-bit 140 * samples. 141 */ 142 #define AUICH_DMALIST_MAX 32 143 #define AUICH_DMASEG_MAX (65536*2) 144 struct auich_dmalist { 145 u_int32_t base; 146 u_int32_t len; 147 #define AUICH_DMAF_IOC 0x80000000 /* 1-int on complete */ 148 #define AUICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 149 }; 150 151 #define AUICH_FIXED_RATE 48000 152 153 struct auich_dma { 154 bus_dmamap_t map; 155 caddr_t addr; 156 bus_dma_segment_t segs[1]; 157 int nsegs; 158 size_t size; 159 }; 160 161 struct auich_cdata { 162 struct auich_dmalist ic_dmalist_pcmo[AUICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_pcmi[AUICH_DMALIST_MAX]; 164 struct auich_dmalist ic_dmalist_mici[AUICH_DMALIST_MAX]; 165 }; 166 167 #define AUICH_CDOFF(x) offsetof(struct auich_cdata, x) 168 #define AUICH_PCMO_OFF(x) AUICH_CDOFF(ic_dmalist_pcmo[(x)]) 169 #define AUICH_PCMI_OFF(x) AUICH_CDOFF(ic_dmalist_pcmi[(x)]) 170 #define AUICH_MICI_OFF(x) AUICH_CDOFF(ic_dmalist_mici[(x)]) 171 172 struct auich_softc { 173 struct device sc_dev; 174 void *sc_ih; 175 176 audio_device_t sc_audev; 177 struct device *audiodev; 178 179 pcireg_t pci_id; 180 bus_space_tag_t iot; 181 bus_space_tag_t iot_mix; 182 bus_space_handle_t mix_ioh; 183 bus_space_handle_t aud_ioh; 184 bus_dma_tag_t dmat; 185 186 struct ac97_codec_if *codec_if; 187 struct ac97_host_if host_if; 188 int sc_spdif; 189 190 /* dma scatter-gather buffer lists */ 191 192 bus_dmamap_t sc_cddmamap; 193 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 194 195 struct auich_cdata *sc_cdata; 196 197 struct auich_ring { 198 int qptr; 199 struct auich_dmalist *dmalist; 200 201 uint32_t start, p, end; 202 int blksize; 203 204 void (*intr)(void *); 205 void *arg; 206 int running; 207 size_t size; 208 uint32_t ap; 209 } pcmo, pcmi, mici; 210 211 struct auich_dma *sc_pdma; /* play */ 212 struct auich_dma *sc_rdma; /* record */ 213 struct auich_dma *sc_cdma; /* calibrate */ 214 215 #ifdef AUICH_DEBUG 216 int pcmi_fifoe; 217 int pcmo_fifoe; 218 #endif 219 220 int suspend; 221 u_int16_t ext_ctrl; 222 int sc_sample_size; 223 int sc_sts_reg; 224 int sc_dmamap_flags; 225 int sc_ignore_codecready; 226 int flags; 227 int sc_ac97rate; 228 229 /* multi-channel control bits */ 230 int sc_pcm246_mask; 231 int sc_pcm2; 232 int sc_pcm4; 233 int sc_pcm6; 234 235 u_int last_rrate; 236 u_int last_prate; 237 u_int last_pchan; 238 }; 239 240 #ifdef AUICH_DEBUG 241 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 242 int auich_debug = 0x0002; 243 #define AUICH_DEBUG_CODECIO 0x0001 244 #define AUICH_DEBUG_DMA 0x0002 245 #define AUICH_DEBUG_INTR 0x0004 246 #else 247 #define DPRINTF(x,y) /* nothing */ 248 #endif 249 250 struct cfdriver auich_cd = { 251 NULL, "auich", DV_DULL 252 }; 253 254 int auich_match(struct device *, void *, void *); 255 void auich_attach(struct device *, struct device *, void *); 256 int auich_intr(void *); 257 258 int auich_activate(struct device *, int); 259 260 struct cfattach auich_ca = { 261 sizeof(struct auich_softc), auich_match, auich_attach, 262 NULL, auich_activate 263 }; 264 265 static const struct auich_devtype { 266 int vendor; 267 int product; 268 int options; 269 char name[8]; 270 } auich_devices[] = { 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_ACA, 0, "ESB" }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_ACA, 0, "ESB2" }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 0, "ICH" }, 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 0, "ICH0" }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 0, "ICH2" }, 276 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_ACA, 0, "ICH3" }, 277 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ACA, 0, "ICH4" }, 278 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_ACA, 0, "ICH5" }, 279 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_ACA, 0, "ICH6" }, 280 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_ACA, 0, "ICH7" }, 281 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 0, "440MX" }, 282 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_ACA, 0, "SiS7012" }, 283 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_ACA, 0, "nForce" }, 284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_ACA, 0, "nForce2" }, 285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_ACA, 286 0, "nForce2" }, 287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_ACA, 0, "nForce3" }, 288 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_ACA, 289 0, "nForce3" }, 290 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_AC, 0, "nForce4" }, 291 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_AC97, 0, "MCP04" }, 292 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_ACA, 0, "MCP51" }, 293 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_ACA, 0, "AMD768" }, 294 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_8111_ACA, 0, "AMD8111" }, 295 }; 296 297 int auich_open(void *, int); 298 void auich_close(void *); 299 int auich_query_encoding(void *, struct audio_encoding *); 300 int auich_set_params(void *, int, int, struct audio_params *, 301 struct audio_params *); 302 int auich_round_blocksize(void *, int); 303 void auich_halt_pipe(struct auich_softc *, int, struct auich_ring *); 304 int auich_halt_output(void *); 305 int auich_halt_input(void *); 306 int auich_getdev(void *, struct audio_device *); 307 int auich_set_port(void *, mixer_ctrl_t *); 308 int auich_get_port(void *, mixer_ctrl_t *); 309 int auich_query_devinfo(void *, mixer_devinfo_t *); 310 void *auich_allocm(void *, int, size_t, int, int); 311 void auich_freem(void *, void *, int); 312 size_t auich_round_buffersize(void *, int, size_t); 313 paddr_t auich_mappage(void *, void *, off_t, int); 314 int auich_get_props(void *); 315 void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 316 void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 317 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 318 void *, struct audio_params *); 319 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 320 void *, struct audio_params *); 321 int auich_alloc_cdata(struct auich_softc *); 322 int auich_allocmem(struct auich_softc *, size_t, size_t, struct auich_dma *); 323 int auich_freemem(struct auich_softc *, struct auich_dma *); 324 void auich_get_default_params(void *, int, struct audio_params *); 325 326 int auich_resume(struct auich_softc *); 327 328 struct audio_hw_if auich_hw_if = { 329 auich_open, 330 auich_close, 331 NULL, /* drain */ 332 auich_query_encoding, 333 auich_set_params, 334 auich_round_blocksize, 335 NULL, /* commit_setting */ 336 NULL, /* init_output */ 337 NULL, /* init_input */ 338 NULL, /* start_output */ 339 NULL, /* start_input */ 340 auich_halt_output, 341 auich_halt_input, 342 NULL, /* speaker_ctl */ 343 auich_getdev, 344 NULL, /* getfd */ 345 auich_set_port, 346 auich_get_port, 347 auich_query_devinfo, 348 auich_allocm, 349 auich_freem, 350 auich_round_buffersize, 351 auich_mappage, 352 auich_get_props, 353 auich_trigger_output, 354 auich_trigger_input, 355 auich_get_default_params 356 }; 357 358 int auich_attach_codec(void *, struct ac97_codec_if *); 359 int auich_read_codec(void *, u_int8_t, u_int16_t *); 360 int auich_write_codec(void *, u_int8_t, u_int16_t); 361 void auich_reset_codec(void *); 362 enum ac97_host_flags auich_flags_codec(void *); 363 unsigned int auich_calibrate(struct auich_softc *); 364 void auich_spdif_event(void *, int); 365 366 int 367 auich_match(struct device *parent, void *match, void *aux) 368 { 369 struct pci_attach_args *pa = aux; 370 int i; 371 372 for (i = nitems(auich_devices); i--;) 373 if (PCI_VENDOR(pa->pa_id) == auich_devices[i].vendor && 374 PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 375 return 1; 376 377 return 0; 378 } 379 380 void 381 auich_attach(struct device *parent, struct device *self, void *aux) 382 { 383 struct auich_softc *sc = (struct auich_softc *)self; 384 struct pci_attach_args *pa = aux; 385 pci_intr_handle_t ih; 386 bus_size_t mix_size, aud_size; 387 pcireg_t csr; 388 const char *intrstr; 389 u_int32_t status; 390 int i; 391 392 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 393 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 394 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 395 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 396 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 397 /* 398 * Use native mode for ICH4/ICH5/ICH6/ICH7 399 */ 400 if (pci_mapreg_map(pa, AUICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 401 &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 402 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 403 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 404 csr | AUICH_CFG_IOSE); 405 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 406 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 407 printf(": can't map codec mem/io space\n"); 408 return; 409 } 410 } 411 412 if (pci_mapreg_map(pa, AUICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 413 &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 414 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 415 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 416 csr | AUICH_CFG_IOSE); 417 if (pci_mapreg_map(pa, AUICH_NABMBAR, 418 PCI_MAPREG_TYPE_IO, 0, &sc->iot, 419 &sc->aud_ioh, NULL, &aud_size, 0)) { 420 printf(": can't map device mem/io space\n"); 421 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 422 return; 423 } 424 } 425 } else { 426 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 427 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 428 printf(": can't map codec i/o space\n"); 429 return; 430 } 431 432 if (pci_mapreg_map(pa, AUICH_NABMBAR, PCI_MAPREG_TYPE_IO, 433 0, &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 434 printf(": can't map device i/o space\n"); 435 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 436 return; 437 } 438 } 439 sc->dmat = pa->pa_dmat; 440 sc->pci_id = pa->pa_id; 441 442 if (pci_intr_map(pa, &ih)) { 443 printf(": can't map interrupt\n"); 444 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 445 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 446 return; 447 } 448 intrstr = pci_intr_string(pa->pa_pc, ih); 449 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO | IPL_MPSAFE, 450 auich_intr, sc, sc->sc_dev.dv_xname); 451 if (!sc->sc_ih) { 452 printf(": can't establish interrupt"); 453 if (intrstr) 454 printf(" at %s", intrstr); 455 printf("\n"); 456 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 457 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 458 return; 459 } 460 461 for (i = nitems(auich_devices); i--;) 462 if (PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 463 break; 464 465 snprintf(sc->sc_audev.name, sizeof sc->sc_audev.name, "%s AC97", 466 auich_devices[i].name); 467 snprintf(sc->sc_audev.version, sizeof sc->sc_audev.version, "0x%02x", 468 PCI_REVISION(pa->pa_class)); 469 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, 470 sizeof sc->sc_audev.config); 471 472 printf(": %s, %s\n", intrstr, sc->sc_audev.name); 473 474 /* SiS 7012 needs special handling */ 475 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 476 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_7012_ACA) { 477 sc->sc_sts_reg = AUICH_PICB; 478 sc->sc_sample_size = 1; 479 sc->sc_pcm246_mask = AUICH_SIS_PCM246_MASK; 480 sc->sc_pcm2 = AUICH_SIS_PCM2; 481 sc->sc_pcm4 = AUICH_SIS_PCM4; 482 sc->sc_pcm6 = AUICH_SIS_PCM6; 483 /* un-mute output */ 484 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 485 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 486 ICH_SIS_CTL_UNMUTE); 487 } else { 488 sc->sc_sts_reg = AUICH_STS; 489 sc->sc_sample_size = 2; 490 sc->sc_pcm246_mask = AUICH_PCM246_MASK; 491 sc->sc_pcm2 = AUICH_PCM2; 492 sc->sc_pcm4 = AUICH_PCM4; 493 sc->sc_pcm6 = AUICH_PCM6; 494 } 495 496 /* Workaround for a 440MX B-stepping erratum */ 497 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 498 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 499 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_ACA) { 500 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 501 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 502 } 503 504 /* Set up DMA lists. */ 505 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 506 auich_alloc_cdata(sc); 507 508 DPRINTF(AUICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 509 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 510 511 /* Reset codec and AC'97 */ 512 auich_reset_codec(sc); 513 status = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 514 if (!(status & AUICH_PCR)) { /* reset failure */ 515 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 516 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 517 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 518 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 519 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 520 /* MSI 845G Max never return AUICH_PCR */ 521 sc->sc_ignore_codecready = 1; 522 } else { 523 printf("%s: reset failed!\n", sc->sc_dev.dv_xname); 524 return; 525 } 526 } 527 528 sc->host_if.arg = sc; 529 sc->host_if.attach = auich_attach_codec; 530 sc->host_if.read = auich_read_codec; 531 sc->host_if.write = auich_write_codec; 532 sc->host_if.reset = auich_reset_codec; 533 sc->host_if.flags = auich_flags_codec; 534 sc->host_if.spdif_event = auich_spdif_event; 535 if (sc->sc_dev.dv_cfdata->cf_flags & 0x0001) 536 sc->flags = AC97_HOST_SWAPPED_CHANNELS; 537 538 if (ac97_attach(&sc->host_if) != 0) { 539 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 540 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 541 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 542 return; 543 } 544 sc->codec_if->vtbl->unlock(sc->codec_if); 545 546 sc->audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 547 548 /* Watch for power changes */ 549 sc->suspend = DVACT_RESUME; 550 551 sc->sc_ac97rate = -1; 552 } 553 554 int 555 auich_activate(struct device *self, int act) 556 { 557 struct auich_softc *sc = (struct auich_softc *)self; 558 int rv = 0; 559 560 switch (act) { 561 case DVACT_RESUME: 562 auich_resume(sc); 563 rv = config_activate_children(self, act); 564 break; 565 case DVACT_DEACTIVATE: 566 if (sc->audiodev != NULL) 567 rv = config_deactivate(sc->audiodev); 568 break; 569 default: 570 rv = config_activate_children(self, act); 571 break; 572 } 573 return (rv); 574 } 575 576 int 577 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 578 { 579 struct auich_softc *sc = v; 580 int i; 581 582 /* wait for an access semaphore */ 583 for (i = AUICH_SEMATIMO; i-- && 584 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 585 586 if (!sc->sc_ignore_codecready && i < 0) { 587 DPRINTF(AUICH_DEBUG_CODECIO, 588 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 589 return (-1); 590 } 591 592 *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg); 593 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: read_codec(%x, %x)\n", 594 sc->sc_dev.dv_xname, reg, *val)); 595 return (0); 596 } 597 598 int 599 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 600 { 601 struct auich_softc *sc = v; 602 int i; 603 604 /* wait for an access semaphore */ 605 for (i = AUICH_SEMATIMO; i-- && 606 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 607 608 if (sc->sc_ignore_codecready || i >= 0) { 609 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: write_codec(%x, %x)\n", 610 sc->sc_dev.dv_xname, reg, val)); 611 bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val); 612 return (0); 613 } else { 614 DPRINTF(AUICH_DEBUG_CODECIO, 615 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 616 return (-1); 617 } 618 } 619 620 int 621 auich_attach_codec(void *v, struct ac97_codec_if *cif) 622 { 623 struct auich_softc *sc = v; 624 625 sc->codec_if = cif; 626 return 0; 627 } 628 629 void 630 auich_reset_codec(void *v) 631 { 632 struct auich_softc *sc = v; 633 u_int32_t control; 634 int i; 635 636 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 637 control &= ~(AUICH_ACLSO | sc->sc_pcm246_mask); 638 control |= (control & AUICH_CRESET) ? AUICH_WRESET : AUICH_CRESET; 639 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 640 641 for (i = AUICH_RESETIMO; i-- && 642 !(bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS) & AUICH_PCR); 643 DELAY(1)); 644 645 if (i < 0) 646 DPRINTF(AUICH_DEBUG_CODECIO, 647 ("%s: reset_codec timeout\n", sc->sc_dev.dv_xname)); 648 } 649 650 enum ac97_host_flags 651 auich_flags_codec(void *v) 652 { 653 struct auich_softc *sc = v; 654 655 return (sc->flags); 656 } 657 658 void 659 auich_spdif_event(void *v, int flag) 660 { 661 struct auich_softc *sc = v; 662 sc->sc_spdif = flag; 663 } 664 665 int 666 auich_open(void *v, int flags) 667 { 668 struct auich_softc *sc = v; 669 670 if (sc->sc_ac97rate == -1) 671 sc->sc_ac97rate = auich_calibrate(sc); 672 673 sc->codec_if->vtbl->lock(sc->codec_if); 674 675 return 0; 676 } 677 678 void 679 auich_close(void *v) 680 { 681 struct auich_softc *sc = v; 682 683 sc->codec_if->vtbl->unlock(sc->codec_if); 684 } 685 686 void 687 auich_get_default_params(void *addr, int mode, struct audio_params *params) 688 { 689 ac97_get_default_params(params); 690 } 691 692 int 693 auich_query_encoding(void *v, struct audio_encoding *aep) 694 { 695 struct auich_softc *sc = v; 696 if (sc->sc_spdif) { 697 switch (aep->index) { 698 case 0: 699 strlcpy(aep->name, AudioEslinear_le, sizeof aep->name); 700 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 701 aep->precision = 16; 702 aep->flags = 0; 703 aep->bps = 2; 704 aep->msb = 1; 705 return (0); 706 default: 707 return (EINVAL); 708 } 709 } else { 710 switch (aep->index) { 711 case 0: 712 strlcpy(aep->name, AudioEulinear, sizeof aep->name); 713 aep->encoding = AUDIO_ENCODING_ULINEAR; 714 aep->precision = 8; 715 aep->flags = 0; 716 break; 717 case 1: 718 strlcpy(aep->name, AudioEmulaw, sizeof aep->name); 719 aep->encoding = AUDIO_ENCODING_ULAW; 720 aep->precision = 8; 721 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 722 break; 723 case 2: 724 strlcpy(aep->name, AudioEalaw, sizeof aep->name); 725 aep->encoding = AUDIO_ENCODING_ALAW; 726 aep->precision = 8; 727 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 728 break; 729 case 3: 730 strlcpy(aep->name, AudioEslinear, sizeof aep->name); 731 aep->encoding = AUDIO_ENCODING_SLINEAR; 732 aep->precision = 8; 733 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 734 break; 735 case 4: 736 strlcpy(aep->name, AudioEslinear_le, sizeof aep->name); 737 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 738 aep->precision = 16; 739 aep->flags = 0; 740 break; 741 case 5: 742 strlcpy(aep->name, AudioEulinear_le, sizeof aep->name); 743 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 744 aep->precision = 16; 745 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 746 break; 747 case 6: 748 strlcpy(aep->name, AudioEslinear_be, sizeof aep->name); 749 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 750 aep->precision = 16; 751 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 752 break; 753 case 7: 754 strlcpy(aep->name, AudioEulinear_be, sizeof aep->name); 755 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 756 aep->precision = 16; 757 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 758 break; 759 default: 760 return (EINVAL); 761 } 762 aep->bps = AUDIO_BPS(aep->precision); 763 aep->msb = 1; 764 return (0); 765 } 766 } 767 768 int 769 auich_set_params(void *v, int setmode, int usemode, 770 struct audio_params *play, struct audio_params *rec) 771 { 772 struct auich_softc *sc = v; 773 struct ac97_codec_if *codec = sc->codec_if; 774 int error; 775 u_int orate; 776 u_int adj_rate; 777 u_int32_t control; 778 u_int16_t ext_id; 779 780 if (setmode & AUMODE_PLAY) { 781 /* only 16-bit 48kHz slinear_le if s/pdif enabled */ 782 if (sc->sc_spdif) { 783 play->sample_rate = 48000; 784 play->precision = 16; 785 play->encoding = AUDIO_ENCODING_SLINEAR_LE; 786 } 787 } 788 if (setmode & AUMODE_PLAY) { 789 play->factor = 1; 790 play->sw_code = NULL; 791 if (play->precision > 16) 792 play->precision = 16; 793 switch(play->encoding) { 794 case AUDIO_ENCODING_ULAW: 795 if (play->channels > 2) 796 play->channels = 2; 797 switch (play->channels) { 798 case 1: 799 play->factor = 4; 800 play->sw_code = mulaw_to_slinear16_le_mts; 801 break; 802 case 2: 803 play->factor = 2; 804 play->sw_code = mulaw_to_slinear16_le; 805 break; 806 default: 807 return (EINVAL); 808 } 809 break; 810 case AUDIO_ENCODING_SLINEAR_LE: 811 switch (play->precision) { 812 case 8: 813 if (play->channels > 2) 814 play->channels = 2; 815 switch (play->channels) { 816 case 1: 817 play->factor = 4; 818 play->sw_code = linear8_to_linear16_le_mts; 819 break; 820 case 2: 821 play->factor = 2; 822 play->sw_code = linear8_to_linear16_le; 823 break; 824 default: 825 return (EINVAL); 826 } 827 break; 828 case 16: 829 if (play->channels > 6) 830 play->channels = 6; 831 if (play->channels > 1) 832 play->channels &= ~1; 833 switch (play->channels) { 834 case 1: 835 play->factor = 2; 836 play->sw_code = noswap_bytes_mts; 837 break; 838 case 2: 839 break; 840 case 4: 841 ext_id = codec->vtbl->get_caps(codec); 842 if (!(ext_id & AC97_EXT_AUDIO_SDAC)) 843 play->channels = 2; 844 break; 845 case 6: 846 ext_id = codec->vtbl->get_caps(codec); 847 if ((ext_id & AC97_BITS_6CH) != 848 AC97_BITS_6CH) 849 play->channels = 2; 850 break; 851 default: 852 return (EINVAL); 853 } 854 break; 855 } 856 break; 857 case AUDIO_ENCODING_ULINEAR_LE: 858 if (play->channels > 2) 859 play->channels = 2; 860 switch (play->precision) { 861 case 8: 862 switch (play->channels) { 863 case 1: 864 play->factor = 4; 865 play->sw_code = ulinear8_to_linear16_le_mts; 866 break; 867 case 2: 868 play->factor = 2; 869 play->sw_code = ulinear8_to_linear16_le; 870 break; 871 default: 872 return (EINVAL); 873 } 874 break; 875 case 16: 876 switch (play->channels) { 877 case 1: 878 play->factor = 2; 879 play->sw_code = change_sign16_le_mts; 880 break; 881 case 2: 882 play->sw_code = change_sign16_le; 883 break; 884 default: 885 return (EINVAL); 886 } 887 break; 888 default: 889 return (EINVAL); 890 } 891 break; 892 case AUDIO_ENCODING_ALAW: 893 if (play->channels > 2) 894 play->channels = 2; 895 switch (play->channels) { 896 case 1: 897 play->factor = 4; 898 play->sw_code = alaw_to_slinear16_le_mts; 899 break; 900 case 2: 901 play->factor = 2; 902 play->sw_code = alaw_to_slinear16_le; 903 break; 904 default: 905 return (EINVAL); 906 } 907 break; 908 case AUDIO_ENCODING_SLINEAR_BE: 909 if (play->channels > 2) 910 play->channels = 2; 911 switch (play->precision) { 912 case 8: 913 switch (play->channels) { 914 case 1: 915 play->factor = 4; 916 play->sw_code = linear8_to_linear16_le_mts; 917 break; 918 case 2: 919 play->factor = 2; 920 play->sw_code = linear8_to_linear16_le; 921 break; 922 default: 923 return (EINVAL); 924 } 925 break; 926 case 16: 927 switch (play->channels) { 928 case 1: 929 play->factor = 2; 930 play->sw_code = swap_bytes_mts; 931 break; 932 case 2: 933 play->sw_code = swap_bytes; 934 break; 935 default: 936 return (EINVAL); 937 } 938 break; 939 default: 940 return (EINVAL); 941 } 942 break; 943 case AUDIO_ENCODING_ULINEAR_BE: 944 if (play->channels > 2) 945 play->channels = 2; 946 switch (play->precision) { 947 case 8: 948 switch (play->channels) { 949 case 1: 950 play->factor = 4; 951 play->sw_code = ulinear8_to_linear16_le_mts; 952 break; 953 case 2: 954 play->factor = 2; 955 play->sw_code = ulinear8_to_linear16_le; 956 break; 957 default: 958 return (EINVAL); 959 } 960 break; 961 case 16: 962 switch (play->channels) { 963 case 1: 964 play->factor = 2; 965 play->sw_code = swap_bytes_change_sign16_le_mts; 966 break; 967 case 2: 968 play->sw_code = swap_bytes_change_sign16_le; 969 break; 970 default: 971 return (EINVAL); 972 } 973 break; 974 default: 975 return (EINVAL); 976 } 977 break; 978 default: 979 return (EINVAL); 980 } 981 play->bps = AUDIO_BPS(play->precision); 982 play->msb = 1; 983 984 orate = adj_rate = play->sample_rate; 985 if (sc->sc_ac97rate != 0) 986 adj_rate = orate * AUICH_FIXED_RATE / sc->sc_ac97rate; 987 988 play->sample_rate = adj_rate; 989 sc->last_prate = play->sample_rate; 990 991 error = ac97_set_rate(sc->codec_if, 992 AC97_REG_PCM_LFE_DAC_RATE, &play->sample_rate); 993 if (error) 994 return (error); 995 996 play->sample_rate = adj_rate; 997 error = ac97_set_rate(sc->codec_if, 998 AC97_REG_PCM_SURR_DAC_RATE, &play->sample_rate); 999 if (error) 1000 return (error); 1001 1002 play->sample_rate = adj_rate; 1003 error = ac97_set_rate(sc->codec_if, 1004 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate); 1005 if (error) 1006 return (error); 1007 1008 if (play->sample_rate == adj_rate) 1009 play->sample_rate = orate; 1010 1011 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 1012 control &= ~(sc->sc_pcm246_mask); 1013 if (play->channels == 4) 1014 control |= sc->sc_pcm4; 1015 else if (play->channels == 6) 1016 control |= sc->sc_pcm6; 1017 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 1018 1019 sc->last_pchan = play->channels; 1020 } 1021 1022 if (setmode & AUMODE_RECORD) { 1023 rec->factor = 1; 1024 rec->sw_code = 0; 1025 if (rec->channels > 2) 1026 rec->channels = 2; 1027 if (rec->precision > 16) 1028 rec->precision = 16; 1029 switch(rec->encoding) { 1030 case AUDIO_ENCODING_ULAW: 1031 switch (rec->channels) { 1032 case 1: 1033 rec->sw_code = slinear16_to_mulaw_le_stm; 1034 rec->factor = 4; 1035 break; 1036 case 2: 1037 rec->sw_code = slinear16_to_mulaw_le; 1038 rec->factor = 2; 1039 break; 1040 } 1041 break; 1042 case AUDIO_ENCODING_ALAW: 1043 switch (rec->channels) { 1044 case 1: 1045 rec->sw_code = slinear16_to_alaw_le_stm; 1046 rec->factor = 4; 1047 break; 1048 case 2: 1049 rec->sw_code = slinear16_to_alaw_le; 1050 rec->factor = 2; 1051 break; 1052 } 1053 break; 1054 case AUDIO_ENCODING_SLINEAR_LE: 1055 switch (rec->precision) { 1056 case 8: 1057 switch (rec->channels) { 1058 case 1: 1059 rec->sw_code = linear16_to_linear8_le_stm; 1060 rec->factor = 4; 1061 break; 1062 case 2: 1063 rec->sw_code = linear16_to_linear8_le; 1064 rec->factor = 2; 1065 break; 1066 } 1067 break; 1068 case 16: 1069 switch (rec->channels) { 1070 case 1: 1071 rec->sw_code = linear16_decimator; 1072 rec->factor = 2; 1073 break; 1074 case 2: 1075 break; 1076 } 1077 break; 1078 default: 1079 return (EINVAL); 1080 } 1081 break; 1082 case AUDIO_ENCODING_ULINEAR_LE: 1083 switch (rec->precision) { 1084 case 8: 1085 switch (rec->channels) { 1086 case 1: 1087 rec->sw_code = linear16_to_ulinear8_le_stm; 1088 rec->factor = 4; 1089 break; 1090 case 2: 1091 rec->sw_code = linear16_to_ulinear8_le; 1092 rec->factor = 2; 1093 break; 1094 } 1095 break; 1096 case 16: 1097 switch (rec->channels) { 1098 case 1: 1099 rec->sw_code = change_sign16_le_stm; 1100 rec->factor = 2; 1101 break; 1102 case 2: 1103 rec->sw_code = change_sign16_le; 1104 break; 1105 } 1106 break; 1107 default: 1108 return (EINVAL); 1109 } 1110 break; 1111 case AUDIO_ENCODING_SLINEAR_BE: 1112 switch (rec->precision) { 1113 case 8: 1114 switch (rec->channels) { 1115 case 1: 1116 rec->sw_code = linear16_to_linear8_le_stm; 1117 rec->factor = 4; 1118 break; 1119 case 2: 1120 rec->sw_code = linear16_to_linear8_le; 1121 rec->factor = 2; 1122 break; 1123 } 1124 break; 1125 case 16: 1126 switch (rec->channels) { 1127 case 1: 1128 rec->sw_code = swap_bytes_stm; 1129 rec->factor = 2; 1130 break; 1131 case 2: 1132 rec->sw_code = swap_bytes; 1133 break; 1134 } 1135 break; 1136 default: 1137 return (EINVAL); 1138 } 1139 break; 1140 case AUDIO_ENCODING_ULINEAR_BE: 1141 switch (rec->precision) { 1142 case 8: 1143 switch (rec->channels) { 1144 case 1: 1145 rec->sw_code = linear16_to_ulinear8_le_stm; 1146 rec->factor = 4; 1147 break; 1148 case 2: 1149 rec->sw_code = linear16_to_ulinear8_le; 1150 rec->factor = 2; 1151 break; 1152 } 1153 break; 1154 case 16: 1155 switch (rec->channels) { 1156 case 1: 1157 rec->sw_code = change_sign16_swap_bytes_le_stm; 1158 rec->factor = 2; 1159 break; 1160 case 2: 1161 rec->sw_code = change_sign16_swap_bytes_le; 1162 break; 1163 } 1164 break; 1165 default: 1166 return (EINVAL); 1167 } 1168 break; 1169 default: 1170 return (EINVAL); 1171 } 1172 rec->bps = AUDIO_BPS(rec->precision); 1173 rec->msb = 1; 1174 1175 orate = rec->sample_rate; 1176 if (sc->sc_ac97rate != 0) 1177 rec->sample_rate = orate * AUICH_FIXED_RATE / 1178 sc->sc_ac97rate; 1179 sc->last_rrate = rec->sample_rate; 1180 error = ac97_set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1181 &rec->sample_rate); 1182 if (error) 1183 return (error); 1184 rec->sample_rate = orate; 1185 } 1186 1187 return (0); 1188 } 1189 1190 int 1191 auich_round_blocksize(void *v, int blk) 1192 { 1193 return (blk + 0x3f) & ~0x3f; 1194 } 1195 1196 1197 void 1198 auich_halt_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1199 { 1200 int i; 1201 uint32_t sts; 1202 1203 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 0); 1204 1205 /* wait for DMA halted and clear interrupt / event bits if needed */ 1206 for (i = 0; i < 1000; i++) { 1207 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1208 pipe + sc->sc_sts_reg); 1209 if (sts & (AUICH_CELV | AUICH_LVBCI | AUICH_BCIS | AUICH_FIFOE)) 1210 bus_space_write_2(sc->iot, sc->aud_ioh, 1211 pipe + sc->sc_sts_reg, 1212 AUICH_CELV | AUICH_LVBCI | 1213 AUICH_BCIS | AUICH_FIFOE); 1214 if (sts & AUICH_DCH) 1215 break; 1216 DELAY(100); 1217 } 1218 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, AUICH_RR); 1219 1220 if (i > 0) 1221 DPRINTF(AUICH_DEBUG_DMA, 1222 ("auich_halt_pipe: halt took %d cycles\n", i)); 1223 1224 ring->running = 0; 1225 } 1226 1227 1228 int 1229 auich_halt_output(void *v) 1230 { 1231 struct auich_softc *sc = v; 1232 1233 DPRINTF(AUICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1234 1235 mtx_enter(&audio_lock); 1236 auich_halt_pipe(sc, AUICH_PCMO, &sc->pcmo); 1237 1238 sc->pcmo.intr = NULL; 1239 mtx_leave(&audio_lock); 1240 return 0; 1241 } 1242 1243 int 1244 auich_halt_input(void *v) 1245 { 1246 struct auich_softc *sc = v; 1247 1248 DPRINTF(AUICH_DEBUG_DMA, 1249 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1250 1251 /* XXX halt both unless known otherwise */ 1252 mtx_enter(&audio_lock); 1253 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1254 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1255 1256 sc->pcmi.intr = NULL; 1257 mtx_leave(&audio_lock); 1258 return 0; 1259 } 1260 1261 int 1262 auich_getdev(void *v, struct audio_device *adp) 1263 { 1264 struct auich_softc *sc = v; 1265 *adp = sc->sc_audev; 1266 return 0; 1267 } 1268 1269 int 1270 auich_set_port(void *v, mixer_ctrl_t *cp) 1271 { 1272 struct auich_softc *sc = v; 1273 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1274 } 1275 1276 int 1277 auich_get_port(void *v, mixer_ctrl_t *cp) 1278 { 1279 struct auich_softc *sc = v; 1280 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1281 } 1282 1283 int 1284 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1285 { 1286 struct auich_softc *sc = v; 1287 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1288 } 1289 1290 void * 1291 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 1292 { 1293 struct auich_softc *sc = v; 1294 struct auich_dma *p; 1295 int error; 1296 1297 /* can only use 1 segment */ 1298 if (size > AUICH_DMASEG_MAX) { 1299 DPRINTF(AUICH_DEBUG_DMA, 1300 ("%s: requested buffer size too large: %zd", \ 1301 sc->sc_dev.dv_xname, size)); 1302 return NULL; 1303 } 1304 1305 p = malloc(sizeof(*p), pool, flags | M_ZERO); 1306 if (!p) 1307 return NULL; 1308 1309 error = auich_allocmem(sc, size, PAGE_SIZE, p); 1310 if (error) { 1311 free(p, pool, 0); 1312 return NULL; 1313 } 1314 1315 if (direction == AUMODE_PLAY) 1316 sc->sc_pdma = p; 1317 else if (direction == AUMODE_RECORD) 1318 sc->sc_rdma = p; 1319 else 1320 sc->sc_cdma = p; 1321 1322 return p->addr; 1323 } 1324 1325 void 1326 auich_freem(void *v, void *ptr, int pool) 1327 { 1328 struct auich_softc *sc; 1329 struct auich_dma *p; 1330 1331 sc = v; 1332 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == ptr) 1333 p = sc->sc_pdma; 1334 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == ptr) 1335 p = sc->sc_rdma; 1336 else if (sc->sc_cdma != NULL && sc->sc_cdma->addr == ptr) 1337 p = sc->sc_cdma; 1338 else 1339 return; 1340 1341 auich_freemem(sc, p); 1342 free(p, pool, 0); 1343 } 1344 1345 size_t 1346 auich_round_buffersize(void *v, int direction, size_t size) 1347 { 1348 if (size > AUICH_DMALIST_MAX * AUICH_DMASEG_MAX) 1349 size = AUICH_DMALIST_MAX * AUICH_DMASEG_MAX; 1350 1351 return size; 1352 } 1353 1354 paddr_t 1355 auich_mappage(void *v, void *mem, off_t off, int prot) 1356 { 1357 struct auich_softc *sc = v; 1358 struct auich_dma *p; 1359 1360 if (off < 0) 1361 return -1; 1362 1363 p = NULL; 1364 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == mem) 1365 p = sc->sc_pdma; 1366 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == mem) 1367 p = sc->sc_rdma; 1368 else 1369 return -1; 1370 1371 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1372 off, prot, BUS_DMA_WAITOK); 1373 } 1374 1375 int 1376 auich_get_props(void *v) 1377 { 1378 return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1379 } 1380 1381 int 1382 auich_intr(void *v) 1383 { 1384 struct auich_softc *sc = v; 1385 int ret = 0, sts, gsts; 1386 1387 mtx_enter(&audio_lock); 1388 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 1389 DPRINTF(AUICH_DEBUG_INTR, ("auich_intr: gsts=%b\n", gsts, AUICH_GSTS_BITS)); 1390 1391 if (gsts & AUICH_POINT) { 1392 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1393 AUICH_PCMO + sc->sc_sts_reg); 1394 DPRINTF(AUICH_DEBUG_INTR, 1395 ("auich_intr: osts=%b\n", sts, AUICH_ISTS_BITS)); 1396 1397 #ifdef AUICH_DEBUG 1398 if (sts & AUICH_FIFOE) { 1399 printf("%s: in fifo underrun # %u civ=%u ctrl=0x%x sts=%b\n", 1400 sc->sc_dev.dv_xname, sc->pcmo_fifoe++, 1401 bus_space_read_1(sc->iot, sc->aud_ioh, 1402 AUICH_PCMO + AUICH_CIV), 1403 bus_space_read_1(sc->iot, sc->aud_ioh, 1404 AUICH_PCMO + AUICH_CTRL), 1405 bus_space_read_2(sc->iot, sc->aud_ioh, 1406 AUICH_PCMO + sc->sc_sts_reg), 1407 AUICH_ISTS_BITS); 1408 } 1409 #endif 1410 1411 if (sts & AUICH_BCIS) 1412 auich_intr_pipe(sc, AUICH_PCMO, &sc->pcmo); 1413 1414 /* int ack */ 1415 bus_space_write_2(sc->iot, sc->aud_ioh, 1416 AUICH_PCMO + sc->sc_sts_reg, sts & 1417 (AUICH_BCIS | AUICH_FIFOE)); 1418 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_POINT); 1419 ret++; 1420 } 1421 1422 if (gsts & AUICH_PIINT) { 1423 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1424 AUICH_PCMI + sc->sc_sts_reg); 1425 DPRINTF(AUICH_DEBUG_INTR, 1426 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1427 1428 #ifdef AUICH_DEBUG 1429 if (sts & AUICH_FIFOE) { 1430 printf("%s: in fifo overrun # %u civ=%u ctrl=0x%x sts=%b\n", 1431 sc->sc_dev.dv_xname, sc->pcmi_fifoe++, 1432 bus_space_read_1(sc->iot, sc->aud_ioh, 1433 AUICH_PCMI + AUICH_CIV), 1434 bus_space_read_1(sc->iot, sc->aud_ioh, 1435 AUICH_PCMI + AUICH_CTRL), 1436 bus_space_read_2(sc->iot, sc->aud_ioh, 1437 AUICH_PCMI + sc->sc_sts_reg), 1438 AUICH_ISTS_BITS); 1439 } 1440 #endif 1441 1442 if (sts & AUICH_BCIS) 1443 auich_intr_pipe(sc, AUICH_PCMI, &sc->pcmi); 1444 1445 /* int ack */ 1446 bus_space_write_2(sc->iot, sc->aud_ioh, 1447 AUICH_PCMI + sc->sc_sts_reg, sts & 1448 (AUICH_BCIS | AUICH_FIFOE)); 1449 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_PIINT); 1450 ret++; 1451 } 1452 1453 if (gsts & AUICH_MINT) { 1454 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1455 AUICH_MICI + sc->sc_sts_reg); 1456 DPRINTF(AUICH_DEBUG_INTR, 1457 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1458 #ifdef AUICH_DEBUG 1459 if (sts & AUICH_FIFOE) { 1460 printf("%s: in fifo overrun civ=%u ctrl=0x%x sts=%b\n", 1461 sc->sc_dev.dv_xname, 1462 bus_space_read_1(sc->iot, sc->aud_ioh, 1463 AUICH_MICI + AUICH_CIV), 1464 bus_space_read_1(sc->iot, sc->aud_ioh, 1465 AUICH_MICI + AUICH_CTRL), 1466 bus_space_read_2(sc->iot, sc->aud_ioh, 1467 AUICH_MICI + sc->sc_sts_reg), 1468 AUICH_ISTS_BITS); 1469 } 1470 #endif 1471 if (sts & AUICH_BCIS) 1472 auich_intr_pipe(sc, AUICH_MICI, &sc->mici); 1473 1474 /* int ack */ 1475 bus_space_write_2(sc->iot, sc->aud_ioh, 1476 AUICH_MICI + sc->sc_sts_reg, 1477 sts + (AUICH_BCIS | AUICH_FIFOE)); 1478 1479 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_MINT); 1480 ret++; 1481 } 1482 mtx_leave(&audio_lock); 1483 return ret; 1484 } 1485 1486 1487 void 1488 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1489 { 1490 int blksize, qptr, oqptr; 1491 struct auich_dmalist *q; 1492 1493 blksize = ring->blksize; 1494 qptr = oqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1495 1496 /* XXX remove this when no one reports problems */ 1497 if(oqptr >= AUICH_DMALIST_MAX) { 1498 printf("%s: Unexpected CIV: %d\n", sc->sc_dev.dv_xname, oqptr); 1499 qptr = oqptr = 0; 1500 } 1501 1502 do { 1503 q = &ring->dmalist[qptr]; 1504 q->base = ring->p; 1505 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1506 1507 DPRINTF(AUICH_DEBUG_INTR, 1508 ("auich_trigger_pipe: %p, %p = %x @ 0x%x qptr=%d\n", 1509 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1510 1511 ring->p += blksize; 1512 if (ring->p >= ring->end) 1513 ring->p = ring->start; 1514 1515 qptr = (qptr + 1) & AUICH_LVI_MASK; 1516 } while (qptr != oqptr); 1517 1518 ring->qptr = qptr; 1519 1520 DPRINTF(AUICH_DEBUG_DMA, 1521 ("auich_trigger_pipe: qptr=%d\n", qptr)); 1522 1523 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1524 (qptr - 1) & AUICH_LVI_MASK); 1525 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 1526 AUICH_IOCE | AUICH_FEIE | AUICH_RPBM); 1527 1528 ring->running = 1; 1529 } 1530 1531 void 1532 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1533 { 1534 int blksize, qptr, nqptr; 1535 struct auich_dmalist *q; 1536 1537 blksize = ring->blksize; 1538 qptr = ring->qptr; 1539 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1540 1541 while (qptr != nqptr) { 1542 q = &ring->dmalist[qptr]; 1543 q->base = ring->p; 1544 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1545 1546 DPRINTF(AUICH_DEBUG_INTR, 1547 ("auich_intr: %p, %p = %x @ 0x%x qptr=%d\n", 1548 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1549 1550 ring->p += blksize; 1551 if (ring->p >= ring->end) 1552 ring->p = ring->start; 1553 1554 qptr = (qptr + 1) & AUICH_LVI_MASK; 1555 if (ring->intr) 1556 ring->intr(ring->arg); 1557 else 1558 printf("auich_intr: got progress with intr==NULL\n"); 1559 1560 ring->ap += blksize; 1561 if (ring->ap >= ring->size) 1562 ring->ap = 0; 1563 } 1564 ring->qptr = qptr; 1565 1566 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1567 (qptr - 1) & AUICH_LVI_MASK); 1568 } 1569 1570 1571 int 1572 auich_trigger_output(void *v, void *start, void *end, int blksize, 1573 void (*intr)(void *), void *arg, struct audio_params *param) 1574 { 1575 struct auich_softc *sc = v; 1576 struct auich_dma *p; 1577 size_t size; 1578 #ifdef AUICH_DEBUG 1579 uint16_t sts; 1580 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1581 AUICH_PCMO + sc->sc_sts_reg); 1582 DPRINTF(AUICH_DEBUG_DMA, 1583 ("auich_trigger_output(%p, %p, %d, %p, %p, %p) sts=%b\n", 1584 start, end, blksize, intr, arg, param, sts, AUICH_ISTS_BITS)); 1585 #endif 1586 1587 if (sc->sc_pdma->addr == start) 1588 p = sc->sc_pdma; 1589 else 1590 return -1; 1591 1592 size = (size_t)((caddr_t)end - (caddr_t)start); 1593 sc->pcmo.size = size; 1594 sc->pcmo.intr = intr; 1595 sc->pcmo.arg = arg; 1596 1597 /* 1598 * The logic behind this is: 1599 * setup one buffer to play, then LVI dump out the rest 1600 * to the scatter-gather chain. 1601 */ 1602 sc->pcmo.start = p->segs->ds_addr; 1603 sc->pcmo.p = sc->pcmo.start; 1604 sc->pcmo.end = sc->pcmo.start + size; 1605 sc->pcmo.blksize = blksize; 1606 1607 mtx_enter(&audio_lock); 1608 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMO + AUICH_BDBAR, 1609 sc->sc_cddma + AUICH_PCMO_OFF(0)); 1610 auich_trigger_pipe(sc, AUICH_PCMO, &sc->pcmo); 1611 mtx_leave(&audio_lock); 1612 return 0; 1613 } 1614 1615 int 1616 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1617 void *v; 1618 void *start, *end; 1619 int blksize; 1620 void (*intr)(void *); 1621 void *arg; 1622 struct audio_params *param; 1623 { 1624 struct auich_softc *sc = v; 1625 struct auich_dma *p; 1626 size_t size; 1627 1628 #ifdef AUICH_DEBUG 1629 DPRINTF(AUICH_DEBUG_DMA, 1630 ("auich_trigger_input(%p, %p, %d, %p, %p, %p) sts=%b\n", 1631 start, end, blksize, intr, arg, param, 1632 bus_space_read_2(sc->iot, sc->aud_ioh, 1633 AUICH_PCMI + sc->sc_sts_reg), 1634 AUICH_ISTS_BITS)); 1635 #endif 1636 if (sc->sc_rdma->addr == start) 1637 p = sc->sc_rdma; 1638 else 1639 return -1; 1640 1641 size = (size_t)((caddr_t)end - (caddr_t)start); 1642 sc->pcmi.size = size; 1643 sc->pcmi.intr = intr; 1644 sc->pcmi.arg = arg; 1645 1646 /* 1647 * The logic behind this is: 1648 * setup one buffer to play, then LVI dump out the rest 1649 * to the scatter-gather chain. 1650 */ 1651 sc->pcmi.start = p->segs->ds_addr; 1652 sc->pcmi.p = sc->pcmi.start; 1653 sc->pcmi.end = sc->pcmi.start + size; 1654 sc->pcmi.blksize = blksize; 1655 mtx_enter(&audio_lock); 1656 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1657 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1658 auich_trigger_pipe(sc, AUICH_PCMI, &sc->pcmi); 1659 mtx_leave(&audio_lock); 1660 return 0; 1661 } 1662 1663 1664 int 1665 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1666 struct auich_dma *p) 1667 { 1668 int error; 1669 1670 p->size = size; 1671 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, p->segs, 1, 1672 &p->nsegs, BUS_DMA_NOWAIT); 1673 if (error) { 1674 DPRINTF(AUICH_DEBUG_DMA, 1675 ("%s: bus_dmamem_alloc failed: error %d\n", 1676 sc->sc_dev.dv_xname, error)); 1677 return error; 1678 } 1679 1680 error = bus_dmamem_map(sc->dmat, p->segs, 1, p->size, &p->addr, 1681 BUS_DMA_NOWAIT | sc->sc_dmamap_flags); 1682 if (error) { 1683 DPRINTF(AUICH_DEBUG_DMA, 1684 ("%s: bus_dmamem_map failed: error %d\n", 1685 sc->sc_dev.dv_xname, error)); 1686 goto free; 1687 } 1688 1689 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 0, 1690 BUS_DMA_NOWAIT, &p->map); 1691 if (error) { 1692 DPRINTF(AUICH_DEBUG_DMA, 1693 ("%s: bus_dmamap_create failed: error %d\n", 1694 sc->sc_dev.dv_xname, error)); 1695 goto unmap; 1696 } 1697 1698 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1699 BUS_DMA_NOWAIT); 1700 if (error) { 1701 DPRINTF(AUICH_DEBUG_DMA, 1702 ("%s: bus_dmamap_load failed: error %d\n", 1703 sc->sc_dev.dv_xname, error)); 1704 goto destroy; 1705 } 1706 return 0; 1707 1708 destroy: 1709 bus_dmamap_destroy(sc->dmat, p->map); 1710 unmap: 1711 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1712 free: 1713 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1714 return error; 1715 } 1716 1717 1718 int 1719 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1720 { 1721 bus_dmamap_unload(sc->dmat, p->map); 1722 bus_dmamap_destroy(sc->dmat, p->map); 1723 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1724 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1725 return 0; 1726 } 1727 1728 1729 1730 int 1731 auich_alloc_cdata(struct auich_softc *sc) 1732 { 1733 bus_dma_segment_t seg; 1734 int error, rseg; 1735 1736 /* 1737 * Allocate the control data structure, and create and load the 1738 * DMA map for it. 1739 */ 1740 if ((error = bus_dmamem_alloc(sc->dmat, sizeof(struct auich_cdata), 1741 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1742 printf("%s: unable to allocate control data, error = %d\n", 1743 sc->sc_dev.dv_xname, error); 1744 goto fail_0; 1745 } 1746 1747 if ((error = bus_dmamem_map(sc->dmat, &seg, 1, 1748 sizeof(struct auich_cdata), (caddr_t *) &sc->sc_cdata, 1749 sc->sc_dmamap_flags)) != 0) { 1750 printf("%s: unable to map control data, error = %d\n", 1751 sc->sc_dev.dv_xname, error); 1752 goto fail_1; 1753 } 1754 1755 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1756 sizeof(struct auich_cdata), 0, 0, &sc->sc_cddmamap)) != 0) { 1757 printf("%s: unable to create control data DMA map, " 1758 "error = %d\n", sc->sc_dev.dv_xname, error); 1759 goto fail_2; 1760 } 1761 1762 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, sc->sc_cdata, 1763 sizeof(struct auich_cdata), NULL, 0)) != 0) { 1764 printf("%s: unable tp load control data DMA map, " 1765 "error = %d\n", sc->sc_dev.dv_xname, error); 1766 goto fail_3; 1767 } 1768 1769 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1770 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1771 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1772 1773 return 0; 1774 1775 fail_3: 1776 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1777 fail_2: 1778 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1779 sizeof(struct auich_cdata)); 1780 fail_1: 1781 bus_dmamem_free(sc->dmat, &seg, rseg); 1782 fail_0: 1783 return error; 1784 } 1785 1786 int 1787 auich_resume(struct auich_softc *sc) 1788 { 1789 /* SiS 7012 needs special handling */ 1790 if (PCI_VENDOR(sc->pci_id) == PCI_VENDOR_SIS && 1791 PCI_PRODUCT(sc->pci_id) == PCI_PRODUCT_SIS_7012_ACA) { 1792 /* un-mute output */ 1793 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 1794 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 1795 ICH_SIS_CTL_UNMUTE); 1796 } 1797 1798 ac97_resume(&sc->host_if, sc->codec_if); 1799 1800 return (0); 1801 } 1802 1803 /* -------------------------------------------------------------------- */ 1804 /* Calibrate card (some boards are overclocked and need scaling) */ 1805 1806 unsigned int 1807 auich_calibrate(struct auich_softc *sc) 1808 { 1809 struct timeval t1, t2; 1810 u_int8_t civ, ociv; 1811 uint16_t sts, osts; 1812 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1813 void *temp_buffer; 1814 struct auich_dma *p; 1815 1816 ac97rate = AUICH_FIXED_RATE; 1817 /* 1818 * Grab audio from input for fixed interval and compare how 1819 * much we actually get with what we expect. Interval needs 1820 * to be sufficiently short that no interrupts are 1821 * generated. 1822 * XXX: Is this true? We don't request any interrupts, 1823 * so why should the chip issue any? 1824 */ 1825 1826 /* Setup a buffer */ 1827 bytes = 16000; 1828 temp_buffer = auich_allocm(sc, 0, bytes, M_DEVBUF, M_NOWAIT); 1829 if (temp_buffer == NULL) 1830 return (ac97rate); 1831 if (sc->sc_cdma->addr == temp_buffer) { 1832 p = sc->sc_cdma; 1833 } else { 1834 printf("auich_calibrate: bad address %p\n", temp_buffer); 1835 return (ac97rate); 1836 } 1837 1838 /* get current CIV (usually 0 after reboot) */ 1839 ociv = civ = bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CIV); 1840 sc->pcmi.dmalist[civ].base = p->map->dm_segs[0].ds_addr; 1841 sc->pcmi.dmalist[civ].len = bytes / sc->sc_sample_size; 1842 1843 1844 /* 1845 * our data format is stereo, 16 bit so each sample is 4 bytes. 1846 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1847 * we're going to start recording with interrupts disabled and measure 1848 * the time taken for one block to complete. we know the block size, 1849 * we know the time in microseconds, we calculate the sample rate: 1850 * 1851 * actual_rate [bps] = bytes / (time [s] * 4) 1852 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1853 * actual_rate [Hz] = (bytes * 250000) / time [us] 1854 */ 1855 1856 /* prepare */ 1857 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1858 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1859 /* we got only one valid sample, so set LVI to CIV 1860 * otherwise we provoke a AUICH_FIFOE FIFO error 1861 * which will confuse the chip later on. */ 1862 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_LVI, 1863 civ & AUICH_LVI_MASK); 1864 1865 /* start, but don't request any interupts */ 1866 microuptime(&t1); 1867 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CTRL, 1868 AUICH_RPBM); 1869 1870 /* XXX remove this sometime */ 1871 osts = bus_space_read_2(sc->iot, sc->aud_ioh, 1872 AUICH_PCMI + sc->sc_sts_reg); 1873 /* wait */ 1874 while(1) { 1875 microuptime(&t2); 1876 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1877 AUICH_PCMI + sc->sc_sts_reg); 1878 civ = bus_space_read_1(sc->iot, sc->aud_ioh, 1879 AUICH_PCMI + AUICH_CIV); 1880 1881 /* turn time delta into us */ 1882 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + 1883 t2.tv_usec - t1.tv_usec; 1884 1885 /* this should actually never happen because civ==lvi */ 1886 if ((civ & AUICH_LVI_MASK) != (ociv & AUICH_LVI_MASK)) { 1887 printf("%s: ac97 CIV progressed after %d us sts=%b civ=%u\n", 1888 sc->sc_dev.dv_xname, wait_us, sts, 1889 AUICH_ISTS_BITS, civ); 1890 ociv = civ; 1891 } 1892 /* normal completion */ 1893 if (sts & (AUICH_DCH | AUICH_CELV | AUICH_LVBCI)) 1894 break; 1895 /* 1896 * check for strange changes in STS - 1897 * XXX remove it when everythings fine 1898 */ 1899 if (sts != osts) { 1900 printf("%s: ac97 sts changed after %d us sts=%b civ=%u\n", 1901 sc->sc_dev.dv_xname, wait_us, sts, 1902 AUICH_ISTS_BITS, civ); 1903 osts = sts; 1904 } 1905 /* 1906 * timeout: we expect 83333 us for 48k sampling rate, 1907 * 600000 us will be enough even for 8k sampling rate 1908 */ 1909 if (wait_us > 600000) { 1910 printf("%s: ac97 link rate timed out %d us sts=%b civ=%u\n", 1911 sc->sc_dev.dv_xname, wait_us, sts, 1912 AUICH_ISTS_BITS, civ); 1913 /* reset and clean up*/ 1914 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1915 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1916 auich_freem(sc, temp_buffer, M_DEVBUF); 1917 /* return default sample rate */ 1918 return (ac97rate); 1919 } 1920 } 1921 1922 DPRINTF(AUICH_DEBUG_CODECIO, 1923 ("%s: ac97 link rate calibration took %d us sts=%b civ=%u\n", 1924 sc->sc_dev.dv_xname, wait_us, sts, AUICH_ISTS_BITS, civ)); 1925 1926 /* reset and clean up */ 1927 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1928 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1929 auich_freem(sc, temp_buffer, M_DEVBUF); 1930 1931 #ifdef AUICH_DEBUG 1932 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1933 AUICH_PCMI + sc->sc_sts_reg); 1934 civ = bus_space_read_4(sc->iot, sc->aud_ioh, 1935 AUICH_PCMI + AUICH_CIV); 1936 printf("%s: after calibration and reset sts=%b civ=%u\n", 1937 sc->sc_dev.dv_xname, sts, AUICH_ISTS_BITS, civ); 1938 #endif 1939 1940 /* now finally calculate measured samplerate */ 1941 actual_48k_rate = (bytes * 250000) / wait_us; 1942 1943 if (actual_48k_rate <= 48500) 1944 ac97rate = AUICH_FIXED_RATE; 1945 else 1946 ac97rate = actual_48k_rate; 1947 1948 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: measured ac97 link rate at %d Hz", 1949 sc->sc_dev.dv_xname, actual_48k_rate)); 1950 if (ac97rate != actual_48k_rate) 1951 DPRINTF(AUICH_DEBUG_CODECIO, (", will use %d Hz", ac97rate)); 1952 DPRINTF(AUICH_DEBUG_CODECIO, ("\n")); 1953 1954 return (ac97rate); 1955 } 1956