1 /* $OpenBSD: auich.c,v 1.96 2012/01/11 16:22:33 dhill Exp $ */ 2 3 /* 4 * Copyright (c) 2000,2001 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * AC'97 audio found on Intel 810/815/820/440MX chipsets. 31 * http://developer.intel.com/design/chipsets/datashts/290655.htm 32 * http://developer.intel.com/design/chipsets/manuals/298028.htm 33 * http://www.intel.com/design/chipsets/datashts/290714.htm 34 * http://www.intel.com/design/chipsets/datashts/290744.htm 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <sys/audioio.h> 47 #include <dev/audio_if.h> 48 #include <dev/mulaw.h> 49 #include <dev/auconv.h> 50 51 #include <machine/bus.h> 52 53 #include <dev/ic/ac97.h> 54 55 /* 12.1.10 NAMBAR - native audio mixer base address register */ 56 #define AUICH_NAMBAR 0x10 57 /* 12.1.11 NABMBAR - native audio bus mastering base address register */ 58 #define AUICH_NABMBAR 0x14 59 #define AUICH_CFG 0x41 60 #define AUICH_CFG_IOSE 0x01 61 /* ICH4/ICH5/ICH6/ICH7 native audio mixer BAR */ 62 #define AUICH_MMBAR 0x18 63 /* ICH4/ICH5/ICH6/ICH7 native bus mastering BAR */ 64 #define AUICH_MBBAR 0x1c 65 #define AUICH_S2CR 0x10000000 /* tertiary codec ready */ 66 67 /* table 12-3. native audio bus master control registers */ 68 #define AUICH_BDBAR 0x00 /* 8-byte aligned address */ 69 #define AUICH_CIV 0x04 /* 5 bits current index value */ 70 #define AUICH_LVI 0x05 /* 5 bits last valid index value */ 71 #define AUICH_LVI_MASK 0x1f 72 #define AUICH_STS 0x06 /* 16 bits status */ 73 #define AUICH_FIFOE 0x10 /* fifo error */ 74 #define AUICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */ 75 #define AUICH_LVBCI 0x04 /* r- last valid bci, wr ack */ 76 #define AUICH_CELV 0x02 /* current equals last valid */ 77 #define AUICH_DCH 0x01 /* dma halted */ 78 #define AUICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe" 79 #define AUICH_PICB 0x08 /* 16 bits */ 80 #define AUICH_PIV 0x0a /* 5 bits prefetched index value */ 81 #define AUICH_CTRL 0x0b /* control */ 82 #define AUICH_IOCE 0x10 /* int on completion enable */ 83 #define AUICH_FEIE 0x08 /* fifo error int enable */ 84 #define AUICH_LVBIE 0x04 /* last valid buf int enable */ 85 #define AUICH_RR 0x02 /* 1 - reset regs */ 86 #define AUICH_RPBM 0x01 /* 1 - run, 0 - pause */ 87 88 #define AUICH_PCMI 0x00 89 #define AUICH_PCMO 0x10 90 #define AUICH_MICI 0x20 91 92 #define AUICH_GCTRL 0x2c 93 #define AUICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */ 94 #define AUICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */ 95 #define AUICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */ 96 #define AUICH_POM16 0x000000 /* PCM out precision 16bit */ 97 #define AUICH_POM20 0x400000 /* PCM out precision 20bit */ 98 #define AUICH_PCM246_MASK 0x300000 99 #define AUICH_PCM2 0x000000 /* 2ch output */ 100 #define AUICH_PCM4 0x100000 /* 4ch output */ 101 #define AUICH_PCM6 0x200000 /* 6ch output */ 102 #define AUICH_SIS_PCM246_MASK 0x0000c0 /* SiS 7012 */ 103 #define AUICH_SIS_PCM2 0x000000 /* SiS 7012 2ch output */ 104 #define AUICH_SIS_PCM4 0x000040 /* SiS 7012 4ch output */ 105 #define AUICH_SIS_PCM6 0x000080 /* SiS 7012 6ch output */ 106 #define AUICH_S2RIE 0x40 /* int when tertiary codec resume */ 107 #define AUICH_SRIE 0x20 /* int when 2ndary codec resume */ 108 #define AUICH_PRIE 0x10 /* int when primary codec resume */ 109 #define AUICH_ACLSO 0x08 /* aclink shut off */ 110 #define AUICH_WRESET 0x04 /* warm reset */ 111 #define AUICH_CRESET 0x02 /* cold reset */ 112 #define AUICH_GIE 0x01 /* gpi int enable */ 113 #define AUICH_GSTS 0x30 114 #define AUICH_MD3 0x20000 /* pwr-dn semaphore for modem */ 115 #define AUICH_AD3 0x10000 /* pwr-dn semaphore for audio */ 116 #define AUICH_RCS 0x08000 /* read completion status */ 117 #define AUICH_B3S12 0x04000 /* bit 3 of slot 12 */ 118 #define AUICH_B2S12 0x02000 /* bit 2 of slot 12 */ 119 #define AUICH_B1S12 0x01000 /* bit 1 of slot 12 */ 120 #define AUICH_SRI 0x00800 /* secondary resume int */ 121 #define AUICH_PRI 0x00400 /* primary resume int */ 122 #define AUICH_SCR 0x00200 /* secondary codec ready */ 123 #define AUICH_PCR 0x00100 /* primary codec ready */ 124 #define AUICH_MINT 0x00080 /* mic in int */ 125 #define AUICH_POINT 0x00040 /* pcm out int */ 126 #define AUICH_PIINT 0x00020 /* pcm in int */ 127 #define AUICH_MOINT 0x00004 /* modem out int */ 128 #define AUICH_MIINT 0x00002 /* modem in int */ 129 #define AUICH_GSCI 0x00001 /* gpi status change */ 130 #define AUICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3" 131 #define AUICH_CAS 0x34 /* 1/8 bit */ 132 #define AUICH_SEMATIMO 1000 /* us */ 133 #define AUICH_RESETIMO 500000 /* us */ 134 135 #define ICH_SIS_NV_CTL 0x4c /* some SiS/NVIDIA register. From Linux */ 136 #define ICH_SIS_CTL_UNMUTE 0x01 /* un-mute the output */ 137 138 /* 139 * There are 32 buffer descriptors. Each can reference up to 2^16 16-bit 140 * samples. 141 */ 142 #define AUICH_DMALIST_MAX 32 143 #define AUICH_DMASEG_MAX (65536*2) 144 struct auich_dmalist { 145 u_int32_t base; 146 u_int32_t len; 147 #define AUICH_DMAF_IOC 0x80000000 /* 1-int on complete */ 148 #define AUICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 149 }; 150 151 #define AUICH_FIXED_RATE 48000 152 153 struct auich_dma { 154 bus_dmamap_t map; 155 caddr_t addr; 156 bus_dma_segment_t segs[1]; 157 int nsegs; 158 size_t size; 159 }; 160 161 struct auich_cdata { 162 struct auich_dmalist ic_dmalist_pcmo[AUICH_DMALIST_MAX]; 163 struct auich_dmalist ic_dmalist_pcmi[AUICH_DMALIST_MAX]; 164 struct auich_dmalist ic_dmalist_mici[AUICH_DMALIST_MAX]; 165 }; 166 167 #define AUICH_CDOFF(x) offsetof(struct auich_cdata, x) 168 #define AUICH_PCMO_OFF(x) AUICH_CDOFF(ic_dmalist_pcmo[(x)]) 169 #define AUICH_PCMI_OFF(x) AUICH_CDOFF(ic_dmalist_pcmi[(x)]) 170 #define AUICH_MICI_OFF(x) AUICH_CDOFF(ic_dmalist_mici[(x)]) 171 172 struct auich_softc { 173 struct device sc_dev; 174 void *sc_ih; 175 176 audio_device_t sc_audev; 177 struct device *audiodev; 178 179 pcireg_t pci_id; 180 bus_space_tag_t iot; 181 bus_space_tag_t iot_mix; 182 bus_space_handle_t mix_ioh; 183 bus_space_handle_t aud_ioh; 184 bus_dma_tag_t dmat; 185 186 struct ac97_codec_if *codec_if; 187 struct ac97_host_if host_if; 188 int sc_spdif; 189 190 /* dma scatter-gather buffer lists */ 191 192 bus_dmamap_t sc_cddmamap; 193 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 194 195 struct auich_cdata *sc_cdata; 196 197 struct auich_ring { 198 int qptr; 199 struct auich_dmalist *dmalist; 200 201 uint32_t start, p, end; 202 int blksize; 203 204 void (*intr)(void *); 205 void *arg; 206 int running; 207 size_t size; 208 uint32_t ap; 209 } pcmo, pcmi, mici; 210 211 struct auich_dma *sc_pdma; /* play */ 212 struct auich_dma *sc_rdma; /* record */ 213 struct auich_dma *sc_cdma; /* calibrate */ 214 215 #ifdef AUICH_DEBUG 216 int pcmi_fifoe; 217 int pcmo_fifoe; 218 #endif 219 220 int suspend; 221 u_int16_t ext_ctrl; 222 int sc_sample_size; 223 int sc_sts_reg; 224 int sc_dmamap_flags; 225 int sc_ignore_codecready; 226 int flags; 227 int sc_ac97rate; 228 229 /* multi-channel control bits */ 230 int sc_pcm246_mask; 231 int sc_pcm2; 232 int sc_pcm4; 233 int sc_pcm6; 234 235 u_int last_rrate; 236 u_int last_prate; 237 u_int last_pchan; 238 }; 239 240 #ifdef AUICH_DEBUG 241 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 242 int auich_debug = 0x0002; 243 #define AUICH_DEBUG_CODECIO 0x0001 244 #define AUICH_DEBUG_DMA 0x0002 245 #define AUICH_DEBUG_INTR 0x0004 246 #else 247 #define DPRINTF(x,y) /* nothing */ 248 #endif 249 250 struct cfdriver auich_cd = { 251 NULL, "auich", DV_DULL 252 }; 253 254 int auich_match(struct device *, void *, void *); 255 void auich_attach(struct device *, struct device *, void *); 256 int auich_intr(void *); 257 258 int auich_activate(struct device *, int); 259 260 struct cfattach auich_ca = { 261 sizeof(struct auich_softc), auich_match, auich_attach, 262 NULL, auich_activate 263 }; 264 265 static const struct auich_devtype { 266 int vendor; 267 int product; 268 int options; 269 char name[8]; 270 } auich_devices[] = { 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_ACA, 0, "ESB" }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_ACA, 0, "ESB2" }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 0, "ICH" }, 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 0, "ICH0" }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 0, "ICH2" }, 276 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_ACA, 0, "ICH3" }, 277 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ACA, 0, "ICH4" }, 278 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_ACA, 0, "ICH5" }, 279 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_ACA, 0, "ICH6" }, 280 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_ACA, 0, "ICH7" }, 281 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 0, "440MX" }, 282 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_ACA, 0, "SiS7012" }, 283 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_ACA, 0, "nForce" }, 284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_ACA, 0, "nForce2" }, 285 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_ACA, 286 0, "nForce2" }, 287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_ACA, 0, "nForce3" }, 288 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_ACA, 289 0, "nForce3" }, 290 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_AC, 0, "nForce4" }, 291 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_AC97, 0, "MCP04" }, 292 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_ACA, 0, "MCP51" }, 293 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_ACA, 0, "AMD768" }, 294 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_8111_ACA, 0, "AMD8111" }, 295 }; 296 297 int auich_open(void *, int); 298 void auich_close(void *); 299 int auich_query_encoding(void *, struct audio_encoding *); 300 int auich_set_params(void *, int, int, struct audio_params *, 301 struct audio_params *); 302 int auich_round_blocksize(void *, int); 303 void auich_halt_pipe(struct auich_softc *, int, struct auich_ring *); 304 int auich_halt_output(void *); 305 int auich_halt_input(void *); 306 int auich_getdev(void *, struct audio_device *); 307 int auich_set_port(void *, mixer_ctrl_t *); 308 int auich_get_port(void *, mixer_ctrl_t *); 309 int auich_query_devinfo(void *, mixer_devinfo_t *); 310 void *auich_allocm(void *, int, size_t, int, int); 311 void auich_freem(void *, void *, int); 312 size_t auich_round_buffersize(void *, int, size_t); 313 paddr_t auich_mappage(void *, void *, off_t, int); 314 int auich_get_props(void *); 315 void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 316 void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 317 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 318 void *, struct audio_params *); 319 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 320 void *, struct audio_params *); 321 int auich_alloc_cdata(struct auich_softc *); 322 int auich_allocmem(struct auich_softc *, size_t, size_t, struct auich_dma *); 323 int auich_freemem(struct auich_softc *, struct auich_dma *); 324 void auich_get_default_params(void *, int, struct audio_params *); 325 326 int auich_resume(struct auich_softc *); 327 328 struct audio_hw_if auich_hw_if = { 329 auich_open, 330 auich_close, 331 NULL, /* drain */ 332 auich_query_encoding, 333 auich_set_params, 334 auich_round_blocksize, 335 NULL, /* commit_setting */ 336 NULL, /* init_output */ 337 NULL, /* init_input */ 338 NULL, /* start_output */ 339 NULL, /* start_input */ 340 auich_halt_output, 341 auich_halt_input, 342 NULL, /* speaker_ctl */ 343 auich_getdev, 344 NULL, /* getfd */ 345 auich_set_port, 346 auich_get_port, 347 auich_query_devinfo, 348 auich_allocm, 349 auich_freem, 350 auich_round_buffersize, 351 auich_mappage, 352 auich_get_props, 353 auich_trigger_output, 354 auich_trigger_input, 355 auich_get_default_params 356 }; 357 358 int auich_attach_codec(void *, struct ac97_codec_if *); 359 int auich_read_codec(void *, u_int8_t, u_int16_t *); 360 int auich_write_codec(void *, u_int8_t, u_int16_t); 361 void auich_reset_codec(void *); 362 enum ac97_host_flags auich_flags_codec(void *); 363 unsigned int auich_calibrate(struct auich_softc *); 364 void auich_spdif_event(void *, int); 365 366 int 367 auich_match(struct device *parent, void *match, void *aux) 368 { 369 struct pci_attach_args *pa = aux; 370 int i; 371 372 for (i = nitems(auich_devices); i--;) 373 if (PCI_VENDOR(pa->pa_id) == auich_devices[i].vendor && 374 PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 375 return 1; 376 377 return 0; 378 } 379 380 void 381 auich_attach(struct device *parent, struct device *self, void *aux) 382 { 383 struct auich_softc *sc = (struct auich_softc *)self; 384 struct pci_attach_args *pa = aux; 385 pci_intr_handle_t ih; 386 bus_size_t mix_size, aud_size; 387 pcireg_t csr; 388 const char *intrstr; 389 u_int32_t status; 390 int i; 391 392 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 393 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 394 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 395 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 396 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 397 /* 398 * Use native mode for ICH4/ICH5/ICH6/ICH7 399 */ 400 if (pci_mapreg_map(pa, AUICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 401 &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 402 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 403 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 404 csr | AUICH_CFG_IOSE); 405 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 406 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 407 printf(": can't map codec mem/io space\n"); 408 return; 409 } 410 } 411 412 if (pci_mapreg_map(pa, AUICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 413 &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 414 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 415 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 416 csr | AUICH_CFG_IOSE); 417 if (pci_mapreg_map(pa, AUICH_NABMBAR, 418 PCI_MAPREG_TYPE_IO, 0, &sc->iot, 419 &sc->aud_ioh, NULL, &aud_size, 0)) { 420 printf(": can't map device mem/io space\n"); 421 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 422 return; 423 } 424 } 425 } else { 426 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 427 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 428 printf(": can't map codec i/o space\n"); 429 return; 430 } 431 432 if (pci_mapreg_map(pa, AUICH_NABMBAR, PCI_MAPREG_TYPE_IO, 433 0, &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 434 printf(": can't map device i/o space\n"); 435 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 436 return; 437 } 438 } 439 sc->dmat = pa->pa_dmat; 440 sc->pci_id = pa->pa_id; 441 442 if (pci_intr_map(pa, &ih)) { 443 printf(": can't map interrupt\n"); 444 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 445 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 446 return; 447 } 448 intrstr = pci_intr_string(pa->pa_pc, ih); 449 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO, auich_intr, 450 sc, sc->sc_dev.dv_xname); 451 if (!sc->sc_ih) { 452 printf(": can't establish interrupt"); 453 if (intrstr) 454 printf(" at %s", intrstr); 455 printf("\n"); 456 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 457 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 458 return; 459 } 460 461 for (i = nitems(auich_devices); i--;) 462 if (PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 463 break; 464 465 snprintf(sc->sc_audev.name, sizeof sc->sc_audev.name, "%s AC97", 466 auich_devices[i].name); 467 snprintf(sc->sc_audev.version, sizeof sc->sc_audev.version, "0x%02x", 468 PCI_REVISION(pa->pa_class)); 469 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, 470 sizeof sc->sc_audev.config); 471 472 printf(": %s, %s\n", intrstr, sc->sc_audev.name); 473 474 /* SiS 7012 needs special handling */ 475 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 476 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_7012_ACA) { 477 sc->sc_sts_reg = AUICH_PICB; 478 sc->sc_sample_size = 1; 479 sc->sc_pcm246_mask = AUICH_SIS_PCM246_MASK; 480 sc->sc_pcm2 = AUICH_SIS_PCM2; 481 sc->sc_pcm4 = AUICH_SIS_PCM4; 482 sc->sc_pcm6 = AUICH_SIS_PCM6; 483 /* un-mute output */ 484 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 485 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 486 ICH_SIS_CTL_UNMUTE); 487 } else { 488 sc->sc_sts_reg = AUICH_STS; 489 sc->sc_sample_size = 2; 490 sc->sc_pcm246_mask = AUICH_PCM246_MASK; 491 sc->sc_pcm2 = AUICH_PCM2; 492 sc->sc_pcm4 = AUICH_PCM4; 493 sc->sc_pcm6 = AUICH_PCM6; 494 } 495 496 /* Workaround for a 440MX B-stepping erratum */ 497 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 498 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 499 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_ACA) { 500 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 501 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 502 } 503 504 /* Set up DMA lists. */ 505 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 506 auich_alloc_cdata(sc); 507 508 DPRINTF(AUICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 509 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 510 511 /* Reset codec and AC'97 */ 512 auich_reset_codec(sc); 513 status = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 514 if (!(status & AUICH_PCR)) { /* reset failure */ 515 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 516 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 517 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 518 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 519 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 520 /* MSI 845G Max never return AUICH_PCR */ 521 sc->sc_ignore_codecready = 1; 522 } else { 523 printf("%s: reset failed!\n", sc->sc_dev.dv_xname); 524 return; 525 } 526 } 527 528 sc->host_if.arg = sc; 529 sc->host_if.attach = auich_attach_codec; 530 sc->host_if.read = auich_read_codec; 531 sc->host_if.write = auich_write_codec; 532 sc->host_if.reset = auich_reset_codec; 533 sc->host_if.flags = auich_flags_codec; 534 sc->host_if.spdif_event = auich_spdif_event; 535 if (sc->sc_dev.dv_cfdata->cf_flags & 0x0001) 536 sc->flags = AC97_HOST_SWAPPED_CHANNELS; 537 538 if (ac97_attach(&sc->host_if) != 0) { 539 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 540 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 541 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 542 return; 543 } 544 sc->codec_if->vtbl->unlock(sc->codec_if); 545 546 sc->audiodev = audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 547 548 /* Watch for power changes */ 549 sc->suspend = DVACT_RESUME; 550 551 sc->sc_ac97rate = -1; 552 } 553 554 int 555 auich_activate(struct device *self, int act) 556 { 557 struct auich_softc *sc = (struct auich_softc *)self; 558 int rv = 0; 559 560 switch (act) { 561 case DVACT_QUIESCE: 562 rv = config_activate_children(self, act); 563 break; 564 case DVACT_SUSPEND: 565 break; 566 case DVACT_RESUME: 567 auich_resume(sc); 568 rv = config_activate_children(self, act); 569 break; 570 case DVACT_DEACTIVATE: 571 if (sc->audiodev != NULL) 572 rv = config_deactivate(sc->audiodev); 573 break; 574 } 575 return (rv); 576 } 577 578 int 579 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 580 { 581 struct auich_softc *sc = v; 582 int i; 583 584 /* wait for an access semaphore */ 585 for (i = AUICH_SEMATIMO; i-- && 586 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 587 588 if (!sc->sc_ignore_codecready && i < 0) { 589 DPRINTF(AUICH_DEBUG_CODECIO, 590 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 591 return (-1); 592 } 593 594 *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg); 595 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: read_codec(%x, %x)\n", 596 sc->sc_dev.dv_xname, reg, *val)); 597 return (0); 598 } 599 600 int 601 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 602 { 603 struct auich_softc *sc = v; 604 int i; 605 606 /* wait for an access semaphore */ 607 for (i = AUICH_SEMATIMO; i-- && 608 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 609 610 if (sc->sc_ignore_codecready || i >= 0) { 611 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: write_codec(%x, %x)\n", 612 sc->sc_dev.dv_xname, reg, val)); 613 bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val); 614 return (0); 615 } else { 616 DPRINTF(AUICH_DEBUG_CODECIO, 617 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 618 return (-1); 619 } 620 } 621 622 int 623 auich_attach_codec(void *v, struct ac97_codec_if *cif) 624 { 625 struct auich_softc *sc = v; 626 627 sc->codec_if = cif; 628 return 0; 629 } 630 631 void 632 auich_reset_codec(void *v) 633 { 634 struct auich_softc *sc = v; 635 u_int32_t control; 636 int i; 637 638 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 639 control &= ~(AUICH_ACLSO | sc->sc_pcm246_mask); 640 control |= (control & AUICH_CRESET) ? AUICH_WRESET : AUICH_CRESET; 641 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 642 643 for (i = AUICH_RESETIMO; i-- && 644 !(bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS) & AUICH_PCR); 645 DELAY(1)); 646 647 if (i < 0) 648 DPRINTF(AUICH_DEBUG_CODECIO, 649 ("%s: reset_codec timeout\n", sc->sc_dev.dv_xname)); 650 } 651 652 enum ac97_host_flags 653 auich_flags_codec(void *v) 654 { 655 struct auich_softc *sc = v; 656 657 return (sc->flags); 658 } 659 660 void 661 auich_spdif_event(void *v, int flag) 662 { 663 struct auich_softc *sc = v; 664 sc->sc_spdif = flag; 665 } 666 667 int 668 auich_open(void *v, int flags) 669 { 670 struct auich_softc *sc = v; 671 672 if (sc->sc_ac97rate == -1) 673 sc->sc_ac97rate = auich_calibrate(sc); 674 675 sc->codec_if->vtbl->lock(sc->codec_if); 676 677 return 0; 678 } 679 680 void 681 auich_close(void *v) 682 { 683 struct auich_softc *sc = v; 684 685 sc->codec_if->vtbl->unlock(sc->codec_if); 686 } 687 688 void 689 auich_get_default_params(void *addr, int mode, struct audio_params *params) 690 { 691 ac97_get_default_params(params); 692 } 693 694 int 695 auich_query_encoding(void *v, struct audio_encoding *aep) 696 { 697 struct auich_softc *sc = v; 698 if (sc->sc_spdif) { 699 switch (aep->index) { 700 case 0: 701 strlcpy(aep->name, AudioEslinear_le, sizeof aep->name); 702 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 703 aep->precision = 16; 704 aep->flags = 0; 705 aep->bps = 2; 706 aep->msb = 1; 707 return (0); 708 default: 709 return (EINVAL); 710 } 711 } else { 712 switch (aep->index) { 713 case 0: 714 strlcpy(aep->name, AudioEulinear, sizeof aep->name); 715 aep->encoding = AUDIO_ENCODING_ULINEAR; 716 aep->precision = 8; 717 aep->flags = 0; 718 break; 719 case 1: 720 strlcpy(aep->name, AudioEmulaw, sizeof aep->name); 721 aep->encoding = AUDIO_ENCODING_ULAW; 722 aep->precision = 8; 723 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 724 break; 725 case 2: 726 strlcpy(aep->name, AudioEalaw, sizeof aep->name); 727 aep->encoding = AUDIO_ENCODING_ALAW; 728 aep->precision = 8; 729 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 730 break; 731 case 3: 732 strlcpy(aep->name, AudioEslinear, sizeof aep->name); 733 aep->encoding = AUDIO_ENCODING_SLINEAR; 734 aep->precision = 8; 735 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 736 break; 737 case 4: 738 strlcpy(aep->name, AudioEslinear_le, sizeof aep->name); 739 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 740 aep->precision = 16; 741 aep->flags = 0; 742 break; 743 case 5: 744 strlcpy(aep->name, AudioEulinear_le, sizeof aep->name); 745 aep->encoding = AUDIO_ENCODING_ULINEAR_LE; 746 aep->precision = 16; 747 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 748 break; 749 case 6: 750 strlcpy(aep->name, AudioEslinear_be, sizeof aep->name); 751 aep->encoding = AUDIO_ENCODING_SLINEAR_BE; 752 aep->precision = 16; 753 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 754 break; 755 case 7: 756 strlcpy(aep->name, AudioEulinear_be, sizeof aep->name); 757 aep->encoding = AUDIO_ENCODING_ULINEAR_BE; 758 aep->precision = 16; 759 aep->flags = AUDIO_ENCODINGFLAG_EMULATED; 760 break; 761 default: 762 return (EINVAL); 763 } 764 aep->bps = AUDIO_BPS(aep->precision); 765 aep->msb = 1; 766 return (0); 767 } 768 } 769 770 int 771 auich_set_params(void *v, int setmode, int usemode, 772 struct audio_params *play, struct audio_params *rec) 773 { 774 struct auich_softc *sc = v; 775 struct ac97_codec_if *codec = sc->codec_if; 776 int error; 777 u_int orate; 778 u_int adj_rate; 779 u_int32_t control; 780 u_int16_t ext_id; 781 782 if (setmode & AUMODE_PLAY) { 783 /* only 16-bit 48kHz slinear_le if s/pdif enabled */ 784 if (sc->sc_spdif) { 785 play->sample_rate = 48000; 786 play->precision = 16; 787 play->encoding = AUDIO_ENCODING_SLINEAR_LE; 788 } 789 } 790 if (setmode & AUMODE_PLAY) { 791 play->factor = 1; 792 play->sw_code = NULL; 793 if (play->precision > 16) 794 play->precision = 16; 795 switch(play->encoding) { 796 case AUDIO_ENCODING_ULAW: 797 if (play->channels > 2) 798 play->channels = 2; 799 switch (play->channels) { 800 case 1: 801 play->factor = 4; 802 play->sw_code = mulaw_to_slinear16_le_mts; 803 break; 804 case 2: 805 play->factor = 2; 806 play->sw_code = mulaw_to_slinear16_le; 807 break; 808 default: 809 return (EINVAL); 810 } 811 break; 812 case AUDIO_ENCODING_SLINEAR_LE: 813 switch (play->precision) { 814 case 8: 815 if (play->channels > 2) 816 play->channels = 2; 817 switch (play->channels) { 818 case 1: 819 play->factor = 4; 820 play->sw_code = linear8_to_linear16_le_mts; 821 break; 822 case 2: 823 play->factor = 2; 824 play->sw_code = linear8_to_linear16_le; 825 break; 826 default: 827 return (EINVAL); 828 } 829 break; 830 case 16: 831 if (play->channels > 6) 832 play->channels = 6; 833 if (play->channels > 1) 834 play->channels &= ~1; 835 switch (play->channels) { 836 case 1: 837 play->factor = 2; 838 play->sw_code = noswap_bytes_mts; 839 break; 840 case 2: 841 break; 842 case 4: 843 ext_id = codec->vtbl->get_caps(codec); 844 if (!(ext_id & AC97_EXT_AUDIO_SDAC)) 845 play->channels = 2; 846 break; 847 case 6: 848 ext_id = codec->vtbl->get_caps(codec); 849 if ((ext_id & AC97_BITS_6CH) != 850 AC97_BITS_6CH) 851 play->channels = 2; 852 break; 853 default: 854 return (EINVAL); 855 } 856 break; 857 } 858 break; 859 case AUDIO_ENCODING_ULINEAR_LE: 860 if (play->channels > 2) 861 play->channels = 2; 862 switch (play->precision) { 863 case 8: 864 switch (play->channels) { 865 case 1: 866 play->factor = 4; 867 play->sw_code = ulinear8_to_linear16_le_mts; 868 break; 869 case 2: 870 play->factor = 2; 871 play->sw_code = ulinear8_to_linear16_le; 872 break; 873 default: 874 return (EINVAL); 875 } 876 break; 877 case 16: 878 switch (play->channels) { 879 case 1: 880 play->factor = 2; 881 play->sw_code = change_sign16_le_mts; 882 break; 883 case 2: 884 play->sw_code = change_sign16_le; 885 break; 886 default: 887 return (EINVAL); 888 } 889 break; 890 default: 891 return (EINVAL); 892 } 893 break; 894 case AUDIO_ENCODING_ALAW: 895 if (play->channels > 2) 896 play->channels = 2; 897 switch (play->channels) { 898 case 1: 899 play->factor = 4; 900 play->sw_code = alaw_to_slinear16_le_mts; 901 break; 902 case 2: 903 play->factor = 2; 904 play->sw_code = alaw_to_slinear16_le; 905 break; 906 default: 907 return (EINVAL); 908 } 909 break; 910 case AUDIO_ENCODING_SLINEAR_BE: 911 if (play->channels > 2) 912 play->channels = 2; 913 switch (play->precision) { 914 case 8: 915 switch (play->channels) { 916 case 1: 917 play->factor = 4; 918 play->sw_code = linear8_to_linear16_le_mts; 919 break; 920 case 2: 921 play->factor = 2; 922 play->sw_code = linear8_to_linear16_le; 923 break; 924 default: 925 return (EINVAL); 926 } 927 break; 928 case 16: 929 switch (play->channels) { 930 case 1: 931 play->factor = 2; 932 play->sw_code = swap_bytes_mts; 933 break; 934 case 2: 935 play->sw_code = swap_bytes; 936 break; 937 default: 938 return (EINVAL); 939 } 940 break; 941 default: 942 return (EINVAL); 943 } 944 break; 945 case AUDIO_ENCODING_ULINEAR_BE: 946 if (play->channels > 2) 947 play->channels = 2; 948 switch (play->precision) { 949 case 8: 950 switch (play->channels) { 951 case 1: 952 play->factor = 4; 953 play->sw_code = ulinear8_to_linear16_le_mts; 954 break; 955 case 2: 956 play->factor = 2; 957 play->sw_code = ulinear8_to_linear16_le; 958 break; 959 default: 960 return (EINVAL); 961 } 962 break; 963 case 16: 964 switch (play->channels) { 965 case 1: 966 play->factor = 2; 967 play->sw_code = swap_bytes_change_sign16_le_mts; 968 break; 969 case 2: 970 play->sw_code = swap_bytes_change_sign16_le; 971 break; 972 default: 973 return (EINVAL); 974 } 975 break; 976 default: 977 return (EINVAL); 978 } 979 break; 980 default: 981 return (EINVAL); 982 } 983 play->bps = AUDIO_BPS(play->precision); 984 play->msb = 1; 985 986 orate = adj_rate = play->sample_rate; 987 if (sc->sc_ac97rate != 0) 988 adj_rate = orate * AUICH_FIXED_RATE / sc->sc_ac97rate; 989 990 play->sample_rate = adj_rate; 991 sc->last_prate = play->sample_rate; 992 993 error = ac97_set_rate(sc->codec_if, 994 AC97_REG_PCM_LFE_DAC_RATE, &play->sample_rate); 995 if (error) 996 return (error); 997 998 play->sample_rate = adj_rate; 999 error = ac97_set_rate(sc->codec_if, 1000 AC97_REG_PCM_SURR_DAC_RATE, &play->sample_rate); 1001 if (error) 1002 return (error); 1003 1004 play->sample_rate = adj_rate; 1005 error = ac97_set_rate(sc->codec_if, 1006 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate); 1007 if (error) 1008 return (error); 1009 1010 if (play->sample_rate == adj_rate) 1011 play->sample_rate = orate; 1012 1013 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 1014 control &= ~(sc->sc_pcm246_mask); 1015 if (play->channels == 4) 1016 control |= sc->sc_pcm4; 1017 else if (play->channels == 6) 1018 control |= sc->sc_pcm6; 1019 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 1020 1021 sc->last_pchan = play->channels; 1022 } 1023 1024 if (setmode & AUMODE_RECORD) { 1025 rec->factor = 1; 1026 rec->sw_code = 0; 1027 if (rec->channels > 2) 1028 rec->channels = 2; 1029 if (rec->precision > 16) 1030 rec->precision = 16; 1031 switch(rec->encoding) { 1032 case AUDIO_ENCODING_ULAW: 1033 switch (rec->channels) { 1034 case 1: 1035 rec->sw_code = slinear16_to_mulaw_le_stm; 1036 rec->factor = 4; 1037 break; 1038 case 2: 1039 rec->sw_code = slinear16_to_mulaw_le; 1040 rec->factor = 2; 1041 break; 1042 } 1043 break; 1044 case AUDIO_ENCODING_ALAW: 1045 switch (rec->channels) { 1046 case 1: 1047 rec->sw_code = slinear16_to_alaw_le_stm; 1048 rec->factor = 4; 1049 break; 1050 case 2: 1051 rec->sw_code = slinear16_to_alaw_le; 1052 rec->factor = 2; 1053 break; 1054 } 1055 break; 1056 case AUDIO_ENCODING_SLINEAR_LE: 1057 switch (rec->precision) { 1058 case 8: 1059 switch (rec->channels) { 1060 case 1: 1061 rec->sw_code = linear16_to_linear8_le_stm; 1062 rec->factor = 4; 1063 break; 1064 case 2: 1065 rec->sw_code = linear16_to_linear8_le; 1066 rec->factor = 2; 1067 break; 1068 } 1069 break; 1070 case 16: 1071 switch (rec->channels) { 1072 case 1: 1073 rec->sw_code = linear16_decimator; 1074 rec->factor = 2; 1075 break; 1076 case 2: 1077 break; 1078 } 1079 break; 1080 default: 1081 return (EINVAL); 1082 } 1083 break; 1084 case AUDIO_ENCODING_ULINEAR_LE: 1085 switch (rec->precision) { 1086 case 8: 1087 switch (rec->channels) { 1088 case 1: 1089 rec->sw_code = linear16_to_ulinear8_le_stm; 1090 rec->factor = 4; 1091 break; 1092 case 2: 1093 rec->sw_code = linear16_to_ulinear8_le; 1094 rec->factor = 2; 1095 break; 1096 } 1097 break; 1098 case 16: 1099 switch (rec->channels) { 1100 case 1: 1101 rec->sw_code = change_sign16_le_stm; 1102 rec->factor = 2; 1103 break; 1104 case 2: 1105 rec->sw_code = change_sign16_le; 1106 break; 1107 } 1108 break; 1109 default: 1110 return (EINVAL); 1111 } 1112 break; 1113 case AUDIO_ENCODING_SLINEAR_BE: 1114 switch (rec->precision) { 1115 case 8: 1116 switch (rec->channels) { 1117 case 1: 1118 rec->sw_code = linear16_to_linear8_le_stm; 1119 rec->factor = 4; 1120 break; 1121 case 2: 1122 rec->sw_code = linear16_to_linear8_le; 1123 rec->factor = 2; 1124 break; 1125 } 1126 break; 1127 case 16: 1128 switch (rec->channels) { 1129 case 1: 1130 rec->sw_code = swap_bytes_stm; 1131 rec->factor = 2; 1132 break; 1133 case 2: 1134 rec->sw_code = swap_bytes; 1135 break; 1136 } 1137 break; 1138 default: 1139 return (EINVAL); 1140 } 1141 break; 1142 case AUDIO_ENCODING_ULINEAR_BE: 1143 switch (rec->precision) { 1144 case 8: 1145 switch (rec->channels) { 1146 case 1: 1147 rec->sw_code = linear16_to_ulinear8_le_stm; 1148 rec->factor = 4; 1149 break; 1150 case 2: 1151 rec->sw_code = linear16_to_ulinear8_le; 1152 rec->factor = 2; 1153 break; 1154 } 1155 break; 1156 case 16: 1157 switch (rec->channels) { 1158 case 1: 1159 rec->sw_code = change_sign16_swap_bytes_le_stm; 1160 rec->factor = 2; 1161 break; 1162 case 2: 1163 rec->sw_code = change_sign16_swap_bytes_le; 1164 break; 1165 } 1166 break; 1167 default: 1168 return (EINVAL); 1169 } 1170 break; 1171 default: 1172 return (EINVAL); 1173 } 1174 rec->bps = AUDIO_BPS(rec->precision); 1175 rec->msb = 1; 1176 1177 orate = rec->sample_rate; 1178 if (sc->sc_ac97rate != 0) 1179 rec->sample_rate = orate * AUICH_FIXED_RATE / 1180 sc->sc_ac97rate; 1181 sc->last_rrate = rec->sample_rate; 1182 error = ac97_set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 1183 &rec->sample_rate); 1184 if (error) 1185 return (error); 1186 rec->sample_rate = orate; 1187 } 1188 1189 return (0); 1190 } 1191 1192 int 1193 auich_round_blocksize(void *v, int blk) 1194 { 1195 return (blk + 0x3f) & ~0x3f; 1196 } 1197 1198 1199 void 1200 auich_halt_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1201 { 1202 int i; 1203 uint32_t sts; 1204 1205 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 0); 1206 1207 /* wait for DMA halted and clear interrupt / event bits if needed */ 1208 for (i = 0; i < 1000; i++) { 1209 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1210 pipe + sc->sc_sts_reg); 1211 if (sts & (AUICH_CELV | AUICH_LVBCI | AUICH_BCIS | AUICH_FIFOE)) 1212 bus_space_write_2(sc->iot, sc->aud_ioh, 1213 pipe + sc->sc_sts_reg, 1214 AUICH_CELV | AUICH_LVBCI | 1215 AUICH_BCIS | AUICH_FIFOE); 1216 if (sts & AUICH_DCH) 1217 break; 1218 DELAY(100); 1219 } 1220 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, AUICH_RR); 1221 1222 if (i > 0) 1223 DPRINTF(AUICH_DEBUG_DMA, 1224 ("auich_halt_pipe: halt took %d cycles\n", i)); 1225 1226 ring->running = 0; 1227 } 1228 1229 1230 int 1231 auich_halt_output(void *v) 1232 { 1233 struct auich_softc *sc = v; 1234 1235 DPRINTF(AUICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 1236 1237 auich_halt_pipe(sc, AUICH_PCMO, &sc->pcmo); 1238 1239 sc->pcmo.intr = NULL; 1240 1241 return 0; 1242 } 1243 1244 int 1245 auich_halt_input(void *v) 1246 { 1247 struct auich_softc *sc = v; 1248 1249 DPRINTF(AUICH_DEBUG_DMA, 1250 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 1251 1252 /* XXX halt both unless known otherwise */ 1253 1254 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1255 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1256 1257 sc->pcmi.intr = NULL; 1258 1259 return 0; 1260 } 1261 1262 int 1263 auich_getdev(void *v, struct audio_device *adp) 1264 { 1265 struct auich_softc *sc = v; 1266 *adp = sc->sc_audev; 1267 return 0; 1268 } 1269 1270 int 1271 auich_set_port(void *v, mixer_ctrl_t *cp) 1272 { 1273 struct auich_softc *sc = v; 1274 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 1275 } 1276 1277 int 1278 auich_get_port(void *v, mixer_ctrl_t *cp) 1279 { 1280 struct auich_softc *sc = v; 1281 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 1282 } 1283 1284 int 1285 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 1286 { 1287 struct auich_softc *sc = v; 1288 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 1289 } 1290 1291 void * 1292 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 1293 { 1294 struct auich_softc *sc = v; 1295 struct auich_dma *p; 1296 int error; 1297 1298 /* can only use 1 segment */ 1299 if (size > AUICH_DMASEG_MAX) { 1300 DPRINTF(AUICH_DEBUG_DMA, 1301 ("%s: requested buffer size too large: %d", \ 1302 sc->sc_dev.dv_xname, size)); 1303 return NULL; 1304 } 1305 1306 p = malloc(sizeof(*p), pool, flags | M_ZERO); 1307 if (!p) 1308 return NULL; 1309 1310 error = auich_allocmem(sc, size, PAGE_SIZE, p); 1311 if (error) { 1312 free(p, pool); 1313 return NULL; 1314 } 1315 1316 if (direction == AUMODE_PLAY) 1317 sc->sc_pdma = p; 1318 else if (direction == AUMODE_RECORD) 1319 sc->sc_rdma = p; 1320 else 1321 sc->sc_cdma = p; 1322 1323 return p->addr; 1324 } 1325 1326 void 1327 auich_freem(void *v, void *ptr, int pool) 1328 { 1329 struct auich_softc *sc; 1330 struct auich_dma *p; 1331 1332 sc = v; 1333 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == ptr) 1334 p = sc->sc_pdma; 1335 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == ptr) 1336 p = sc->sc_rdma; 1337 else if (sc->sc_cdma != NULL && sc->sc_cdma->addr == ptr) 1338 p = sc->sc_cdma; 1339 else 1340 return; 1341 1342 auich_freemem(sc, p); 1343 free(p, pool); 1344 } 1345 1346 size_t 1347 auich_round_buffersize(void *v, int direction, size_t size) 1348 { 1349 if (size > AUICH_DMALIST_MAX * AUICH_DMASEG_MAX) 1350 size = AUICH_DMALIST_MAX * AUICH_DMASEG_MAX; 1351 1352 return size; 1353 } 1354 1355 paddr_t 1356 auich_mappage(void *v, void *mem, off_t off, int prot) 1357 { 1358 struct auich_softc *sc = v; 1359 struct auich_dma *p; 1360 1361 if (off < 0) 1362 return -1; 1363 1364 p = NULL; 1365 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == mem) 1366 p = sc->sc_pdma; 1367 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == mem) 1368 p = sc->sc_rdma; 1369 else 1370 return -1; 1371 1372 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 1373 off, prot, BUS_DMA_WAITOK); 1374 } 1375 1376 int 1377 auich_get_props(void *v) 1378 { 1379 return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1380 } 1381 1382 int 1383 auich_intr(void *v) 1384 { 1385 struct auich_softc *sc = v; 1386 int ret = 0, sts, gsts; 1387 1388 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 1389 DPRINTF(AUICH_DEBUG_INTR, ("auich_intr: gsts=%b\n", gsts, AUICH_GSTS_BITS)); 1390 1391 if (gsts & AUICH_POINT) { 1392 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1393 AUICH_PCMO + sc->sc_sts_reg); 1394 DPRINTF(AUICH_DEBUG_INTR, 1395 ("auich_intr: osts=%b\n", sts, AUICH_ISTS_BITS)); 1396 1397 #ifdef AUICH_DEBUG 1398 if (sts & AUICH_FIFOE) { 1399 printf("%s: in fifo underrun # %u civ=%u ctrl=0x%x sts=%b\n", 1400 sc->sc_dev.dv_xname, sc->pcmo_fifoe++, 1401 bus_space_read_1(sc->iot, sc->aud_ioh, 1402 AUICH_PCMO + AUICH_CIV), 1403 bus_space_read_1(sc->iot, sc->aud_ioh, 1404 AUICH_PCMO + AUICH_CTRL), 1405 bus_space_read_2(sc->iot, sc->aud_ioh, 1406 AUICH_PCMO + sc->sc_sts_reg), 1407 AUICH_ISTS_BITS); 1408 } 1409 #endif 1410 1411 if (sts & AUICH_BCIS) 1412 auich_intr_pipe(sc, AUICH_PCMO, &sc->pcmo); 1413 1414 /* int ack */ 1415 bus_space_write_2(sc->iot, sc->aud_ioh, 1416 AUICH_PCMO + sc->sc_sts_reg, sts & 1417 (AUICH_BCIS | AUICH_FIFOE)); 1418 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_POINT); 1419 ret++; 1420 } 1421 1422 if (gsts & AUICH_PIINT) { 1423 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1424 AUICH_PCMI + sc->sc_sts_reg); 1425 DPRINTF(AUICH_DEBUG_INTR, 1426 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1427 1428 #ifdef AUICH_DEBUG 1429 if (sts & AUICH_FIFOE) { 1430 printf("%s: in fifo overrun civ=%u ctrl=0x%x sts=%b\n", 1431 sc->sc_dev.dv_xname, sc->pcmi_fifoe++, 1432 bus_space_read_1(sc->iot, sc->aud_ioh, 1433 AUICH_PCMI + AUICH_CIV), 1434 bus_space_read_1(sc->iot, sc->aud_ioh, 1435 AUICH_PCMI + AUICH_CTRL), 1436 bus_space_read_2(sc->iot, sc->aud_ioh, 1437 AUICH_PCMI + sc->sc_sts_reg), 1438 AUICH_ISTS_BITS); 1439 } 1440 #endif 1441 1442 if (sts & AUICH_BCIS) 1443 auich_intr_pipe(sc, AUICH_PCMI, &sc->pcmi); 1444 1445 /* int ack */ 1446 bus_space_write_2(sc->iot, sc->aud_ioh, 1447 AUICH_PCMI + sc->sc_sts_reg, sts & 1448 (AUICH_BCIS | AUICH_FIFOE)); 1449 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_PIINT); 1450 ret++; 1451 } 1452 1453 if (gsts & AUICH_MINT) { 1454 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1455 AUICH_MICI + sc->sc_sts_reg); 1456 DPRINTF(AUICH_DEBUG_INTR, 1457 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1458 #ifdef AUICH_DEBUG 1459 if (sts & AUICH_FIFOE) { 1460 printf("%s: in fifo overrun # %u civ=%u ctrl=0x%x sts=%b\n", 1461 sc->sc_dev.dv_xname, 1462 bus_space_read_1(sc->iot, sc->aud_ioh, 1463 AUICH_MICI + AUICH_CIV), 1464 bus_space_read_1(sc->iot, sc->aud_ioh, 1465 AUICH_MICI + AUICH_CTRL), 1466 bus_space_read_2(sc->iot, sc->aud_ioh, 1467 AUICH_MICI + sc->sc_sts_reg), 1468 AUICH_ISTS_BITS); 1469 } 1470 #endif 1471 if (sts & AUICH_BCIS) 1472 auich_intr_pipe(sc, AUICH_MICI, &sc->mici); 1473 1474 /* int ack */ 1475 bus_space_write_2(sc->iot, sc->aud_ioh, 1476 AUICH_MICI + sc->sc_sts_reg, 1477 sts + (AUICH_BCIS | AUICH_FIFOE)); 1478 1479 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_MINT); 1480 ret++; 1481 } 1482 1483 return ret; 1484 } 1485 1486 1487 void 1488 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1489 { 1490 int blksize, qptr, oqptr; 1491 struct auich_dmalist *q; 1492 1493 blksize = ring->blksize; 1494 qptr = oqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1495 1496 /* XXX remove this when no one reports problems */ 1497 if(oqptr >= AUICH_DMALIST_MAX) { 1498 printf("%s: Unexpected CIV: %d\n", sc->sc_dev.dv_xname, oqptr); 1499 qptr = oqptr = 0; 1500 } 1501 1502 do { 1503 q = &ring->dmalist[qptr]; 1504 q->base = ring->p; 1505 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1506 1507 DPRINTF(AUICH_DEBUG_INTR, 1508 ("auich_trigger_pipe: %p, %p = %x @ 0x%x qptr=%d\n", 1509 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1510 1511 ring->p += blksize; 1512 if (ring->p >= ring->end) 1513 ring->p = ring->start; 1514 1515 qptr = (qptr + 1) & AUICH_LVI_MASK; 1516 } while (qptr != oqptr); 1517 1518 ring->qptr = qptr; 1519 1520 DPRINTF(AUICH_DEBUG_DMA, 1521 ("auich_trigger_pipe: qptr=%d\n", qptr)); 1522 1523 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1524 (qptr - 1) & AUICH_LVI_MASK); 1525 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 1526 AUICH_IOCE | AUICH_FEIE | AUICH_RPBM); 1527 1528 ring->running = 1; 1529 } 1530 1531 void 1532 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1533 { 1534 int blksize, qptr, nqptr; 1535 struct auich_dmalist *q; 1536 1537 blksize = ring->blksize; 1538 qptr = ring->qptr; 1539 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1540 1541 while (qptr != nqptr) { 1542 q = &ring->dmalist[qptr]; 1543 q->base = ring->p; 1544 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1545 1546 DPRINTF(AUICH_DEBUG_INTR, 1547 ("auich_intr: %p, %p = %x @ 0x%x qptr=%d\n", 1548 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1549 1550 ring->p += blksize; 1551 if (ring->p >= ring->end) 1552 ring->p = ring->start; 1553 1554 qptr = (qptr + 1) & AUICH_LVI_MASK; 1555 if (ring->intr) 1556 ring->intr(ring->arg); 1557 else 1558 printf("auich_intr: got progress with intr==NULL\n"); 1559 1560 ring->ap += blksize; 1561 if (ring->ap >= ring->size) 1562 ring->ap = 0; 1563 } 1564 ring->qptr = qptr; 1565 1566 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1567 (qptr - 1) & AUICH_LVI_MASK); 1568 } 1569 1570 1571 int 1572 auich_trigger_output(void *v, void *start, void *end, int blksize, 1573 void (*intr)(void *), void *arg, struct audio_params *param) 1574 { 1575 struct auich_softc *sc = v; 1576 struct auich_dma *p; 1577 size_t size; 1578 #ifdef AUICH_DEBUG 1579 uint16_t sts; 1580 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1581 AUICH_PCMO + sc->sc_sts_reg); 1582 DPRINTF(AUICH_DEBUG_DMA, 1583 ("auich_trigger_output(%x, %x, %d, %p, %p, %p) sts=%b\n", 1584 start, end, blksize, intr, arg, param, sts, AUICH_ISTS_BITS)); 1585 #endif 1586 1587 if (sc->sc_pdma->addr == start) 1588 p = sc->sc_pdma; 1589 else 1590 return -1; 1591 1592 size = (size_t)((caddr_t)end - (caddr_t)start); 1593 sc->pcmo.size = size; 1594 sc->pcmo.intr = intr; 1595 sc->pcmo.arg = arg; 1596 1597 /* 1598 * The logic behind this is: 1599 * setup one buffer to play, then LVI dump out the rest 1600 * to the scatter-gather chain. 1601 */ 1602 sc->pcmo.start = p->segs->ds_addr; 1603 sc->pcmo.p = sc->pcmo.start; 1604 sc->pcmo.end = sc->pcmo.start + size; 1605 sc->pcmo.blksize = blksize; 1606 1607 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMO + AUICH_BDBAR, 1608 sc->sc_cddma + AUICH_PCMO_OFF(0)); 1609 auich_trigger_pipe(sc, AUICH_PCMO, &sc->pcmo); 1610 1611 return 0; 1612 } 1613 1614 int 1615 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1616 void *v; 1617 void *start, *end; 1618 int blksize; 1619 void (*intr)(void *); 1620 void *arg; 1621 struct audio_params *param; 1622 { 1623 struct auich_softc *sc = v; 1624 struct auich_dma *p; 1625 size_t size; 1626 1627 #ifdef AUICH_DEBUG 1628 DPRINTF(AUICH_DEBUG_DMA, 1629 ("auich_trigger_input(%x, %x, %d, %p, %p, %p) sts=%b\n", 1630 start, end, blksize, intr, arg, param, 1631 bus_space_read_2(sc->iot, sc->aud_ioh, 1632 AUICH_PCMI + sc->sc_sts_reg), 1633 AUICH_ISTS_BITS)); 1634 #endif 1635 if (sc->sc_rdma->addr == start) 1636 p = sc->sc_rdma; 1637 else 1638 return -1; 1639 1640 size = (size_t)((caddr_t)end - (caddr_t)start); 1641 sc->pcmi.size = size; 1642 sc->pcmi.intr = intr; 1643 sc->pcmi.arg = arg; 1644 1645 /* 1646 * The logic behind this is: 1647 * setup one buffer to play, then LVI dump out the rest 1648 * to the scatter-gather chain. 1649 */ 1650 sc->pcmi.start = p->segs->ds_addr; 1651 sc->pcmi.p = sc->pcmi.start; 1652 sc->pcmi.end = sc->pcmi.start + size; 1653 sc->pcmi.blksize = blksize; 1654 1655 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1656 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1657 auich_trigger_pipe(sc, AUICH_PCMI, &sc->pcmi); 1658 1659 return 0; 1660 } 1661 1662 1663 int 1664 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1665 struct auich_dma *p) 1666 { 1667 int error; 1668 1669 p->size = size; 1670 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, p->segs, 1, 1671 &p->nsegs, BUS_DMA_NOWAIT); 1672 if (error) { 1673 DPRINTF(AUICH_DEBUG_DMA, 1674 ("%s: bus_dmamem_alloc failed: error %d\n", 1675 sc->sc_dev.dv_xname, error)); 1676 return error; 1677 } 1678 1679 error = bus_dmamem_map(sc->dmat, p->segs, 1, p->size, &p->addr, 1680 BUS_DMA_NOWAIT | sc->sc_dmamap_flags); 1681 if (error) { 1682 DPRINTF(AUICH_DEBUG_DMA, 1683 ("%s: bus_dmamem_map failed: error %d\n", 1684 sc->sc_dev.dv_xname, error)); 1685 goto free; 1686 } 1687 1688 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 0, 1689 BUS_DMA_NOWAIT, &p->map); 1690 if (error) { 1691 DPRINTF(AUICH_DEBUG_DMA, 1692 ("%s: bus_dmamap_create failed: error %d\n", 1693 sc->sc_dev.dv_xname, error)); 1694 goto unmap; 1695 } 1696 1697 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1698 BUS_DMA_NOWAIT); 1699 if (error) { 1700 DPRINTF(AUICH_DEBUG_DMA, 1701 ("%s: bus_dmamap_load failed: error %d\n", 1702 sc->sc_dev.dv_xname, error)); 1703 goto destroy; 1704 } 1705 return 0; 1706 1707 destroy: 1708 bus_dmamap_destroy(sc->dmat, p->map); 1709 unmap: 1710 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1711 free: 1712 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1713 return error; 1714 } 1715 1716 1717 int 1718 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1719 { 1720 bus_dmamap_unload(sc->dmat, p->map); 1721 bus_dmamap_destroy(sc->dmat, p->map); 1722 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1723 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1724 return 0; 1725 } 1726 1727 1728 1729 int 1730 auich_alloc_cdata(struct auich_softc *sc) 1731 { 1732 bus_dma_segment_t seg; 1733 int error, rseg; 1734 1735 /* 1736 * Allocate the control data structure, and create and load the 1737 * DMA map for it. 1738 */ 1739 if ((error = bus_dmamem_alloc(sc->dmat, sizeof(struct auich_cdata), 1740 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1741 printf("%s: unable to allocate control data, error = %d\n", 1742 sc->sc_dev.dv_xname, error); 1743 goto fail_0; 1744 } 1745 1746 if ((error = bus_dmamem_map(sc->dmat, &seg, 1, 1747 sizeof(struct auich_cdata), (caddr_t *) &sc->sc_cdata, 1748 sc->sc_dmamap_flags)) != 0) { 1749 printf("%s: unable to map control data, error = %d\n", 1750 sc->sc_dev.dv_xname, error); 1751 goto fail_1; 1752 } 1753 1754 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1755 sizeof(struct auich_cdata), 0, 0, &sc->sc_cddmamap)) != 0) { 1756 printf("%s: unable to create control data DMA map, " 1757 "error = %d\n", sc->sc_dev.dv_xname, error); 1758 goto fail_2; 1759 } 1760 1761 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, sc->sc_cdata, 1762 sizeof(struct auich_cdata), NULL, 0)) != 0) { 1763 printf("%s: unable tp load control data DMA map, " 1764 "error = %d\n", sc->sc_dev.dv_xname, error); 1765 goto fail_3; 1766 } 1767 1768 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1769 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1770 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1771 1772 return 0; 1773 1774 fail_3: 1775 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1776 fail_2: 1777 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1778 sizeof(struct auich_cdata)); 1779 fail_1: 1780 bus_dmamem_free(sc->dmat, &seg, rseg); 1781 fail_0: 1782 return error; 1783 } 1784 1785 int 1786 auich_resume(struct auich_softc *sc) 1787 { 1788 /* SiS 7012 needs special handling */ 1789 if (PCI_VENDOR(sc->pci_id) == PCI_VENDOR_SIS && 1790 PCI_PRODUCT(sc->pci_id) == PCI_PRODUCT_SIS_7012_ACA) { 1791 /* un-mute output */ 1792 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 1793 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 1794 ICH_SIS_CTL_UNMUTE); 1795 } 1796 1797 ac97_resume(&sc->host_if, sc->codec_if); 1798 1799 return (0); 1800 } 1801 1802 /* -------------------------------------------------------------------- */ 1803 /* Calibrate card (some boards are overclocked and need scaling) */ 1804 1805 unsigned int 1806 auich_calibrate(struct auich_softc *sc) 1807 { 1808 struct timeval t1, t2; 1809 u_int8_t civ, ociv; 1810 uint16_t sts, osts; 1811 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1812 void *temp_buffer; 1813 struct auich_dma *p; 1814 1815 ac97rate = AUICH_FIXED_RATE; 1816 /* 1817 * Grab audio from input for fixed interval and compare how 1818 * much we actually get with what we expect. Interval needs 1819 * to be sufficiently short that no interrupts are 1820 * generated. 1821 * XXX: Is this true? We don't request any interrupts, 1822 * so why should the chip issue any? 1823 */ 1824 1825 /* Setup a buffer */ 1826 bytes = 16000; 1827 temp_buffer = auich_allocm(sc, 0, bytes, M_DEVBUF, M_NOWAIT); 1828 if (temp_buffer == NULL) 1829 return (ac97rate); 1830 if (sc->sc_cdma->addr == temp_buffer) { 1831 p = sc->sc_cdma; 1832 } else { 1833 printf("auich_calibrate: bad address %p\n", temp_buffer); 1834 return (ac97rate); 1835 } 1836 1837 /* get current CIV (usually 0 after reboot) */ 1838 ociv = civ = bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CIV); 1839 sc->pcmi.dmalist[civ].base = p->map->dm_segs[0].ds_addr; 1840 sc->pcmi.dmalist[civ].len = bytes / sc->sc_sample_size; 1841 1842 1843 /* 1844 * our data format is stereo, 16 bit so each sample is 4 bytes. 1845 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1846 * we're going to start recording with interrupts disabled and measure 1847 * the time taken for one block to complete. we know the block size, 1848 * we know the time in microseconds, we calculate the sample rate: 1849 * 1850 * actual_rate [bps] = bytes / (time [s] * 4) 1851 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1852 * actual_rate [Hz] = (bytes * 250000) / time [us] 1853 */ 1854 1855 /* prepare */ 1856 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1857 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1858 /* we got only one valid sample, so set LVI to CIV 1859 * otherwise we provoke a AUICH_FIFOE FIFO error 1860 * which will confuse the chip later on. */ 1861 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_LVI, 1862 civ & AUICH_LVI_MASK); 1863 1864 /* start, but don't request any interupts */ 1865 microuptime(&t1); 1866 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CTRL, 1867 AUICH_RPBM); 1868 1869 /* XXX remove this sometime */ 1870 osts = bus_space_read_2(sc->iot, sc->aud_ioh, 1871 AUICH_PCMI + sc->sc_sts_reg); 1872 /* wait */ 1873 while(1) { 1874 microuptime(&t2); 1875 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1876 AUICH_PCMI + sc->sc_sts_reg); 1877 civ = bus_space_read_1(sc->iot, sc->aud_ioh, 1878 AUICH_PCMI + AUICH_CIV); 1879 1880 /* turn time delta into us */ 1881 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + 1882 t2.tv_usec - t1.tv_usec; 1883 1884 /* this should actually never happen because civ==lvi */ 1885 if ((civ & AUICH_LVI_MASK) != (ociv & AUICH_LVI_MASK)) { 1886 printf("%s: ac97 CIV progressed after %d us sts=%b civ=%u\n", 1887 sc->sc_dev.dv_xname, wait_us, sts, 1888 AUICH_ISTS_BITS, civ); 1889 ociv = civ; 1890 } 1891 /* normal completion */ 1892 if (sts & (AUICH_DCH | AUICH_CELV | AUICH_LVBCI)) 1893 break; 1894 /* 1895 * check for strange changes in STS - 1896 * XXX remove it when everythings fine 1897 */ 1898 if (sts != osts) { 1899 printf("%s: ac97 sts changed after %d us sts=%b civ=%u\n", 1900 sc->sc_dev.dv_xname, wait_us, sts, 1901 AUICH_ISTS_BITS, civ); 1902 osts = sts; 1903 } 1904 /* 1905 * timeout: we expect 83333 us for 48k sampling rate, 1906 * 600000 us will be enough even for 8k sampling rate 1907 */ 1908 if (wait_us > 600000) { 1909 printf("%s: ac97 link rate timed out %d us sts=%b civ=%u\n", 1910 sc->sc_dev.dv_xname, wait_us, sts, 1911 AUICH_ISTS_BITS, civ); 1912 /* reset and clean up*/ 1913 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1914 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1915 auich_freem(sc, temp_buffer, M_DEVBUF); 1916 /* return default sample rate */ 1917 return (ac97rate); 1918 } 1919 } 1920 1921 DPRINTF(AUICH_DEBUG_CODECIO, 1922 ("%s: ac97 link rate calibration took %d us sts=%b civ=%u\n", 1923 sc->sc_dev.dv_xname, wait_us, sts, AUICH_ISTS_BITS, civ)); 1924 1925 /* reset and clean up */ 1926 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1927 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1928 auich_freem(sc, temp_buffer, M_DEVBUF); 1929 1930 #ifdef AUICH_DEBUG 1931 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1932 AUICH_PCMI + sc->sc_sts_reg); 1933 civ = bus_space_read_4(sc->iot, sc->aud_ioh, 1934 AUICH_PCMI + AUICH_CIV); 1935 printf("%s: after calibration and reset sts=%b civ=%u\n", 1936 sc->sc_dev.dv_xname, sts, AUICH_ISTS_BITS, civ); 1937 #endif 1938 1939 /* now finally calculate measured samplerate */ 1940 actual_48k_rate = (bytes * 250000) / wait_us; 1941 1942 if (actual_48k_rate <= 48500) 1943 ac97rate = AUICH_FIXED_RATE; 1944 else 1945 ac97rate = actual_48k_rate; 1946 1947 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: measured ac97 link rate at %d Hz", 1948 sc->sc_dev.dv_xname, actual_48k_rate)); 1949 if (ac97rate != actual_48k_rate) 1950 DPRINTF(AUICH_DEBUG_CODECIO, (", will use %d Hz", ac97rate)); 1951 DPRINTF(AUICH_DEBUG_CODECIO, ("\n")); 1952 1953 return (ac97rate); 1954 } 1955