1 /* $OpenBSD: auich.c,v 1.104 2015/05/11 06:46:21 ratchov Exp $ */ 2 3 /* 4 * Copyright (c) 2000,2001 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * AC'97 audio found on Intel 810/815/820/440MX chipsets. 31 * http://developer.intel.com/design/chipsets/datashts/290655.htm 32 * http://developer.intel.com/design/chipsets/manuals/298028.htm 33 * http://www.intel.com/design/chipsets/datashts/290714.htm 34 * http://www.intel.com/design/chipsets/datashts/290744.htm 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/device.h> 41 42 #include <dev/pci/pcidevs.h> 43 #include <dev/pci/pcivar.h> 44 45 #include <sys/audioio.h> 46 #include <dev/audio_if.h> 47 48 #include <machine/bus.h> 49 50 #include <dev/ic/ac97.h> 51 52 /* 12.1.10 NAMBAR - native audio mixer base address register */ 53 #define AUICH_NAMBAR 0x10 54 /* 12.1.11 NABMBAR - native audio bus mastering base address register */ 55 #define AUICH_NABMBAR 0x14 56 #define AUICH_CFG 0x41 57 #define AUICH_CFG_IOSE 0x01 58 /* ICH4/ICH5/ICH6/ICH7 native audio mixer BAR */ 59 #define AUICH_MMBAR 0x18 60 /* ICH4/ICH5/ICH6/ICH7 native bus mastering BAR */ 61 #define AUICH_MBBAR 0x1c 62 #define AUICH_S2CR 0x10000000 /* tertiary codec ready */ 63 64 /* table 12-3. native audio bus master control registers */ 65 #define AUICH_BDBAR 0x00 /* 8-byte aligned address */ 66 #define AUICH_CIV 0x04 /* 5 bits current index value */ 67 #define AUICH_LVI 0x05 /* 5 bits last valid index value */ 68 #define AUICH_LVI_MASK 0x1f 69 #define AUICH_STS 0x06 /* 16 bits status */ 70 #define AUICH_FIFOE 0x10 /* fifo error */ 71 #define AUICH_BCIS 0x08 /* r- buf cmplt int sts; wr ack */ 72 #define AUICH_LVBCI 0x04 /* r- last valid bci, wr ack */ 73 #define AUICH_CELV 0x02 /* current equals last valid */ 74 #define AUICH_DCH 0x01 /* dma halted */ 75 #define AUICH_ISTS_BITS "\020\01dch\02celv\03lvbci\04bcis\05fifoe" 76 #define AUICH_PICB 0x08 /* 16 bits */ 77 #define AUICH_PIV 0x0a /* 5 bits prefetched index value */ 78 #define AUICH_CTRL 0x0b /* control */ 79 #define AUICH_IOCE 0x10 /* int on completion enable */ 80 #define AUICH_FEIE 0x08 /* fifo error int enable */ 81 #define AUICH_LVBIE 0x04 /* last valid buf int enable */ 82 #define AUICH_RR 0x02 /* 1 - reset regs */ 83 #define AUICH_RPBM 0x01 /* 1 - run, 0 - pause */ 84 85 #define AUICH_PCMI 0x00 86 #define AUICH_PCMO 0x10 87 #define AUICH_MICI 0x20 88 89 #define AUICH_GCTRL 0x2c 90 #define AUICH_SSM_78 0x40000000 /* S/PDIF slots 7 and 8 */ 91 #define AUICH_SSM_69 0x80000000 /* S/PDIF slots 6 and 9 */ 92 #define AUICH_SSM_1011 0xc0000000 /* S/PDIF slots 10 and 11 */ 93 #define AUICH_POM16 0x000000 /* PCM out precision 16bit */ 94 #define AUICH_POM20 0x400000 /* PCM out precision 20bit */ 95 #define AUICH_PCM246_MASK 0x300000 96 #define AUICH_PCM2 0x000000 /* 2ch output */ 97 #define AUICH_PCM4 0x100000 /* 4ch output */ 98 #define AUICH_PCM6 0x200000 /* 6ch output */ 99 #define AUICH_SIS_PCM246_MASK 0x0000c0 /* SiS 7012 */ 100 #define AUICH_SIS_PCM2 0x000000 /* SiS 7012 2ch output */ 101 #define AUICH_SIS_PCM4 0x000040 /* SiS 7012 4ch output */ 102 #define AUICH_SIS_PCM6 0x000080 /* SiS 7012 6ch output */ 103 #define AUICH_S2RIE 0x40 /* int when tertiary codec resume */ 104 #define AUICH_SRIE 0x20 /* int when 2ndary codec resume */ 105 #define AUICH_PRIE 0x10 /* int when primary codec resume */ 106 #define AUICH_ACLSO 0x08 /* aclink shut off */ 107 #define AUICH_WRESET 0x04 /* warm reset */ 108 #define AUICH_CRESET 0x02 /* cold reset */ 109 #define AUICH_GIE 0x01 /* gpi int enable */ 110 #define AUICH_GSTS 0x30 111 #define AUICH_MD3 0x20000 /* pwr-dn semaphore for modem */ 112 #define AUICH_AD3 0x10000 /* pwr-dn semaphore for audio */ 113 #define AUICH_RCS 0x08000 /* read completion status */ 114 #define AUICH_B3S12 0x04000 /* bit 3 of slot 12 */ 115 #define AUICH_B2S12 0x02000 /* bit 2 of slot 12 */ 116 #define AUICH_B1S12 0x01000 /* bit 1 of slot 12 */ 117 #define AUICH_SRI 0x00800 /* secondary resume int */ 118 #define AUICH_PRI 0x00400 /* primary resume int */ 119 #define AUICH_SCR 0x00200 /* secondary codec ready */ 120 #define AUICH_PCR 0x00100 /* primary codec ready */ 121 #define AUICH_MINT 0x00080 /* mic in int */ 122 #define AUICH_POINT 0x00040 /* pcm out int */ 123 #define AUICH_PIINT 0x00020 /* pcm in int */ 124 #define AUICH_MOINT 0x00004 /* modem out int */ 125 #define AUICH_MIINT 0x00002 /* modem in int */ 126 #define AUICH_GSCI 0x00001 /* gpi status change */ 127 #define AUICH_GSTS_BITS "\020\01gsci\02miict\03moint\06piint\07point\010mint\011pcr\012scr\013pri\014sri\015b1s12\016b2s12\017b3s12\020rcs\021ad3\022md3" 128 #define AUICH_CAS 0x34 /* 1/8 bit */ 129 #define AUICH_SEMATIMO 1000 /* us */ 130 #define AUICH_RESETIMO 500000 /* us */ 131 132 #define ICH_SIS_NV_CTL 0x4c /* some SiS/NVIDIA register. From Linux */ 133 #define ICH_SIS_CTL_UNMUTE 0x01 /* un-mute the output */ 134 135 /* 136 * There are 32 buffer descriptors. Each can reference up to 2^16 16-bit 137 * samples. 138 */ 139 #define AUICH_DMALIST_MAX 32 140 #define AUICH_DMASEG_MAX (65536*2) 141 struct auich_dmalist { 142 u_int32_t base; 143 u_int32_t len; 144 #define AUICH_DMAF_IOC 0x80000000 /* 1-int on complete */ 145 #define AUICH_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */ 146 }; 147 148 #define AUICH_FIXED_RATE 48000 149 150 struct auich_dma { 151 bus_dmamap_t map; 152 caddr_t addr; 153 bus_dma_segment_t segs[1]; 154 int nsegs; 155 size_t size; 156 }; 157 158 struct auich_cdata { 159 struct auich_dmalist ic_dmalist_pcmo[AUICH_DMALIST_MAX]; 160 struct auich_dmalist ic_dmalist_pcmi[AUICH_DMALIST_MAX]; 161 struct auich_dmalist ic_dmalist_mici[AUICH_DMALIST_MAX]; 162 }; 163 164 #define AUICH_CDOFF(x) offsetof(struct auich_cdata, x) 165 #define AUICH_PCMO_OFF(x) AUICH_CDOFF(ic_dmalist_pcmo[(x)]) 166 #define AUICH_PCMI_OFF(x) AUICH_CDOFF(ic_dmalist_pcmi[(x)]) 167 #define AUICH_MICI_OFF(x) AUICH_CDOFF(ic_dmalist_mici[(x)]) 168 169 struct auich_softc { 170 struct device sc_dev; 171 void *sc_ih; 172 173 audio_device_t sc_audev; 174 175 pcireg_t pci_id; 176 bus_space_tag_t iot; 177 bus_space_tag_t iot_mix; 178 bus_space_handle_t mix_ioh; 179 bus_space_handle_t aud_ioh; 180 bus_dma_tag_t dmat; 181 182 struct ac97_codec_if *codec_if; 183 struct ac97_host_if host_if; 184 int sc_spdif; 185 186 /* dma scatter-gather buffer lists */ 187 188 bus_dmamap_t sc_cddmamap; 189 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 190 191 struct auich_cdata *sc_cdata; 192 193 struct auich_ring { 194 int qptr; 195 struct auich_dmalist *dmalist; 196 197 uint32_t start, p, end; 198 int blksize; 199 200 void (*intr)(void *); 201 void *arg; 202 int running; 203 size_t size; 204 uint32_t ap; 205 } pcmo, pcmi, mici; 206 207 struct auich_dma *sc_pdma; /* play */ 208 struct auich_dma *sc_rdma; /* record */ 209 struct auich_dma *sc_cdma; /* calibrate */ 210 211 #ifdef AUICH_DEBUG 212 int pcmi_fifoe; 213 int pcmo_fifoe; 214 #endif 215 216 int suspend; 217 u_int16_t ext_ctrl; 218 int sc_sample_size; 219 int sc_sts_reg; 220 int sc_dmamap_flags; 221 int sc_ignore_codecready; 222 int flags; 223 int sc_ac97rate; 224 225 /* multi-channel control bits */ 226 int sc_pcm246_mask; 227 int sc_pcm2; 228 int sc_pcm4; 229 int sc_pcm6; 230 231 u_int last_rrate; 232 u_int last_prate; 233 u_int last_pchan; 234 }; 235 236 #ifdef AUICH_DEBUG 237 #define DPRINTF(l,x) do { if (auich_debug & (l)) printf x; } while(0) 238 int auich_debug = 0x0002; 239 #define AUICH_DEBUG_CODECIO 0x0001 240 #define AUICH_DEBUG_DMA 0x0002 241 #define AUICH_DEBUG_INTR 0x0004 242 #else 243 #define DPRINTF(x,y) /* nothing */ 244 #endif 245 246 struct cfdriver auich_cd = { 247 NULL, "auich", DV_DULL 248 }; 249 250 int auich_match(struct device *, void *, void *); 251 void auich_attach(struct device *, struct device *, void *); 252 int auich_intr(void *); 253 254 int auich_activate(struct device *, int); 255 256 struct cfattach auich_ca = { 257 sizeof(struct auich_softc), auich_match, auich_attach, 258 NULL, auich_activate 259 }; 260 261 static const struct auich_devtype { 262 int vendor; 263 int product; 264 int options; 265 char name[8]; 266 } auich_devices[] = { 267 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_ACA, 0, "ESB" }, 268 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_ACA, 0, "ESB2" }, 269 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA, 0, "ICH" }, 270 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA, 0, "ICH0" }, 271 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA, 0, "ICH2" }, 272 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_ACA, 0, "ICH3" }, 273 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_ACA, 0, "ICH4" }, 274 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_ACA, 0, "ICH5" }, 275 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_ACA, 0, "ICH6" }, 276 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_ACA, 0, "ICH7" }, 277 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA, 0, "440MX" }, 278 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_ACA, 0, "SiS7012" }, 279 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_ACA, 0, "nForce" }, 280 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_ACA, 0, "nForce2" }, 281 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_ACA, 282 0, "nForce2" }, 283 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_ACA, 0, "nForce3" }, 284 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_ACA, 285 0, "nForce3" }, 286 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_AC, 0, "nForce4" }, 287 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_AC97, 0, "MCP04" }, 288 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_ACA, 0, "MCP51" }, 289 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PBC768_ACA, 0, "AMD768" }, 290 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_8111_ACA, 0, "AMD8111" }, 291 }; 292 293 int auich_open(void *, int); 294 void auich_close(void *); 295 int auich_query_encoding(void *, struct audio_encoding *); 296 int auich_set_params(void *, int, int, struct audio_params *, 297 struct audio_params *); 298 int auich_round_blocksize(void *, int); 299 void auich_halt_pipe(struct auich_softc *, int, struct auich_ring *); 300 int auich_halt_output(void *); 301 int auich_halt_input(void *); 302 int auich_getdev(void *, struct audio_device *); 303 int auich_set_port(void *, mixer_ctrl_t *); 304 int auich_get_port(void *, mixer_ctrl_t *); 305 int auich_query_devinfo(void *, mixer_devinfo_t *); 306 void *auich_allocm(void *, int, size_t, int, int); 307 void auich_freem(void *, void *, int); 308 size_t auich_round_buffersize(void *, int, size_t); 309 paddr_t auich_mappage(void *, void *, off_t, int); 310 int auich_get_props(void *); 311 void auich_trigger_pipe(struct auich_softc *, int, struct auich_ring *); 312 void auich_intr_pipe(struct auich_softc *, int, struct auich_ring *); 313 int auich_trigger_output(void *, void *, void *, int, void (*)(void *), 314 void *, struct audio_params *); 315 int auich_trigger_input(void *, void *, void *, int, void (*)(void *), 316 void *, struct audio_params *); 317 int auich_alloc_cdata(struct auich_softc *); 318 int auich_allocmem(struct auich_softc *, size_t, size_t, struct auich_dma *); 319 int auich_freemem(struct auich_softc *, struct auich_dma *); 320 void auich_get_default_params(void *, int, struct audio_params *); 321 322 int auich_resume(struct auich_softc *); 323 324 struct audio_hw_if auich_hw_if = { 325 auich_open, 326 auich_close, 327 NULL, /* drain */ 328 auich_query_encoding, 329 auich_set_params, 330 auich_round_blocksize, 331 NULL, /* commit_setting */ 332 NULL, /* init_output */ 333 NULL, /* init_input */ 334 NULL, /* start_output */ 335 NULL, /* start_input */ 336 auich_halt_output, 337 auich_halt_input, 338 NULL, /* speaker_ctl */ 339 auich_getdev, 340 NULL, /* getfd */ 341 auich_set_port, 342 auich_get_port, 343 auich_query_devinfo, 344 auich_allocm, 345 auich_freem, 346 auich_round_buffersize, 347 auich_mappage, 348 auich_get_props, 349 auich_trigger_output, 350 auich_trigger_input, 351 auich_get_default_params 352 }; 353 354 int auich_attach_codec(void *, struct ac97_codec_if *); 355 int auich_read_codec(void *, u_int8_t, u_int16_t *); 356 int auich_write_codec(void *, u_int8_t, u_int16_t); 357 void auich_reset_codec(void *); 358 enum ac97_host_flags auich_flags_codec(void *); 359 unsigned int auich_calibrate(struct auich_softc *); 360 void auich_spdif_event(void *, int); 361 362 int 363 auich_match(struct device *parent, void *match, void *aux) 364 { 365 struct pci_attach_args *pa = aux; 366 int i; 367 368 for (i = nitems(auich_devices); i--;) 369 if (PCI_VENDOR(pa->pa_id) == auich_devices[i].vendor && 370 PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 371 return 1; 372 373 return 0; 374 } 375 376 void 377 auich_attach(struct device *parent, struct device *self, void *aux) 378 { 379 struct auich_softc *sc = (struct auich_softc *)self; 380 struct pci_attach_args *pa = aux; 381 pci_intr_handle_t ih; 382 bus_size_t mix_size, aud_size; 383 pcireg_t csr; 384 const char *intrstr; 385 u_int32_t status; 386 int i; 387 388 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 389 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 390 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 391 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 392 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 393 /* 394 * Use native mode for ICH4/ICH5/ICH6/ICH7 395 */ 396 if (pci_mapreg_map(pa, AUICH_MMBAR, PCI_MAPREG_TYPE_MEM, 0, 397 &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 398 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 399 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 400 csr | AUICH_CFG_IOSE); 401 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 402 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 403 printf(": can't map codec mem/io space\n"); 404 return; 405 } 406 } 407 408 if (pci_mapreg_map(pa, AUICH_MBBAR, PCI_MAPREG_TYPE_MEM, 0, 409 &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 410 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG); 411 pci_conf_write(pa->pa_pc, pa->pa_tag, AUICH_CFG, 412 csr | AUICH_CFG_IOSE); 413 if (pci_mapreg_map(pa, AUICH_NABMBAR, 414 PCI_MAPREG_TYPE_IO, 0, &sc->iot, 415 &sc->aud_ioh, NULL, &aud_size, 0)) { 416 printf(": can't map device mem/io space\n"); 417 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 418 return; 419 } 420 } 421 } else { 422 if (pci_mapreg_map(pa, AUICH_NAMBAR, PCI_MAPREG_TYPE_IO, 423 0, &sc->iot_mix, &sc->mix_ioh, NULL, &mix_size, 0)) { 424 printf(": can't map codec i/o space\n"); 425 return; 426 } 427 428 if (pci_mapreg_map(pa, AUICH_NABMBAR, PCI_MAPREG_TYPE_IO, 429 0, &sc->iot, &sc->aud_ioh, NULL, &aud_size, 0)) { 430 printf(": can't map device i/o space\n"); 431 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 432 return; 433 } 434 } 435 sc->dmat = pa->pa_dmat; 436 sc->pci_id = pa->pa_id; 437 438 if (pci_intr_map(pa, &ih)) { 439 printf(": can't map interrupt\n"); 440 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 441 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 442 return; 443 } 444 intrstr = pci_intr_string(pa->pa_pc, ih); 445 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_AUDIO | IPL_MPSAFE, 446 auich_intr, sc, sc->sc_dev.dv_xname); 447 if (!sc->sc_ih) { 448 printf(": can't establish interrupt"); 449 if (intrstr) 450 printf(" at %s", intrstr); 451 printf("\n"); 452 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 453 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 454 return; 455 } 456 457 for (i = nitems(auich_devices); i--;) 458 if (PCI_PRODUCT(pa->pa_id) == auich_devices[i].product) 459 break; 460 461 snprintf(sc->sc_audev.name, sizeof sc->sc_audev.name, "%s AC97", 462 auich_devices[i].name); 463 snprintf(sc->sc_audev.version, sizeof sc->sc_audev.version, "0x%02x", 464 PCI_REVISION(pa->pa_class)); 465 strlcpy(sc->sc_audev.config, sc->sc_dev.dv_xname, 466 sizeof sc->sc_audev.config); 467 468 printf(": %s, %s\n", intrstr, sc->sc_audev.name); 469 470 /* SiS 7012 needs special handling */ 471 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 472 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_7012_ACA) { 473 sc->sc_sts_reg = AUICH_PICB; 474 sc->sc_sample_size = 1; 475 sc->sc_pcm246_mask = AUICH_SIS_PCM246_MASK; 476 sc->sc_pcm2 = AUICH_SIS_PCM2; 477 sc->sc_pcm4 = AUICH_SIS_PCM4; 478 sc->sc_pcm6 = AUICH_SIS_PCM6; 479 /* un-mute output */ 480 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 481 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 482 ICH_SIS_CTL_UNMUTE); 483 } else { 484 sc->sc_sts_reg = AUICH_STS; 485 sc->sc_sample_size = 2; 486 sc->sc_pcm246_mask = AUICH_PCM246_MASK; 487 sc->sc_pcm2 = AUICH_PCM2; 488 sc->sc_pcm4 = AUICH_PCM4; 489 sc->sc_pcm6 = AUICH_PCM6; 490 } 491 492 /* Workaround for a 440MX B-stepping erratum */ 493 sc->sc_dmamap_flags = BUS_DMA_COHERENT; 494 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 495 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82440MX_ACA) { 496 sc->sc_dmamap_flags |= BUS_DMA_NOCACHE; 497 printf("%s: DMA bug workaround enabled\n", sc->sc_dev.dv_xname); 498 } 499 500 /* Set up DMA lists. */ 501 sc->pcmo.qptr = sc->pcmi.qptr = sc->mici.qptr = 0; 502 auich_alloc_cdata(sc); 503 504 DPRINTF(AUICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n", 505 sc->pcmo.dmalist, sc->pcmi.dmalist, sc->mici.dmalist)); 506 507 /* Reset codec and AC'97 */ 508 auich_reset_codec(sc); 509 status = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 510 if (!(status & AUICH_PCR)) { /* reset failure */ 511 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 512 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801DB_ACA || 513 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801EB_ACA || 514 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_ACA || 515 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801GB_ACA)) { 516 /* MSI 845G Max never return AUICH_PCR */ 517 sc->sc_ignore_codecready = 1; 518 } else { 519 printf("%s: reset failed!\n", sc->sc_dev.dv_xname); 520 return; 521 } 522 } 523 524 sc->host_if.arg = sc; 525 sc->host_if.attach = auich_attach_codec; 526 sc->host_if.read = auich_read_codec; 527 sc->host_if.write = auich_write_codec; 528 sc->host_if.reset = auich_reset_codec; 529 sc->host_if.flags = auich_flags_codec; 530 sc->host_if.spdif_event = auich_spdif_event; 531 if (sc->sc_dev.dv_cfdata->cf_flags & 0x0001) 532 sc->flags = AC97_HOST_SWAPPED_CHANNELS; 533 534 if (ac97_attach(&sc->host_if) != 0) { 535 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 536 bus_space_unmap(sc->iot, sc->aud_ioh, aud_size); 537 bus_space_unmap(sc->iot_mix, sc->mix_ioh, mix_size); 538 return; 539 } 540 sc->codec_if->vtbl->unlock(sc->codec_if); 541 542 audio_attach_mi(&auich_hw_if, sc, &sc->sc_dev); 543 544 /* Watch for power changes */ 545 sc->suspend = DVACT_RESUME; 546 547 sc->sc_ac97rate = -1; 548 } 549 550 int 551 auich_activate(struct device *self, int act) 552 { 553 struct auich_softc *sc = (struct auich_softc *)self; 554 int rv = 0; 555 556 switch (act) { 557 case DVACT_RESUME: 558 auich_resume(sc); 559 rv = config_activate_children(self, act); 560 break; 561 default: 562 rv = config_activate_children(self, act); 563 break; 564 } 565 return (rv); 566 } 567 568 int 569 auich_read_codec(void *v, u_int8_t reg, u_int16_t *val) 570 { 571 struct auich_softc *sc = v; 572 int i; 573 574 /* wait for an access semaphore */ 575 for (i = AUICH_SEMATIMO; i-- && 576 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 577 578 if (!sc->sc_ignore_codecready && i < 0) { 579 DPRINTF(AUICH_DEBUG_CODECIO, 580 ("%s: read_codec timeout\n", sc->sc_dev.dv_xname)); 581 return (-1); 582 } 583 584 *val = bus_space_read_2(sc->iot_mix, sc->mix_ioh, reg); 585 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: read_codec(%x, %x)\n", 586 sc->sc_dev.dv_xname, reg, *val)); 587 return (0); 588 } 589 590 int 591 auich_write_codec(void *v, u_int8_t reg, u_int16_t val) 592 { 593 struct auich_softc *sc = v; 594 int i; 595 596 /* wait for an access semaphore */ 597 for (i = AUICH_SEMATIMO; i-- && 598 bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_CAS) & 1; DELAY(1)); 599 600 if (sc->sc_ignore_codecready || i >= 0) { 601 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: write_codec(%x, %x)\n", 602 sc->sc_dev.dv_xname, reg, val)); 603 bus_space_write_2(sc->iot_mix, sc->mix_ioh, reg, val); 604 return (0); 605 } else { 606 DPRINTF(AUICH_DEBUG_CODECIO, 607 ("%s: write_codec timeout\n", sc->sc_dev.dv_xname)); 608 return (-1); 609 } 610 } 611 612 int 613 auich_attach_codec(void *v, struct ac97_codec_if *cif) 614 { 615 struct auich_softc *sc = v; 616 617 sc->codec_if = cif; 618 return 0; 619 } 620 621 void 622 auich_reset_codec(void *v) 623 { 624 struct auich_softc *sc = v; 625 u_int32_t control; 626 int i; 627 628 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 629 control &= ~(AUICH_ACLSO | sc->sc_pcm246_mask); 630 control |= (control & AUICH_CRESET) ? AUICH_WRESET : AUICH_CRESET; 631 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 632 633 for (i = AUICH_RESETIMO; i-- && 634 !(bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS) & AUICH_PCR); 635 DELAY(1)); 636 637 if (i < 0) 638 DPRINTF(AUICH_DEBUG_CODECIO, 639 ("%s: reset_codec timeout\n", sc->sc_dev.dv_xname)); 640 } 641 642 enum ac97_host_flags 643 auich_flags_codec(void *v) 644 { 645 struct auich_softc *sc = v; 646 647 return (sc->flags); 648 } 649 650 void 651 auich_spdif_event(void *v, int flag) 652 { 653 struct auich_softc *sc = v; 654 sc->sc_spdif = flag; 655 } 656 657 int 658 auich_open(void *v, int flags) 659 { 660 struct auich_softc *sc = v; 661 662 if (sc->sc_ac97rate == -1) 663 sc->sc_ac97rate = auich_calibrate(sc); 664 665 sc->codec_if->vtbl->lock(sc->codec_if); 666 667 return 0; 668 } 669 670 void 671 auich_close(void *v) 672 { 673 struct auich_softc *sc = v; 674 675 sc->codec_if->vtbl->unlock(sc->codec_if); 676 } 677 678 void 679 auich_get_default_params(void *addr, int mode, struct audio_params *params) 680 { 681 ac97_get_default_params(params); 682 } 683 684 int 685 auich_query_encoding(void *v, struct audio_encoding *aep) 686 { 687 switch (aep->index) { 688 case 0: 689 strlcpy(aep->name, AudioEslinear_le, sizeof aep->name); 690 aep->encoding = AUDIO_ENCODING_SLINEAR_LE; 691 aep->precision = 16; 692 aep->flags = 0; 693 aep->bps = 2; 694 aep->msb = 1; 695 return (0); 696 default: 697 return (EINVAL); 698 } 699 } 700 701 int 702 auich_set_params(void *v, int setmode, int usemode, 703 struct audio_params *play, struct audio_params *rec) 704 { 705 struct auich_softc *sc = v; 706 struct ac97_codec_if *codec = sc->codec_if; 707 int error; 708 u_int orate; 709 u_int adj_rate; 710 u_int32_t control; 711 u_int16_t ext_id; 712 713 if (setmode & AUMODE_PLAY) { 714 /* only 16-bit 48kHz slinear_le if s/pdif enabled */ 715 if (sc->sc_spdif) { 716 play->sample_rate = 48000; 717 play->precision = 16; 718 play->encoding = AUDIO_ENCODING_SLINEAR_LE; 719 } 720 } 721 if (setmode & AUMODE_PLAY) { 722 play->precision = 16; 723 switch(play->encoding) { 724 case AUDIO_ENCODING_SLINEAR_LE: 725 if (play->channels > 6) 726 play->channels = 6; 727 if (play->channels > 1) 728 play->channels &= ~1; 729 switch (play->channels) { 730 case 1: 731 play->channels = 2; 732 break; 733 case 2: 734 break; 735 case 4: 736 ext_id = codec->vtbl->get_caps(codec); 737 if (!(ext_id & AC97_EXT_AUDIO_SDAC)) 738 play->channels = 2; 739 break; 740 case 6: 741 ext_id = codec->vtbl->get_caps(codec); 742 if ((ext_id & AC97_BITS_6CH) != 743 AC97_BITS_6CH) 744 play->channels = 2; 745 break; 746 default: 747 return (EINVAL); 748 } 749 break; 750 default: 751 return (EINVAL); 752 } 753 play->bps = AUDIO_BPS(play->precision); 754 play->msb = 1; 755 756 orate = adj_rate = play->sample_rate; 757 if (sc->sc_ac97rate != 0) 758 adj_rate = orate * AUICH_FIXED_RATE / sc->sc_ac97rate; 759 760 play->sample_rate = adj_rate; 761 sc->last_prate = play->sample_rate; 762 763 error = ac97_set_rate(sc->codec_if, 764 AC97_REG_PCM_LFE_DAC_RATE, &play->sample_rate); 765 if (error) 766 return (error); 767 768 play->sample_rate = adj_rate; 769 error = ac97_set_rate(sc->codec_if, 770 AC97_REG_PCM_SURR_DAC_RATE, &play->sample_rate); 771 if (error) 772 return (error); 773 774 play->sample_rate = adj_rate; 775 error = ac97_set_rate(sc->codec_if, 776 AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate); 777 if (error) 778 return (error); 779 780 if (play->sample_rate == adj_rate) 781 play->sample_rate = orate; 782 783 control = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GCTRL); 784 control &= ~(sc->sc_pcm246_mask); 785 if (play->channels == 4) 786 control |= sc->sc_pcm4; 787 else if (play->channels == 6) 788 control |= sc->sc_pcm6; 789 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GCTRL, control); 790 791 sc->last_pchan = play->channels; 792 } 793 794 if (setmode & AUMODE_RECORD) { 795 rec->channels = 2; 796 rec->precision = 16; 797 rec->encoding = AUDIO_ENCODING_SLINEAR_LE; 798 rec->bps = AUDIO_BPS(rec->precision); 799 rec->msb = 1; 800 801 orate = rec->sample_rate; 802 if (sc->sc_ac97rate != 0) 803 rec->sample_rate = orate * AUICH_FIXED_RATE / 804 sc->sc_ac97rate; 805 sc->last_rrate = rec->sample_rate; 806 error = ac97_set_rate(sc->codec_if, AC97_REG_PCM_LR_ADC_RATE, 807 &rec->sample_rate); 808 if (error) 809 return (error); 810 rec->sample_rate = orate; 811 } 812 813 return (0); 814 } 815 816 int 817 auich_round_blocksize(void *v, int blk) 818 { 819 return (blk + 0x3f) & ~0x3f; 820 } 821 822 823 void 824 auich_halt_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 825 { 826 int i; 827 uint32_t sts; 828 829 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 0); 830 831 /* wait for DMA halted and clear interrupt / event bits if needed */ 832 for (i = 0; i < 1000; i++) { 833 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 834 pipe + sc->sc_sts_reg); 835 if (sts & (AUICH_CELV | AUICH_LVBCI | AUICH_BCIS | AUICH_FIFOE)) 836 bus_space_write_2(sc->iot, sc->aud_ioh, 837 pipe + sc->sc_sts_reg, 838 AUICH_CELV | AUICH_LVBCI | 839 AUICH_BCIS | AUICH_FIFOE); 840 if (sts & AUICH_DCH) 841 break; 842 DELAY(100); 843 } 844 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, AUICH_RR); 845 846 if (i > 0) 847 DPRINTF(AUICH_DEBUG_DMA, 848 ("auich_halt_pipe: halt took %d cycles\n", i)); 849 850 ring->running = 0; 851 } 852 853 854 int 855 auich_halt_output(void *v) 856 { 857 struct auich_softc *sc = v; 858 859 DPRINTF(AUICH_DEBUG_DMA, ("%s: halt_output\n", sc->sc_dev.dv_xname)); 860 861 mtx_enter(&audio_lock); 862 auich_halt_pipe(sc, AUICH_PCMO, &sc->pcmo); 863 864 sc->pcmo.intr = NULL; 865 mtx_leave(&audio_lock); 866 return 0; 867 } 868 869 int 870 auich_halt_input(void *v) 871 { 872 struct auich_softc *sc = v; 873 874 DPRINTF(AUICH_DEBUG_DMA, 875 ("%s: halt_input\n", sc->sc_dev.dv_xname)); 876 877 /* XXX halt both unless known otherwise */ 878 mtx_enter(&audio_lock); 879 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 880 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 881 882 sc->pcmi.intr = NULL; 883 mtx_leave(&audio_lock); 884 return 0; 885 } 886 887 int 888 auich_getdev(void *v, struct audio_device *adp) 889 { 890 struct auich_softc *sc = v; 891 *adp = sc->sc_audev; 892 return 0; 893 } 894 895 int 896 auich_set_port(void *v, mixer_ctrl_t *cp) 897 { 898 struct auich_softc *sc = v; 899 return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp); 900 } 901 902 int 903 auich_get_port(void *v, mixer_ctrl_t *cp) 904 { 905 struct auich_softc *sc = v; 906 return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp); 907 } 908 909 int 910 auich_query_devinfo(void *v, mixer_devinfo_t *dp) 911 { 912 struct auich_softc *sc = v; 913 return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp); 914 } 915 916 void * 917 auich_allocm(void *v, int direction, size_t size, int pool, int flags) 918 { 919 struct auich_softc *sc = v; 920 struct auich_dma *p; 921 int error; 922 923 /* can only use 1 segment */ 924 if (size > AUICH_DMASEG_MAX) { 925 DPRINTF(AUICH_DEBUG_DMA, 926 ("%s: requested buffer size too large: %zd", \ 927 sc->sc_dev.dv_xname, size)); 928 return NULL; 929 } 930 931 p = malloc(sizeof(*p), pool, flags | M_ZERO); 932 if (!p) 933 return NULL; 934 935 error = auich_allocmem(sc, size, PAGE_SIZE, p); 936 if (error) { 937 free(p, pool, 0); 938 return NULL; 939 } 940 941 if (direction == AUMODE_PLAY) 942 sc->sc_pdma = p; 943 else if (direction == AUMODE_RECORD) 944 sc->sc_rdma = p; 945 else 946 sc->sc_cdma = p; 947 948 return p->addr; 949 } 950 951 void 952 auich_freem(void *v, void *ptr, int pool) 953 { 954 struct auich_softc *sc; 955 struct auich_dma *p; 956 957 sc = v; 958 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == ptr) 959 p = sc->sc_pdma; 960 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == ptr) 961 p = sc->sc_rdma; 962 else if (sc->sc_cdma != NULL && sc->sc_cdma->addr == ptr) 963 p = sc->sc_cdma; 964 else 965 return; 966 967 auich_freemem(sc, p); 968 free(p, pool, 0); 969 } 970 971 size_t 972 auich_round_buffersize(void *v, int direction, size_t size) 973 { 974 if (size > AUICH_DMALIST_MAX * AUICH_DMASEG_MAX) 975 size = AUICH_DMALIST_MAX * AUICH_DMASEG_MAX; 976 977 return size; 978 } 979 980 paddr_t 981 auich_mappage(void *v, void *mem, off_t off, int prot) 982 { 983 struct auich_softc *sc = v; 984 struct auich_dma *p; 985 986 if (off < 0) 987 return -1; 988 989 p = NULL; 990 if (sc->sc_pdma != NULL && sc->sc_pdma->addr == mem) 991 p = sc->sc_pdma; 992 else if (sc->sc_rdma != NULL && sc->sc_rdma->addr == mem) 993 p = sc->sc_rdma; 994 else 995 return -1; 996 997 return bus_dmamem_mmap(sc->dmat, p->segs, p->nsegs, 998 off, prot, BUS_DMA_WAITOK); 999 } 1000 1001 int 1002 auich_get_props(void *v) 1003 { 1004 return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1005 } 1006 1007 int 1008 auich_intr(void *v) 1009 { 1010 struct auich_softc *sc = v; 1011 int ret = 0, sts, gsts; 1012 1013 mtx_enter(&audio_lock); 1014 gsts = bus_space_read_4(sc->iot, sc->aud_ioh, AUICH_GSTS); 1015 DPRINTF(AUICH_DEBUG_INTR, ("auich_intr: gsts=%b\n", gsts, AUICH_GSTS_BITS)); 1016 1017 if (gsts & AUICH_POINT) { 1018 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1019 AUICH_PCMO + sc->sc_sts_reg); 1020 DPRINTF(AUICH_DEBUG_INTR, 1021 ("auich_intr: osts=%b\n", sts, AUICH_ISTS_BITS)); 1022 1023 #ifdef AUICH_DEBUG 1024 if (sts & AUICH_FIFOE) { 1025 printf("%s: in fifo underrun # %u civ=%u ctrl=0x%x sts=%b\n", 1026 sc->sc_dev.dv_xname, sc->pcmo_fifoe++, 1027 bus_space_read_1(sc->iot, sc->aud_ioh, 1028 AUICH_PCMO + AUICH_CIV), 1029 bus_space_read_1(sc->iot, sc->aud_ioh, 1030 AUICH_PCMO + AUICH_CTRL), 1031 bus_space_read_2(sc->iot, sc->aud_ioh, 1032 AUICH_PCMO + sc->sc_sts_reg), 1033 AUICH_ISTS_BITS); 1034 } 1035 #endif 1036 1037 if (sts & AUICH_BCIS) 1038 auich_intr_pipe(sc, AUICH_PCMO, &sc->pcmo); 1039 1040 /* int ack */ 1041 bus_space_write_2(sc->iot, sc->aud_ioh, 1042 AUICH_PCMO + sc->sc_sts_reg, sts & 1043 (AUICH_BCIS | AUICH_FIFOE)); 1044 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_POINT); 1045 ret++; 1046 } 1047 1048 if (gsts & AUICH_PIINT) { 1049 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1050 AUICH_PCMI + sc->sc_sts_reg); 1051 DPRINTF(AUICH_DEBUG_INTR, 1052 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1053 1054 #ifdef AUICH_DEBUG 1055 if (sts & AUICH_FIFOE) { 1056 printf("%s: in fifo overrun # %u civ=%u ctrl=0x%x sts=%b\n", 1057 sc->sc_dev.dv_xname, sc->pcmi_fifoe++, 1058 bus_space_read_1(sc->iot, sc->aud_ioh, 1059 AUICH_PCMI + AUICH_CIV), 1060 bus_space_read_1(sc->iot, sc->aud_ioh, 1061 AUICH_PCMI + AUICH_CTRL), 1062 bus_space_read_2(sc->iot, sc->aud_ioh, 1063 AUICH_PCMI + sc->sc_sts_reg), 1064 AUICH_ISTS_BITS); 1065 } 1066 #endif 1067 1068 if (sts & AUICH_BCIS) 1069 auich_intr_pipe(sc, AUICH_PCMI, &sc->pcmi); 1070 1071 /* int ack */ 1072 bus_space_write_2(sc->iot, sc->aud_ioh, 1073 AUICH_PCMI + sc->sc_sts_reg, sts & 1074 (AUICH_BCIS | AUICH_FIFOE)); 1075 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_PIINT); 1076 ret++; 1077 } 1078 1079 if (gsts & AUICH_MINT) { 1080 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1081 AUICH_MICI + sc->sc_sts_reg); 1082 DPRINTF(AUICH_DEBUG_INTR, 1083 ("auich_intr: ists=%b\n", sts, AUICH_ISTS_BITS)); 1084 #ifdef AUICH_DEBUG 1085 if (sts & AUICH_FIFOE) { 1086 printf("%s: in fifo overrun civ=%u ctrl=0x%x sts=%b\n", 1087 sc->sc_dev.dv_xname, 1088 bus_space_read_1(sc->iot, sc->aud_ioh, 1089 AUICH_MICI + AUICH_CIV), 1090 bus_space_read_1(sc->iot, sc->aud_ioh, 1091 AUICH_MICI + AUICH_CTRL), 1092 bus_space_read_2(sc->iot, sc->aud_ioh, 1093 AUICH_MICI + sc->sc_sts_reg), 1094 AUICH_ISTS_BITS); 1095 } 1096 #endif 1097 if (sts & AUICH_BCIS) 1098 auich_intr_pipe(sc, AUICH_MICI, &sc->mici); 1099 1100 /* int ack */ 1101 bus_space_write_2(sc->iot, sc->aud_ioh, 1102 AUICH_MICI + sc->sc_sts_reg, 1103 sts + (AUICH_BCIS | AUICH_FIFOE)); 1104 1105 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_GSTS, AUICH_MINT); 1106 ret++; 1107 } 1108 mtx_leave(&audio_lock); 1109 return ret; 1110 } 1111 1112 1113 void 1114 auich_trigger_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1115 { 1116 int blksize, qptr, oqptr; 1117 struct auich_dmalist *q; 1118 1119 blksize = ring->blksize; 1120 qptr = oqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1121 1122 /* XXX remove this when no one reports problems */ 1123 if(oqptr >= AUICH_DMALIST_MAX) { 1124 printf("%s: Unexpected CIV: %d\n", sc->sc_dev.dv_xname, oqptr); 1125 qptr = oqptr = 0; 1126 } 1127 1128 do { 1129 q = &ring->dmalist[qptr]; 1130 q->base = ring->p; 1131 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1132 1133 DPRINTF(AUICH_DEBUG_INTR, 1134 ("auich_trigger_pipe: %p, %p = %x @ 0x%x qptr=%d\n", 1135 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1136 1137 ring->p += blksize; 1138 if (ring->p >= ring->end) 1139 ring->p = ring->start; 1140 1141 qptr = (qptr + 1) & AUICH_LVI_MASK; 1142 } while (qptr != oqptr); 1143 1144 ring->qptr = qptr; 1145 1146 DPRINTF(AUICH_DEBUG_DMA, 1147 ("auich_trigger_pipe: qptr=%d\n", qptr)); 1148 1149 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1150 (qptr - 1) & AUICH_LVI_MASK); 1151 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_CTRL, 1152 AUICH_IOCE | AUICH_FEIE | AUICH_RPBM); 1153 1154 ring->running = 1; 1155 } 1156 1157 void 1158 auich_intr_pipe(struct auich_softc *sc, int pipe, struct auich_ring *ring) 1159 { 1160 int blksize, qptr, nqptr; 1161 struct auich_dmalist *q; 1162 1163 blksize = ring->blksize; 1164 qptr = ring->qptr; 1165 nqptr = bus_space_read_1(sc->iot, sc->aud_ioh, pipe + AUICH_CIV); 1166 1167 while (qptr != nqptr) { 1168 q = &ring->dmalist[qptr]; 1169 q->base = ring->p; 1170 q->len = (blksize / sc->sc_sample_size) | AUICH_DMAF_IOC; 1171 1172 DPRINTF(AUICH_DEBUG_INTR, 1173 ("auich_intr: %p, %p = %x @ 0x%x qptr=%d\n", 1174 &ring->dmalist[qptr], q, q->len, q->base, qptr)); 1175 1176 ring->p += blksize; 1177 if (ring->p >= ring->end) 1178 ring->p = ring->start; 1179 1180 qptr = (qptr + 1) & AUICH_LVI_MASK; 1181 if (ring->intr) 1182 ring->intr(ring->arg); 1183 else 1184 printf("auich_intr: got progress with intr==NULL\n"); 1185 1186 ring->ap += blksize; 1187 if (ring->ap >= ring->size) 1188 ring->ap = 0; 1189 } 1190 ring->qptr = qptr; 1191 1192 bus_space_write_1(sc->iot, sc->aud_ioh, pipe + AUICH_LVI, 1193 (qptr - 1) & AUICH_LVI_MASK); 1194 } 1195 1196 1197 int 1198 auich_trigger_output(void *v, void *start, void *end, int blksize, 1199 void (*intr)(void *), void *arg, struct audio_params *param) 1200 { 1201 struct auich_softc *sc = v; 1202 struct auich_dma *p; 1203 size_t size; 1204 #ifdef AUICH_DEBUG 1205 uint16_t sts; 1206 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1207 AUICH_PCMO + sc->sc_sts_reg); 1208 DPRINTF(AUICH_DEBUG_DMA, 1209 ("auich_trigger_output(%p, %p, %d, %p, %p, %p) sts=%b\n", 1210 start, end, blksize, intr, arg, param, sts, AUICH_ISTS_BITS)); 1211 #endif 1212 1213 if (sc->sc_pdma->addr == start) 1214 p = sc->sc_pdma; 1215 else 1216 return -1; 1217 1218 size = (size_t)((caddr_t)end - (caddr_t)start); 1219 sc->pcmo.size = size; 1220 sc->pcmo.intr = intr; 1221 sc->pcmo.arg = arg; 1222 1223 /* 1224 * The logic behind this is: 1225 * setup one buffer to play, then LVI dump out the rest 1226 * to the scatter-gather chain. 1227 */ 1228 sc->pcmo.start = p->segs->ds_addr; 1229 sc->pcmo.p = sc->pcmo.start; 1230 sc->pcmo.end = sc->pcmo.start + size; 1231 sc->pcmo.blksize = blksize; 1232 1233 mtx_enter(&audio_lock); 1234 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMO + AUICH_BDBAR, 1235 sc->sc_cddma + AUICH_PCMO_OFF(0)); 1236 auich_trigger_pipe(sc, AUICH_PCMO, &sc->pcmo); 1237 mtx_leave(&audio_lock); 1238 return 0; 1239 } 1240 1241 int 1242 auich_trigger_input(v, start, end, blksize, intr, arg, param) 1243 void *v; 1244 void *start, *end; 1245 int blksize; 1246 void (*intr)(void *); 1247 void *arg; 1248 struct audio_params *param; 1249 { 1250 struct auich_softc *sc = v; 1251 struct auich_dma *p; 1252 size_t size; 1253 1254 #ifdef AUICH_DEBUG 1255 DPRINTF(AUICH_DEBUG_DMA, 1256 ("auich_trigger_input(%p, %p, %d, %p, %p, %p) sts=%b\n", 1257 start, end, blksize, intr, arg, param, 1258 bus_space_read_2(sc->iot, sc->aud_ioh, 1259 AUICH_PCMI + sc->sc_sts_reg), 1260 AUICH_ISTS_BITS)); 1261 #endif 1262 if (sc->sc_rdma->addr == start) 1263 p = sc->sc_rdma; 1264 else 1265 return -1; 1266 1267 size = (size_t)((caddr_t)end - (caddr_t)start); 1268 sc->pcmi.size = size; 1269 sc->pcmi.intr = intr; 1270 sc->pcmi.arg = arg; 1271 1272 /* 1273 * The logic behind this is: 1274 * setup one buffer to play, then LVI dump out the rest 1275 * to the scatter-gather chain. 1276 */ 1277 sc->pcmi.start = p->segs->ds_addr; 1278 sc->pcmi.p = sc->pcmi.start; 1279 sc->pcmi.end = sc->pcmi.start + size; 1280 sc->pcmi.blksize = blksize; 1281 mtx_enter(&audio_lock); 1282 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1283 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1284 auich_trigger_pipe(sc, AUICH_PCMI, &sc->pcmi); 1285 mtx_leave(&audio_lock); 1286 return 0; 1287 } 1288 1289 1290 int 1291 auich_allocmem(struct auich_softc *sc, size_t size, size_t align, 1292 struct auich_dma *p) 1293 { 1294 int error; 1295 1296 p->size = size; 1297 error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, p->segs, 1, 1298 &p->nsegs, BUS_DMA_NOWAIT); 1299 if (error) { 1300 DPRINTF(AUICH_DEBUG_DMA, 1301 ("%s: bus_dmamem_alloc failed: error %d\n", 1302 sc->sc_dev.dv_xname, error)); 1303 return error; 1304 } 1305 1306 error = bus_dmamem_map(sc->dmat, p->segs, 1, p->size, &p->addr, 1307 BUS_DMA_NOWAIT | sc->sc_dmamap_flags); 1308 if (error) { 1309 DPRINTF(AUICH_DEBUG_DMA, 1310 ("%s: bus_dmamem_map failed: error %d\n", 1311 sc->sc_dev.dv_xname, error)); 1312 goto free; 1313 } 1314 1315 error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 0, 1316 BUS_DMA_NOWAIT, &p->map); 1317 if (error) { 1318 DPRINTF(AUICH_DEBUG_DMA, 1319 ("%s: bus_dmamap_create failed: error %d\n", 1320 sc->sc_dev.dv_xname, error)); 1321 goto unmap; 1322 } 1323 1324 error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1325 BUS_DMA_NOWAIT); 1326 if (error) { 1327 DPRINTF(AUICH_DEBUG_DMA, 1328 ("%s: bus_dmamap_load failed: error %d\n", 1329 sc->sc_dev.dv_xname, error)); 1330 goto destroy; 1331 } 1332 return 0; 1333 1334 destroy: 1335 bus_dmamap_destroy(sc->dmat, p->map); 1336 unmap: 1337 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1338 free: 1339 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1340 return error; 1341 } 1342 1343 1344 int 1345 auich_freemem(struct auich_softc *sc, struct auich_dma *p) 1346 { 1347 bus_dmamap_unload(sc->dmat, p->map); 1348 bus_dmamap_destroy(sc->dmat, p->map); 1349 bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1350 bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1351 return 0; 1352 } 1353 1354 1355 1356 int 1357 auich_alloc_cdata(struct auich_softc *sc) 1358 { 1359 bus_dma_segment_t seg; 1360 int error, rseg; 1361 1362 /* 1363 * Allocate the control data structure, and create and load the 1364 * DMA map for it. 1365 */ 1366 if ((error = bus_dmamem_alloc(sc->dmat, sizeof(struct auich_cdata), 1367 PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) { 1368 printf("%s: unable to allocate control data, error = %d\n", 1369 sc->sc_dev.dv_xname, error); 1370 goto fail_0; 1371 } 1372 1373 if ((error = bus_dmamem_map(sc->dmat, &seg, 1, 1374 sizeof(struct auich_cdata), (caddr_t *) &sc->sc_cdata, 1375 sc->sc_dmamap_flags)) != 0) { 1376 printf("%s: unable to map control data, error = %d\n", 1377 sc->sc_dev.dv_xname, error); 1378 goto fail_1; 1379 } 1380 1381 if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auich_cdata), 1, 1382 sizeof(struct auich_cdata), 0, 0, &sc->sc_cddmamap)) != 0) { 1383 printf("%s: unable to create control data DMA map, " 1384 "error = %d\n", sc->sc_dev.dv_xname, error); 1385 goto fail_2; 1386 } 1387 1388 if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap, sc->sc_cdata, 1389 sizeof(struct auich_cdata), NULL, 0)) != 0) { 1390 printf("%s: unable tp load control data DMA map, " 1391 "error = %d\n", sc->sc_dev.dv_xname, error); 1392 goto fail_3; 1393 } 1394 1395 sc->pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo; 1396 sc->pcmi.dmalist = sc->sc_cdata->ic_dmalist_pcmi; 1397 sc->mici.dmalist = sc->sc_cdata->ic_dmalist_mici; 1398 1399 return 0; 1400 1401 fail_3: 1402 bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap); 1403 fail_2: 1404 bus_dmamem_unmap(sc->dmat, (caddr_t) sc->sc_cdata, 1405 sizeof(struct auich_cdata)); 1406 fail_1: 1407 bus_dmamem_free(sc->dmat, &seg, rseg); 1408 fail_0: 1409 return error; 1410 } 1411 1412 int 1413 auich_resume(struct auich_softc *sc) 1414 { 1415 /* SiS 7012 needs special handling */ 1416 if (PCI_VENDOR(sc->pci_id) == PCI_VENDOR_SIS && 1417 PCI_PRODUCT(sc->pci_id) == PCI_PRODUCT_SIS_7012_ACA) { 1418 /* un-mute output */ 1419 bus_space_write_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL, 1420 bus_space_read_4(sc->iot, sc->aud_ioh, ICH_SIS_NV_CTL) | 1421 ICH_SIS_CTL_UNMUTE); 1422 } 1423 1424 ac97_resume(&sc->host_if, sc->codec_if); 1425 1426 return (0); 1427 } 1428 1429 /* -------------------------------------------------------------------- */ 1430 /* Calibrate card (some boards are overclocked and need scaling) */ 1431 1432 unsigned int 1433 auich_calibrate(struct auich_softc *sc) 1434 { 1435 struct timeval t1, t2; 1436 u_int8_t civ, ociv; 1437 uint16_t sts, osts; 1438 u_int32_t wait_us, actual_48k_rate, bytes, ac97rate; 1439 void *temp_buffer; 1440 struct auich_dma *p; 1441 1442 ac97rate = AUICH_FIXED_RATE; 1443 /* 1444 * Grab audio from input for fixed interval and compare how 1445 * much we actually get with what we expect. Interval needs 1446 * to be sufficiently short that no interrupts are 1447 * generated. 1448 * XXX: Is this true? We don't request any interrupts, 1449 * so why should the chip issue any? 1450 */ 1451 1452 /* Setup a buffer */ 1453 bytes = 16000; 1454 temp_buffer = auich_allocm(sc, 0, bytes, M_DEVBUF, M_NOWAIT); 1455 if (temp_buffer == NULL) 1456 return (ac97rate); 1457 if (sc->sc_cdma->addr == temp_buffer) { 1458 p = sc->sc_cdma; 1459 } else { 1460 printf("auich_calibrate: bad address %p\n", temp_buffer); 1461 return (ac97rate); 1462 } 1463 1464 /* get current CIV (usually 0 after reboot) */ 1465 ociv = civ = bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CIV); 1466 sc->pcmi.dmalist[civ].base = p->map->dm_segs[0].ds_addr; 1467 sc->pcmi.dmalist[civ].len = bytes / sc->sc_sample_size; 1468 1469 1470 /* 1471 * our data format is stereo, 16 bit so each sample is 4 bytes. 1472 * assuming we get 48000 samples per second, we get 192000 bytes/sec. 1473 * we're going to start recording with interrupts disabled and measure 1474 * the time taken for one block to complete. we know the block size, 1475 * we know the time in microseconds, we calculate the sample rate: 1476 * 1477 * actual_rate [bps] = bytes / (time [s] * 4) 1478 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4) 1479 * actual_rate [Hz] = (bytes * 250000) / time [us] 1480 */ 1481 1482 /* prepare */ 1483 bus_space_write_4(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_BDBAR, 1484 sc->sc_cddma + AUICH_PCMI_OFF(0)); 1485 /* we got only one valid sample, so set LVI to CIV 1486 * otherwise we provoke a AUICH_FIFOE FIFO error 1487 * which will confuse the chip later on. */ 1488 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_LVI, 1489 civ & AUICH_LVI_MASK); 1490 1491 /* start, but don't request any interupts */ 1492 microuptime(&t1); 1493 bus_space_write_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CTRL, 1494 AUICH_RPBM); 1495 1496 /* XXX remove this sometime */ 1497 osts = bus_space_read_2(sc->iot, sc->aud_ioh, 1498 AUICH_PCMI + sc->sc_sts_reg); 1499 /* wait */ 1500 while(1) { 1501 microuptime(&t2); 1502 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1503 AUICH_PCMI + sc->sc_sts_reg); 1504 civ = bus_space_read_1(sc->iot, sc->aud_ioh, 1505 AUICH_PCMI + AUICH_CIV); 1506 1507 /* turn time delta into us */ 1508 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + 1509 t2.tv_usec - t1.tv_usec; 1510 1511 /* this should actually never happen because civ==lvi */ 1512 if ((civ & AUICH_LVI_MASK) != (ociv & AUICH_LVI_MASK)) { 1513 printf("%s: ac97 CIV progressed after %d us sts=%b civ=%u\n", 1514 sc->sc_dev.dv_xname, wait_us, sts, 1515 AUICH_ISTS_BITS, civ); 1516 ociv = civ; 1517 } 1518 /* normal completion */ 1519 if (sts & (AUICH_DCH | AUICH_CELV | AUICH_LVBCI)) 1520 break; 1521 /* 1522 * check for strange changes in STS - 1523 * XXX remove it when everythings fine 1524 */ 1525 if (sts != osts) { 1526 printf("%s: ac97 sts changed after %d us sts=%b civ=%u\n", 1527 sc->sc_dev.dv_xname, wait_us, sts, 1528 AUICH_ISTS_BITS, civ); 1529 osts = sts; 1530 } 1531 /* 1532 * timeout: we expect 83333 us for 48k sampling rate, 1533 * 600000 us will be enough even for 8k sampling rate 1534 */ 1535 if (wait_us > 600000) { 1536 printf("%s: ac97 link rate timed out %d us sts=%b civ=%u\n", 1537 sc->sc_dev.dv_xname, wait_us, sts, 1538 AUICH_ISTS_BITS, civ); 1539 /* reset and clean up*/ 1540 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1541 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1542 auich_freem(sc, temp_buffer, M_DEVBUF); 1543 /* return default sample rate */ 1544 return (ac97rate); 1545 } 1546 } 1547 1548 DPRINTF(AUICH_DEBUG_CODECIO, 1549 ("%s: ac97 link rate calibration took %d us sts=%b civ=%u\n", 1550 sc->sc_dev.dv_xname, wait_us, sts, AUICH_ISTS_BITS, civ)); 1551 1552 /* reset and clean up */ 1553 auich_halt_pipe(sc, AUICH_PCMI, &sc->pcmi); 1554 auich_halt_pipe(sc, AUICH_MICI, &sc->mici); 1555 auich_freem(sc, temp_buffer, M_DEVBUF); 1556 1557 #ifdef AUICH_DEBUG 1558 sts = bus_space_read_2(sc->iot, sc->aud_ioh, 1559 AUICH_PCMI + sc->sc_sts_reg); 1560 civ = bus_space_read_4(sc->iot, sc->aud_ioh, 1561 AUICH_PCMI + AUICH_CIV); 1562 printf("%s: after calibration and reset sts=%b civ=%u\n", 1563 sc->sc_dev.dv_xname, sts, AUICH_ISTS_BITS, civ); 1564 #endif 1565 1566 /* now finally calculate measured samplerate */ 1567 actual_48k_rate = (bytes * 250000) / wait_us; 1568 1569 if (actual_48k_rate <= 48500) 1570 ac97rate = AUICH_FIXED_RATE; 1571 else 1572 ac97rate = actual_48k_rate; 1573 1574 DPRINTF(AUICH_DEBUG_CODECIO, ("%s: measured ac97 link rate at %d Hz", 1575 sc->sc_dev.dv_xname, actual_48k_rate)); 1576 if (ac97rate != actual_48k_rate) 1577 DPRINTF(AUICH_DEBUG_CODECIO, (", will use %d Hz", ac97rate)); 1578 DPRINTF(AUICH_DEBUG_CODECIO, ("\n")); 1579 1580 return (ac97rate); 1581 } 1582