1 /* $OpenBSD: arc.c,v 1.110 2020/02/13 15:11:32 krw Exp $ */ 2 3 /* 4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Ching Huang Support ARC1880,1882,1213,1223,1214 21 */ 22 #include "bio.h" 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/buf.h> 27 #include <sys/kernel.h> 28 #include <sys/malloc.h> 29 #include <sys/mutex.h> 30 #include <sys/device.h> 31 #include <sys/rwlock.h> 32 #include <sys/task.h> 33 34 #include <machine/bus.h> 35 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 40 #include <scsi/scsi_all.h> 41 #include <scsi/scsiconf.h> 42 43 #include <sys/sensors.h> 44 #if NBIO > 0 45 #include <sys/ioctl.h> 46 #include <dev/biovar.h> 47 #endif 48 49 #ifdef ARC_DEBUG 50 #define ARC_D_INIT (1<<0) 51 #define ARC_D_RW (1<<1) 52 #define ARC_D_DB (1<<2) 53 54 int arcdebug = 0; 55 56 #define DPRINTF(p...) do { if (arcdebug) printf(p); } while (0) 57 #define DNPRINTF(n, p...) do { if ((n) & arcdebug) printf(p); } while (0) 58 59 #else 60 #define DPRINTF(p...) /* p */ 61 #define DNPRINTF(n, p...) /* n, p */ 62 #endif 63 64 #define ARC_HBA_TYPE_A 0x00000001 65 #define ARC_HBA_TYPE_B 0x00000002 66 #define ARC_HBA_TYPE_C 0x00000003 67 #define ARC_HBA_TYPE_D 0x00000004 68 69 #define ARC_RA_PCI_BAR PCI_MAPREG_START 70 #define ARC_RB_DOORBELL_BAR PCI_MAPREG_START 71 #define ARC_RB_RWBUFFER_BAR PCI_MAPREG_PPB_END 72 #define ARC_RC_PCI_BAR PCI_MAPREG_PCB_END 73 #define ARC_RD_PCI_BAR PCI_MAPREG_START 74 75 #define ARCMSR_MAX_CCB_COUNT 264 76 #define ARCMSR_MAX_HBB_POSTQUEUE 264 77 #define ARCMSR_MAX_HBD_POSTQUEUE 256 78 79 /* Areca boards using the Intel IOP are Type A (RA) */ 80 81 #define ARC_RA_INB_MSG0 0x0010 82 #define ARC_RA_INB_MSG0_NOP (0x00000000) 83 #define ARC_RA_INB_MSG0_GET_CONFIG (0x00000001) 84 #define ARC_RA_INB_MSG0_SET_CONFIG (0x00000002) 85 #define ARC_RA_INB_MSG0_ABORT_CMD (0x00000003) 86 #define ARC_RA_INB_MSG0_STOP_BGRB (0x00000004) 87 #define ARC_RA_INB_MSG0_FLUSH_CACHE (0x00000005) 88 #define ARC_RA_INB_MSG0_START_BGRB (0x00000006) 89 #define ARC_RA_INB_MSG0_CHK331PENDING (0x00000007) 90 #define ARC_RA_INB_MSG0_SYNC_TIMER (0x00000008) 91 #define ARC_RA_INB_MSG1 0x0014 92 #define ARC_RA_OUTB_ADDR0 0x0018 93 #define ARC_RA_OUTB_ADDR1 0x001c 94 #define ARC_RA_OUTB_ADDR1_FIRMWARE_OK (1<<31) 95 #define ARC_RA_INB_DOORBELL 0x0020 96 #define ARC_RA_INB_DOORBELL_WRITE_OK (1<<0) 97 #define ARC_RA_INB_DOORBELL_READ_OK (1<<1) 98 #define ARC_RA_OUTB_DOORBELL 0x002c 99 #define ARC_RA_OUTB_DOORBELL_WRITE_OK (1<<0) 100 #define ARC_RA_OUTB_DOORBELL_READ_OK (1<<1) 101 #define ARC_RA_INTRSTAT 0x0030 102 #define ARC_RA_INTRSTAT_MSG0 (1<<0) 103 #define ARC_RA_INTRSTAT_MSG1 (1<<1) 104 #define ARC_RA_INTRSTAT_DOORBELL (1<<2) 105 #define ARC_RA_INTRSTAT_POSTQUEUE (1<<3) 106 #define ARC_RA_INTRSTAT_PCI (1<<4) 107 #define ARC_RA_INTR_STAT_ALL 0x1F 108 #define ARC_RA_INTRMASK 0x0034 109 #define ARC_RA_INTRMASK_MSG0 (1<<0) 110 #define ARC_RA_INTRMASK_MSG1 (1<<1) 111 #define ARC_RA_INTRMASK_DOORBELL (1<<2) 112 #define ARC_RA_INTRMASK_POSTQUEUE (1<<3) 113 #define ARC_RA_INTRMASK_PCI (1<<4) 114 #define ARC_RA_INTR_MASK_ALL 0x1F 115 #define ARC_RA_POST_QUEUE 0x0040 116 #define ARC_RA_POST_QUEUE_ADDR_SHIFT 5 117 #define ARC_RA_POST_QUEUE_IAMBIOS (1<<30) 118 #define ARC_RA_POST_QUEUE_BIGFRAME (1<<31) 119 #define ARC_RA_REPLY_QUEUE 0x0044 120 #define ARC_RA_REPLY_QUEUE_ADDR_SHIFT 5 121 #define ARC_RA_REPLY_QUEUE_ERR (1<<28) 122 #define ARC_RA_REPLY_QUEUE_IAMBIOS (1<<30) 123 #define ARC_RA_MSGBUF 0x0a00 124 #define ARC_RA_MSGBUF_LEN 1024 125 #define ARC_RA_IOC_WBUF_LEN 0x0e00 126 #define ARC_RA_IOC_WBUF 0x0e04 127 #define ARC_RA_IOC_RBUF_LEN 0x0f00 128 #define ARC_RA_IOC_RBUF 0x0f04 129 #define ARC_RA_IOC_RWBUF_MAXLEN 124 /* for both RBUF and WBUF */ 130 131 /* Areca boards using the Marvel IOP0 are Type B (RB) */ 132 133 #define ARC_RB_DRV2IOP_DOORBELL 0x00020400 134 #define ARC_RB_DRV2IOP_DOORBELL_MASK 0x00020404 135 #define ARC_RB_IOP2DRV_DOORBELL 0x00020408 136 #define ARC_RB_IOP2DRV_DOORBELL_FIRMWARE_OK (1<<31) 137 #define ARC_RB_IOP2DRV_DOORBELL_MASK 0x0002040c 138 139 /* Areca boards using the LSI IOP are Type C (RC) */ 140 141 #define ARC_RC_INB_DOORBELL 0x20 142 #define ARC_RC_INTR_STAT 0x30 143 #define ARC_RC_INTR_MASK 0x34 144 #define ARC_RC_OUTB_DOORBELL 0x9C 145 #define ARC_RC_OUTB_DOORBELL_CLR 0xA0 146 #define ARC_RC_D2I_MSG_CMD_DONE 0x08 147 #define ARC_RC_I2D_MSG_CMD_DONE 0x08 148 #define ARC_RC_I2D_MSG_CMD_DONE_CLR 0x08 149 #define ARC_RC_INB_MSGADDR0 0xB0 150 #define ARC_RC_INB_MSGADDR1 0xB4 151 #define ARC_RC_OUTB_MSGADDR0 0xB8 152 #define ARC_RC_OUTB_MSGADDR1 0xBC 153 #define ARC_RC_OUTB_MSG_FIRMWARE_OK 0x80000000 154 #define ARC_RC_INB_POSTQ_LOW 0xC0 155 #define ARC_RC_INB_POSTQ_HIGH 0xC4 156 #define ARC_RC_OUTB_REPLYQ_LOW 0xC8 157 #define ARC_RC_OUTB_REPLYQ_HIGH 0xCC 158 #define ARC_RC_MSG_WBUF_LEN 0x2000 159 #define ARC_RC_MSG_WBUF 0x2004 160 #define ARC_RC_MSG_RBUF_LEN 0x2100 161 #define ARC_RC_MSG_RBUF 0x2104 162 #define ARC_RC_MSG_RWBUF 0x2200 163 164 #define ARC_RC_INB_MSG0_NOP (0x00000000) 165 #define ARC_RC_INB_MSG0_GET_CONFIG (0x00000001) 166 #define ARC_RC_INB_MSG0_SET_CONFIG (0x00000002) 167 #define ARC_RC_INB_MSG0_ABORT_CMD (0x00000003) 168 #define ARC_RC_INB_MSG0_STOP_BGRB (0x00000004) 169 #define ARC_RC_INB_MSG0_FLUSH_CACHE (0x00000005) 170 #define ARC_RC_INB_MSG0_START_BGRB (0x00000006) 171 #define ARC_RC_INB_MSG0_CHK331PENDING (0x00000007) 172 #define ARC_RC_INB_MSG0_SYNC_TIMER (0x00000008) 173 174 #define ARC_RC_D2I_DATA_WRITE_OK 0x00000002 175 #define ARC_RC_D2I_DATA_READ_OK 0x00000004 176 #define ARC_RC_D2I_MESSAGE_CMD_DONE 0x00000008 177 #define ARC_RC_D2I_POSTQUEUE_THROTTLING 0x00000010 178 #define ARC_RC_I2D_DATA_WRITE_OK 0x00000002 179 #define ARC_RC_I2D_DATA_WRITE_OK_CLEAR 0x00000002 180 #define ARC_RC_I2D_DATA_READ_OK 0x00000004 181 #define ARC_RC_I2D_DATA_READ_OK_CLEAR 0x00000004 182 #define ARC_RC_I2D_MESSAGE_CMD_DONE 0x00000008 183 #define ARC_RC_I2D_MESSAGE_CMD_DONE_CLEAR 0x00000008 184 #define ARC_RC_MESSAGE_FIRMWARE_OK 0x80000000 185 186 #define ARC_RC_INTR_STAT_UTILITY_A (1<<0) 187 #define ARC_RC_INTR_STAT_DOORBELL (1<<2) 188 #define ARC_RC_INTR_STAT_POSTQUEUE (1<<3) 189 #define ARC_RC_INTR_MASK_ALL 0x0000000D 190 #define ARC_RC_INTR_MASK_UTILITY_A (1<<0) 191 #define ARC_RC_INTR_MASK_DOORBELL (1<<2) 192 #define ARC_RC_INTR_MASK_POSTQUEUE (1<<3) 193 #define ARC_RC_REPLY_QUEUE_ERR 1 194 #define ARC_RC_THROTTLE 12 195 196 /* Areca boards using the Marvell IOP 9580 are Type D (RD) */ 197 198 #define ARC_RD_INTR_STAT 0x200 199 #define ARC_RD_HOST_INT_ENABLE 0x204 200 #define ARC_RD_INTR_ENABLE 0x20C 201 #define ARC_RD_D2I_MSG_CMD_DONE 0x08 202 #define ARC_RD_I2D_MSG_CMD_DONE 0x2000000 203 #define ARC_RD_I2D_MSG_CMD_DONE_CLR 0x2000000 204 #define ARC_RD_INB_MSGADDR0 0x400 205 #define ARC_RD_INB_MSGADDR1 0x404 206 #define ARC_RD_OUTB_MSGADDR0 0x420 207 #define ARC_RD_OUTB_MSGADDR1 0x424 208 #define ARC_RD_INB_DOORBELL 0x460 209 #define ARC_RD_OUTB_DOORBELL 0x480 210 #define ARC_RD_OUTB_DOORBELL_CLR 0x480 211 #define ARC_RD_OUTB_DOORBELL_ENABLE 0x484 212 #define ARC_RD_OUTB_MSG_FIRMWARE_OK 0x80000000 213 #define ARC_RD_INB_POSTQ_LOW 0x1000 214 #define ARC_RD_INB_POSTQ_HIGH 0x1004 215 #define ARC_RD_OUTB_REPLYQ_LOW 0x1060 216 #define ARC_RD_OUTB_REPLYQ_HIGH 0x1064 217 218 #define ARC_RD_INB_WRITE_PTR 0x1018 219 #define ARC_RD_INB_READ_PTR 0x101C 220 #define ARC_RD_OUTB_COPY_PTR 0x106C 221 #define ARC_RD_OUTB_READ_PTR 0x1070 222 #define ARC_RD_OUTB_INTR_CAUSE 0x1088 223 #define ARC_RD_OUTB_INT_ENABLE 0x108C 224 #define ARC_RD_MSG_WBUF_LEN 0x2000 225 #define ARC_RD_MSG_WBUF 0x2004 226 #define ARC_RD_MSG_RBUF_LEN 0x2100 227 #define ARC_RD_MSG_RBUF 0x2104 228 #define ARC_RD_MSG_RWBUF 0x2200 229 230 #define ARC_RD_INB_MSG0_NOP (0x00000000) 231 #define ARC_RD_INB_MSG0_GET_CONFIG (0x00000001) 232 #define ARC_RD_INB_MSG0_SET_CONFIG (0x00000002) 233 #define ARC_RD_INB_MSG0_ABORT_CMD (0x00000003) 234 #define ARC_RD_INB_MSG0_STOP_BGRB (0x00000004) 235 #define ARC_RD_INB_MSG0_FLUSH_CACHE (0x00000005) 236 #define ARC_RD_INB_MSG0_START_BGRB (0x00000006) 237 #define ARC_RD_INB_MSG0_CHK331PENDING (0x00000007) 238 #define ARC_RD_INB_MSG0_SYNC_TIMER (0x00000008) 239 240 #define ARC_RD_D2I_DATA_WRITE_OK 0x00000001 241 #define ARC_RD_D2I_DATA_READ_OK 0x00000002 242 #define ARC_RD_D2I_MESSAGE_CMD_DONE 0x02000000 243 #define ARC_RD_D2I_POSTQUEUE_THROTTLING 0x00000010 244 #define ARC_RD_I2D_DATA_WRITE_OK 0x00000001 245 #define ARC_RD_I2D_DATA_WRITE_CLEAR 0x00000001 246 #define ARC_RD_I2D_DATA_READ_OK 0x00000002 247 #define ARC_RD_I2D_DATA_READ_CLEAR 0x00000002 248 #define ARC_RD_I2D_MESSAGE_CMD_DONE 0x02000000 249 #define ARC_RD_I2D_MESSAGE_CMD_DONE_CLEAR 0x02000000 250 #define ARC_RD_MESSAGE_FIRMWARE_OK 0x80000000 251 252 #define ARC_RD_INTR_STAT_DOORBELL 0x00001000 253 #define ARC_RD_INTR_STAT_POSTQUEUE 0x00000010 254 #define ARC_RD_INTR_ENABLE_ALL 0x00001010 255 #define ARC_RD_INTR_DISABLE_ALL 0x00000000 256 #define ARC_RD_INTR_ENABLE_DOORBELL 0x00001000 257 #define ARC_RD_INTR_ENABLE_POSTQUEUE 0x00000010 258 #define ARC_RD_REPLY_QUEUE_ERR 1 259 #define ARC_RD_OUTB_LIST_INT_CLR 1 260 261 struct arc_msg_firmware_info { 262 u_int32_t signature; 263 #define ARC_FWINFO_SIGNATURE_GET_CONFIG (0x87974060) 264 #define ARC_FWINFO_SIGNATURE_SET_CONFIG (0x87974063) 265 u_int32_t request_len; 266 u_int32_t queue_len; 267 u_int32_t sdram_size; 268 u_int32_t sata_ports; 269 u_int8_t vendor[40]; 270 u_int8_t model[8]; 271 u_int8_t fw_version[16]; 272 u_int8_t device_map[16]; 273 u_int32_t cfgVersion; 274 u_int8_t cfgSerial[16]; 275 u_int32_t cfgPicStatus; 276 } __packed; 277 278 /* definitions of the firmware commands sent via the doorbells */ 279 280 struct arc_fw_hdr { 281 u_int8_t byte1; 282 u_int8_t byte2; 283 u_int8_t byte3; 284 } __packed; 285 286 /* the fw header must always equal this */ 287 struct arc_fw_hdr arc_fw_hdr = { 0x5e, 0x01, 0x61 }; 288 289 struct arc_fw_bufhdr { 290 struct arc_fw_hdr hdr; 291 u_int16_t len; 292 } __packed; 293 294 #define ARC_FW_RAIDINFO 0x20 /* opcode + raid# */ 295 #define ARC_FW_VOLINFO 0x21 /* opcode + vol# */ 296 #define ARC_FW_DISKINFO 0x22 /* opcode + physdisk# */ 297 #define ARC_FW_SYSINFO 0x23 /* opcode. reply is fw_sysinfo */ 298 #define ARC_FW_MUTE_ALARM 0x30 /* opcode only */ 299 #define ARC_FW_SET_ALARM 0x31 /* opcode + 1 byte for setting */ 300 #define ARC_FW_SET_ALARM_DISABLE 0x00 301 #define ARC_FW_SET_ALARM_ENABLE 0x01 302 #define ARC_FW_NOP 0x38 /* opcode only */ 303 304 #define ARC_FW_CMD_OK 0x41 305 #define ARC_FW_BLINK 0x43 306 #define ARC_FW_BLINK_ENABLE 0x00 307 #define ARC_FW_BLINK_DISABLE 0x01 308 #define ARC_FW_CMD_PASS_REQD 0x4d 309 310 struct arc_fw_comminfo { 311 u_int8_t baud_rate; 312 u_int8_t data_bits; 313 u_int8_t stop_bits; 314 u_int8_t parity; 315 u_int8_t flow_control; 316 } __packed; 317 318 struct arc_fw_scsiattr { 319 u_int8_t channel; /* channel for SCSI target (0/1) */ 320 u_int8_t target; 321 u_int8_t lun; 322 u_int8_t tagged; 323 u_int8_t cache; 324 u_int8_t speed; 325 } __packed; 326 327 struct arc_fw_raidinfo { 328 u_int8_t set_name[16]; 329 u_int32_t capacity; 330 u_int32_t capacity2; 331 u_int32_t fail_mask; 332 u_int8_t device_array[32]; 333 u_int8_t member_devices; 334 u_int8_t new_member_devices; 335 u_int8_t raid_state; 336 u_int8_t volumes; 337 u_int8_t volume_list[16]; 338 u_int8_t reserved1[3]; 339 u_int8_t free_segments; 340 u_int32_t raw_stripes[8]; 341 u_int32_t reserved2[3]; 342 u_int8_t vol_ListX[112]; 343 u_int8_t devEncArray[32]; 344 } __packed; 345 346 struct arc_fw_volinfo { 347 u_int8_t set_name[16]; 348 u_int32_t capacity; 349 u_int32_t capacity2; 350 u_int32_t fail_mask; 351 u_int32_t stripe_size; /* in blocks */ 352 u_int32_t new_fail_mask; 353 u_int32_t new_stripe_size; 354 u_int32_t volume_status; 355 #define ARC_FW_VOL_STATUS_NORMAL 0x00 356 #define ARC_FW_VOL_STATUS_INITTING (1<<0) 357 #define ARC_FW_VOL_STATUS_FAILED (1<<1) 358 #define ARC_FW_VOL_STATUS_MIGRATING (1<<2) 359 #define ARC_FW_VOL_STATUS_REBUILDING (1<<3) 360 #define ARC_FW_VOL_STATUS_NEED_INIT (1<<4) 361 #define ARC_FW_VOL_STATUS_NEED_MIGRATE (1<<5) 362 #define ARC_FW_VOL_STATUS_INIT_FLAG (1<<6) 363 #define ARC_FW_VOL_STATUS_NEED_REGEN (1<<7) 364 #define ARC_FW_VOL_STATUS_CHECKING (1<<8) 365 #define ARC_FW_VOL_STATUS_NEED_CHECK (1<<9) 366 u_int32_t progress; 367 struct arc_fw_scsiattr scsi_attr; 368 u_int8_t member_disks; 369 u_int8_t raid_level; 370 #define ARC_FW_VOL_RAIDLEVEL_0 0x00 371 #define ARC_FW_VOL_RAIDLEVEL_1 0x01 372 #define ARC_FW_VOL_RAIDLEVEL_3 0x02 373 #define ARC_FW_VOL_RAIDLEVEL_5 0x03 374 #define ARC_FW_VOL_RAIDLEVEL_6 0x04 375 #define ARC_FW_VOL_RAIDLEVEL_PASSTHRU 0x05 376 u_int8_t new_member_disks; 377 u_int8_t new_raid_level; 378 u_int8_t raid_set_number; 379 u_int8_t vol_state0; 380 u_int32_t host_speed; 381 u_int32_t vol_state; 382 u_int8_t vol_array[16]; 383 u_int8_t num_5060volumes; 384 u_int8_t reserved[43]; 385 } __packed; 386 387 struct arc_fw_diskinfo { 388 u_int8_t model[40]; 389 u_int8_t serial[20]; 390 u_int8_t firmware_rev[8]; 391 u_int32_t capacity; 392 u_int32_t capacity2; 393 u_int8_t device_state; 394 u_int8_t pio_mode; 395 u_int8_t current_udma_mode; 396 u_int8_t udma_mode; 397 u_int8_t hot_spare_type; 398 u_int8_t raid_number; /* 0xff unowned */ 399 struct arc_fw_scsiattr scsi_attr; 400 u_int8_t reserved[170]; 401 } __packed; 402 403 struct arc_fw_sysinfo { 404 u_int8_t vendor_name[40]; 405 u_int8_t serial_number[16]; 406 u_int8_t firmware_version[16]; 407 u_int8_t boot_version[16]; 408 u_int8_t mb_version[16]; 409 u_int8_t model_name[8]; 410 411 u_int8_t local_ip[4]; 412 u_int8_t current_ip[4]; 413 414 u_int32_t time_tick; 415 u_int32_t cpu_speed; 416 u_int32_t icache; 417 u_int32_t dcache; 418 u_int32_t scache; 419 u_int32_t memory_size; 420 u_int32_t memory_speed; 421 u_int32_t events; 422 423 u_int8_t gsiMacAddress[6]; 424 u_int8_t gsiDhcp; 425 u_int8_t alarm; 426 u_int8_t channel_usage; 427 u_int8_t max_ata_mode; 428 u_int8_t sdram_ecc; 429 u_int8_t rebuild_priority; 430 struct arc_fw_comminfo comm_a; 431 struct arc_fw_comminfo comm_b; 432 u_int8_t ide_channels; 433 u_int8_t scsi_host_channels; 434 u_int8_t ide_host_channels; 435 u_int8_t max_volume_set; 436 u_int8_t max_raid_set; 437 u_int8_t ether_port; 438 u_int8_t raid6_engine; 439 u_int8_t reserved[75]; 440 } __packed; 441 442 struct arc_iop; 443 struct arc_ccb; 444 SLIST_HEAD(arc_ccb_list, arc_ccb); 445 446 struct InBound_SRB { 447 u_int32_t addressLow; /* pointer to SRB block */ 448 u_int32_t addressHigh; 449 u_int32_t length; /* in DWORDs */ 450 u_int32_t reserved0; 451 }; 452 453 struct OutBound_SRB { 454 u_int32_t addressLow; /* pointer to SRB block */ 455 u_int32_t addressHigh; 456 }; 457 458 struct arc_HBD_Msgu { 459 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 460 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 461 u_int16_t postq_index; 462 u_int16_t doneq_index; 463 }; 464 465 #define ARC_MAX_CMDQ_PTR_LEN sizeof(struct arc_HBD_Msgu) 466 467 struct arc_msg_scsicmd { 468 u_int8_t bus; 469 u_int8_t target; 470 u_int8_t lun; 471 u_int8_t function; 472 473 u_int8_t cdb_len; 474 u_int8_t sgl_len; 475 u_int8_t flags; 476 #define ARC_MSG_SCSICMD_FLAG_SGL_BSIZE_512 (1<<0) 477 #define ARC_MSG_SCSICMD_FLAG_FROM_BIOS (1<<1) 478 #define ARC_MSG_SCSICMD_FLAG_WRITE (1<<2) 479 #define ARC_MSG_SCSICMD_FLAG_SIMPLEQ (0x00) 480 #define ARC_MSG_SCSICMD_FLAG_HEADQ (0x08) 481 #define ARC_MSG_SCSICMD_FLAG_ORDERQ (0x10) 482 u_int8_t msgPages; 483 484 u_int32_t context; 485 u_int32_t data_len; 486 487 #define ARC_MSG_CDBLEN 16 488 u_int8_t cdb[ARC_MSG_CDBLEN]; 489 490 u_int8_t status; 491 #define ARC_MSG_STATUS_SELTIMEOUT 0xf0 492 #define ARC_MSG_STATUS_ABORTED 0xf1 493 #define ARC_MSG_STATUS_INIT_FAIL 0xf2 494 #define ARC_MSG_SENSELEN 15 495 u_int8_t sense_data[ARC_MSG_SENSELEN]; 496 497 /* followed by an sgl */ 498 } __packed; 499 500 struct arc_sge { 501 u_int32_t sg_length; 502 #define ARC_SGE_64BIT (1<<24) 503 u_int32_t sg_lo_addr; 504 u_int32_t sg_hi_addr; 505 } __packed; 506 507 #define ARC_MAX_TARGET 16 508 #define ARC_MAX_LUN 8 509 #define ARC_MAX_IOCMDLEN 512 510 #define ARC_BLOCKSIZE 512 511 512 /* the firmware deals with up to 256 or 512 byte command frames. */ 513 /* sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 38) == 508 */ 514 #define ARC_SGL_MAXLEN 38 515 /* sizeof(struct arc_msg_scsicmd) + (sizeof(struct arc_sge) * 17) == 252 */ 516 #define ARC_SGL_256LEN 17 517 518 struct arc_io_cmd { 519 struct arc_msg_scsicmd cmd; 520 struct arc_sge sgl[ARC_SGL_MAXLEN]; 521 u_int32_t reserved1; 522 struct arc_ccb *ccb; 523 u_int32_t reserved2[6]; 524 } __packed; 525 526 #define ARC_IO_CMD_LEN 512+32 527 528 /* stuff to manage a scsi command */ 529 struct arc_ccb { 530 struct arc_softc *ccb_sc; 531 532 struct scsi_xfer *ccb_xs; 533 534 bus_dmamap_t ccb_dmamap; 535 bus_addr_t cmd_dma_offset; 536 struct arc_io_cmd *ccb_cmd; 537 u_int32_t ccb_cmd_post; 538 539 SLIST_ENTRY(arc_ccb) ccb_link; 540 u_int32_t arc_io_cmd_length; 541 }; 542 543 struct arc_softc { 544 struct device sc_dev; 545 const struct arc_iop *sc_iop; 546 struct scsi_link sc_link; 547 548 pci_chipset_tag_t sc_pc; 549 pcitag_t sc_tag; 550 551 bus_space_tag_t sc_iot; 552 bus_space_handle_t sc_ioh; 553 bus_size_t sc_ios; 554 bus_dma_tag_t sc_dmat; 555 556 void *sc_ih; 557 558 u_int32_t sc_req_count; 559 560 struct arc_dmamem *sc_requests; 561 struct arc_ccb *sc_ccbs; 562 struct arc_ccb_list sc_ccb_free; 563 struct mutex sc_ccb_mtx; 564 565 struct scsi_iopool sc_iopool; 566 struct scsibus_softc *sc_scsibus; 567 568 struct rwlock sc_lock; 569 volatile int sc_talking; 570 571 struct ksensor *sc_sensors; 572 struct ksensordev sc_sensordev; 573 int sc_nsensors; 574 575 u_int32_t sc_ledmask; 576 u_int32_t sc_adp_type; 577 u_int32_t sc_ccb_phys_hi; 578 u_int32_t postQ_buffer; 579 u_int32_t doneQ_buffer; 580 bus_addr_t cmdQ_ptr_offset; 581 struct arc_HBD_Msgu *pmu; 582 }; 583 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 584 585 /* wrap up the bus_dma api */ 586 struct arc_dmamem { 587 bus_dmamap_t adm_map; 588 bus_dma_segment_t adm_seg; 589 size_t adm_size; 590 caddr_t adm_kva; 591 }; 592 #define ARC_DMA_MAP(_adm) ((_adm)->adm_map) 593 #define ARC_DMA_DVA(_adm) ((_adm)->adm_map->dm_segs[0].ds_addr) 594 #define ARC_DMA_KVA(_adm) ((void *)(_adm)->adm_kva) 595 596 int arc_match(struct device *, void *, void *); 597 void arc_attach(struct device *, struct device *, void *); 598 int arc_detach(struct device *, int); 599 int arc_activate(struct device *, int); 600 int arc_intr(void *); 601 int arc_intr_A(void *); 602 int arc_intr_C(void *); 603 int arc_intr_D(void *); 604 605 /* interface for scsi midlayer to talk to */ 606 void arc_scsi_cmd(struct scsi_xfer *); 607 608 /* code to deal with getting bits in and out of the bus space */ 609 u_int32_t arc_read(struct arc_softc *, bus_size_t); 610 void arc_read_region(struct arc_softc *, bus_size_t, 611 void *, size_t); 612 void arc_write(struct arc_softc *, bus_size_t, u_int32_t); 613 void arc_write_region(struct arc_softc *, bus_size_t, 614 void *, size_t); 615 int arc_wait_eq(struct arc_softc *, bus_size_t, 616 u_int32_t, u_int32_t); 617 int arc_wait_ne(struct arc_softc *, bus_size_t, 618 u_int32_t, u_int32_t); 619 int arc_msg0(struct arc_softc *, u_int32_t); 620 621 struct arc_dmamem *arc_dmamem_alloc(struct arc_softc *, size_t); 622 void arc_dmamem_free(struct arc_softc *, 623 struct arc_dmamem *); 624 void arc_free_ccb_src(struct arc_softc *sc); 625 626 int arc_alloc_ccbs(struct arc_softc *); 627 struct arc_ccb *arc_get_ccb(struct arc_softc *); 628 void arc_put_ccb(struct arc_softc *, struct arc_ccb *); 629 int arc_load_xs(struct arc_ccb *); 630 int arc_complete(struct arc_softc *, struct arc_ccb *, 631 int); 632 void arc_scsi_cmd_done(struct arc_softc *, struct arc_ccb *, 633 u_int32_t); 634 635 int arc_map_pci_resources(struct arc_softc *, 636 struct pci_attach_args *); 637 void arc_unmap_pci_resources(struct arc_softc *); 638 int arc_chipA_firmware(struct arc_softc *); 639 int arc_chipB_firmware(struct arc_softc *); 640 int arc_chipC_firmware(struct arc_softc *); 641 int arc_chipD_firmware(struct arc_softc *); 642 void arc_enable_all_intr(struct arc_softc *); 643 void arc_disable_all_intr(struct arc_softc *); 644 void arc_stop_bgrb_proc(struct arc_softc *sc); 645 void arc_flush_cache(struct arc_softc *sc); 646 void arc_iop_set_conf(struct arc_softc *sc); 647 648 #if NBIO > 0 649 /* stuff to do messaging via the doorbells */ 650 void arc_lock(struct arc_softc *); 651 void arc_unlock(struct arc_softc *); 652 void arc_wait(struct arc_softc *); 653 u_int8_t arc_msg_cksum(void *, u_int16_t); 654 int arc_msgbuf(struct arc_softc *, void *, size_t, 655 void *, size_t, int); 656 657 /* bioctl */ 658 int arc_bioctl(struct device *, u_long, caddr_t); 659 int arc_bio_inq(struct arc_softc *, struct bioc_inq *); 660 int arc_bio_vol(struct arc_softc *, struct bioc_vol *); 661 int arc_bio_disk(struct arc_softc *, struct bioc_disk *); 662 int arc_bio_alarm(struct arc_softc *, struct bioc_alarm *); 663 int arc_bio_alarm_state(struct arc_softc *, 664 struct bioc_alarm *); 665 int arc_bio_blink(struct arc_softc *, struct bioc_blink *); 666 667 int arc_bio_getvol(struct arc_softc *, int, 668 struct arc_fw_volinfo *); 669 670 #ifndef SMALL_KERNEL 671 struct arc_task { 672 struct task t; 673 struct arc_softc *sc; 674 }; 675 /* sensors */ 676 void arc_create_sensors(void *); 677 void arc_refresh_sensors(void *); 678 #endif /* SMALL_KERNEL */ 679 #endif 680 681 struct cfattach arc_ca = { 682 sizeof(struct arc_softc), arc_match, arc_attach, arc_detach, 683 arc_activate 684 }; 685 686 struct cfdriver arc_cd = { 687 NULL, "arc", DV_DULL 688 }; 689 690 struct scsi_adapter arc_switch = { 691 arc_scsi_cmd, NULL, NULL, NULL, NULL 692 }; 693 694 /* real stuff for dealing with the hardware */ 695 struct arc_iop { 696 int (*iop_query_firmware)(struct arc_softc *); 697 }; 698 699 static const struct arc_iop arc_intel = { 700 arc_chipA_firmware 701 }; 702 703 static const struct arc_iop arc_marvell = { 704 arc_chipB_firmware 705 }; 706 707 static const struct arc_iop arc_lsi = { 708 arc_chipC_firmware 709 }; 710 711 static const struct arc_iop arc_marvell2 = { 712 arc_chipD_firmware 713 }; 714 715 struct arc_board { 716 pcireg_t ab_vendor; 717 pcireg_t ab_product; 718 const struct arc_iop *ab_iop; 719 }; 720 const struct arc_board *arc_match_board(struct pci_attach_args *); 721 722 static const struct arc_board arc_devices[] = { 723 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1110, &arc_intel }, 724 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1120, &arc_intel }, 725 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1130, &arc_intel }, 726 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1160, &arc_intel }, 727 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1170, &arc_intel }, 728 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1200, &arc_intel }, 729 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1200_B, &arc_marvell }, 730 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1202, &arc_intel }, 731 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1210, &arc_intel }, 732 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1214, &arc_marvell2 }, 733 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1220, &arc_intel }, 734 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1230, &arc_intel }, 735 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1260, &arc_intel }, 736 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1270, &arc_intel }, 737 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1280, &arc_intel }, 738 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1380, &arc_intel }, 739 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1381, &arc_intel }, 740 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1680, &arc_intel }, 741 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1681, &arc_intel }, 742 { PCI_VENDOR_ARECA, PCI_PRODUCT_ARECA_ARC1880, &arc_lsi } 743 }; 744 745 const struct arc_board * 746 arc_match_board(struct pci_attach_args *pa) 747 { 748 const struct arc_board *ab; 749 int i; 750 751 for (i = 0; i < sizeof(arc_devices) / sizeof(arc_devices[0]); i++) { 752 ab = &arc_devices[i]; 753 754 if (PCI_VENDOR(pa->pa_id) == ab->ab_vendor && 755 PCI_PRODUCT(pa->pa_id) == ab->ab_product) 756 return (ab); 757 } 758 759 return (NULL); 760 } 761 762 int 763 arc_match(struct device *parent, void *match, void *aux) 764 { 765 return ((arc_match_board(aux) == NULL) ? 0 : 1); 766 } 767 768 void 769 arc_attach(struct device *parent, struct device *self, void *aux) 770 { 771 struct arc_softc *sc = (struct arc_softc *)self; 772 struct pci_attach_args *pa = aux; 773 struct scsibus_attach_args saa; 774 struct device *child; 775 776 sc->sc_talking = 0; 777 rw_init(&sc->sc_lock, "arcmsg"); 778 779 sc->sc_iop = arc_match_board(pa)->ab_iop; 780 if(sc->sc_iop == &arc_intel) 781 sc->sc_adp_type = ARC_HBA_TYPE_A; 782 else if(sc->sc_iop == &arc_marvell) 783 sc->sc_adp_type = ARC_HBA_TYPE_B; 784 else if(sc->sc_iop == &arc_lsi) 785 sc->sc_adp_type = ARC_HBA_TYPE_C; 786 else if(sc->sc_iop == &arc_marvell2) 787 sc->sc_adp_type = ARC_HBA_TYPE_D; 788 if (arc_map_pci_resources(sc, pa) != 0) { 789 /* error message printed by arc_map_pci_resources */ 790 return; 791 } 792 793 if (arc_alloc_ccbs(sc) != 0) { 794 /* error message printed by arc_alloc_ccbs */ 795 goto unmap_pci; 796 } 797 798 arc_iop_set_conf(sc); 799 800 if (sc->sc_iop->iop_query_firmware(sc) != 0) { 801 /* error message printed by arc_query_firmware */ 802 goto unmap_pci; 803 } 804 805 sc->sc_link.adapter = &arc_switch; 806 sc->sc_link.adapter_softc = sc; 807 sc->sc_link.adapter_target = ARC_MAX_TARGET; 808 sc->sc_link.adapter_buswidth = ARC_MAX_TARGET; 809 sc->sc_link.openings = sc->sc_req_count; 810 sc->sc_link.pool = &sc->sc_iopool; 811 812 bzero(&saa, sizeof(saa)); 813 saa.saa_sc_link = &sc->sc_link; 814 815 child = config_found(self, &saa, scsiprint); 816 sc->sc_scsibus = (struct scsibus_softc *)child; 817 818 /* enable interrupts */ 819 arc_enable_all_intr(sc); 820 821 #if NBIO > 0 822 if (bio_register(self, arc_bioctl) != 0) 823 panic("%s: bioctl registration failed", DEVNAME(sc)); 824 825 #ifndef SMALL_KERNEL 826 /* 827 * you need to talk to the firmware to get volume info. our firmware 828 * interface relies on being able to sleep, so we need to use a thread 829 * to do the work. 830 */ 831 { 832 struct arc_task *at; 833 at = malloc(sizeof(*at), M_TEMP, M_WAITOK); 834 835 at->sc = sc; 836 task_set(&at->t, arc_create_sensors, at); 837 task_add(systq, &at->t); 838 } 839 #endif 840 #endif 841 842 return; 843 unmap_pci: 844 arc_unmap_pci_resources(sc); 845 } 846 847 int 848 arc_activate(struct device *self, int act) 849 { 850 int rv = 0; 851 852 switch (act) { 853 case DVACT_POWERDOWN: 854 rv = config_activate_children(self, act); 855 arc_detach(self, 0); 856 break; 857 default: 858 rv = config_activate_children(self, act); 859 break; 860 } 861 return (rv); 862 } 863 864 int 865 arc_detach(struct device *self, int flags) 866 { 867 struct arc_softc *sc = (struct arc_softc *)self; 868 869 arc_stop_bgrb_proc(sc); 870 arc_flush_cache(sc); 871 872 return (0); 873 } 874 875 int 876 arc_intr_A(void *arg) 877 { 878 struct arc_softc *sc = arg; 879 struct arc_ccb *ccb = NULL; 880 char *kva = ARC_DMA_KVA(sc->sc_requests); 881 struct arc_io_cmd *cmd; 882 u_int32_t reg, intrstat, error; 883 int ret = 0; 884 885 intrstat = arc_read(sc, ARC_RA_INTRSTAT); 886 intrstat &= ARC_RA_INTRSTAT_POSTQUEUE | ARC_RA_INTRSTAT_DOORBELL | 887 ARC_RA_INTRSTAT_MSG0; 888 arc_write(sc, ARC_RA_INTRSTAT, intrstat); 889 890 if (intrstat & ARC_RA_INTRSTAT_DOORBELL) { 891 ret = 1; 892 if (sc->sc_talking) { 893 /* if an ioctl is talking, wake it up */ 894 arc_write(sc, ARC_RA_INTRMASK, 895 ~ARC_RA_INTRMASK_POSTQUEUE); 896 wakeup(sc); 897 } else { 898 /* otherwise drop it */ 899 reg = arc_read(sc, ARC_RA_OUTB_DOORBELL); 900 arc_write(sc, ARC_RA_OUTB_DOORBELL, reg); 901 if (reg & ARC_RA_OUTB_DOORBELL_WRITE_OK) 902 arc_write(sc, ARC_RA_INB_DOORBELL, 903 ARC_RA_INB_DOORBELL_READ_OK); 904 } 905 } 906 907 if (intrstat & ARC_RA_INTRSTAT_POSTQUEUE) { 908 while ((reg = arc_read(sc, ARC_RA_REPLY_QUEUE)) != 0xffffffff) { 909 ret = 1; 910 cmd = (struct arc_io_cmd *)(kva + 911 ((reg << ARC_RA_REPLY_QUEUE_ADDR_SHIFT) - 912 (u_int32_t)ARC_DMA_DVA(sc->sc_requests))); 913 ccb = cmd->ccb; 914 915 bus_dmamap_sync(sc->sc_dmat, ARC_DMA_MAP(sc->sc_requests), 916 ccb->cmd_dma_offset, ARC_MAX_IOCMDLEN, 917 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 918 919 error = (reg & ARC_RA_REPLY_QUEUE_ERR)? 1:0; 920 arc_scsi_cmd_done(sc, ccb, error); 921 } 922 } 923 return (ret); 924 } 925 926 int 927 arc_intr_C(void *arg) 928 { 929 struct arc_softc *sc = arg; 930 struct arc_ccb *ccb = NULL; 931 char *kva = ARC_DMA_KVA(sc->sc_requests); 932 struct arc_io_cmd *cmd; 933 u_int32_t reg, intrstat, obmsg, error; 934 int ret = 0, throttling; 935 936 intrstat = arc_read(sc, ARC_RC_INTR_STAT); 937 if (!(intrstat & (ARC_RC_INTR_STAT_POSTQUEUE | 938 ARC_RC_INTR_STAT_DOORBELL))) 939 return (ret); 940 941 if (intrstat & ARC_RC_INTR_STAT_DOORBELL) { 942 ret = 1; 943 if (sc->sc_talking) { 944 /* if an ioctl is talking, wake it up */ 945 arc_write(sc, ARC_RC_INTR_MASK, 946 ~ARC_RC_INTR_MASK_POSTQUEUE); 947 wakeup(sc); 948 } else { 949 /* otherwise drop it */ 950 reg = arc_read(sc, ARC_RC_OUTB_DOORBELL); 951 arc_write(sc, ARC_RC_OUTB_DOORBELL_CLR, reg); 952 if (reg & ARC_RC_I2D_DATA_WRITE_OK) { 953 arc_write(sc, ARC_RC_INB_DOORBELL, 954 ARC_RC_I2D_DATA_READ_OK); 955 } 956 /* if (reg & ARC_RC_I2D_DATA_READ_OK) { 957 arc_write(sc, ARC_RC_INB_DOORBELL, 958 ARC_RC_D2I_DATA_WRITE_OK); 959 } 960 */ 961 if (reg & ARC_RC_I2D_MESSAGE_CMD_DONE) { 962 arc_write(sc, ARC_RC_OUTB_DOORBELL_CLR, 963 ARC_RC_I2D_MSG_CMD_DONE_CLR); 964 obmsg = arc_read(sc, ARC_RC_MSG_RWBUF); 965 if (obmsg == ARC_FWINFO_SIGNATURE_GET_CONFIG) 966 ; /* handle devices hot-plug */ 967 } 968 969 } 970 } 971 972 if (intrstat & ARC_RC_INTR_STAT_POSTQUEUE) { 973 ret = 1; 974 throttling = 0; 975 while (arc_read(sc, ARC_RC_INTR_STAT) & 976 ARC_RC_INTR_STAT_POSTQUEUE) { 977 reg = arc_read(sc, ARC_RC_OUTB_REPLYQ_LOW); 978 cmd = (struct arc_io_cmd *)(kva + ((reg & 0xFFFFFFE0) - 979 (u_int32_t)ARC_DMA_DVA(sc->sc_requests))); 980 ccb = cmd->ccb; 981 982 bus_dmamap_sync(sc->sc_dmat, ARC_DMA_MAP(sc->sc_requests), 983 ccb->cmd_dma_offset, ARC_MAX_IOCMDLEN, 984 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 985 986 error = (reg & ARC_RC_REPLY_QUEUE_ERR); 987 arc_scsi_cmd_done(sc, ccb, error); 988 throttling++; 989 if(throttling == ARC_RC_THROTTLE) { 990 arc_write(sc, ARC_RC_INB_DOORBELL, 991 ARC_RC_D2I_POSTQUEUE_THROTTLING); 992 throttling = 0; 993 } 994 } 995 } 996 997 return (ret); 998 } 999 1000 static u_int16_t 1001 arcmsr_get_doneq_index(struct arc_HBD_Msgu *phbdmu) 1002 { 1003 u_int16_t doneq_index, index_stripped; 1004 1005 doneq_index = phbdmu->doneq_index; 1006 if (doneq_index & 0x4000) { 1007 index_stripped = doneq_index & 0xFF; 1008 index_stripped += 1; 1009 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1010 phbdmu->doneq_index = index_stripped ? 1011 (index_stripped | 0x4000) : index_stripped; 1012 } else { 1013 index_stripped = doneq_index; 1014 index_stripped += 1; 1015 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1016 phbdmu->doneq_index = index_stripped ? 1017 index_stripped : (index_stripped | 0x4000); 1018 } 1019 return (phbdmu->doneq_index); 1020 } 1021 1022 int 1023 arc_intr_D(void *arg) 1024 { 1025 struct arc_softc *sc = arg; 1026 struct arc_ccb *ccb = NULL; 1027 char *kva = ARC_DMA_KVA(sc->sc_requests); 1028 struct arc_io_cmd *cmd; 1029 u_int32_t reg, intrstat, obmsg, error; 1030 u_int32_t ob_write_ptr; 1031 u_int16_t doneq_index; 1032 int ret = 0; 1033 struct arc_HBD_Msgu *pmu; 1034 1035 intrstat = arc_read(sc, ARC_RD_INTR_STAT); 1036 if (!(intrstat & (ARC_RD_INTR_STAT_POSTQUEUE | 1037 ARC_RD_INTR_STAT_DOORBELL))) 1038 return (ret); 1039 1040 if (intrstat & ARC_RD_INTR_STAT_DOORBELL) { 1041 ret = 1; 1042 if (sc->sc_talking) { 1043 /* if an ioctl is talking, wake it up */ 1044 arc_write(sc, ARC_RD_INTR_ENABLE, 1045 ARC_RD_INTR_ENABLE_POSTQUEUE); 1046 wakeup(sc); 1047 } else { 1048 /* otherwise drop it */ 1049 reg = arc_read(sc, ARC_RD_OUTB_DOORBELL); 1050 arc_write(sc, ARC_RD_OUTB_DOORBELL, reg); 1051 if (reg & ARC_RD_I2D_DATA_WRITE_OK) { 1052 arc_write(sc, ARC_RD_INB_DOORBELL, 1053 ARC_RD_I2D_DATA_READ_OK); 1054 } 1055 /* if (reg & ARC_RD_I2D_DATA_READ_OK) { 1056 arc_write(sc, ARC_RD_INB_DOORBELL, 1057 ARC_RD_D2I_DATA_WRITE_OK); 1058 } 1059 */ 1060 if (reg & ARC_RD_I2D_MESSAGE_CMD_DONE) { 1061 arc_write(sc, ARC_RD_OUTB_DOORBELL_CLR, 1062 ARC_RD_I2D_MSG_CMD_DONE_CLR); 1063 obmsg = arc_read(sc, ARC_RD_MSG_RWBUF); 1064 if (obmsg == ARC_FWINFO_SIGNATURE_GET_CONFIG) 1065 ; /* handle devices hot-plug */ 1066 } 1067 1068 } 1069 } 1070 1071 if (intrstat & ARC_RD_INTR_STAT_POSTQUEUE) { 1072 ret = 1; 1073 arc_write(sc, ARC_RD_OUTB_INTR_CAUSE, ARC_RD_OUTB_LIST_INT_CLR); 1074 bus_dmamap_sync(sc->sc_dmat, ARC_DMA_MAP(sc->sc_requests), 1075 sc->cmdQ_ptr_offset, ARC_MAX_CMDQ_PTR_LEN, 1076 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1077 pmu = sc->pmu; 1078 ob_write_ptr = pmu->done_qbuffer[0].addressLow; 1079 doneq_index = pmu->doneq_index; 1080 while ((doneq_index & 0xFF) != (ob_write_ptr & 0xFF)) { 1081 doneq_index = arcmsr_get_doneq_index(pmu); 1082 reg = pmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 1083 cmd = (struct arc_io_cmd *)(kva + ((reg & 0xFFFFFFF0) - 1084 (u_int32_t)ARC_DMA_DVA(sc->sc_requests))); 1085 ccb = cmd->ccb; 1086 bus_dmamap_sync(sc->sc_dmat, ARC_DMA_MAP(sc->sc_requests), 1087 ccb->cmd_dma_offset, ARC_MAX_IOCMDLEN, 1088 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1089 error = (reg & ARC_RD_REPLY_QUEUE_ERR); 1090 arc_scsi_cmd_done(sc, ccb, error); 1091 arc_write(sc, ARC_RD_OUTB_READ_PTR, doneq_index); 1092 ob_write_ptr = pmu->done_qbuffer[0].addressLow; 1093 } 1094 } 1095 1096 return (ret); 1097 } 1098 1099 int 1100 arc_intr(void *arg) 1101 { 1102 struct arc_softc *sc = arg; 1103 int ret = 0; 1104 1105 switch(sc->sc_adp_type) { 1106 case ARC_HBA_TYPE_A: 1107 ret = arc_intr_A(arg); 1108 break; 1109 case ARC_HBA_TYPE_C: 1110 ret = arc_intr_C(arg); 1111 break; 1112 case ARC_HBA_TYPE_D: 1113 ret = arc_intr_D(arg); 1114 break; 1115 } 1116 return (ret); 1117 } 1118 1119 void 1120 arc_scsi_cmd(struct scsi_xfer *xs) 1121 { 1122 struct scsi_link *link = xs->sc_link; 1123 struct arc_softc *sc = link->adapter_softc; 1124 struct arc_ccb *ccb; 1125 struct arc_msg_scsicmd *cmd; 1126 u_int32_t reg, cdb_len; 1127 int s; 1128 struct arc_HBD_Msgu *pmu; 1129 u_int16_t index_stripped; 1130 u_int16_t postq_index; 1131 struct InBound_SRB *pinbound_srb; 1132 1133 if (xs->cmdlen > ARC_MSG_CDBLEN) { 1134 bzero(&xs->sense, sizeof(xs->sense)); 1135 xs->sense.error_code = SSD_ERRCODE_VALID | 0x70; 1136 xs->sense.flags = SKEY_ILLEGAL_REQUEST; 1137 xs->sense.add_sense_code = 0x20; 1138 xs->error = XS_SENSE; 1139 scsi_done(xs); 1140 return; 1141 } 1142 1143 ccb = xs->io; 1144 ccb->ccb_xs = xs; 1145 1146 if (arc_load_xs(ccb) != 0) { 1147 xs->error = XS_DRIVER_STUFFUP; 1148 scsi_done(xs); 1149 return; 1150 } 1151 1152 cmd = &ccb->ccb_cmd->cmd; 1153 reg = ccb->ccb_cmd_post; 1154 ccb->ccb_cmd->ccb = ccb; 1155 /* bus is always 0 */ 1156 cmd->target = link->target; 1157 cmd->lun = link->lun; 1158 cmd->function = 1; /* XXX magic number */ 1159 1160 cmd->cdb_len = xs->cmdlen; 1161 cmd->sgl_len = ccb->ccb_dmamap->dm_nsegs; 1162 if (xs->flags & SCSI_DATA_OUT) 1163 cmd->flags = ARC_MSG_SCSICMD_FLAG_WRITE; 1164 if (ccb->ccb_dmamap->dm_nsegs > ARC_SGL_256LEN) { 1165 cmd->flags |= ARC_MSG_SCSICMD_FLAG_SGL_BSIZE_512; 1166 /* reg |= ARC_RA_POST_QUEUE_BIGFRAME; */ 1167 } 1168 1169 cmd->data_len = htole32(xs->datalen); 1170 1171 bcopy(xs->cmd, cmd->cdb, xs->cmdlen); 1172 1173 /* we've built the command, let's put it on the hw */ 1174 bus_dmamap_sync(sc->sc_dmat, ARC_DMA_MAP(sc->sc_requests), 1175 ccb->cmd_dma_offset, ARC_MAX_IOCMDLEN, 1176 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1177 1178 s = splbio(); 1179 switch(sc->sc_adp_type) { 1180 case ARC_HBA_TYPE_A: 1181 if (cmd->flags & ARC_MSG_SCSICMD_FLAG_SGL_BSIZE_512) 1182 reg |= ARC_RA_POST_QUEUE_BIGFRAME; 1183 arc_write(sc, ARC_RA_POST_QUEUE, reg); 1184 break; 1185 case ARC_HBA_TYPE_C: 1186 cdb_len = sizeof(struct arc_msg_scsicmd) + 1187 sizeof(struct arc_sge) * ccb->ccb_dmamap->dm_nsegs; 1188 if (cdb_len > 0x300) 1189 cdb_len = 0x300; 1190 reg = reg | ((cdb_len - 1) >> 6) | 1; 1191 if (sc->sc_ccb_phys_hi) 1192 arc_write(sc, ARC_RC_INB_POSTQ_HIGH, sc->sc_ccb_phys_hi); 1193 arc_write(sc, ARC_RC_INB_POSTQ_LOW, reg); 1194 break; 1195 case ARC_HBA_TYPE_D: 1196 pmu = sc->pmu; 1197 postq_index = pmu->postq_index; 1198 pinbound_srb = (struct InBound_SRB *)&pmu->post_qbuffer[postq_index & 0xFF]; 1199 1200 pinbound_srb->addressHigh = sc->sc_ccb_phys_hi; 1201 pinbound_srb->addressLow = ccb->ccb_cmd_post; 1202 pinbound_srb->length = ccb->arc_io_cmd_length >> 2; 1203 cmd->context = ccb->ccb_cmd_post; 1204 if (postq_index & 0x4000) { 1205 index_stripped = postq_index & 0xFF; 1206 index_stripped += 1; 1207 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1208 pmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1209 } else { 1210 index_stripped = postq_index; 1211 index_stripped += 1; 1212 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1213 pmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1214 } 1215 bus_dmamap_sync(sc->sc_dmat, ARC_DMA_MAP(sc->sc_requests), 1216 sc->cmdQ_ptr_offset, ARC_MAX_CMDQ_PTR_LEN, 1217 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1218 arc_write(sc, ARC_RD_INB_WRITE_PTR, postq_index); 1219 break; 1220 } 1221 if (xs->flags & SCSI_POLL) { 1222 if (arc_complete(sc, ccb, xs->timeout) != 0) { 1223 xs->error = XS_DRIVER_STUFFUP; 1224 scsi_done(xs); 1225 } 1226 } 1227 splx(s); 1228 } 1229 1230 int 1231 arc_load_xs(struct arc_ccb *ccb) 1232 { 1233 struct arc_softc *sc = ccb->ccb_sc; 1234 struct scsi_xfer *xs = ccb->ccb_xs; 1235 bus_dmamap_t dmap = ccb->ccb_dmamap; 1236 struct arc_sge *sgl = ccb->ccb_cmd->sgl, *sge; 1237 u_int64_t addr; 1238 int i, error; 1239 u_int32_t msg_length; 1240 1241 if (xs->datalen == 0) 1242 { 1243 ccb->arc_io_cmd_length = sizeof(struct arc_msg_scsicmd); 1244 ccb->ccb_cmd->cmd.msgPages = 1; 1245 return (0); 1246 } 1247 error = bus_dmamap_load(sc->sc_dmat, dmap, 1248 xs->data, xs->datalen, NULL, 1249 (xs->flags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 1250 if (error != 0) { 1251 printf("%s: error %d loading dmamap\n", DEVNAME(sc), error); 1252 return (1); 1253 } 1254 1255 for (i = 0; i < dmap->dm_nsegs; i++) { 1256 sge = &sgl[i]; 1257 1258 sge->sg_length = htole32(ARC_SGE_64BIT | dmap->dm_segs[i].ds_len); 1259 addr = dmap->dm_segs[i].ds_addr; 1260 sge->sg_hi_addr = htole32((u_int32_t)(addr >> 32)); 1261 sge->sg_lo_addr = htole32((u_int32_t)addr); 1262 } 1263 ccb->arc_io_cmd_length = sizeof(struct arc_msg_scsicmd) + 1264 sizeof(struct arc_sge) * dmap->dm_nsegs; 1265 msg_length = ccb->arc_io_cmd_length; 1266 ccb->ccb_cmd->cmd.msgPages = (msg_length/256) + ((msg_length % 256) ? 1 : 0); 1267 1268 bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize, 1269 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : 1270 BUS_DMASYNC_PREWRITE); 1271 1272 return (0); 1273 } 1274 1275 void 1276 arc_scsi_cmd_done(struct arc_softc *sc, struct arc_ccb *ccb, u_int32_t error) 1277 { 1278 struct scsi_xfer *xs = ccb->ccb_xs; 1279 struct arc_msg_scsicmd *cmd; 1280 1281 if (xs->datalen != 0) { 1282 bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap, 0, 1283 ccb->ccb_dmamap->dm_mapsize, (xs->flags & SCSI_DATA_IN) ? 1284 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1285 bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap); 1286 } 1287 1288 if (error) { 1289 cmd = &ccb->ccb_cmd->cmd; 1290 DPRINTF("%s: arc_scsi_cmd_done error! target 0x%x, lun 0x%x, " 1291 "status = 0x%x\n", DEVNAME(sc), cmd->target, cmd->lun, 1292 cmd->status); 1293 DPRINTF("%s: scsi cdb: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x" 1294 ", 0x%x, 0x%x, 0x%x\n", DEVNAME(sc), cmd->cdb[0], cmd->cdb[1], 1295 cmd->cdb[2], cmd->cdb[3],cmd->cdb[4], cmd->cdb[5], 1296 cmd->cdb[6], cmd->cdb[7],cmd->cdb[8], cmd->cdb[9]); 1297 1298 switch (cmd->status) { 1299 case ARC_MSG_STATUS_SELTIMEOUT: 1300 case ARC_MSG_STATUS_ABORTED: 1301 case ARC_MSG_STATUS_INIT_FAIL: 1302 xs->status = SCSI_OK; 1303 xs->error = XS_SELTIMEOUT; 1304 break; 1305 1306 case SCSI_CHECK: 1307 bzero(&xs->sense, sizeof(xs->sense)); 1308 bcopy(cmd->sense_data, &xs->sense, 1309 min(ARC_MSG_SENSELEN, sizeof(xs->sense))); 1310 xs->sense.error_code = SSD_ERRCODE_VALID | 0x70; 1311 xs->status = SCSI_CHECK; 1312 xs->error = XS_SENSE; 1313 xs->resid = 0; 1314 break; 1315 1316 default: 1317 /* unknown device status */ 1318 xs->error = XS_BUSY; /* try again later? */ 1319 xs->status = SCSI_BUSY; 1320 break; 1321 } 1322 } else { 1323 xs->status = SCSI_OK; 1324 xs->error = XS_NOERROR; 1325 xs->resid = 0; 1326 } 1327 1328 scsi_done(xs); 1329 } 1330 1331 int 1332 arc_complete(struct arc_softc *sc, struct arc_ccb *nccb, int timeout) 1333 { 1334 struct arc_ccb *ccb = NULL; 1335 char *kva = ARC_DMA_KVA(sc->sc_requests); 1336 struct arc_io_cmd *cmd; 1337 u_int32_t reg, error, write_ptr; 1338 u_int16_t doneq_index; 1339 struct arc_HBD_Msgu *phbdmu; 1340 int ret = 0; 1341 1342 arc_disable_all_intr(sc); 1343 do { 1344 switch(sc->sc_adp_type) { 1345 case ARC_HBA_TYPE_A: 1346 reg = arc_read(sc, ARC_RA_REPLY_QUEUE); 1347 error = (reg & ARC_RA_REPLY_QUEUE_ERR)? 1:0; 1348 break; 1349 case ARC_HBA_TYPE_C: 1350 reg = arc_read(sc, ARC_RC_OUTB_REPLYQ_LOW); 1351 error = (reg & ARC_RC_REPLY_QUEUE_ERR); 1352 break; 1353 case ARC_HBA_TYPE_D: 1354 phbdmu = sc->pmu; 1355 write_ptr = phbdmu->done_qbuffer[0].addressLow; 1356 doneq_index = phbdmu->doneq_index; 1357 if((write_ptr & 0xff) == (doneq_index & 0xff)) { 1358 Loop0: 1359 reg = 0xffffffff; 1360 } 1361 else { 1362 doneq_index = arcmsr_get_doneq_index(phbdmu); 1363 reg = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 1364 if (reg == 0) 1365 goto Loop0; 1366 arc_write(sc, ARC_RD_OUTB_READ_PTR, doneq_index); 1367 } 1368 error = (reg & ARC_RD_REPLY_QUEUE_ERR); 1369 break; 1370 } 1371 if (reg == 0xffffffff) { 1372 if (timeout-- == 0) { 1373 return (1); 1374 } 1375 delay(1000); 1376 continue; 1377 } 1378 1379 switch(sc->sc_adp_type) { 1380 case ARC_HBA_TYPE_A: 1381 cmd = (struct arc_io_cmd *)(kva + 1382 ((reg << ARC_RA_REPLY_QUEUE_ADDR_SHIFT) - 1383 ARC_DMA_DVA(sc->sc_requests))); 1384 break; 1385 case ARC_HBA_TYPE_C: 1386 case ARC_HBA_TYPE_D: 1387 cmd = (struct arc_io_cmd *)(kva + ((reg & 0xFFFFFFE0) - 1388 ARC_DMA_DVA(sc->sc_requests))); 1389 break; 1390 } 1391 ccb = cmd->ccb; 1392 1393 bus_dmamap_sync(sc->sc_dmat, ARC_DMA_MAP(sc->sc_requests), 1394 ccb->cmd_dma_offset, ARC_MAX_IOCMDLEN, 1395 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1396 1397 arc_scsi_cmd_done(sc, ccb, error); 1398 1399 } while (nccb != ccb); 1400 arc_enable_all_intr(sc); 1401 1402 return (ret); 1403 } 1404 1405 void 1406 arc_enable_all_intr(struct arc_softc *sc) 1407 { 1408 u_int32_t int_mask; 1409 1410 switch(sc->sc_adp_type) { 1411 case ARC_HBA_TYPE_A: 1412 int_mask = arc_read(sc, ARC_RA_INTRMASK); 1413 int_mask &= ~(ARC_RA_INTRMASK_POSTQUEUE | 1414 ARC_RA_INTRMASK_DOORBELL | ARC_RA_INTRMASK_MSG0); 1415 arc_write(sc, ARC_RA_INTRMASK, int_mask); 1416 break; 1417 case ARC_HBA_TYPE_C: 1418 int_mask = arc_read(sc, ARC_RC_INTR_MASK); 1419 int_mask &= ~(ARC_RC_INTR_MASK_POSTQUEUE | 1420 ARC_RC_INTR_MASK_DOORBELL | ARC_RC_INTR_MASK_UTILITY_A); 1421 arc_write(sc, ARC_RC_INTR_MASK, int_mask); 1422 break; 1423 case ARC_HBA_TYPE_D: 1424 int_mask = arc_read(sc, ARC_RD_INTR_ENABLE); 1425 int_mask |= ARC_RD_INTR_ENABLE_ALL; 1426 arc_write(sc, ARC_RD_INTR_ENABLE, int_mask); 1427 break; 1428 } 1429 } 1430 1431 void 1432 arc_disable_all_intr(struct arc_softc *sc) 1433 { 1434 u_int32_t int_mask; 1435 1436 switch(sc->sc_adp_type) { 1437 case ARC_HBA_TYPE_A: 1438 int_mask = arc_read(sc, ARC_RA_INTRMASK); 1439 int_mask |= ARC_RA_INTR_MASK_ALL; 1440 arc_write(sc, ARC_RA_INTRMASK, int_mask); 1441 break; 1442 case ARC_HBA_TYPE_C: 1443 int_mask = arc_read(sc, ARC_RC_INTR_MASK); 1444 int_mask |= ARC_RC_INTR_MASK_ALL; 1445 arc_write(sc, ARC_RC_INTR_MASK, int_mask); 1446 break; 1447 case ARC_HBA_TYPE_D: 1448 int_mask = arc_read(sc, ARC_RD_INTR_ENABLE); 1449 int_mask &= ~ARC_RD_INTR_ENABLE_ALL; 1450 arc_write(sc, ARC_RD_INTR_ENABLE, ARC_RD_INTR_DISABLE_ALL); 1451 break; 1452 } 1453 } 1454 1455 int 1456 arc_map_pci_resources(struct arc_softc *sc, struct pci_attach_args *pa) 1457 { 1458 pcireg_t memtype; 1459 pci_intr_handle_t ih; 1460 1461 sc->sc_pc = pa->pa_pc; 1462 sc->sc_tag = pa->pa_tag; 1463 sc->sc_dmat = pa->pa_dmat; 1464 1465 switch(sc->sc_adp_type) { 1466 case ARC_HBA_TYPE_A: 1467 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, ARC_RA_PCI_BAR); 1468 if (pci_mapreg_map(pa, ARC_RA_PCI_BAR, memtype, 0, &sc->sc_iot, 1469 &sc->sc_ioh, NULL, &sc->sc_ios, 0) != 0) { 1470 printf(": unable to map ARC_HBA_TYPE_A system" 1471 " interface register\n"); 1472 return(1); 1473 } 1474 break; 1475 case ARC_HBA_TYPE_C: 1476 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, ARC_RC_PCI_BAR); 1477 if (pci_mapreg_map(pa, ARC_RC_PCI_BAR, memtype, 0, &sc->sc_iot, 1478 &sc->sc_ioh, NULL, &sc->sc_ios, 0) != 0) { 1479 printf(": unable to map ARC_HBA_TYPE_C system" 1480 " interface register\n"); 1481 return(1); 1482 } 1483 break; 1484 case ARC_HBA_TYPE_D: 1485 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, ARC_RD_PCI_BAR); 1486 if (pci_mapreg_map(pa, ARC_RD_PCI_BAR, memtype, 0, &sc->sc_iot, 1487 &sc->sc_ioh, NULL, &sc->sc_ios, 0) != 0) { 1488 printf(": unable to map ARC_HBA_TYPE_D system" 1489 " interface register\n"); 1490 return(1); 1491 } 1492 break; 1493 } 1494 1495 arc_disable_all_intr(sc); 1496 1497 if (pci_intr_map(pa, &ih) != 0) { 1498 printf(": unable to map interrupt\n"); 1499 goto unmap; 1500 } 1501 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 1502 arc_intr, sc, DEVNAME(sc)); 1503 if (sc->sc_ih == NULL) { 1504 printf(": unable to map interrupt\n"); 1505 goto unmap; 1506 } 1507 printf(": %s\n", pci_intr_string(pa->pa_pc, ih)); 1508 1509 return (0); 1510 1511 unmap: 1512 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 1513 sc->sc_ios = 0; 1514 return (1); 1515 } 1516 1517 void 1518 arc_unmap_pci_resources(struct arc_softc *sc) 1519 { 1520 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1521 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 1522 sc->sc_ios = 0; 1523 } 1524 1525 int 1526 arc_chipA_firmware(struct arc_softc *sc) 1527 { 1528 struct arc_msg_firmware_info fwinfo; 1529 char string[81]; /* sizeof(vendor)*2+1 */ 1530 u_int32_t ob_doorbell; 1531 1532 if (arc_wait_eq(sc, ARC_RA_OUTB_ADDR1, ARC_RA_OUTB_ADDR1_FIRMWARE_OK, 1533 ARC_RA_OUTB_ADDR1_FIRMWARE_OK) != 0) { 1534 printf("%s: timeout waiting for firmware ok\n", DEVNAME(sc)); 1535 return (1); 1536 } 1537 1538 if (arc_msg0(sc, ARC_RA_INB_MSG0_GET_CONFIG) != 0) { 1539 printf("%s: timeout waiting for get config\n", DEVNAME(sc)); 1540 return (1); 1541 } 1542 1543 arc_read_region(sc, ARC_RA_MSGBUF, &fwinfo, sizeof(fwinfo)); 1544 1545 DNPRINTF(ARC_D_INIT, "%s: signature: 0x%08x\n", DEVNAME(sc), 1546 letoh32(fwinfo.signature)); 1547 1548 if (letoh32(fwinfo.signature) != ARC_FWINFO_SIGNATURE_GET_CONFIG) { 1549 printf("%s: invalid firmware info from iop\n", DEVNAME(sc)); 1550 return (1); 1551 } 1552 1553 DNPRINTF(ARC_D_INIT, "%s: request_len: %d\n", DEVNAME(sc), 1554 letoh32(fwinfo.request_len)); 1555 DNPRINTF(ARC_D_INIT, "%s: queue_len: %d\n", DEVNAME(sc), 1556 letoh32(fwinfo.queue_len)); 1557 DNPRINTF(ARC_D_INIT, "%s: sdram_size: %d\n", DEVNAME(sc), 1558 letoh32(fwinfo.sdram_size)); 1559 DNPRINTF(ARC_D_INIT, "%s: sata_ports: %d\n", DEVNAME(sc), 1560 letoh32(fwinfo.sata_ports), letoh32(fwinfo.sata_ports)); 1561 1562 scsi_strvis(string, fwinfo.vendor, sizeof(fwinfo.vendor)); 1563 DNPRINTF(ARC_D_INIT, "%s: vendor: \"%s\"\n", DEVNAME(sc), string); 1564 scsi_strvis(string, fwinfo.model, sizeof(fwinfo.model)); 1565 DNPRINTF(ARC_D_INIT, "%s: model: \"%s\"\n", DEVNAME(sc), string); 1566 1567 scsi_strvis(string, fwinfo.fw_version, sizeof(fwinfo.fw_version)); 1568 DNPRINTF(ARC_D_INIT, "%s: firmware: \"%s\"\n", DEVNAME(sc), string); 1569 1570 if (letoh32(fwinfo.request_len) != ARC_MAX_IOCMDLEN) { 1571 printf("%s: unexpected request frame size (%d != %d)\n", 1572 DEVNAME(sc), letoh32(fwinfo.request_len), ARC_MAX_IOCMDLEN); 1573 return (1); 1574 } 1575 1576 sc->sc_req_count = letoh32(fwinfo.queue_len); 1577 1578 if (arc_msg0(sc, ARC_RA_INB_MSG0_START_BGRB) != 0) { 1579 printf("%s: timeout waiting to start bg rebuild\n", 1580 DEVNAME(sc)); 1581 return (1); 1582 } 1583 1584 /* clear doorbell buffer */ 1585 ob_doorbell = arc_read(sc, ARC_RA_OUTB_DOORBELL); 1586 arc_write(sc, ARC_RA_OUTB_DOORBELL, ob_doorbell); 1587 arc_write(sc, ARC_RA_INB_DOORBELL, ARC_RA_INB_DOORBELL_READ_OK); 1588 1589 printf("%s: %d ports, %dMB SDRAM, firmware %s\n", 1590 DEVNAME(sc), letoh32(fwinfo.sata_ports), 1591 letoh32(fwinfo.sdram_size), string); 1592 1593 return (0); 1594 } 1595 1596 int 1597 arc_chipB_firmware(struct arc_softc *sc) 1598 { 1599 if (arc_wait_eq(sc, ARC_RB_IOP2DRV_DOORBELL, 1600 ARC_RA_OUTB_ADDR1_FIRMWARE_OK, 1601 ARC_RA_OUTB_ADDR1_FIRMWARE_OK) != 0) { 1602 printf("%s: timeout waiting for firmware ok\n", DEVNAME(sc)); 1603 return (1); 1604 } 1605 1606 return (1); 1607 } 1608 1609 int 1610 arc_chipC_firmware(struct arc_softc *sc) 1611 { 1612 struct arc_msg_firmware_info fwinfo; 1613 char string[81]; /* sizeof(vendor)*2+1 */ 1614 u_int32_t ob_doorbell; 1615 1616 if (arc_wait_eq(sc, ARC_RC_OUTB_MSGADDR1, ARC_RC_OUTB_MSG_FIRMWARE_OK, 1617 ARC_RC_OUTB_MSG_FIRMWARE_OK) != 0) { 1618 printf("%s: timeout waiting for firmware ok\n", DEVNAME(sc)); 1619 return (1); 1620 } 1621 1622 if (arc_msg0(sc, ARC_RC_INB_MSG0_GET_CONFIG) != 0) { 1623 printf("%s: timeout waiting for get config\n", DEVNAME(sc)); 1624 return (1); 1625 } 1626 1627 arc_read_region(sc, ARC_RC_MSG_RWBUF, &fwinfo, sizeof(fwinfo)); 1628 1629 DNPRINTF(ARC_D_INIT, "%s: signature: 0x%08x\n", DEVNAME(sc), 1630 letoh32(fwinfo.signature)); 1631 1632 if (letoh32(fwinfo.signature) != ARC_FWINFO_SIGNATURE_GET_CONFIG) { 1633 printf("%s: invalid firmware info from iop\n", DEVNAME(sc)); 1634 return (1); 1635 } 1636 1637 DNPRINTF(ARC_D_INIT, "%s: request_len: %d\n", DEVNAME(sc), 1638 letoh32(fwinfo.request_len)); 1639 DNPRINTF(ARC_D_INIT, "%s: queue_len: %d\n", DEVNAME(sc), 1640 letoh32(fwinfo.queue_len)); 1641 DNPRINTF(ARC_D_INIT, "%s: sdram_size: %d\n", DEVNAME(sc), 1642 letoh32(fwinfo.sdram_size)); 1643 DNPRINTF(ARC_D_INIT, "%s: sata_ports: %d\n", DEVNAME(sc), 1644 letoh32(fwinfo.sata_ports), letoh32(fwinfo.sata_ports)); 1645 1646 scsi_strvis(string, fwinfo.vendor, sizeof(fwinfo.vendor)); 1647 DNPRINTF(ARC_D_INIT, "%s: vendor: \"%s\"\n", DEVNAME(sc), string); 1648 scsi_strvis(string, fwinfo.model, sizeof(fwinfo.model)); 1649 DNPRINTF(ARC_D_INIT, "%s: model: \"%s\"\n", DEVNAME(sc), string); 1650 1651 scsi_strvis(string, fwinfo.fw_version, sizeof(fwinfo.fw_version)); 1652 DNPRINTF(ARC_D_INIT, "%s: firmware: \"%s\"\n", DEVNAME(sc), string); 1653 1654 if (letoh32(fwinfo.request_len) != ARC_MAX_IOCMDLEN) { 1655 printf("%s: unexpected request frame size (%d != %d)\n", 1656 DEVNAME(sc), letoh32(fwinfo.request_len), ARC_MAX_IOCMDLEN); 1657 return (1); 1658 } 1659 1660 sc->sc_req_count = letoh32(fwinfo.queue_len); 1661 1662 if (arc_msg0(sc, ARC_RC_INB_MSG0_START_BGRB) != 0) { 1663 printf("%s: timeout waiting to start bg rebuild\n", 1664 DEVNAME(sc)); 1665 return (1); 1666 } 1667 1668 /* clear doorbell buffer */ 1669 ob_doorbell = arc_read(sc, ARC_RC_OUTB_DOORBELL); 1670 arc_write(sc, ARC_RC_OUTB_DOORBELL_CLR, ob_doorbell); 1671 arc_write(sc, ARC_RC_INB_DOORBELL, ARC_RC_D2I_DATA_READ_OK); 1672 1673 printf("%s: %d ports, %dMB SDRAM, firmware %s\n", 1674 DEVNAME(sc), letoh32(fwinfo.sata_ports), 1675 letoh32(fwinfo.sdram_size), string); 1676 1677 return (0); 1678 } 1679 1680 int 1681 arc_chipD_firmware(struct arc_softc *sc) 1682 { 1683 struct arc_msg_firmware_info fwinfo; 1684 char string[81]; /* sizeof(vendor)*2+1 */ 1685 u_int32_t ob_doorbell; 1686 1687 if (arc_wait_eq(sc, ARC_RD_OUTB_MSGADDR1, ARC_RD_OUTB_MSG_FIRMWARE_OK, 1688 ARC_RD_OUTB_MSG_FIRMWARE_OK) != 0) { 1689 printf("%s: timeout waiting for firmware ok\n", DEVNAME(sc)); 1690 return (1); 1691 } 1692 1693 if ((arc_read(sc, ARC_RD_OUTB_DOORBELL) & ARC_RD_I2D_MESSAGE_CMD_DONE)) 1694 arc_write(sc, ARC_RD_OUTB_DOORBELL, ARC_RD_I2D_MESSAGE_CMD_DONE_CLEAR); 1695 1696 if (arc_msg0(sc, ARC_RD_INB_MSG0_GET_CONFIG) != 0) { 1697 printf("%s: timeout waiting for get config\n", DEVNAME(sc)); 1698 return (1); 1699 } 1700 1701 arc_read_region(sc, ARC_RD_MSG_RWBUF, &fwinfo, sizeof(fwinfo)); 1702 1703 DNPRINTF(ARC_D_INIT, "%s: signature: 0x%08x\n", DEVNAME(sc), 1704 letoh32(fwinfo.signature)); 1705 1706 if (letoh32(fwinfo.signature) != ARC_FWINFO_SIGNATURE_GET_CONFIG) { 1707 printf("%s: invalid firmware info from iop\n", DEVNAME(sc)); 1708 return (1); 1709 } 1710 1711 DNPRINTF(ARC_D_INIT, "%s: request_len: %d\n", DEVNAME(sc), 1712 letoh32(fwinfo.request_len)); 1713 DNPRINTF(ARC_D_INIT, "%s: queue_len: %d\n", DEVNAME(sc), 1714 letoh32(fwinfo.queue_len)); 1715 DNPRINTF(ARC_D_INIT, "%s: sdram_size: %d\n", DEVNAME(sc), 1716 letoh32(fwinfo.sdram_size)); 1717 DNPRINTF(ARC_D_INIT, "%s: sata_ports: %d\n", DEVNAME(sc), 1718 letoh32(fwinfo.sata_ports), letoh32(fwinfo.sata_ports)); 1719 1720 scsi_strvis(string, fwinfo.vendor, sizeof(fwinfo.vendor)); 1721 DNPRINTF(ARC_D_INIT, "%s: vendor: \"%s\"\n", DEVNAME(sc), string); 1722 scsi_strvis(string, fwinfo.model, sizeof(fwinfo.model)); 1723 DNPRINTF(ARC_D_INIT, "%s: model: \"%s\"\n", DEVNAME(sc), string); 1724 1725 scsi_strvis(string, fwinfo.fw_version, sizeof(fwinfo.fw_version)); 1726 DNPRINTF(ARC_D_INIT, "%s: firmware: \"%s\"\n", DEVNAME(sc), string); 1727 1728 if (letoh32(fwinfo.request_len) != ARC_MAX_IOCMDLEN) { 1729 printf("%s: unexpected request frame size (%d != %d)\n", 1730 DEVNAME(sc), letoh32(fwinfo.request_len), ARC_MAX_IOCMDLEN); 1731 return (1); 1732 } 1733 1734 sc->sc_req_count = letoh32(fwinfo.queue_len) - 1; 1735 1736 if (arc_msg0(sc, ARC_RD_INB_MSG0_START_BGRB) != 0) { 1737 printf("%s: timeout waiting to start bg rebuild\n", 1738 DEVNAME(sc)); 1739 return (1); 1740 } 1741 1742 /* clear doorbell buffer */ 1743 ob_doorbell = arc_read(sc, ARC_RD_OUTB_DOORBELL); 1744 arc_write(sc, ARC_RD_OUTB_DOORBELL_CLR, ob_doorbell); 1745 arc_write(sc, ARC_RD_INB_DOORBELL, ARC_RD_D2I_DATA_READ_OK); 1746 1747 printf("%s: %d ports, %dMB SDRAM, firmware %s\n", 1748 DEVNAME(sc), letoh32(fwinfo.sata_ports), 1749 letoh32(fwinfo.sdram_size), string); 1750 1751 return (0); 1752 } 1753 1754 void 1755 arc_stop_bgrb_proc(struct arc_softc *sc) 1756 { 1757 switch(sc->sc_adp_type) { 1758 case ARC_HBA_TYPE_A: 1759 if (arc_msg0(sc, ARC_RA_INB_MSG0_STOP_BGRB) != 0) 1760 printf("%s: timeout waiting to stop bg rebuild\n", 1761 DEVNAME(sc)); 1762 break; 1763 case ARC_HBA_TYPE_C: 1764 if (arc_msg0(sc, ARC_RC_INB_MSG0_STOP_BGRB) != 0) 1765 printf("%s: timeout waiting to stop bg rebuild\n", 1766 DEVNAME(sc)); 1767 break; 1768 case ARC_HBA_TYPE_D: 1769 if (arc_msg0(sc, ARC_RD_INB_MSG0_STOP_BGRB) != 0) 1770 printf("%s: timeout waiting to stop bg rebuild\n", 1771 DEVNAME(sc)); 1772 break; 1773 } 1774 } 1775 1776 void 1777 arc_flush_cache(struct arc_softc *sc) 1778 { 1779 switch(sc->sc_adp_type) { 1780 case ARC_HBA_TYPE_A: 1781 if (arc_msg0(sc, ARC_RA_INB_MSG0_FLUSH_CACHE) != 0) 1782 printf("%s: timeout waiting to flush cache\n", 1783 DEVNAME(sc)); 1784 break; 1785 case ARC_HBA_TYPE_C: 1786 if (arc_msg0(sc, ARC_RC_INB_MSG0_FLUSH_CACHE) != 0) 1787 printf("%s: timeout waiting to flush cache\n", 1788 DEVNAME(sc)); 1789 break; 1790 case ARC_HBA_TYPE_D: 1791 if (arc_msg0(sc, ARC_RD_INB_MSG0_FLUSH_CACHE) != 0) 1792 printf("%s: timeout waiting to flush cache\n", 1793 DEVNAME(sc)); 1794 break; 1795 } 1796 } 1797 1798 void 1799 arc_iop_set_conf(struct arc_softc *sc) 1800 { 1801 u_int32_t ccb_phys_hi; 1802 struct arc_HBD_Msgu *phbdmu; 1803 1804 ccb_phys_hi = sc->sc_ccb_phys_hi; 1805 switch (sc->sc_adp_type) { 1806 case ARC_HBA_TYPE_A: 1807 arc_write(sc, ARC_RA_MSGBUF, ARC_FWINFO_SIGNATURE_SET_CONFIG); 1808 arc_write(sc, ARC_RA_MSGBUF+1, ccb_phys_hi); 1809 arc_msg0(sc, ARC_RA_INB_MSG0_SET_CONFIG); 1810 break; 1811 case ARC_HBA_TYPE_C: 1812 arc_write(sc, ARC_RC_MSG_RWBUF, ARC_FWINFO_SIGNATURE_SET_CONFIG); 1813 arc_write(sc, ARC_RC_MSG_RWBUF+1, ccb_phys_hi); 1814 arc_msg0(sc, ARC_RC_INB_MSG0_SET_CONFIG); 1815 break; 1816 case ARC_HBA_TYPE_D: 1817 phbdmu = sc->pmu; 1818 phbdmu->postq_index = 0; 1819 phbdmu->doneq_index = 0x40FF; 1820 arc_write(sc, ARC_RD_MSG_RWBUF, ARC_FWINFO_SIGNATURE_SET_CONFIG); 1821 arc_write(sc, ARC_RD_MSG_RWBUF+4, ccb_phys_hi); 1822 arc_write(sc, ARC_RD_MSG_RWBUF+8, sc->postQ_buffer); 1823 arc_write(sc, ARC_RD_MSG_RWBUF+12, sc->doneQ_buffer); 1824 arc_write(sc, ARC_RD_MSG_RWBUF+16, 0x100); 1825 arc_msg0(sc, ARC_RD_INB_MSG0_SET_CONFIG); 1826 break; 1827 } 1828 } 1829 1830 #if NBIO > 0 1831 int 1832 arc_bioctl(struct device *self, u_long cmd, caddr_t addr) 1833 { 1834 struct arc_softc *sc = (struct arc_softc *)self; 1835 int error = 0; 1836 1837 DPRINTF("%s: arc_bioctl\n", DEVNAME(sc)); 1838 switch (cmd) { 1839 case BIOCINQ: 1840 error = arc_bio_inq(sc, (struct bioc_inq *)addr); 1841 break; 1842 1843 case BIOCVOL: 1844 error = arc_bio_vol(sc, (struct bioc_vol *)addr); 1845 break; 1846 1847 case BIOCDISK: 1848 error = arc_bio_disk(sc, (struct bioc_disk *)addr); 1849 break; 1850 1851 case BIOCALARM: 1852 error = arc_bio_alarm(sc, (struct bioc_alarm *)addr); 1853 break; 1854 1855 case BIOCBLINK: 1856 error = arc_bio_blink(sc, (struct bioc_blink *)addr); 1857 break; 1858 1859 default: 1860 error = ENOTTY; 1861 break; 1862 } 1863 1864 return (error); 1865 } 1866 1867 int 1868 arc_bio_alarm(struct arc_softc *sc, struct bioc_alarm *ba) 1869 { 1870 u_int8_t request[2]; 1871 u_int8_t reply[1]; 1872 size_t len; 1873 int error = 0; 1874 1875 DPRINTF("%s: arc_bio_alarm\n", DEVNAME(sc)); 1876 switch (ba->ba_opcode) { 1877 case BIOC_SAENABLE: 1878 case BIOC_SADISABLE: 1879 request[0] = ARC_FW_SET_ALARM; 1880 request[1] = (ba->ba_opcode == BIOC_SAENABLE) ? 1881 ARC_FW_SET_ALARM_ENABLE : ARC_FW_SET_ALARM_DISABLE; 1882 len = sizeof(request); 1883 1884 break; 1885 1886 case BIOC_SASILENCE: 1887 request[0] = ARC_FW_MUTE_ALARM; 1888 len = 1; 1889 1890 break; 1891 1892 case BIOC_GASTATUS: 1893 /* system info is too big/ugly to deal with here */ 1894 return (arc_bio_alarm_state(sc, ba)); 1895 1896 default: 1897 return (EOPNOTSUPP); 1898 } 1899 1900 arc_lock(sc); 1901 error = arc_msgbuf(sc, request, len, reply, sizeof(reply), 0); 1902 arc_unlock(sc); 1903 1904 if (error != 0) 1905 return (error); 1906 1907 switch (reply[0]) { 1908 case ARC_FW_CMD_OK: 1909 return (0); 1910 case ARC_FW_CMD_PASS_REQD: 1911 return (EPERM); 1912 default: 1913 return (EIO); 1914 } 1915 } 1916 1917 int 1918 arc_bio_alarm_state(struct arc_softc *sc, struct bioc_alarm *ba) 1919 { 1920 u_int8_t request = ARC_FW_SYSINFO; 1921 struct arc_fw_sysinfo *sysinfo; 1922 int error = 0; 1923 1924 sysinfo = malloc(sizeof(struct arc_fw_sysinfo), M_TEMP, M_WAITOK); 1925 1926 request = ARC_FW_SYSINFO; 1927 1928 arc_lock(sc); 1929 error = arc_msgbuf(sc, &request, sizeof(request), 1930 sysinfo, sizeof(struct arc_fw_sysinfo), 0); 1931 arc_unlock(sc); 1932 1933 if (error != 0) 1934 goto out; 1935 1936 ba->ba_status = sysinfo->alarm; 1937 1938 out: 1939 free(sysinfo, M_TEMP, sizeof *sysinfo); 1940 return (error); 1941 } 1942 1943 1944 int 1945 arc_bio_inq(struct arc_softc *sc, struct bioc_inq *bi) 1946 { 1947 u_int8_t request[2]; 1948 struct arc_fw_sysinfo *sysinfo; 1949 struct arc_fw_volinfo *volinfo; 1950 int maxvols, nvols = 0, i; 1951 int error = 0; 1952 char string[20]; 1953 1954 DPRINTF("%s: arc_bio_inq\n", DEVNAME(sc)); 1955 sysinfo = malloc(sizeof(struct arc_fw_sysinfo), M_TEMP, M_WAITOK); 1956 volinfo = malloc(sizeof(struct arc_fw_volinfo), M_TEMP, M_WAITOK); 1957 1958 arc_lock(sc); 1959 1960 request[0] = ARC_FW_SYSINFO; 1961 error = arc_msgbuf(sc, request, 1, sysinfo, 1962 sizeof(struct arc_fw_sysinfo), 0); 1963 if (error != 0) { 1964 DPRINTF("%s: arc_bio_inq get sysinfo failed!\n", DEVNAME(sc)); 1965 goto out; 1966 } 1967 1968 maxvols = sysinfo->max_volume_set; 1969 1970 request[0] = ARC_FW_VOLINFO; 1971 for (i = 0; i < maxvols; i++) { 1972 request[1] = i; 1973 error = arc_msgbuf(sc, request, sizeof(request), volinfo, 1974 sizeof(struct arc_fw_volinfo), 0); 1975 if (error != 0) { 1976 DPRINTF("%s: arc_bio_inq get volinfo failed!\n", DEVNAME(sc)); 1977 goto out; 1978 } 1979 1980 /* 1981 * I can't find an easy way to see if the volume exists or not 1982 * except to say that if it has no capacity then it isn't there. 1983 * Ignore passthru volumes, bioc_vol doesn't understand them. 1984 */ 1985 if ((volinfo->capacity != 0 || volinfo->capacity2 != 0) && 1986 volinfo->raid_level != ARC_FW_VOL_RAIDLEVEL_PASSTHRU) { 1987 nvols++; 1988 scsi_strvis(string, volinfo->set_name, 16); 1989 DPRINTF("%s: volume set: \"%s\"\n", DEVNAME(sc), string); 1990 } 1991 } 1992 1993 strlcpy(bi->bi_dev, DEVNAME(sc), sizeof(bi->bi_dev)); 1994 bi->bi_novol = nvols; 1995 DPRINTF("%s: volume set number = %d\n", DEVNAME(sc), nvols); 1996 out: 1997 arc_unlock(sc); 1998 free(volinfo, M_TEMP, sizeof *volinfo); 1999 free(sysinfo, M_TEMP, sizeof *sysinfo); 2000 return (error); 2001 } 2002 2003 int 2004 arc_bio_blink(struct arc_softc *sc, struct bioc_blink *blink) 2005 { 2006 u_int8_t request[6]; 2007 u_int32_t mask; 2008 int error = 0; 2009 2010 DPRINTF("%s: arc_bio_blink\n", DEVNAME(sc)); 2011 request[0] = ARC_FW_BLINK; 2012 request[1] = ARC_FW_BLINK_ENABLE; 2013 2014 switch (blink->bb_status) { 2015 case BIOC_SBUNBLINK: 2016 sc->sc_ledmask &= ~(1 << blink->bb_target); 2017 break; 2018 case BIOC_SBBLINK: 2019 sc->sc_ledmask |= (1 << blink->bb_target); 2020 break; 2021 default: 2022 return (EINVAL); 2023 } 2024 2025 mask = htole32(sc->sc_ledmask); 2026 bcopy(&mask, &request[2], 4); 2027 2028 arc_lock(sc); 2029 error = arc_msgbuf(sc, request, sizeof(request), NULL, 0, 0); 2030 arc_unlock(sc); 2031 if (error) 2032 return (EIO); 2033 2034 return (0); 2035 } 2036 2037 int 2038 arc_bio_getvol(struct arc_softc *sc, int vol, struct arc_fw_volinfo *volinfo) 2039 { 2040 u_int8_t request[2]; 2041 struct arc_fw_sysinfo *sysinfo; 2042 int error = 0; 2043 int maxvols, nvols = 0, i; 2044 2045 DPRINTF("%s: arc_bio_getvol\n", DEVNAME(sc)); 2046 sysinfo = malloc(sizeof(struct arc_fw_sysinfo), M_TEMP, M_WAITOK); 2047 2048 request[0] = ARC_FW_SYSINFO; 2049 error = arc_msgbuf(sc, request, 1, sysinfo, 2050 sizeof(struct arc_fw_sysinfo), 0); 2051 if (error != 0) 2052 goto out; 2053 2054 maxvols = sysinfo->max_volume_set; 2055 2056 request[0] = ARC_FW_VOLINFO; 2057 for (i = 0; i < maxvols; i++) { 2058 request[1] = i; 2059 error = arc_msgbuf(sc, request, sizeof(request), volinfo, 2060 sizeof(struct arc_fw_volinfo), 0); 2061 if (error != 0) 2062 goto out; 2063 2064 if ((volinfo->capacity == 0 && volinfo->capacity2 == 0) || 2065 volinfo->raid_level == ARC_FW_VOL_RAIDLEVEL_PASSTHRU) 2066 continue; 2067 2068 if (nvols == vol) 2069 break; 2070 2071 nvols++; 2072 } 2073 2074 if (nvols != vol || 2075 (volinfo->capacity == 0 && volinfo->capacity2 == 0) || 2076 volinfo->raid_level == ARC_FW_VOL_RAIDLEVEL_PASSTHRU) { 2077 error = ENODEV; 2078 goto out; 2079 } 2080 2081 out: 2082 free(sysinfo, M_TEMP, sizeof *sysinfo); 2083 return (error); 2084 } 2085 2086 int 2087 arc_bio_vol(struct arc_softc *sc, struct bioc_vol *bv) 2088 { 2089 struct arc_fw_volinfo *volinfo; 2090 struct scsi_link *sc_link; 2091 struct device *dev; 2092 u_int64_t blocks; 2093 u_int32_t status; 2094 int error = 0; 2095 2096 DPRINTF("%s: arc_bio_vol\n", DEVNAME(sc)); 2097 volinfo = malloc(sizeof(struct arc_fw_volinfo), M_TEMP, M_WAITOK); 2098 2099 arc_lock(sc); 2100 error = arc_bio_getvol(sc, bv->bv_volid, volinfo); 2101 arc_unlock(sc); 2102 2103 if (error != 0) 2104 goto out; 2105 2106 bv->bv_percent = -1; 2107 bv->bv_seconds = 0; 2108 2109 status = letoh32(volinfo->volume_status); 2110 if (status == 0x0) { 2111 if (letoh32(volinfo->fail_mask) == 0x0) 2112 bv->bv_status = BIOC_SVONLINE; 2113 else 2114 bv->bv_status = BIOC_SVDEGRADED; 2115 } else if (status & ARC_FW_VOL_STATUS_NEED_REGEN) 2116 bv->bv_status = BIOC_SVDEGRADED; 2117 else if (status & ARC_FW_VOL_STATUS_FAILED) 2118 bv->bv_status = BIOC_SVOFFLINE; 2119 else if (status & ARC_FW_VOL_STATUS_INITTING) { 2120 bv->bv_status = BIOC_SVBUILDING; 2121 bv->bv_percent = letoh32(volinfo->progress) / 10; 2122 } else if (status & ARC_FW_VOL_STATUS_REBUILDING) { 2123 bv->bv_status = BIOC_SVREBUILD; 2124 bv->bv_percent = letoh32(volinfo->progress) / 10; 2125 } 2126 2127 blocks = (u_int64_t)letoh32(volinfo->capacity2) << 32; 2128 blocks += (u_int64_t)letoh32(volinfo->capacity); 2129 bv->bv_size = blocks * ARC_BLOCKSIZE; /* XXX */ 2130 2131 switch (volinfo->raid_level) { 2132 case ARC_FW_VOL_RAIDLEVEL_0: 2133 bv->bv_level = 0; 2134 break; 2135 case ARC_FW_VOL_RAIDLEVEL_1: 2136 bv->bv_level = 1; 2137 break; 2138 case ARC_FW_VOL_RAIDLEVEL_3: 2139 bv->bv_level = 3; 2140 break; 2141 case ARC_FW_VOL_RAIDLEVEL_5: 2142 bv->bv_level = 5; 2143 break; 2144 case ARC_FW_VOL_RAIDLEVEL_6: 2145 bv->bv_level = 6; 2146 break; 2147 case ARC_FW_VOL_RAIDLEVEL_PASSTHRU: 2148 default: 2149 bv->bv_level = -1; 2150 break; 2151 } 2152 2153 bv->bv_nodisk = volinfo->member_disks; 2154 sc_link = scsi_get_link(sc->sc_scsibus, volinfo->scsi_attr.target, 2155 volinfo->scsi_attr.lun); 2156 if (sc_link != NULL) { 2157 dev = sc_link->device_softc; 2158 strlcpy(bv->bv_dev, dev->dv_xname, sizeof(bv->bv_dev)); 2159 } 2160 2161 out: 2162 free(volinfo, M_TEMP, sizeof *volinfo); 2163 return (error); 2164 } 2165 2166 int 2167 arc_bio_disk(struct arc_softc *sc, struct bioc_disk *bd) 2168 { 2169 u_int8_t request[2]; 2170 struct arc_fw_volinfo *volinfo; 2171 struct arc_fw_raidinfo *raidinfo; 2172 struct arc_fw_diskinfo *diskinfo; 2173 int error = 0; 2174 u_int64_t blocks; 2175 char model[81]; 2176 char serial[41]; 2177 char rev[17]; 2178 2179 DPRINTF("%s: arc_bio_disk\n", DEVNAME(sc)); 2180 volinfo = malloc(sizeof(struct arc_fw_volinfo), M_TEMP, M_WAITOK); 2181 raidinfo = malloc(sizeof(struct arc_fw_raidinfo), M_TEMP, M_WAITOK); 2182 diskinfo = malloc(sizeof(struct arc_fw_diskinfo), M_TEMP, M_WAITOK); 2183 2184 arc_lock(sc); 2185 2186 error = arc_bio_getvol(sc, bd->bd_volid, volinfo); 2187 if (error != 0) 2188 goto out; 2189 2190 request[0] = ARC_FW_RAIDINFO; 2191 request[1] = volinfo->raid_set_number; 2192 error = arc_msgbuf(sc, request, sizeof(request), raidinfo, 2193 sizeof(struct arc_fw_raidinfo), 0); 2194 if (error != 0) 2195 goto out; 2196 2197 if (bd->bd_diskid > raidinfo->member_devices) { 2198 error = ENODEV; 2199 goto out; 2200 } 2201 2202 if (raidinfo->device_array[bd->bd_diskid] == 0xff) { 2203 /* 2204 * the disk doesn't exist anymore. bio is too dumb to be 2205 * able to display that, so put it on another bus 2206 */ 2207 bd->bd_channel = 1; 2208 bd->bd_target = 0; 2209 bd->bd_lun = 0; 2210 bd->bd_status = BIOC_SDOFFLINE; 2211 strlcpy(bd->bd_vendor, "disk missing", sizeof(bd->bd_vendor)); 2212 goto out; 2213 } 2214 2215 request[0] = ARC_FW_DISKINFO; 2216 request[1] = raidinfo->device_array[bd->bd_diskid]; 2217 error = arc_msgbuf(sc, request, sizeof(request), diskinfo, 2218 sizeof(struct arc_fw_diskinfo), 1); 2219 if (error != 0) 2220 goto out; 2221 2222 #if 0 2223 bd->bd_channel = diskinfo->scsi_attr.channel; 2224 bd->bd_target = diskinfo->scsi_attr.target; 2225 bd->bd_lun = diskinfo->scsi_attr.lun; 2226 #endif 2227 /* 2228 * the firwmare doesnt seem to fill scsi_attr in, so fake it with 2229 * the diskid. 2230 */ 2231 bd->bd_channel = 0; 2232 bd->bd_target = raidinfo->device_array[bd->bd_diskid]; 2233 bd->bd_lun = 0; 2234 2235 bd->bd_status = BIOC_SDONLINE; 2236 blocks = (u_int64_t)letoh32(diskinfo->capacity2) << 32; 2237 blocks += (u_int64_t)letoh32(diskinfo->capacity); 2238 bd->bd_size = blocks * ARC_BLOCKSIZE; /* XXX */ 2239 2240 scsi_strvis(model, diskinfo->model, sizeof(diskinfo->model)); 2241 scsi_strvis(serial, diskinfo->serial, sizeof(diskinfo->serial)); 2242 scsi_strvis(rev, diskinfo->firmware_rev, 2243 sizeof(diskinfo->firmware_rev)); 2244 2245 snprintf(bd->bd_vendor, sizeof(bd->bd_vendor), "%s %s", 2246 model, rev); 2247 strlcpy(bd->bd_serial, serial, sizeof(bd->bd_serial)); 2248 2249 out: 2250 arc_unlock(sc); 2251 free(diskinfo, M_TEMP, sizeof *diskinfo); 2252 free(raidinfo, M_TEMP, sizeof *raidinfo); 2253 free(volinfo, M_TEMP, sizeof *volinfo); 2254 return (error); 2255 } 2256 2257 u_int8_t 2258 arc_msg_cksum(void *cmd, u_int16_t len) 2259 { 2260 u_int8_t *buf = cmd; 2261 u_int8_t cksum; 2262 int i; 2263 2264 cksum = (u_int8_t)(len >> 8) + (u_int8_t)len; 2265 for (i = 0; i < len; i++) 2266 cksum += buf[i]; 2267 2268 return (cksum); 2269 } 2270 2271 int 2272 arc_msgbuf(struct arc_softc *sc, void *wptr, size_t wbuflen, void *rptr, 2273 size_t rbuflen, int sreadok) 2274 { 2275 u_int8_t rwbuf[ARC_RA_IOC_RWBUF_MAXLEN]; 2276 u_int8_t *wbuf, *rbuf, cksum; 2277 int wlen, wdone = 0, rlen, rdone = 0; 2278 u_int16_t rlenhdr = 0; 2279 struct arc_fw_bufhdr *bufhdr; 2280 u_int32_t reg, rwlen, write_ok, read_ok; 2281 int error = 0; 2282 #ifdef ARC_DEBUG 2283 int i; 2284 #endif 2285 2286 DPRINTF("%s: arc_msgbuf wbuflen: %d rbuflen: %d\n", 2287 DEVNAME(sc), wbuflen, rbuflen); 2288 2289 switch(sc->sc_adp_type) { 2290 case ARC_HBA_TYPE_A: 2291 reg = arc_read(sc, ARC_RA_OUTB_DOORBELL); 2292 break; 2293 case ARC_HBA_TYPE_C: 2294 reg = arc_read(sc, ARC_RC_OUTB_DOORBELL); 2295 break; 2296 case ARC_HBA_TYPE_D: 2297 reg = arc_read(sc, ARC_RD_OUTB_DOORBELL); 2298 break; 2299 } 2300 /* if (reg) 2301 return (EBUSY); */ 2302 2303 wlen = sizeof(struct arc_fw_bufhdr) + wbuflen + 1; /* 1 for cksum */ 2304 wbuf = malloc(wlen, M_TEMP, M_WAITOK); 2305 2306 rlen = sizeof(struct arc_fw_bufhdr) + rbuflen + 1; /* 1 for cksum */ 2307 rbuf = malloc(rlen, M_TEMP, M_WAITOK); 2308 2309 DNPRINTF(ARC_D_DB, "%s: arc_msgbuf wlen: %d rlen: %d\n", DEVNAME(sc), 2310 wlen, rlen); 2311 2312 bufhdr = (struct arc_fw_bufhdr *)wbuf; 2313 bufhdr->hdr = arc_fw_hdr; 2314 bufhdr->len = htole16(wbuflen); 2315 bcopy(wptr, wbuf + sizeof(struct arc_fw_bufhdr), wbuflen); 2316 wbuf[wlen - 1] = arc_msg_cksum(wptr, wbuflen); 2317 2318 /* reg = ARC_RA_OUTB_DOORBELL_READ_OK; */ 2319 read_ok = 1; 2320 do { 2321 if ((read_ok) && wdone < wlen) { 2322 bzero(rwbuf, sizeof(rwbuf)); 2323 rwlen = (wlen - wdone) % sizeof(rwbuf); 2324 bcopy(&wbuf[wdone], rwbuf, rwlen); 2325 2326 #ifdef ARC_DEBUG 2327 if (arcdebug & ARC_D_DB) { 2328 printf("%s: write %d:", DEVNAME(sc), rwlen); 2329 for (i = 0; i < rwlen; i++) 2330 printf(" 0x%02x", rwbuf[i]); 2331 printf("\n"); 2332 } 2333 #endif 2334 2335 switch(sc->sc_adp_type) { 2336 case ARC_HBA_TYPE_A: 2337 /* copy the chunk to the hw */ 2338 arc_write(sc, ARC_RA_IOC_WBUF_LEN, rwlen); 2339 arc_write_region(sc, ARC_RA_IOC_WBUF, rwbuf, 2340 sizeof(rwbuf)); 2341 2342 /* say we have a buffer for the hw */ 2343 arc_write(sc, ARC_RA_INB_DOORBELL, 2344 ARC_RA_INB_DOORBELL_WRITE_OK); 2345 break; 2346 case ARC_HBA_TYPE_C: 2347 /* copy the chunk to the hw */ 2348 arc_write(sc, ARC_RC_MSG_WBUF_LEN, rwlen); 2349 arc_write_region(sc, ARC_RC_MSG_WBUF, rwbuf, 2350 sizeof(rwbuf)); 2351 2352 /* say we have a buffer for the hw */ 2353 arc_write(sc, ARC_RC_INB_DOORBELL, 2354 ARC_RC_D2I_DATA_WRITE_OK); 2355 break; 2356 case ARC_HBA_TYPE_D: 2357 /* copy the chunk to the hw */ 2358 arc_write(sc, ARC_RD_MSG_WBUF_LEN, rwlen); 2359 arc_write_region(sc, ARC_RD_MSG_WBUF, rwbuf, 2360 sizeof(rwbuf)); 2361 2362 /* say we have a buffer for the hw */ 2363 arc_write(sc, ARC_RD_INB_DOORBELL, 2364 ARC_RD_D2I_DATA_WRITE_OK); 2365 break; 2366 } 2367 wdone += rwlen; 2368 } 2369 2370 if (rptr == NULL) 2371 goto out; 2372 2373 switch(sc->sc_adp_type) { 2374 case ARC_HBA_TYPE_A: 2375 while ((reg = arc_read(sc, ARC_RA_OUTB_DOORBELL)) == 0) 2376 arc_wait(sc); 2377 arc_write(sc, ARC_RA_OUTB_DOORBELL, reg); 2378 write_ok = reg & ARC_RA_OUTB_DOORBELL_WRITE_OK; 2379 read_ok = reg & ARC_RA_OUTB_DOORBELL_READ_OK; 2380 break; 2381 case ARC_HBA_TYPE_C: 2382 while ((reg = arc_read(sc, ARC_RC_OUTB_DOORBELL)) == 0) 2383 arc_wait(sc); 2384 arc_write(sc, ARC_RC_OUTB_DOORBELL_CLR, reg); 2385 write_ok = reg & ARC_RC_I2D_DATA_WRITE_OK; 2386 read_ok = reg & ARC_RC_I2D_DATA_READ_OK; 2387 break; 2388 case ARC_HBA_TYPE_D: 2389 while ((reg = arc_read(sc, ARC_RD_OUTB_DOORBELL)) == 0) 2390 arc_wait(sc); 2391 arc_write(sc, ARC_RD_OUTB_DOORBELL_CLR, reg); 2392 write_ok = reg & ARC_RD_I2D_DATA_WRITE_OK; 2393 read_ok = reg & ARC_RD_I2D_DATA_READ_OK; 2394 break; 2395 } 2396 DNPRINTF(ARC_D_DB, "%s: reg: 0x%08x\n", DEVNAME(sc), reg); 2397 2398 if ((write_ok) && rdone < rlen) { 2399 switch(sc->sc_adp_type) { 2400 case ARC_HBA_TYPE_A: 2401 rwlen = arc_read(sc, ARC_RA_IOC_RBUF_LEN); 2402 break; 2403 case ARC_HBA_TYPE_C: 2404 rwlen = arc_read(sc, ARC_RC_MSG_RBUF_LEN); 2405 break; 2406 case ARC_HBA_TYPE_D: 2407 rwlen = arc_read(sc, ARC_RD_MSG_RBUF_LEN); 2408 break; 2409 } 2410 if (rwlen > sizeof(rwbuf)) { 2411 DNPRINTF(ARC_D_DB, "%s: rwlen too big\n", 2412 DEVNAME(sc)); 2413 error = EIO; 2414 goto out; 2415 } 2416 2417 switch(sc->sc_adp_type) { 2418 case ARC_HBA_TYPE_A: 2419 arc_read_region(sc, ARC_RA_IOC_RBUF, rwbuf, 2420 sizeof(rwbuf)); 2421 arc_write(sc, ARC_RA_INB_DOORBELL, 2422 ARC_RA_INB_DOORBELL_READ_OK); 2423 break; 2424 case ARC_HBA_TYPE_C: 2425 arc_read_region(sc, ARC_RC_MSG_RBUF, rwbuf, 2426 sizeof(rwbuf)); 2427 arc_write(sc, ARC_RC_INB_DOORBELL, 2428 ARC_RC_I2D_DATA_READ_OK); 2429 break; 2430 case ARC_HBA_TYPE_D: 2431 arc_read_region(sc, ARC_RD_MSG_RBUF, rwbuf, 2432 sizeof(rwbuf)); 2433 arc_write(sc, ARC_RD_INB_DOORBELL, 2434 ARC_RD_I2D_DATA_READ_OK); 2435 break; 2436 } 2437 if ((rlen > 3) && (rdone == 3)) { 2438 rlen = *(u_int16_t *)rwbuf; 2439 rlen = sizeof(struct arc_fw_bufhdr) + rlen + 1; 2440 } 2441 #ifdef ARC_DEBUG 2442 printf("%s: len: %d+%d=%d/%d\n", DEVNAME(sc), 2443 rwlen, rdone, rwlen + rdone, rlen); 2444 if (arcdebug & ARC_D_DB) { 2445 printf("%s: read:", DEVNAME(sc)); 2446 for (i = 0; i < rwlen; i++) 2447 printf(" 0x%02x", rwbuf[i]); 2448 printf("\n"); 2449 } 2450 #endif 2451 2452 if ((rdone + rwlen) > rlen) { 2453 DNPRINTF(ARC_D_DB, "%s: rwbuf too big\n", 2454 DEVNAME(sc)); 2455 error = EIO; 2456 goto out; 2457 } 2458 2459 bcopy(rwbuf, &rbuf[rdone], rwlen); 2460 rdone += rwlen; 2461 2462 /* 2463 * Allow for short reads, by reading the length 2464 * value from the response header and shrinking our 2465 * idea of size, if required. 2466 * This deals with the growth of diskinfo struct from 2467 * 128 to 132 bytes. 2468 */ 2469 if (sreadok && rdone >= sizeof(struct arc_fw_bufhdr) && 2470 rlenhdr == 0) { 2471 bufhdr = (struct arc_fw_bufhdr *)rbuf; 2472 rlenhdr = letoh16(bufhdr->len); 2473 if (rlenhdr < rbuflen) { 2474 rbuflen = rlenhdr; 2475 rlen = sizeof(struct arc_fw_bufhdr) + 2476 rbuflen + 1; /* 1 for cksum */ 2477 } 2478 } 2479 } 2480 } while (rdone != rlen); 2481 2482 bufhdr = (struct arc_fw_bufhdr *)rbuf; 2483 if (memcmp(&bufhdr->hdr, &arc_fw_hdr, sizeof(bufhdr->hdr)) != 0) { 2484 DNPRINTF(ARC_D_DB, "%s: rbuf hdr is wrong\n", DEVNAME(sc)); 2485 error = EIO; 2486 goto out; 2487 } 2488 2489 if (bufhdr->len != htole16(rbuflen)) { 2490 DNPRINTF(ARC_D_DB, "%s: get_len: 0x%x, req_len: 0x%x\n", 2491 DEVNAME(sc), bufhdr->len, rbuflen); 2492 } 2493 2494 bcopy(rbuf + sizeof(struct arc_fw_bufhdr), rptr, bufhdr->len); 2495 cksum = arc_msg_cksum(rptr, bufhdr->len); 2496 if (rbuf[rlen - 1] != cksum) { 2497 DNPRINTF(ARC_D_DB, "%s: invalid cksum, got :0x%x, calculated:" 2498 " 0x%x\n", DEVNAME(sc), rbuf[rlen-1], cksum); 2499 error = EIO; 2500 goto out; 2501 } 2502 2503 out: 2504 free(wbuf, M_TEMP, 0); 2505 free(rbuf, M_TEMP, 0); 2506 2507 return (error); 2508 } 2509 2510 void 2511 arc_lock(struct arc_softc *sc) 2512 { 2513 int s; 2514 u_int32_t int_mask; 2515 2516 rw_enter_write(&sc->sc_lock); 2517 s = splbio(); 2518 switch(sc->sc_adp_type) { 2519 case ARC_HBA_TYPE_A: 2520 int_mask = arc_read(sc, ARC_RA_INTRMASK) | ARC_RA_INTRMASK_DOORBELL; 2521 arc_write(sc, ARC_RA_INTRMASK, int_mask); 2522 break; 2523 case ARC_HBA_TYPE_C: 2524 int_mask = arc_read(sc, ARC_RC_INTR_MASK) | ARC_RC_INTR_MASK_DOORBELL; 2525 arc_write(sc, ARC_RC_INTR_MASK, int_mask); 2526 break; 2527 case ARC_HBA_TYPE_D: 2528 int_mask = arc_read(sc, ARC_RD_INTR_ENABLE) & ~ARC_RD_INTR_ENABLE_DOORBELL; 2529 arc_write(sc, ARC_RD_INTR_ENABLE, int_mask); 2530 break; 2531 } 2532 sc->sc_talking = 1; 2533 splx(s); 2534 } 2535 2536 void 2537 arc_unlock(struct arc_softc *sc) 2538 { 2539 int s; 2540 u_int32_t int_mask; 2541 2542 s = splbio(); 2543 sc->sc_talking = 0; 2544 switch(sc->sc_adp_type) { 2545 case ARC_HBA_TYPE_A: 2546 int_mask = arc_read(sc, ARC_RA_INTRMASK) & ~ARC_RA_INTRMASK_DOORBELL; 2547 arc_write(sc, ARC_RA_INTRMASK, int_mask); 2548 break; 2549 case ARC_HBA_TYPE_C: 2550 int_mask = arc_read(sc, ARC_RC_INTR_MASK) & ~ARC_RC_INTR_MASK_DOORBELL; 2551 arc_write(sc, ARC_RC_INTR_MASK, int_mask); 2552 break; 2553 case ARC_HBA_TYPE_D: 2554 int_mask = arc_read(sc, ARC_RD_INTR_ENABLE) | ARC_RD_INTR_ENABLE_DOORBELL; 2555 arc_write(sc, ARC_RD_INTR_ENABLE, int_mask); 2556 break; 2557 } 2558 splx(s); 2559 rw_exit_write(&sc->sc_lock); 2560 } 2561 2562 void 2563 arc_wait(struct arc_softc *sc) 2564 { 2565 int error, s; 2566 u_int32_t int_mask; 2567 2568 s = splbio(); 2569 switch(sc->sc_adp_type) { 2570 case ARC_HBA_TYPE_A: 2571 int_mask = arc_read(sc, ARC_RA_INTRMASK) & ~ARC_RA_INTRMASK_DOORBELL; 2572 arc_write(sc, ARC_RA_INTRMASK, int_mask); 2573 error = tsleep_nsec(sc, PWAIT, "arcdb", SEC_TO_NSEC(1)); 2574 if (error == EWOULDBLOCK) { 2575 int_mask = arc_read(sc, ARC_RA_INTRMASK) | ARC_RA_INTRMASK_DOORBELL; 2576 arc_write(sc, ARC_RA_INTRMASK, int_mask); 2577 } 2578 break; 2579 case ARC_HBA_TYPE_C: 2580 int_mask = arc_read(sc, ARC_RC_INTR_MASK) & ~ARC_RC_INTR_MASK_DOORBELL; 2581 arc_write(sc, ARC_RC_INTR_MASK, int_mask); 2582 error = tsleep_nsec(sc, PWAIT, "arcdb", SEC_TO_NSEC(1)); 2583 if (error == EWOULDBLOCK) { 2584 int_mask = arc_read(sc, ARC_RC_INTR_MASK) | ARC_RC_INTR_MASK_DOORBELL; 2585 arc_write(sc, ARC_RC_INTR_MASK, int_mask); 2586 } 2587 break; 2588 case ARC_HBA_TYPE_D: 2589 int_mask = arc_read(sc, ARC_RD_INTR_ENABLE) | ARC_RD_INTR_ENABLE_DOORBELL; 2590 arc_write(sc, ARC_RD_INTR_ENABLE, int_mask); 2591 error = tsleep_nsec(sc, PWAIT, "arcdb", SEC_TO_NSEC(1)); 2592 if (error == EWOULDBLOCK) { 2593 int_mask = arc_read(sc, ARC_RD_INTR_ENABLE) & ~ARC_RD_INTR_ENABLE_DOORBELL; 2594 arc_write(sc, ARC_RD_INTR_ENABLE, int_mask); 2595 } 2596 break; 2597 } 2598 splx(s); 2599 } 2600 2601 #ifndef SMALL_KERNEL 2602 void 2603 arc_create_sensors(void *xat) 2604 { 2605 struct arc_task *at = xat; 2606 struct arc_softc *sc = at->sc; 2607 struct bioc_inq bi; 2608 struct bioc_vol bv; 2609 int i; 2610 2611 free(at, M_TEMP, sizeof(*at)); 2612 2613 DPRINTF("%s: arc_create_sensors\n", DEVNAME(sc)); 2614 /* 2615 * XXX * this is bollocks. the firmware has garbage coming out of it 2616 * so we have to wait a bit for it to finish spewing. 2617 */ 2618 tsleep_nsec(sc, PWAIT, "arcspew", SEC_TO_NSEC(2)); 2619 2620 bzero(&bi, sizeof(bi)); 2621 if (arc_bio_inq(sc, &bi) != 0) { 2622 printf("%s: unable to query firmware for sensor info\n", 2623 DEVNAME(sc)); 2624 return; 2625 } 2626 sc->sc_nsensors = bi.bi_novol; 2627 2628 sc->sc_sensors = mallocarray(sc->sc_nsensors, sizeof(struct ksensor), 2629 M_DEVBUF, M_WAITOK | M_ZERO); 2630 2631 strlcpy(sc->sc_sensordev.xname, DEVNAME(sc), 2632 sizeof(sc->sc_sensordev.xname)); 2633 2634 for (i = 0; i < sc->sc_nsensors; i++) { 2635 bzero(&bv, sizeof(bv)); 2636 bv.bv_volid = i; 2637 if (arc_bio_vol(sc, &bv) != 0) { 2638 DPRINTF("%s: arc_bio_vol failed!\n", DEVNAME(sc)); 2639 goto bad; 2640 } 2641 2642 sc->sc_sensors[i].type = SENSOR_DRIVE; 2643 sc->sc_sensors[i].status = SENSOR_S_UNKNOWN; 2644 2645 strlcpy(sc->sc_sensors[i].desc, bv.bv_dev, 2646 sizeof(sc->sc_sensors[i].desc)); 2647 2648 sensor_attach(&sc->sc_sensordev, &sc->sc_sensors[i]); 2649 } 2650 2651 if (sensor_task_register(sc, arc_refresh_sensors, 120) == NULL) { 2652 DPRINTF("%s: sensor_task_register failed!\n", DEVNAME(sc)); 2653 goto bad; 2654 } 2655 2656 sensordev_install(&sc->sc_sensordev); 2657 2658 return; 2659 2660 bad: 2661 free(sc->sc_sensors, M_DEVBUF, 2662 sc->sc_nsensors * sizeof(struct ksensor)); 2663 } 2664 2665 void 2666 arc_refresh_sensors(void *arg) 2667 { 2668 struct arc_softc *sc = arg; 2669 struct bioc_vol bv; 2670 int i; 2671 2672 for (i = 0; i < sc->sc_nsensors; i++) { 2673 bzero(&bv, sizeof(bv)); 2674 bv.bv_volid = i; 2675 if (arc_bio_vol(sc, &bv)) { 2676 sc->sc_sensors[i].flags = SENSOR_FINVALID; 2677 return; 2678 } 2679 2680 switch(bv.bv_status) { 2681 case BIOC_SVOFFLINE: 2682 sc->sc_sensors[i].value = SENSOR_DRIVE_FAIL; 2683 sc->sc_sensors[i].status = SENSOR_S_CRIT; 2684 break; 2685 2686 case BIOC_SVDEGRADED: 2687 sc->sc_sensors[i].value = SENSOR_DRIVE_PFAIL; 2688 sc->sc_sensors[i].status = SENSOR_S_WARN; 2689 break; 2690 2691 case BIOC_SVSCRUB: 2692 case BIOC_SVONLINE: 2693 sc->sc_sensors[i].value = SENSOR_DRIVE_ONLINE; 2694 sc->sc_sensors[i].status = SENSOR_S_OK; 2695 break; 2696 2697 case BIOC_SVINVALID: 2698 /* FALLTRHOUGH */ 2699 default: 2700 sc->sc_sensors[i].value = 0; /* unknown */ 2701 sc->sc_sensors[i].status = SENSOR_S_UNKNOWN; 2702 } 2703 2704 } 2705 } 2706 #endif /* SMALL_KERNEL */ 2707 #endif /* NBIO > 0 */ 2708 2709 u_int32_t 2710 arc_read(struct arc_softc *sc, bus_size_t r) 2711 { 2712 u_int32_t v; 2713 2714 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 2715 BUS_SPACE_BARRIER_READ); 2716 v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 2717 2718 DNPRINTF(ARC_D_RW, "%s: arc_read 0x%x 0x%08x\n", DEVNAME(sc), r, v); 2719 2720 return (v); 2721 } 2722 2723 void 2724 arc_read_region(struct arc_softc *sc, bus_size_t r, void *buf, size_t len) 2725 { 2726 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, len, 2727 BUS_SPACE_BARRIER_READ); 2728 bus_space_read_raw_region_4(sc->sc_iot, sc->sc_ioh, r, buf, len); 2729 } 2730 2731 void 2732 arc_write(struct arc_softc *sc, bus_size_t r, u_int32_t v) 2733 { 2734 DNPRINTF(ARC_D_RW, "%s: arc_write 0x%x 0x%08x\n", DEVNAME(sc), r, v); 2735 2736 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v); 2737 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 2738 BUS_SPACE_BARRIER_WRITE); 2739 } 2740 2741 void 2742 arc_write_region(struct arc_softc *sc, bus_size_t r, void *buf, size_t len) 2743 { 2744 bus_space_write_raw_region_4(sc->sc_iot, sc->sc_ioh, r, buf, len); 2745 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, len, 2746 BUS_SPACE_BARRIER_WRITE); 2747 } 2748 2749 int 2750 arc_wait_eq(struct arc_softc *sc, bus_size_t r, u_int32_t mask, 2751 u_int32_t target) 2752 { 2753 int i; 2754 2755 DNPRINTF(ARC_D_RW, "%s: arc_wait_eq 0x%x 0x%08x 0x%08x\n", 2756 DEVNAME(sc), r, mask, target); 2757 2758 for (i = 0; i < 10000; i++) { 2759 if ((arc_read(sc, r) & mask) == target) 2760 return (0); 2761 delay(1000); 2762 } 2763 2764 return (1); 2765 } 2766 2767 int 2768 arc_wait_ne(struct arc_softc *sc, bus_size_t r, u_int32_t mask, 2769 u_int32_t target) 2770 { 2771 int i; 2772 2773 DNPRINTF(ARC_D_RW, "%s: arc_wait_ne 0x%x 0x%08x 0x%08x\n", 2774 DEVNAME(sc), r, mask, target); 2775 2776 for (i = 0; i < 10000; i++) { 2777 if ((arc_read(sc, r) & mask) != target) 2778 return (0); 2779 delay(1000); 2780 } 2781 2782 return (1); 2783 } 2784 2785 int 2786 arc_msg0(struct arc_softc *sc, u_int32_t m) 2787 { 2788 switch(sc->sc_adp_type) { 2789 case ARC_HBA_TYPE_A: 2790 /* post message */ 2791 arc_write(sc, ARC_RA_INB_MSG0, m); 2792 /* wait for the fw to do it */ 2793 if (arc_wait_eq(sc, ARC_RA_INTRSTAT, ARC_RA_INTRSTAT_MSG0, 2794 ARC_RA_INTRSTAT_MSG0) != 0) 2795 return (1); 2796 2797 /* ack it */ 2798 arc_write(sc, ARC_RA_INTRSTAT, ARC_RA_INTRSTAT_MSG0); 2799 break; 2800 2801 case ARC_HBA_TYPE_C: 2802 /* post message */ 2803 arc_write(sc, ARC_RC_INB_MSGADDR0, m); 2804 arc_write(sc, ARC_RC_INB_DOORBELL, ARC_RC_D2I_MSG_CMD_DONE); 2805 /* wait for the fw to do it */ 2806 if (arc_wait_eq(sc, ARC_RC_OUTB_DOORBELL, ARC_RC_I2D_MSG_CMD_DONE, 2807 ARC_RC_I2D_MSG_CMD_DONE) != 0) 2808 return (1); 2809 2810 /* ack it */ 2811 arc_write(sc, ARC_RC_OUTB_DOORBELL_CLR, ARC_RC_I2D_MSG_CMD_DONE_CLR); 2812 break; 2813 2814 case ARC_HBA_TYPE_D: 2815 /* post message */ 2816 arc_write(sc, ARC_RD_INB_MSGADDR0, m); 2817 /* wait for the fw to do it */ 2818 if (arc_wait_eq(sc, ARC_RD_OUTB_DOORBELL, ARC_RD_I2D_MSG_CMD_DONE, 2819 ARC_RD_I2D_MSG_CMD_DONE) != 0) 2820 return (1); 2821 2822 /* ack it */ 2823 arc_write(sc, ARC_RD_OUTB_DOORBELL_CLR, ARC_RD_I2D_MSG_CMD_DONE_CLR); 2824 break; 2825 } 2826 return (0); 2827 } 2828 2829 struct arc_dmamem * 2830 arc_dmamem_alloc(struct arc_softc *sc, size_t size) 2831 { 2832 struct arc_dmamem *adm; 2833 int nsegs; 2834 2835 adm = malloc(sizeof(*adm), M_DEVBUF, M_NOWAIT | M_ZERO); 2836 if (adm == NULL) 2837 return (NULL); 2838 2839 adm->adm_size = size; 2840 2841 if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 2842 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &adm->adm_map) != 0) 2843 goto admfree; 2844 2845 if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &adm->adm_seg, 2846 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) 2847 goto destroy; 2848 2849 if (bus_dmamem_map(sc->sc_dmat, &adm->adm_seg, nsegs, size, 2850 &adm->adm_kva, BUS_DMA_NOWAIT) != 0) 2851 goto free; 2852 2853 if (bus_dmamap_load(sc->sc_dmat, adm->adm_map, adm->adm_kva, size, 2854 NULL, BUS_DMA_NOWAIT) != 0) 2855 goto unmap; 2856 2857 return (adm); 2858 2859 unmap: 2860 bus_dmamem_unmap(sc->sc_dmat, adm->adm_kva, size); 2861 free: 2862 bus_dmamem_free(sc->sc_dmat, &adm->adm_seg, 1); 2863 destroy: 2864 bus_dmamap_destroy(sc->sc_dmat, adm->adm_map); 2865 admfree: 2866 free(adm, M_DEVBUF, sizeof *adm); 2867 2868 return (NULL); 2869 } 2870 2871 void 2872 arc_dmamem_free(struct arc_softc *sc, struct arc_dmamem *adm) 2873 { 2874 bus_dmamap_unload(sc->sc_dmat, adm->adm_map); 2875 bus_dmamem_unmap(sc->sc_dmat, adm->adm_kva, adm->adm_size); 2876 bus_dmamem_free(sc->sc_dmat, &adm->adm_seg, 1); 2877 bus_dmamap_destroy(sc->sc_dmat, adm->adm_map); 2878 free(adm, M_DEVBUF, sizeof *adm); 2879 } 2880 2881 int 2882 arc_alloc_ccbs(struct arc_softc *sc) 2883 { 2884 struct arc_ccb *ccb; 2885 u_int8_t *cmd; 2886 u_int32_t i, size, len; 2887 2888 SLIST_INIT(&sc->sc_ccb_free); 2889 mtx_init(&sc->sc_ccb_mtx, IPL_BIO); 2890 2891 size = sizeof(struct arc_ccb) * ARCMSR_MAX_CCB_COUNT; 2892 sc->sc_ccbs = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 2893 2894 len = ARC_IO_CMD_LEN; 2895 size = ARCMSR_MAX_CCB_COUNT * len; 2896 if(sc->sc_adp_type == ARC_HBA_TYPE_D) 2897 size += sizeof(struct arc_HBD_Msgu); 2898 sc->sc_requests = arc_dmamem_alloc(sc, size); 2899 if (sc->sc_requests == NULL) { 2900 printf("%s: unable to allocate ccb dmamem\n", DEVNAME(sc)); 2901 goto free_ccbs; 2902 } 2903 cmd = ARC_DMA_KVA(sc->sc_requests); 2904 2905 for (i = 0; i < ARCMSR_MAX_CCB_COUNT; i++) { 2906 ccb = &sc->sc_ccbs[i]; 2907 2908 if (bus_dmamap_create(sc->sc_dmat, MAXPHYS, ARC_SGL_MAXLEN, 2909 MAXPHYS, 0, 0, &ccb->ccb_dmamap) != 0) { 2910 printf("%s: unable to create dmamap for ccb %d\n", 2911 DEVNAME(sc), i); 2912 goto free_maps; 2913 } 2914 2915 ccb->ccb_sc = sc; 2916 ccb->cmd_dma_offset = len * i; 2917 2918 ccb->ccb_cmd = (struct arc_io_cmd *)&cmd[ccb->cmd_dma_offset]; 2919 ccb->ccb_cmd_post = (ARC_DMA_DVA(sc->sc_requests) + 2920 ccb->cmd_dma_offset); 2921 if ((sc->sc_adp_type != ARC_HBA_TYPE_C) && 2922 (sc->sc_adp_type != ARC_HBA_TYPE_D)) 2923 ccb->ccb_cmd_post = ccb->ccb_cmd_post >> 2924 ARC_RA_POST_QUEUE_ADDR_SHIFT; 2925 arc_put_ccb(sc, ccb); 2926 } 2927 sc->sc_ccb_phys_hi = (u_int64_t)ARC_DMA_DVA(sc->sc_requests) >> 32; 2928 if(sc->sc_adp_type == ARC_HBA_TYPE_D) { 2929 sc->postQ_buffer = ARC_DMA_DVA(sc->sc_requests) + 2930 (ARCMSR_MAX_CCB_COUNT * len); 2931 sc->doneQ_buffer = sc->postQ_buffer + (sizeof(struct InBound_SRB) * 2932 ARCMSR_MAX_HBD_POSTQUEUE); 2933 sc->pmu = (struct arc_HBD_Msgu *)&cmd[ARCMSR_MAX_CCB_COUNT * len]; 2934 sc->cmdQ_ptr_offset = ARCMSR_MAX_CCB_COUNT * len; 2935 } 2936 scsi_iopool_init(&sc->sc_iopool, sc, 2937 (void *(*)(void *))arc_get_ccb, 2938 (void (*)(void *, void *))arc_put_ccb); 2939 2940 return (0); 2941 2942 free_maps: 2943 while ((ccb = arc_get_ccb(sc)) != NULL) 2944 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 2945 arc_dmamem_free(sc, sc->sc_requests); 2946 2947 free_ccbs: 2948 free(sc->sc_ccbs, M_DEVBUF, sizeof(struct arc_ccb) * ARCMSR_MAX_CCB_COUNT); 2949 2950 return (1); 2951 } 2952 2953 void 2954 arc_free_ccb_src(struct arc_softc *sc) 2955 { 2956 struct arc_ccb *ccb; 2957 2958 while ((ccb = arc_get_ccb(sc)) != NULL) 2959 bus_dmamap_destroy(sc->sc_dmat, ccb->ccb_dmamap); 2960 arc_dmamem_free(sc, sc->sc_requests); 2961 free(sc->sc_ccbs, M_DEVBUF, 0); 2962 } 2963 2964 struct arc_ccb * 2965 arc_get_ccb(struct arc_softc *sc) 2966 { 2967 struct arc_ccb *ccb; 2968 2969 mtx_enter(&sc->sc_ccb_mtx); 2970 ccb = SLIST_FIRST(&sc->sc_ccb_free); 2971 if (ccb != NULL) 2972 SLIST_REMOVE_HEAD(&sc->sc_ccb_free, ccb_link); 2973 mtx_leave(&sc->sc_ccb_mtx); 2974 2975 return (ccb); 2976 } 2977 2978 void 2979 arc_put_ccb(struct arc_softc *sc, struct arc_ccb *ccb) 2980 { 2981 ccb->ccb_xs = NULL; 2982 bzero(ccb->ccb_cmd, ARC_IO_CMD_LEN); 2983 mtx_enter(&sc->sc_ccb_mtx); 2984 SLIST_INSERT_HEAD(&sc->sc_ccb_free, ccb, ccb_link); 2985 mtx_leave(&sc->sc_ccb_mtx); 2986 } 2987