1 /* $OpenBSD: ahd_pci.c,v 1.17 2007/10/22 03:16:35 fgsch Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Milos Urbanek, Kenneth R. Westerback & Marco Peereboom 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Product specific probe and attach routines for: 32 * aic7901 and aic7902 SCSI controllers 33 * 34 * Copyright (c) 1994-2001 Justin T. Gibbs. 35 * Copyright (c) 2000-2002 Adaptec Inc. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions, and the following disclaimer, 43 * without modification. 44 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 45 * substantially similar to the "NO WARRANTY" disclaimer below 46 * ("Disclaimer") and any redistribution must be conditioned upon 47 * including a substantially similar Disclaimer requirement for further 48 * binary redistribution. 49 * 3. Neither the names of the above-listed copyright holders nor the names 50 * of any contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * Alternatively, this software may be distributed under the terms of the 54 * GNU General Public License ("GPL") version 2 as published by the Free 55 * Software Foundation. 56 * 57 * NO WARRANTY 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 59 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 60 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 61 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 62 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 67 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGES. 69 * 70 */ 71 72 #include <sys/cdefs.h> 73 /* 74 __FBSDID("$FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.18 2004/02/04 16:38:38 gibbs Exp $"); 75 */ 76 77 #include <dev/ic/aic79xx_openbsd.h> 78 #include <dev/ic/aic79xx_inline.h> 79 #include <dev/ic/aic79xx.h> 80 81 #include <dev/pci/pcivar.h> 82 83 __inline uint64_t ahd_compose_id(u_int, u_int, u_int, u_int); 84 __inline uint64_t 85 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 86 { 87 uint64_t id; 88 89 id = subvendor 90 | (subdevice << 16) 91 | ((uint64_t)vendor << 32) 92 | ((uint64_t)device << 48); 93 94 return (id); 95 } 96 97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 98 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 99 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 100 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 101 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 102 103 #define ID_AIC7901 0x800F9005FFFF9005ull 104 #define ID_AHA_29320A 0x8000900500609005ull 105 #define ID_AHA_29320ALP 0x8017900500449005ull 106 107 #define ID_AIC7901A 0x801E9005FFFF9005ull 108 #define ID_AHA_29320LP 0x8014900500449005ull 109 110 #define ID_AIC7902 0x801F9005FFFF9005ull 111 #define ID_AIC7902_B 0x801D9005FFFF9005ull 112 #define ID_AHA_39320 0x8010900500409005ull 113 #define ID_AHA_29320 0x8012900500429005ull 114 #define ID_AHA_29320B 0x8013900500439005ull 115 #define ID_AHA_39320_B 0x8015900500409005ull 116 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 117 #define ID_AHA_39320A 0x8016900500409005ull 118 #define ID_AHA_39320D 0x8011900500419005ull 119 #define ID_AHA_39320D_B 0x801C900500419005ull 120 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 121 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 122 #define ID_AIC7902_PCI_REV_A4 0x3 123 #define ID_AIC7902_PCI_REV_B0 0x10 124 #define SUBID_HP 0x0E11 125 126 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 127 128 #define DEVID_9005_TYPE(id) ((id) & 0xF) 129 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 130 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 131 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 132 133 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 134 135 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 136 137 #define SUBID_9005_TYPE(id) ((id) & 0xF) 138 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 139 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 140 141 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 142 143 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 144 145 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 146 #define SUBID_9005_SEEPTYPE_NONE 0x0 147 #define SUBID_9005_SEEPTYPE_4K 0x1 148 149 ahd_device_setup_t ahd_aic7901_setup; 150 ahd_device_setup_t ahd_aic7901A_setup; 151 ahd_device_setup_t ahd_aic7902_setup; 152 ahd_device_setup_t ahd_aic790X_setup; 153 154 struct ahd_pci_identity ahd_pci_ident_table [] = 155 { 156 /* aic7901 based controllers */ 157 { 158 ID_AHA_29320A, 159 ID_ALL_MASK, 160 ahd_aic7901_setup 161 }, 162 { 163 ID_AHA_29320ALP, 164 ID_ALL_MASK, 165 ahd_aic7901_setup 166 }, 167 /* aic7901A based controllers */ 168 { 169 ID_AHA_29320LP, 170 ID_ALL_MASK, 171 ahd_aic7901A_setup 172 }, 173 /* aic7902 based controllers */ 174 { 175 ID_AHA_29320, 176 ID_ALL_MASK, 177 ahd_aic7902_setup 178 }, 179 { 180 ID_AHA_29320B, 181 ID_ALL_MASK, 182 ahd_aic7902_setup 183 }, 184 { 185 ID_AHA_39320, 186 ID_ALL_MASK, 187 ahd_aic7902_setup 188 }, 189 { 190 ID_AHA_39320_B, 191 ID_ALL_MASK, 192 ahd_aic7902_setup 193 }, 194 { 195 ID_AHA_39320_B_DELL, 196 ID_ALL_MASK, 197 ahd_aic7902_setup 198 }, 199 { 200 ID_AHA_39320A, 201 ID_ALL_MASK, 202 ahd_aic7902_setup 203 }, 204 { 205 ID_AHA_39320D, 206 ID_ALL_MASK, 207 ahd_aic7902_setup 208 }, 209 { 210 ID_AHA_39320D_HP, 211 ID_ALL_MASK, 212 ahd_aic7902_setup 213 }, 214 { 215 ID_AHA_39320D_B, 216 ID_ALL_MASK, 217 ahd_aic7902_setup 218 }, 219 { 220 ID_AHA_39320D_B_HP, 221 ID_ALL_MASK, 222 ahd_aic7902_setup 223 }, 224 /* Generic chip probes for devices we don't know 'exactly' */ 225 { 226 ID_AIC7901 & ID_9005_GENERIC_MASK, 227 ID_9005_GENERIC_MASK, 228 ahd_aic7901_setup 229 }, 230 { 231 ID_AIC7901A & ID_DEV_VENDOR_MASK, 232 ID_DEV_VENDOR_MASK, 233 ahd_aic7901A_setup 234 }, 235 { 236 ID_AIC7902 & ID_9005_GENERIC_MASK, 237 ID_9005_GENERIC_MASK, 238 ahd_aic7902_setup 239 } 240 }; 241 242 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 243 244 #define DEVCONFIG 0x40 245 #define PCIXINITPAT 0x0000E000ul 246 #define PCIXINIT_PCI33_66 0x0000E000ul 247 #define PCIXINIT_PCIX50_66 0x0000C000ul 248 #define PCIXINIT_PCIX66_100 0x0000A000ul 249 #define PCIXINIT_PCIX100_133 0x00008000ul 250 #define PCI_BUS_MODES_INDEX(devconfig) \ 251 (((devconfig) & PCIXINITPAT) >> 13) 252 253 static const char *pci_bus_modes[] = 254 { 255 "PCI bus mode unknown", 256 "PCI bus mode unknown", 257 "PCI bus mode unknown", 258 "PCI bus mode unknown", 259 "PCI-X 101-133MHz", 260 "PCI-X 67-100MHz", 261 "PCI-X 50-66MHz", 262 "PCI 33 or 66MHz" 263 }; 264 265 #define TESTMODE 0x00000800ul 266 #define IRDY_RST 0x00000200ul 267 #define FRAME_RST 0x00000100ul 268 #define PCI64BIT 0x00000080ul 269 #define MRDCEN 0x00000040ul 270 #define ENDIANSEL 0x00000020ul 271 #define MIXQWENDIANEN 0x00000008ul 272 #define DACEN 0x00000004ul 273 #define STPWLEVEL 0x00000002ul 274 #define QWENDIANSEL 0x00000001ul 275 276 #define DEVCONFIG1 0x44 277 #define PREQDIS 0x01 278 279 #define CSIZE_LATTIME 0x0c 280 #define CACHESIZE 0x000000fful 281 #define LATTIME 0x0000ff00ul 282 283 int ahd_pci_probe(struct device *, void *, void *); 284 void ahd_pci_attach(struct device *, struct device *, void *); 285 286 struct cfattach ahd_pci_ca = { 287 sizeof(struct ahd_softc), ahd_pci_probe, ahd_pci_attach 288 }; 289 290 int ahd_check_extport(struct ahd_softc *ahd); 291 void ahd_configure_termination(struct ahd_softc *ahd, 292 u_int adapter_control); 293 void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 294 295 const struct ahd_pci_identity * 296 ahd_find_pci_device(pcireg_t id, pcireg_t subid) 297 { 298 const struct ahd_pci_identity *entry; 299 u_int64_t full_id; 300 u_int i; 301 302 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 303 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 304 305 /* 306 * If we are configured to attach to HostRAID 307 * controllers, mask out the IROC/HostRAID bit 308 * in the 309 */ 310 if (ahd_attach_to_HostRAID_controllers) 311 full_id &= ID_ALL_IROC_MASK; 312 313 for (i = 0; i < ahd_num_pci_devs; i++) { 314 entry = &ahd_pci_ident_table[i]; 315 if (entry->full_id == (full_id & entry->id_mask)) { 316 return (entry); 317 } 318 } 319 return (NULL); 320 } 321 322 int 323 ahd_pci_probe(struct device *parent, void *match, void *aux) 324 { 325 const struct ahd_pci_identity *entry; 326 struct pci_attach_args *pa = aux; 327 pcireg_t subid; 328 329 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 330 entry = ahd_find_pci_device(pa->pa_id, subid); 331 return entry != NULL ? 1 : 0; 332 } 333 334 void 335 ahd_pci_attach(struct device *parent, struct device *self, void *aux) 336 { 337 const struct ahd_pci_identity *entry; 338 struct pci_attach_args *pa = aux; 339 struct ahd_softc *ahd = (void *)self; 340 pci_intr_handle_t ih; 341 const char *intrstr; 342 pcireg_t devconfig, memtype, subid; 343 uint16_t device, subvendor; 344 int error, ioh_valid, ioh2_valid, l, memh_valid; 345 346 ahd->dev_softc = pa; 347 ahd->parent_dmat = pa->pa_dmat; 348 349 if (ahd_alloc(ahd, ahd->sc_dev.dv_xname) == NULL) 350 return; 351 352 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 353 entry = ahd_find_pci_device(pa->pa_id, subid); 354 if (entry == NULL) 355 return; 356 357 /* 358 * Record if this is a HostRAID board. 359 */ 360 device = PCI_PRODUCT(pa->pa_id); 361 if (DEVID_9005_HOSTRAID(device)) 362 ahd->flags |= AHD_HOSTRAID_BOARD; 363 364 /* 365 * Record if this is an HP board. 366 */ 367 subvendor = PCI_VENDOR(subid); 368 if (subvendor == SUBID_HP) 369 ahd->flags |= AHD_HP_BOARD; 370 371 error = entry->setup(ahd, pa); 372 if (error != 0) 373 return; 374 375 /* XXX ahc on sparc64 needs this twice */ 376 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 377 378 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 379 ahd->chip |= AHD_PCI; 380 /* Disable PCIX workarounds when running in PCI mode. */ 381 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 382 } else { 383 ahd->chip |= AHD_PCIX; 384 } 385 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 386 387 memh_valid = ioh_valid = ioh2_valid = 0; 388 389 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 390 &ahd->pcix_off, NULL)) { 391 if (ahd->chip & AHD_PCIX) 392 printf("%s: warning: can't find PCI-X capability\n", 393 ahd_name(ahd)); 394 ahd->chip &= ~AHD_PCIX; 395 ahd->chip |= AHD_PCI; 396 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 397 } 398 399 /* 400 * Map PCI registers 401 */ 402 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 403 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 404 AHD_PCI_MEMADDR); 405 switch (memtype) { 406 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 407 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 408 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 409 memtype, 0, &ahd->tags[0], &ahd->bshs[0], NULL, 410 NULL, 0) == 0); 411 if (memh_valid) { 412 ahd->tags[1] = ahd->tags[0]; 413 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 414 /*offset*/0x100, /*size*/0x100, 415 &ahd->bshs[1]); 416 if (ahd_pci_test_register_access(ahd) != 0) 417 memh_valid = 0; 418 } 419 break; 420 default: 421 memh_valid = 0; 422 printf("%s: unknown memory type: 0x%x\n", 423 ahd_name(ahd), memtype); 424 break; 425 } 426 427 #ifdef AHD_DEBUG 428 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, shs0 " 429 "0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 430 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 431 #endif 432 } 433 434 if (!memh_valid) { 435 /* First BAR */ 436 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 437 PCI_MAPREG_TYPE_IO, 0, &ahd->tags[0], &ahd->bshs[0], NULL, 438 NULL, 0) == 0); 439 440 /* 2nd BAR */ 441 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 442 PCI_MAPREG_TYPE_IO, 0, &ahd->tags[1], &ahd->bshs[1], NULL, 443 NULL, 0) == 0); 444 445 #ifdef AHD_DEBUG 446 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, shs0 0x%lx, " 447 "shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], ahd->tags[1], 448 ahd->bshs[0], ahd->bshs[1]); 449 #endif 450 } 451 452 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 453 printf("%s: unable to map registers\n", ahd_name(ahd)); 454 return; 455 } 456 457 /* 458 * Set Power State D0. 459 */ 460 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 461 462 /* 463 * Should we bother disabling 39Bit addressing 464 * based on installed memory? 465 */ 466 if (sizeof(bus_addr_t) > 4) 467 ahd->flags |= AHD_39BIT_ADDRESSING; 468 469 /* 470 * If we need to support high memory, enable dual 471 * address cycles. This bit must be set to enable 472 * high address bit generation even if we are on a 473 * 64bit bus (PCI64BIT set in devconfig). 474 */ 475 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 476 if (bootverbose) 477 printf("%s: Enabling 39Bit Addressing\n", 478 ahd_name(ahd)); 479 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 480 devconfig |= DACEN; 481 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 482 } 483 484 ahd_softc_init(ahd); 485 486 /* 487 * Map the interrupts routines 488 */ 489 ahd->bus_intr = ahd_pci_intr; 490 491 error = ahd_reset(ahd, /*reinit*/FALSE); 492 if (error != 0) { 493 ahd_free(ahd); 494 return; 495 } 496 497 if (pci_intr_map(pa, &ih)) { 498 printf("%s: couldn't map interrupt\n", ahd_name(ahd)); 499 ahd_free(ahd); 500 return; 501 } 502 intrstr = pci_intr_string(pa->pa_pc, ih); 503 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 504 ahd_platform_intr, ahd, ahd->sc_dev.dv_xname); 505 if (ahd->ih == NULL) { 506 printf("%s: couldn't establish interrupt", ahd_name(ahd)); 507 if (intrstr != NULL) 508 printf(" at %s", intrstr); 509 printf("\n"); 510 ahd_free(ahd); 511 return; 512 } 513 if (intrstr != NULL) 514 printf(": %s\n", intrstr); 515 516 /* Get the size of the cache */ 517 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 518 ahd->pci_cachesize *= 4; 519 520 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 521 /* See if we have a SEEPROM and perform auto-term */ 522 error = ahd_check_extport(ahd); 523 if (error != 0) 524 return; 525 526 /* Core initialization */ 527 error = ahd_init(ahd); 528 if (error != 0) 529 return; 530 531 ahd_list_lock(&l); 532 /* 533 * Link this softc in with all other ahd instances. 534 */ 535 ahd_softc_insert(ahd); 536 ahd_list_unlock(&l); 537 538 /* complete the attach */ 539 ahd_attach(ahd); 540 } 541 542 /* 543 * Perform some simple tests that should catch situations where 544 * our registers are invalidly mapped. 545 */ 546 int 547 ahd_pci_test_register_access(struct ahd_softc *ahd) 548 { 549 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 550 const pcitag_t tag = ahd->dev_softc->pa_tag; 551 pcireg_t cmd; 552 u_int targpcistat; 553 pcireg_t pci_status1; 554 int error; 555 uint8_t hcntrl; 556 557 error = EIO; 558 559 /* 560 * Enable PCI error interrupt status, but suppress NMIs 561 * generated by SERR raised due to target aborts. 562 */ 563 cmd = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 564 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 565 cmd & ~PCI_COMMAND_SERR_ENABLE); 566 567 /* 568 * First a simple test to see if any 569 * registers can be read. Reading 570 * HCNTRL has no side effects and has 571 * at least one bit that is guaranteed to 572 * be zero so it is a good register to 573 * use for this test. 574 */ 575 hcntrl = ahd_inb(ahd, HCNTRL); 576 if (hcntrl == 0xFF) 577 goto fail; 578 579 /* 580 * Next create a situation where write combining 581 * or read prefetching could be initiated by the 582 * CPU or host bridge. Our device does not support 583 * either, so look for data corruption and/or flaged 584 * PCI errors. First pause without causing another 585 * chip reset. 586 */ 587 hcntrl &= ~CHIPRST; 588 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 589 while (ahd_is_paused(ahd) == 0) 590 ; 591 592 /* Clear any PCI errors that occurred before our driver attached. */ 593 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 594 targpcistat = ahd_inb(ahd, TARGPCISTAT); 595 ahd_outb(ahd, TARGPCISTAT, targpcistat); 596 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 597 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_status1); 598 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 599 ahd_outb(ahd, CLRINT, CLRPCIINT); 600 601 ahd_outb(ahd, SEQCTL0, PERRORDIS); 602 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 603 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 604 goto fail; 605 606 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 607 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 608 targpcistat = ahd_inb(ahd, TARGPCISTAT); 609 if ((targpcistat & STA) != 0) 610 goto fail; 611 } 612 613 error = 0; 614 615 fail: 616 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 617 618 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 619 targpcistat = ahd_inb(ahd, TARGPCISTAT); 620 621 /* Silently clear any latched errors. */ 622 ahd_outb(ahd, TARGPCISTAT, targpcistat); 623 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 624 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, pci_status1); 625 ahd_outb(ahd, CLRINT, CLRPCIINT); 626 } 627 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 628 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, cmd); 629 return (error); 630 } 631 632 /* 633 * Check the external port logic for a serial eeprom 634 * and termination/cable detection contrls. 635 */ 636 int 637 ahd_check_extport(struct ahd_softc *ahd) 638 { 639 struct vpd_config vpd; 640 struct seeprom_config *sc; 641 u_int adapter_control; 642 int have_seeprom; 643 int error; 644 645 sc = ahd->seep_config; 646 have_seeprom = ahd_acquire_seeprom(ahd); 647 if (have_seeprom) { 648 u_int start_addr; 649 650 /* 651 * Fetch VPD for this function and parse it. 652 */ 653 if (bootverbose) 654 printf("%s: Reading VPD from SEEPROM...", 655 ahd_name(ahd)); 656 657 /* Address is always in units of 16bit words */ 658 start_addr = ((2 * sizeof(*sc)) 659 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 660 661 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 662 start_addr, sizeof(vpd)/2, 663 /*bytestream*/TRUE); 664 if (error == 0) 665 error = ahd_parse_vpddata(ahd, &vpd); 666 if (bootverbose) 667 printf("%s: VPD parsing %s\n", 668 ahd_name(ahd), 669 error == 0 ? "successful" : "failed"); 670 671 if (bootverbose) 672 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 673 674 /* Address is always in units of 16bit words */ 675 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 676 677 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 678 start_addr, sizeof(*sc)/2, 679 /*bytestream*/FALSE); 680 681 if (error != 0) { 682 printf("Unable to read SEEPROM\n"); 683 have_seeprom = 0; 684 } else { 685 have_seeprom = ahd_verify_cksum(sc); 686 687 if (bootverbose) { 688 if (have_seeprom == 0) 689 printf ("checksum error\n"); 690 else 691 printf ("done.\n"); 692 } 693 } 694 ahd_release_seeprom(ahd); 695 } 696 697 if (!have_seeprom) { 698 u_int nvram_scb; 699 700 /* 701 * Pull scratch ram settings and treat them as 702 * if they are the contents of an seeprom if 703 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 704 * in SCB 0xFF. We manually compose the data as 16bit 705 * values to avoid endian issues. 706 */ 707 ahd_set_scbptr(ahd, 0xFF); 708 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 709 if (nvram_scb != 0xFF 710 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 711 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 712 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 713 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 714 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 715 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 716 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 717 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 718 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 719 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 720 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 721 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 722 uint16_t *sc_data; 723 int i; 724 725 ahd_set_scbptr(ahd, nvram_scb); 726 sc_data = (uint16_t *)sc; 727 for (i = 0; i < 64; i += 2) 728 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 729 have_seeprom = ahd_verify_cksum(sc); 730 if (have_seeprom) 731 ahd->flags |= AHD_SCB_CONFIG_USED; 732 } 733 } 734 735 #ifdef AHD_DEBUG 736 if (have_seeprom != 0 737 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 738 uint16_t *sc_data; 739 int i; 740 741 printf("%s: Seeprom Contents:", ahd_name(ahd)); 742 sc_data = (uint16_t *)sc; 743 for (i = 0; i < (sizeof(*sc)); i += 2) 744 printf("\n\t0x%.4x", sc_data[i]); 745 printf("\n"); 746 } 747 #endif 748 749 if (!have_seeprom) { 750 if (bootverbose) 751 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 752 ahd->flags |= AHD_USEDEFAULTS; 753 error = ahd_default_config(ahd); 754 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 755 free(ahd->seep_config, M_DEVBUF); 756 ahd->seep_config = NULL; 757 } else { 758 error = ahd_parse_cfgdata(ahd, sc); 759 adapter_control = sc->adapter_control; 760 } 761 if (error != 0) 762 return (error); 763 764 ahd_configure_termination(ahd, adapter_control); 765 766 return (0); 767 } 768 769 void 770 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 771 { 772 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 773 const pcitag_t tag = ahd->dev_softc->pa_tag; 774 int error; 775 u_int sxfrctl1; 776 uint8_t termctl; 777 pcireg_t devconfig; 778 779 devconfig = pci_conf_read(pc, tag, DEVCONFIG); 780 devconfig &= ~STPWLEVEL; 781 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 782 devconfig |= STPWLEVEL; 783 if (bootverbose) 784 printf("%s: STPWLEVEL is %s\n", 785 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 786 pci_conf_write(pc, tag, DEVCONFIG, devconfig); 787 788 /* Make sure current sensing is off. */ 789 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 790 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 791 } 792 793 /* 794 * Read to sense. Write to set. 795 */ 796 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 797 if ((adapter_control & CFAUTOTERM) == 0) { 798 if (bootverbose) 799 printf("%s: Manual Primary Termination\n", 800 ahd_name(ahd)); 801 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 802 if ((adapter_control & CFSTERM) != 0) 803 termctl |= FLX_TERMCTL_ENPRILOW; 804 if ((adapter_control & CFWSTERM) != 0) 805 termctl |= FLX_TERMCTL_ENPRIHIGH; 806 } else if (error != 0) { 807 printf("%s: Primary Auto-Term Sensing failed! " 808 "Using Defaults.\n", ahd_name(ahd)); 809 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 810 } 811 812 if ((adapter_control & CFSEAUTOTERM) == 0) { 813 if (bootverbose) 814 printf("%s: Manual Secondary Termination\n", 815 ahd_name(ahd)); 816 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 817 if ((adapter_control & CFSELOWTERM) != 0) 818 termctl |= FLX_TERMCTL_ENSECLOW; 819 if ((adapter_control & CFSEHIGHTERM) != 0) 820 termctl |= FLX_TERMCTL_ENSECHIGH; 821 } else if (error != 0) { 822 printf("%s: Secondary Auto-Term Sensing failed! " 823 "Using Defaults.\n", ahd_name(ahd)); 824 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 825 } 826 827 /* 828 * Now set the termination based on what we found. 829 */ 830 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 831 ahd->flags &= ~AHD_TERM_ENB_A; 832 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 833 ahd->flags |= AHD_TERM_ENB_A; 834 sxfrctl1 |= STPWEN; 835 } 836 /* Must set the latch once in order to be effective. */ 837 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 838 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 839 840 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 841 if (error != 0) { 842 printf("%s: Unable to set termination settings!\n", 843 ahd_name(ahd)); 844 } else if (bootverbose) { 845 printf("%s: Primary High byte termination %sabled\n", 846 ahd_name(ahd), 847 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 848 849 printf("%s: Primary Low byte termination %sabled\n", 850 ahd_name(ahd), 851 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 852 853 printf("%s: Secondary High byte termination %sabled\n", 854 ahd_name(ahd), 855 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 856 857 printf("%s: Secondary Low byte termination %sabled\n", 858 ahd_name(ahd), 859 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 860 } 861 return; 862 } 863 864 #define DPE 0x80 865 #define SSE 0x40 866 #define RMA 0x20 867 #define RTA 0x10 868 #define STA 0x08 869 #define DPR 0x01 870 871 static const char *split_status_source[] = 872 { 873 "DFF0", 874 "DFF1", 875 "OVLY", 876 "CMC", 877 }; 878 879 static const char *pci_status_source[] = 880 { 881 "DFF0", 882 "DFF1", 883 "SG", 884 "CMC", 885 "OVLY", 886 "NONE", 887 "MSI", 888 "TARG" 889 }; 890 891 static const char *split_status_strings[] = 892 { 893 "%s: Received split response in %s.\n", 894 "%s: Received split completion error message in %s\n", 895 "%s: Receive overrun in %s\n", 896 "%s: Count not complete in %s\n", 897 "%s: Split completion data bucket in %s\n", 898 "%s: Split completion address error in %s\n", 899 "%s: Split completion byte count error in %s\n", 900 "%s: Signaled Target-abort to early terminate a split in %s\n" 901 }; 902 903 static const char *pci_status_strings[] = 904 { 905 "%s: Data Parity Error has been reported via PERR# in %s\n", 906 "%s: Target initial wait state error in %s\n", 907 "%s: Split completion read data parity error in %s\n", 908 "%s: Split completion address attribute parity error in %s\n", 909 "%s: Received a Target Abort in %s\n", 910 "%s: Received a Master Abort in %s\n", 911 "%s: Signal System Error Detected in %s\n", 912 "%s: Address or Write Phase Parity Error Detected in %s.\n" 913 }; 914 915 void 916 ahd_pci_intr(struct ahd_softc *ahd) 917 { 918 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 919 const pcitag_t tag = ahd->dev_softc->pa_tag; 920 uint8_t pci_status[8]; 921 ahd_mode_state saved_modes; 922 pcireg_t pci_status1; 923 u_int intstat; 924 u_int i; 925 u_int reg; 926 927 intstat = ahd_inb(ahd, INTSTAT); 928 929 if ((intstat & SPLTINT) != 0) 930 ahd_pci_split_intr(ahd, intstat); 931 932 if ((intstat & PCIINT) == 0) 933 return; 934 935 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 936 saved_modes = ahd_save_modes(ahd); 937 ahd_dump_card_state(ahd); 938 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 939 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 940 941 if (i == 5) 942 continue; 943 pci_status[i] = ahd_inb(ahd, reg); 944 /* Clear latched errors. So our interrupt deasserts. */ 945 ahd_outb(ahd, reg, pci_status[i]); 946 } 947 948 for (i = 0; i < 8; i++) { 949 u_int bit; 950 951 if (i == 5) 952 continue; 953 954 for (bit = 0; bit < 8; bit++) { 955 956 if ((pci_status[i] & (0x1 << bit)) != 0) { 957 static const char *s; 958 959 s = pci_status_strings[bit]; 960 if (i == 7/*TARG*/ && bit == 3) 961 s = "%s: Signaled Target Abort\n"; 962 printf(s, ahd_name(ahd), pci_status_source[i]); 963 } 964 } 965 } 966 pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 967 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG , pci_status1); 968 969 ahd_restore_modes(ahd, saved_modes); 970 ahd_outb(ahd, CLRINT, CLRPCIINT); 971 ahd_unpause(ahd); 972 973 return; 974 } 975 976 void 977 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 978 { 979 const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc; 980 const pcitag_t tag = ahd->dev_softc->pa_tag; 981 uint8_t split_status[4]; 982 uint8_t split_status1[4]; 983 uint8_t sg_split_status[2]; 984 uint8_t sg_split_status1[2]; 985 ahd_mode_state saved_modes; 986 u_int i; 987 pcireg_t pcix_status; 988 989 /* 990 * Check for splits in all modes. Modes 0 and 1 991 * additionally have SG engine splits to look at. 992 */ 993 pcix_status = pci_conf_read(pc, tag, ahd->pcix_off + 0x04); 994 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 995 ahd_name(ahd), pcix_status); 996 997 saved_modes = ahd_save_modes(ahd); 998 for (i = 0; i < 4; i++) { 999 ahd_set_modes(ahd, i, i); 1000 1001 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1002 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1003 /* Clear latched errors. So our interrupt deasserts. */ 1004 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1005 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1006 if (i > 1) 1007 continue; 1008 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1009 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1010 /* Clear latched errors. So our interrupt deasserts. */ 1011 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1012 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1013 } 1014 1015 for (i = 0; i < 4; i++) { 1016 u_int bit; 1017 1018 for (bit = 0; bit < 8; bit++) { 1019 1020 if ((split_status[i] & (0x1 << bit)) != 0) { 1021 static const char *s; 1022 1023 s = split_status_strings[bit]; 1024 printf(s, ahd_name(ahd), 1025 split_status_source[i]); 1026 } 1027 1028 if (i > 1) 1029 continue; 1030 1031 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1032 static const char *s; 1033 1034 s = split_status_strings[bit]; 1035 printf(s, ahd_name(ahd), "SG"); 1036 } 1037 } 1038 } 1039 /* 1040 * Clear PCI-X status bits. 1041 */ 1042 pci_conf_write(pc, tag, ahd->pcix_off + 0x04, pcix_status); 1043 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1044 ahd_restore_modes(ahd, saved_modes); 1045 } 1046 1047 int 1048 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1049 { 1050 1051 ahd->chip = AHD_AIC7901; 1052 ahd->features = AHD_AIC7901_FE; 1053 return (ahd_aic790X_setup(ahd, pa)); 1054 } 1055 1056 int 1057 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1058 { 1059 1060 ahd->chip = AHD_AIC7901A; 1061 ahd->features = AHD_AIC7901A_FE; 1062 return (ahd_aic790X_setup(ahd, pa)); 1063 } 1064 1065 int 1066 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1067 { 1068 ahd->chip = AHD_AIC7902; 1069 ahd->features = AHD_AIC7902_FE; 1070 return (ahd_aic790X_setup(ahd, pa)); 1071 } 1072 1073 int 1074 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1075 { 1076 u_int rev; 1077 1078 rev = PCI_REVISION(pa->pa_class); 1079 #ifdef AHD_DEBUG 1080 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1081 #endif 1082 if (rev < ID_AIC7902_PCI_REV_A4) { 1083 printf("%s: Unable to attach to unsupported chip revision %d\n", 1084 ahd_name(ahd), rev); 1085 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1086 return (ENXIO); 1087 } 1088 1089 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1090 if (rev < ID_AIC7902_PCI_REV_B0) { 1091 /* 1092 * Enable A series workarounds. 1093 */ 1094 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1095 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1096 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1097 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1098 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1099 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1100 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1101 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1102 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1103 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1104 | AHD_FAINT_LED_BUG; 1105 1106 /* 1107 * IO Cell parameter setup. 1108 */ 1109 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1110 1111 if ((ahd->flags & AHD_HP_BOARD) == 0) 1112 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1113 } else { 1114 pcireg_t devconfig1; 1115 1116 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1117 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1118 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG 1119 | AHD_BUSFREEREV_BUG; 1120 1121 /* 1122 * Some issues have been resolved in the 7901B. 1123 */ 1124 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1125 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1126 1127 /* 1128 * IO Cell parameter setup. 1129 */ 1130 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1131 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1132 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1133 1134 /* 1135 * Set the PREQDIS bit for H2B which disables some workaround 1136 * that doesn't work on regular PCI busses. 1137 * XXX - Find out exactly what this does from the hardware 1138 * folks! 1139 */ 1140 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1141 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1142 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1143 } 1144 1145 return (0); 1146 } 1147