1 /* $OpenBSD: ahd_pci.c,v 1.6 2004/08/23 18:36:10 marco Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Milos Urbanek, Kenneth R. Westerback & Marco Peereboom 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * Product specific probe and attach routines for: 32 * aic7901 and aic7902 SCSI controllers 33 * 34 * Copyright (c) 1994-2001 Justin T. Gibbs. 35 * Copyright (c) 2000-2002 Adaptec Inc. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions, and the following disclaimer, 43 * without modification. 44 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 45 * substantially similar to the "NO WARRANTY" disclaimer below 46 * ("Disclaimer") and any redistribution must be conditioned upon 47 * including a substantially similar Disclaimer requirement for further 48 * binary redistribution. 49 * 3. Neither the names of the above-listed copyright holders nor the names 50 * of any contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * Alternatively, this software may be distributed under the terms of the 54 * GNU General Public License ("GPL") version 2 as published by the Free 55 * Software Foundation. 56 * 57 * NO WARRANTY 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 59 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 60 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 61 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 62 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 64 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 65 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 66 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 67 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 68 * POSSIBILITY OF SUCH DAMAGES. 69 * 70 */ 71 72 #include <sys/cdefs.h> 73 /* 74 __FBSDID("$FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.18 2004/02/04 16:38:38 gibbs Exp $"); 75 */ 76 77 #include <dev/ic/aic79xx_openbsd.h> 78 #include <dev/ic/aic79xx_inline.h> 79 #include <dev/ic/aic79xx.h> 80 81 #include <dev/pci/pcivar.h> 82 83 __inline uint64_t ahd_compose_id(u_int, u_int, u_int, u_int); 84 __inline uint64_t 85 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 86 { 87 uint64_t id; 88 89 id = subvendor 90 | (subdevice << 16) 91 | ((uint64_t)vendor << 32) 92 | ((uint64_t)device << 48); 93 94 return (id); 95 } 96 97 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 98 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 99 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 100 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 101 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 102 103 #define ID_AIC7901 0x800F9005FFFF9005ull 104 #define ID_AHA_29320A 0x8000900500609005ull 105 #define ID_AHA_29320ALP 0x8017900500449005ull 106 107 #define ID_AIC7901A 0x801E9005FFFF9005ull 108 #define ID_AHA_29320LP 0x8014900500449005ull 109 110 #define ID_AIC7902 0x801F9005FFFF9005ull 111 #define ID_AIC7902_B 0x801D9005FFFF9005ull 112 #define ID_AHA_39320 0x8010900500409005ull 113 #define ID_AHA_29320 0x8012900500429005ull 114 #define ID_AHA_29320B 0x8013900500439005ull 115 #define ID_AHA_39320_B 0x8015900500409005ull 116 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 117 #define ID_AHA_39320A 0x8016900500409005ull 118 #define ID_AHA_39320D 0x8011900500419005ull 119 #define ID_AHA_39320D_B 0x801C900500419005ull 120 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 121 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 122 #define ID_AIC7902_PCI_REV_A4 0x3 123 #define ID_AIC7902_PCI_REV_B0 0x10 124 #define SUBID_HP 0x0E11 125 126 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 127 128 #define DEVID_9005_TYPE(id) ((id) & 0xF) 129 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 130 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 131 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 132 133 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 134 135 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 136 137 #define SUBID_9005_TYPE(id) ((id) & 0xF) 138 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 139 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 140 141 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 142 143 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 144 145 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 146 #define SUBID_9005_SEEPTYPE_NONE 0x0 147 #define SUBID_9005_SEEPTYPE_4K 0x1 148 149 ahd_device_setup_t ahd_aic7901_setup; 150 ahd_device_setup_t ahd_aic7901A_setup; 151 ahd_device_setup_t ahd_aic7902_setup; 152 ahd_device_setup_t ahd_aic790X_setup; 153 154 struct ahd_pci_identity ahd_pci_ident_table [] = 155 { 156 /* aic7901 based controllers */ 157 { 158 ID_AHA_29320A, 159 ID_ALL_MASK, 160 ahd_aic7901_setup 161 }, 162 { 163 ID_AHA_29320ALP, 164 ID_ALL_MASK, 165 ahd_aic7901_setup 166 }, 167 /* aic7901A based controllers */ 168 { 169 ID_AHA_29320LP, 170 ID_ALL_MASK, 171 ahd_aic7901A_setup 172 }, 173 /* aic7902 based controllers */ 174 { 175 ID_AHA_29320, 176 ID_ALL_MASK, 177 ahd_aic7902_setup 178 }, 179 { 180 ID_AHA_29320B, 181 ID_ALL_MASK, 182 ahd_aic7902_setup 183 }, 184 { 185 ID_AHA_39320, 186 ID_ALL_MASK, 187 ahd_aic7902_setup 188 }, 189 { 190 ID_AHA_39320_B, 191 ID_ALL_MASK, 192 ahd_aic7902_setup 193 }, 194 { 195 ID_AHA_39320_B_DELL, 196 ID_ALL_MASK, 197 ahd_aic7902_setup 198 }, 199 { 200 ID_AHA_39320A, 201 ID_ALL_MASK, 202 ahd_aic7902_setup 203 }, 204 { 205 ID_AHA_39320D, 206 ID_ALL_MASK, 207 ahd_aic7902_setup 208 }, 209 { 210 ID_AHA_39320D_HP, 211 ID_ALL_MASK, 212 ahd_aic7902_setup 213 }, 214 { 215 ID_AHA_39320D_B, 216 ID_ALL_MASK, 217 ahd_aic7902_setup 218 }, 219 { 220 ID_AHA_39320D_B_HP, 221 ID_ALL_MASK, 222 ahd_aic7902_setup 223 }, 224 /* Generic chip probes for devices we don't know 'exactly' */ 225 { 226 ID_AIC7901 & ID_9005_GENERIC_MASK, 227 ID_9005_GENERIC_MASK, 228 ahd_aic7901_setup 229 }, 230 { 231 ID_AIC7901A & ID_DEV_VENDOR_MASK, 232 ID_DEV_VENDOR_MASK, 233 ahd_aic7901A_setup 234 }, 235 { 236 ID_AIC7902 & ID_9005_GENERIC_MASK, 237 ID_9005_GENERIC_MASK, 238 ahd_aic7902_setup 239 } 240 }; 241 242 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 243 244 #define DEVCONFIG 0x40 245 #define PCIXINITPAT 0x0000E000ul 246 #define PCIXINIT_PCI33_66 0x0000E000ul 247 #define PCIXINIT_PCIX50_66 0x0000C000ul 248 #define PCIXINIT_PCIX66_100 0x0000A000ul 249 #define PCIXINIT_PCIX100_133 0x00008000ul 250 #define PCI_BUS_MODES_INDEX(devconfig) \ 251 (((devconfig) & PCIXINITPAT) >> 13) 252 253 static const char *pci_bus_modes[] = 254 { 255 "PCI bus mode unknown", 256 "PCI bus mode unknown", 257 "PCI bus mode unknown", 258 "PCI bus mode unknown", 259 "PCI-X 101-133Mhz", 260 "PCI-X 67-100Mhz", 261 "PCI-X 50-66Mhz", 262 "PCI 33 or 66Mhz" 263 }; 264 265 #define TESTMODE 0x00000800ul 266 #define IRDY_RST 0x00000200ul 267 #define FRAME_RST 0x00000100ul 268 #define PCI64BIT 0x00000080ul 269 #define MRDCEN 0x00000040ul 270 #define ENDIANSEL 0x00000020ul 271 #define MIXQWENDIANEN 0x00000008ul 272 #define DACEN 0x00000004ul 273 #define STPWLEVEL 0x00000002ul 274 #define QWENDIANSEL 0x00000001ul 275 276 #define DEVCONFIG1 0x44 277 #define PREQDIS 0x01 278 279 #define CSIZE_LATTIME 0x0c 280 #define CACHESIZE 0x000000fful 281 #define LATTIME 0x0000ff00ul 282 283 int ahd_pci_probe(struct device *, void *, void *); 284 void ahd_pci_attach(struct device *, struct device *, void *); 285 286 struct cfattach ahd_pci_ca = { 287 sizeof(struct ahd_softc), ahd_pci_probe, ahd_pci_attach 288 }; 289 290 int ahd_check_extport(struct ahd_softc *ahd); 291 void ahd_configure_termination(struct ahd_softc *ahd, 292 u_int adapter_control); 293 void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 294 295 const struct ahd_pci_identity * 296 ahd_find_pci_device(id, subid) 297 pcireg_t id, subid; 298 { 299 u_int64_t full_id; 300 const struct ahd_pci_identity *entry; 301 u_int i; 302 303 full_id = ahd_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 304 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 305 306 /* 307 * If we are configured to attach to HostRAID 308 * controllers, mask out the IROC/HostRAID bit 309 * in the 310 */ 311 if (ahd_attach_to_HostRAID_controllers) 312 full_id &= ID_ALL_IROC_MASK; 313 314 for (i = 0; i < ahd_num_pci_devs; i++) { 315 entry = &ahd_pci_ident_table[i]; 316 if (entry->full_id == (full_id & entry->id_mask)) { 317 return (entry); 318 } 319 } 320 return (NULL); 321 } 322 323 int 324 ahd_pci_probe(parent, match, aux) 325 struct device *parent; 326 void *match; 327 void *aux; 328 { 329 struct pci_attach_args *pa = aux; 330 const struct ahd_pci_identity *entry; 331 pcireg_t subid; 332 333 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 334 entry = ahd_find_pci_device(pa->pa_id, subid); 335 return entry != NULL ? 1 : 0; 336 } 337 338 void 339 ahd_pci_attach(parent, self, aux) 340 struct device *parent, *self; 341 void *aux; 342 { 343 struct pci_attach_args *pa = aux; 344 struct ahd_softc *ahd = (void *)self; 345 struct scb_data *shared_scb_data; 346 const struct ahd_pci_identity *entry; 347 int ioh_valid, ioh2_valid, memh_valid; 348 pcireg_t memtype; 349 int l; 350 u_int command; 351 uint32_t devconfig; 352 uint16_t device; 353 uint16_t subvendor; 354 pcireg_t subid; 355 int error; 356 pci_intr_handle_t ih; 357 const char *intrstr; 358 int pci_pwrmgmt_cap_reg, pci_pwrmgmt_csr_reg; 359 pcireg_t reg; 360 struct ahd_pci_busdata *bd; 361 362 shared_scb_data = NULL; 363 ahd->dev_softc = pa; 364 365 ahd_set_name(ahd, ahd->sc_dev.dv_xname); 366 ahd->parent_dmat = pa->pa_dmat; 367 368 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 369 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 370 entry = ahd_find_pci_device(pa->pa_id, subid); 371 if (entry == NULL) 372 return; 373 374 /* Keep information about the PCI bus */ 375 bd = malloc(sizeof (struct ahd_pci_busdata), M_DEVBUF, M_NOWAIT); 376 if (bd == NULL) { 377 printf("%s: unable to allocate bus-specific data\n", ahd_name(ahd)); 378 return; 379 } 380 memset(bd, 0, sizeof(struct ahd_pci_busdata)); 381 382 bd->pc = pa->pa_pc; 383 bd->tag = pa->pa_tag; 384 bd->func = pa->pa_function; 385 bd->dev = pa->pa_device; 386 bd->class = pa->pa_class; 387 388 ahd->bus_data = bd; 389 390 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 391 M_DEVBUF, M_NOWAIT); 392 if (ahd->seep_config == NULL) { 393 printf("%s: cannot malloc seep_config!\n", ahd_name(ahd)); 394 return; 395 } 396 memset(ahd->seep_config, 0, sizeof(*ahd->seep_config)); 397 398 LIST_INIT(&ahd->pending_scbs); 399 400 timeout_set(&ahd->reset_timer, ahd_reset_poll, ahd); 401 timeout_set(&ahd->stat_timer, ahd_stat_timer, ahd); 402 403 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 404 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 405 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 406 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 407 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 408 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 409 ahd->int_coalescing_stop_threshold = AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 410 411 if (ahd_platform_alloc(ahd, NULL) != 0) { 412 ahd_free(ahd); 413 return; 414 } 415 416 /* 417 * Record if this is a HostRAID board. 418 */ 419 device = PCI_PRODUCT(pa->pa_id); 420 if (DEVID_9005_HOSTRAID(device)) 421 ahd->flags |= AHD_HOSTRAID_BOARD; 422 423 /* 424 * Record if this is an HP board. 425 */ 426 subvendor = PCI_VENDOR(subid); 427 if (subvendor == SUBID_HP) 428 ahd->flags |= AHD_HP_BOARD; 429 430 error = entry->setup(ahd, pa); 431 if (error != 0) 432 return; 433 434 /* XXX ahc on sparc64 needs this twice */ 435 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 436 437 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 438 ahd->chip |= AHD_PCI; 439 /* Disable PCIX workarounds when running in PCI mode. */ 440 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 441 } else { 442 ahd->chip |= AHD_PCIX; 443 } 444 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 445 446 memh_valid = ioh_valid = ioh2_valid = 0; 447 448 if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIX, 449 &bd->pcix_off, NULL)) { 450 if (ahd->chip & AHD_PCIX) 451 printf("%s: warning: can't find PCI-X capability\n", ahd->sc_dev.dv_xname); 452 ahd->chip &= ~AHD_PCIX; 453 ahd->chip |= AHD_PCI; 454 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 455 } 456 457 /* 458 * Map PCI registers 459 */ 460 if ((ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0) { 461 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 462 AHD_PCI_MEMADDR); 463 switch (memtype) { 464 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 465 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 466 memh_valid = (pci_mapreg_map(pa, AHD_PCI_MEMADDR, 467 memtype, 0, &ahd->tags[0], 468 &ahd->bshs[0], 469 NULL, NULL, 0) == 0); 470 if (memh_valid) { 471 ahd->tags[1] = ahd->tags[0]; 472 bus_space_subregion(ahd->tags[0], ahd->bshs[0], 473 /*offset*/0x100, 474 /*size*/0x100, 475 &ahd->bshs[1]); 476 if (ahd_pci_test_register_access(ahd) != 0) 477 memh_valid = 0; 478 } 479 break; 480 default: 481 memh_valid = 0; 482 printf("%s: unknown memory type: 0x%x\n", 483 ahd_name(ahd), memtype); 484 break; 485 } 486 487 if (memh_valid) { 488 command &= ~PCI_COMMAND_IO_ENABLE; 489 pci_conf_write(pa->pa_pc, pa->pa_tag, 490 PCI_COMMAND_STATUS_REG, command); 491 } 492 #ifdef AHD_DEBUG 493 printf("%s: doing memory mapping tag0 0x%x, tag1 0x%x, " 494 "shs0 0x%lx, shs1 0x%lx\n", 495 ahd_name(ahd), ahd->tags[0], ahd->tags[1], 496 ahd->bshs[0], ahd->bshs[1]); 497 #endif 498 } 499 500 if (command & PCI_COMMAND_IO_ENABLE) { 501 /* First BAR */ 502 ioh_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR, 503 PCI_MAPREG_TYPE_IO, 0, 504 &ahd->tags[0], &ahd->bshs[0], 505 NULL, NULL, 0) == 0); 506 507 /* 2nd BAR */ 508 ioh2_valid = (pci_mapreg_map(pa, AHD_PCI_IOADDR1, 509 PCI_MAPREG_TYPE_IO, 0, 510 &ahd->tags[1], &ahd->bshs[1], 511 NULL, NULL, 0) == 0); 512 513 if (ioh_valid && ioh2_valid) { 514 KASSERT(memh_valid == 0); 515 command &= ~PCI_COMMAND_MEM_ENABLE; 516 pci_conf_write(pa->pa_pc, pa->pa_tag, 517 PCI_COMMAND_STATUS_REG, command); 518 } 519 #ifdef AHD_DEBUG 520 printf("%s: doing io mapping tag0 0x%x, tag1 0x%x, " 521 "shs0 0x%lx, shs1 0x%lx\n", ahd_name(ahd), ahd->tags[0], 522 ahd->tags[1], ahd->bshs[0], ahd->bshs[1]); 523 #endif 524 525 } 526 527 if (memh_valid == 0 && (ioh_valid == 0 || ioh2_valid == 0)) { 528 printf("%s: unable to map registers\n", ahd_name(ahd)); 529 return; 530 } 531 532 /* 533 * Set Power State D0. 534 */ 535 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, 536 &pci_pwrmgmt_cap_reg, 0)) { 537 538 pci_pwrmgmt_csr_reg = pci_pwrmgmt_cap_reg + 4; 539 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 540 pci_pwrmgmt_csr_reg); 541 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 542 pci_conf_write(pa->pa_pc, pa->pa_tag, pci_pwrmgmt_csr_reg, 543 (reg & ~PCI_PMCSR_STATE_MASK) | 544 PCI_PMCSR_STATE_D0); 545 } 546 } 547 548 /* 549 * Should we bother disabling 39Bit addressing 550 * based on installed memory? 551 * */ 552 if (sizeof(bus_addr_t) > 4) 553 ahd->flags |= AHD_39BIT_ADDRESSING; 554 555 /* 556 * If we need to support high memory, enable dual 557 * address cycles. This bit must be set to enable 558 * high address bit generation even if we are on a 559 * 64bit bus (PCI64BIT set in devconfig). 560 */ 561 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 562 uint32_t devconfig; 563 564 if (bootverbose) 565 printf("%s: Enabling 39Bit Addressing\n", 566 ahd_name(ahd)); 567 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 568 devconfig |= DACEN; 569 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 570 } 571 572 /* Ensure busmastering is enabled */ 573 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 574 command |= PCI_COMMAND_MASTER_ENABLE; 575 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 576 577 ahd_softc_init(ahd); 578 579 /* 580 * Map the interrupts routines 581 */ 582 ahd->bus_intr = ahd_pci_intr; 583 584 error = ahd_reset(ahd, /*reinit*/FALSE); 585 if (error != 0) { 586 ahd_free(ahd); 587 return; 588 } 589 590 if (pci_intr_map(pa, &ih)) { 591 printf("%s: couldn't map interrupt\n", ahd_name(ahd)); 592 ahd_free(ahd); 593 return; 594 } 595 intrstr = pci_intr_string(pa->pa_pc, ih); 596 ahd->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 597 ahd_platform_intr, ahd, ahd->sc_dev.dv_xname); 598 if (ahd->ih == NULL) { 599 printf("%s: couldn't establish interrupt", ahd_name(ahd)); 600 if (intrstr != NULL) 601 printf(" at %s", intrstr); 602 printf("\n"); 603 ahd_free(ahd); 604 return; 605 } 606 if (intrstr != NULL) 607 printf(": %s\n", intrstr); 608 609 /* Get the size of the cache */ 610 ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 611 ahd->pci_cachesize *= 4; 612 613 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 614 /* See if we have a SEEPROM and perform auto-term */ 615 error = ahd_check_extport(ahd); 616 if (error != 0) 617 return; 618 619 /* Core initialization */ 620 error = ahd_init(ahd); 621 if (error != 0) 622 return; 623 624 ahd_list_lock(&l); 625 /* 626 * Link this softc in with all other ahd instances. 627 */ 628 ahd_softc_insert(ahd); 629 ahd_list_unlock(&l); 630 631 /* complete the attach */ 632 ahd_attach(ahd); 633 } 634 635 /* 636 * Perform some simple tests that should catch situations where 637 * our registers are invalidly mapped. 638 */ 639 int 640 ahd_pci_test_register_access(struct ahd_softc *ahd) 641 { 642 uint32_t cmd; 643 struct ahd_pci_busdata *bd = ahd->bus_data; 644 u_int targpcistat; 645 u_int pci_status1; 646 int error; 647 uint8_t hcntrl; 648 649 error = EIO; 650 651 /* 652 * Enable PCI error interrupt status, but suppress NMIs 653 * generated by SERR raised due to target aborts. 654 */ 655 cmd = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 656 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 657 cmd & ~PCI_COMMAND_SERR_ENABLE); 658 659 /* 660 * First a simple test to see if any 661 * registers can be read. Reading 662 * HCNTRL has no side effects and has 663 * at least one bit that is guaranteed to 664 * be zero so it is a good register to 665 * use for this test. 666 */ 667 hcntrl = ahd_inb(ahd, HCNTRL); 668 if (hcntrl == 0xFF) 669 goto fail; 670 671 /* 672 * Next create a situation where write combining 673 * or read prefetching could be initiated by the 674 * CPU or host bridge. Our device does not support 675 * either, so look for data corruption and/or flaged 676 * PCI errors. First pause without causing another 677 * chip reset. 678 */ 679 hcntrl &= ~CHIPRST; 680 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 681 while (ahd_is_paused(ahd) == 0) 682 ; 683 684 /* Clear any PCI errors that occurred before our driver attached. */ 685 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 686 targpcistat = ahd_inb(ahd, TARGPCISTAT); 687 ahd_outb(ahd, TARGPCISTAT, targpcistat); 688 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 689 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, pci_status1); 690 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 691 ahd_outb(ahd, CLRINT, CLRPCIINT); 692 693 ahd_outb(ahd, SEQCTL0, PERRORDIS); 694 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 695 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 696 goto fail; 697 698 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 699 u_int targpcistat; 700 701 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 702 targpcistat = ahd_inb(ahd, TARGPCISTAT); 703 if ((targpcistat & STA) != 0) 704 goto fail; 705 } 706 707 error = 0; 708 709 fail: 710 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 711 712 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 713 targpcistat = ahd_inb(ahd, TARGPCISTAT); 714 715 /* Silently clear any latched errors. */ 716 ahd_outb(ahd, TARGPCISTAT, targpcistat); 717 pci_status1 = pci_conf_read(bd->pc, bd->tag, 718 PCI_COMMAND_STATUS_REG); 719 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, 720 pci_status1); 721 ahd_outb(ahd, CLRINT, CLRPCIINT); 722 } 723 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 724 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG, cmd); 725 return (error); 726 } 727 728 /* 729 * Check the external port logic for a serial eeprom 730 * and termination/cable detection contrls. 731 */ 732 int 733 ahd_check_extport(struct ahd_softc *ahd) 734 { 735 struct vpd_config vpd; 736 struct seeprom_config *sc; 737 u_int adapter_control; 738 int have_seeprom; 739 int error; 740 741 sc = ahd->seep_config; 742 have_seeprom = ahd_acquire_seeprom(ahd); 743 if (have_seeprom) { 744 u_int start_addr; 745 746 /* 747 * Fetch VPD for this function and parse it. 748 */ 749 if (bootverbose) 750 printf("%s: Reading VPD from SEEPROM...", 751 ahd_name(ahd)); 752 753 /* Address is always in units of 16bit words */ 754 start_addr = ((2 * sizeof(*sc)) 755 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 756 757 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 758 start_addr, sizeof(vpd)/2, 759 /*bytestream*/TRUE); 760 if (error == 0) 761 error = ahd_parse_vpddata(ahd, &vpd); 762 if (bootverbose) 763 printf("%s: VPD parsing %s\n", 764 ahd_name(ahd), 765 error == 0 ? "successful" : "failed"); 766 767 if (bootverbose) 768 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 769 770 /* Address is always in units of 16bit words */ 771 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 772 773 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 774 start_addr, sizeof(*sc)/2, 775 /*bytestream*/FALSE); 776 777 if (error != 0) { 778 printf("Unable to read SEEPROM\n"); 779 have_seeprom = 0; 780 } else { 781 have_seeprom = ahd_verify_cksum(sc); 782 783 if (bootverbose) { 784 if (have_seeprom == 0) 785 printf ("checksum error\n"); 786 else 787 printf ("done.\n"); 788 } 789 } 790 ahd_release_seeprom(ahd); 791 } 792 793 if (!have_seeprom) { 794 u_int nvram_scb; 795 796 /* 797 * Pull scratch ram settings and treat them as 798 * if they are the contents of an seeprom if 799 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 800 * in SCB 0xFF. We manually compose the data as 16bit 801 * values to avoid endian issues. 802 */ 803 ahd_set_scbptr(ahd, 0xFF); 804 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 805 if (nvram_scb != 0xFF 806 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 807 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 808 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 809 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 810 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 811 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 812 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 813 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 814 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 815 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 816 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 817 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 818 uint16_t *sc_data; 819 int i; 820 821 ahd_set_scbptr(ahd, nvram_scb); 822 sc_data = (uint16_t *)sc; 823 for (i = 0; i < 64; i += 2) 824 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 825 have_seeprom = ahd_verify_cksum(sc); 826 if (have_seeprom) 827 ahd->flags |= AHD_SCB_CONFIG_USED; 828 } 829 } 830 831 #ifdef AHD_DEBUG 832 if (have_seeprom != 0 833 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 834 uint16_t *sc_data; 835 int i; 836 837 printf("%s: Seeprom Contents:", ahd_name(ahd)); 838 sc_data = (uint16_t *)sc; 839 for (i = 0; i < (sizeof(*sc)); i += 2) 840 printf("\n\t0x%.4x", sc_data[i]); 841 printf("\n"); 842 } 843 #endif 844 845 if (!have_seeprom) { 846 if (bootverbose) 847 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 848 ahd->flags |= AHD_USEDEFAULTS; 849 error = ahd_default_config(ahd); 850 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 851 free(ahd->seep_config, M_DEVBUF); 852 ahd->seep_config = NULL; 853 } else { 854 error = ahd_parse_cfgdata(ahd, sc); 855 adapter_control = sc->adapter_control; 856 } 857 if (error != 0) 858 return (error); 859 860 ahd_configure_termination(ahd, adapter_control); 861 862 return (0); 863 } 864 865 void 866 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 867 { 868 int error; 869 u_int sxfrctl1; 870 uint8_t termctl; 871 uint32_t devconfig; 872 struct ahd_pci_busdata *bd = ahd->bus_data; 873 874 devconfig = pci_conf_read(bd->pc, bd->tag, DEVCONFIG); 875 devconfig &= ~STPWLEVEL; 876 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 877 devconfig |= STPWLEVEL; 878 if (bootverbose) 879 printf("%s: STPWLEVEL is %s\n", 880 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 881 pci_conf_write(bd->pc, bd->tag, DEVCONFIG, devconfig); 882 883 /* Make sure current sensing is off. */ 884 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 885 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 886 } 887 888 /* 889 * Read to sense. Write to set. 890 */ 891 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 892 if ((adapter_control & CFAUTOTERM) == 0) { 893 if (bootverbose) 894 printf("%s: Manual Primary Termination\n", 895 ahd_name(ahd)); 896 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 897 if ((adapter_control & CFSTERM) != 0) 898 termctl |= FLX_TERMCTL_ENPRILOW; 899 if ((adapter_control & CFWSTERM) != 0) 900 termctl |= FLX_TERMCTL_ENPRIHIGH; 901 } else if (error != 0) { 902 printf("%s: Primary Auto-Term Sensing failed! " 903 "Using Defaults.\n", ahd_name(ahd)); 904 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 905 } 906 907 if ((adapter_control & CFSEAUTOTERM) == 0) { 908 if (bootverbose) 909 printf("%s: Manual Secondary Termination\n", 910 ahd_name(ahd)); 911 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 912 if ((adapter_control & CFSELOWTERM) != 0) 913 termctl |= FLX_TERMCTL_ENSECLOW; 914 if ((adapter_control & CFSEHIGHTERM) != 0) 915 termctl |= FLX_TERMCTL_ENSECHIGH; 916 } else if (error != 0) { 917 printf("%s: Secondary Auto-Term Sensing failed! " 918 "Using Defaults.\n", ahd_name(ahd)); 919 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 920 } 921 922 /* 923 * Now set the termination based on what we found. 924 */ 925 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 926 ahd->flags &= ~AHD_TERM_ENB_A; 927 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 928 ahd->flags |= AHD_TERM_ENB_A; 929 sxfrctl1 |= STPWEN; 930 } 931 /* Must set the latch once in order to be effective. */ 932 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 933 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 934 935 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 936 if (error != 0) { 937 printf("%s: Unable to set termination settings!\n", 938 ahd_name(ahd)); 939 } else if (bootverbose) { 940 printf("%s: Primary High byte termination %sabled\n", 941 ahd_name(ahd), 942 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 943 944 printf("%s: Primary Low byte termination %sabled\n", 945 ahd_name(ahd), 946 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 947 948 printf("%s: Secondary High byte termination %sabled\n", 949 ahd_name(ahd), 950 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 951 952 printf("%s: Secondary Low byte termination %sabled\n", 953 ahd_name(ahd), 954 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 955 } 956 return; 957 } 958 959 #define DPE 0x80 960 #define SSE 0x40 961 #define RMA 0x20 962 #define RTA 0x10 963 #define STA 0x08 964 #define DPR 0x01 965 966 static const char *split_status_source[] = 967 { 968 "DFF0", 969 "DFF1", 970 "OVLY", 971 "CMC", 972 }; 973 974 static const char *pci_status_source[] = 975 { 976 "DFF0", 977 "DFF1", 978 "SG", 979 "CMC", 980 "OVLY", 981 "NONE", 982 "MSI", 983 "TARG" 984 }; 985 986 static const char *split_status_strings[] = 987 { 988 "%s: Received split response in %s.\n", 989 "%s: Received split completion error message in %s\n", 990 "%s: Receive overrun in %s\n", 991 "%s: Count not complete in %s\n", 992 "%s: Split completion data bucket in %s\n", 993 "%s: Split completion address error in %s\n", 994 "%s: Split completion byte count error in %s\n", 995 "%s: Signaled Target-abort to early terminate a split in %s\n" 996 }; 997 998 static const char *pci_status_strings[] = 999 { 1000 "%s: Data Parity Error has been reported via PERR# in %s\n", 1001 "%s: Target initial wait state error in %s\n", 1002 "%s: Split completion read data parity error in %s\n", 1003 "%s: Split completion address attribute parity error in %s\n", 1004 "%s: Received a Target Abort in %s\n", 1005 "%s: Received a Master Abort in %s\n", 1006 "%s: Signal System Error Detected in %s\n", 1007 "%s: Address or Write Phase Parity Error Detected in %s.\n" 1008 }; 1009 1010 void 1011 ahd_pci_intr(struct ahd_softc *ahd) 1012 { 1013 uint8_t pci_status[8]; 1014 ahd_mode_state saved_modes; 1015 u_int pci_status1; 1016 u_int intstat; 1017 u_int i; 1018 u_int reg; 1019 struct ahd_pci_busdata *bd = ahd->bus_data; 1020 1021 intstat = ahd_inb(ahd, INTSTAT); 1022 1023 if ((intstat & SPLTINT) != 0) 1024 ahd_pci_split_intr(ahd, intstat); 1025 1026 if ((intstat & PCIINT) == 0) 1027 return; 1028 1029 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 1030 saved_modes = ahd_save_modes(ahd); 1031 ahd_dump_card_state(ahd); 1032 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1033 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 1034 1035 if (i == 5) 1036 continue; 1037 pci_status[i] = ahd_inb(ahd, reg); 1038 /* Clear latched errors. So our interrupt deasserts. */ 1039 ahd_outb(ahd, reg, pci_status[i]); 1040 } 1041 1042 for (i = 0; i < 8; i++) { 1043 u_int bit; 1044 1045 if (i == 5) 1046 continue; 1047 1048 for (bit = 0; bit < 8; bit++) { 1049 1050 if ((pci_status[i] & (0x1 << bit)) != 0) { 1051 static const char *s; 1052 1053 s = pci_status_strings[bit]; 1054 if (i == 7/*TARG*/ && bit == 3) 1055 s = "%s: Signaled Target Abort\n"; 1056 printf(s, ahd_name(ahd), pci_status_source[i]); 1057 } 1058 } 1059 } 1060 pci_status1 = pci_conf_read(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG); 1061 pci_conf_write(bd->pc, bd->tag, PCI_COMMAND_STATUS_REG , pci_status1); 1062 1063 ahd_restore_modes(ahd, saved_modes); 1064 ahd_outb(ahd, CLRINT, CLRPCIINT); 1065 ahd_unpause(ahd); 1066 1067 return; 1068 } 1069 1070 void 1071 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 1072 { 1073 uint8_t split_status[4]; 1074 uint8_t split_status1[4]; 1075 uint8_t sg_split_status[2]; 1076 uint8_t sg_split_status1[2]; 1077 ahd_mode_state saved_modes; 1078 u_int i; 1079 uint16_t pcix_status; 1080 struct ahd_pci_busdata *bd = ahd->bus_data; 1081 1082 /* 1083 * Check for splits in all modes. Modes 0 and 1 1084 * additionally have SG engine splits to look at. 1085 */ 1086 pcix_status = pci_conf_read(bd->pc, bd->tag, 1087 bd->pcix_off + 0x04); 1088 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 1089 ahd_name(ahd), pcix_status); 1090 1091 saved_modes = ahd_save_modes(ahd); 1092 for (i = 0; i < 4; i++) { 1093 ahd_set_modes(ahd, i, i); 1094 1095 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 1096 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 1097 /* Clear latched errors. So our interrupt deasserts. */ 1098 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 1099 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 1100 if (i > 1) 1101 continue; 1102 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 1103 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 1104 /* Clear latched errors. So our interrupt deasserts. */ 1105 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 1106 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 1107 } 1108 1109 for (i = 0; i < 4; i++) { 1110 u_int bit; 1111 1112 for (bit = 0; bit < 8; bit++) { 1113 1114 if ((split_status[i] & (0x1 << bit)) != 0) { 1115 static const char *s; 1116 1117 s = split_status_strings[bit]; 1118 printf(s, ahd_name(ahd), 1119 split_status_source[i]); 1120 } 1121 1122 if (i > 1) 1123 continue; 1124 1125 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 1126 static const char *s; 1127 1128 s = split_status_strings[bit]; 1129 printf(s, ahd_name(ahd), "SG"); 1130 } 1131 } 1132 } 1133 /* 1134 * Clear PCI-X status bits. 1135 */ 1136 pci_conf_write(bd->pc, bd->tag, bd->pcix_off + 0x04, 1137 pcix_status); 1138 ahd_outb(ahd, CLRINT, CLRSPLTINT); 1139 ahd_restore_modes(ahd, saved_modes); 1140 } 1141 1142 int 1143 ahd_aic7901_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1144 { 1145 1146 ahd->chip = AHD_AIC7901; 1147 ahd->features = AHD_AIC7901_FE; 1148 return (ahd_aic790X_setup(ahd, pa)); 1149 } 1150 1151 int 1152 ahd_aic7901A_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1153 { 1154 1155 ahd->chip = AHD_AIC7901A; 1156 ahd->features = AHD_AIC7901A_FE; 1157 return (ahd_aic790X_setup(ahd, pa)); 1158 } 1159 1160 int 1161 ahd_aic7902_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1162 { 1163 ahd->chip = AHD_AIC7902; 1164 ahd->features = AHD_AIC7902_FE; 1165 return (ahd_aic790X_setup(ahd, pa)); 1166 } 1167 1168 int 1169 ahd_aic790X_setup(struct ahd_softc *ahd, struct pci_attach_args *pa) 1170 { 1171 u_int rev; 1172 1173 rev = PCI_REVISION(pa->pa_class); 1174 #ifdef AHD_DEBUG 1175 printf("\n%s: aic7902 chip revision 0x%x\n", ahd_name(ahd), rev); 1176 #endif 1177 if (rev < ID_AIC7902_PCI_REV_A4) { 1178 printf("%s: Unable to attach to unsupported chip revision %d\n", 1179 ahd_name(ahd), rev); 1180 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 0); 1181 return (ENXIO); 1182 } 1183 1184 ahd->channel = (pa->pa_function == 1) ? 'B' : 'A'; 1185 if (rev < ID_AIC7902_PCI_REV_B0) { 1186 /* 1187 * Enable A series workarounds. 1188 */ 1189 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 1190 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1191 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1192 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1193 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1194 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1195 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1196 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1197 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1198 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1199 | AHD_FAINT_LED_BUG; 1200 1201 /* 1202 * IO Cell paramter setup. 1203 */ 1204 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1205 1206 if ((ahd->flags & AHD_HP_BOARD) == 0) 1207 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1208 } else { 1209 u_int devconfig1; 1210 1211 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1212 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1213 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1214 1215 /* 1216 * Some issues have been resolved in the 7901B. 1217 */ 1218 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1219 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1220 1221 /* 1222 * IO Cell paramter setup. 1223 */ 1224 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1225 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1226 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1227 1228 /* 1229 * Set the PREQDIS bit for H2B which disables some workaround 1230 * that doesn't work on regular PCI busses. 1231 * XXX - Find out exactly what this does from the hardware 1232 * folks! 1233 */ 1234 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1235 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG1, devconfig1|PREQDIS); 1236 devconfig1 = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG1); 1237 } 1238 1239 return (0); 1240 } 1241