1 /* $OpenBSD: ahc_pci.c,v 1.43 2004/01/05 01:09:18 krw Exp $ */ 2 /* 3 * Product specific probe and attach routines for: 4 * 3940, 2940, aic7895, aic7890, aic7880, 5 * aic7870, aic7860 and aic7850 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2001 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * $Id: ahc_pci.c,v 1.43 2004/01/05 01:09:18 krw Exp $ 44 * 45 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 46 * 47 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 48 */ 49 /* 50 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 51 */ 52 53 #include <sys/cdefs.h> 54 /* __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.43 2003/08/18 09:16:22 taca Exp $"); */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 #include <sys/reboot.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 71 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 72 73 #include <dev/ic/aic7xxx_openbsd.h> 74 #include <dev/ic/aic7xxx_inline.h> 75 76 #include <dev/ic/smc93cx6var.h> 77 78 79 static __inline uint64_t 80 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 81 { 82 uint64_t id; 83 84 id = subvendor 85 | (subdevice << 16) 86 | ((uint64_t)vendor << 32) 87 | ((uint64_t)device << 48); 88 89 return (id); 90 } 91 92 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 93 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 94 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 95 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 96 #define ID_9005_SISL_ID 0x0005900500000000ull 97 #define ID_AIC7850 0x5078900400000000ull 98 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 99 #define ID_AIC7855 0x5578900400000000ull 100 #define ID_AIC7859 0x3860900400000000ull 101 #define ID_AHA_2930CU 0x3860900438699004ull 102 #define ID_AIC7860 0x6078900400000000ull 103 #define ID_AIC7860C 0x6078900478609004ull 104 #define ID_AHA_1480A 0x6075900400000000ull 105 #define ID_AHA_2940AU_0 0x6178900400000000ull 106 #define ID_AHA_2940AU_1 0x6178900478619004ull 107 #define ID_AHA_2940AU_CN 0x2178900478219004ull 108 #define ID_AHA_2930C_VAR 0x6038900438689004ull 109 110 #define ID_AIC7870 0x7078900400000000ull 111 #define ID_AHA_2940 0x7178900400000000ull 112 #define ID_AHA_3940 0x7278900400000000ull 113 #define ID_AHA_398X 0x7378900400000000ull 114 #define ID_AHA_2944 0x7478900400000000ull 115 #define ID_AHA_3944 0x7578900400000000ull 116 #define ID_AHA_4944 0x7678900400000000ull 117 118 #define ID_AIC7880 0x8078900400000000ull 119 #define ID_AIC7880_B 0x8078900478809004ull 120 #define ID_AHA_2940U 0x8178900400000000ull 121 #define ID_AHA_3940U 0x8278900400000000ull 122 #define ID_AHA_2944U 0x8478900400000000ull 123 #define ID_AHA_3944U 0x8578900400000000ull 124 #define ID_AHA_398XU 0x8378900400000000ull 125 #define ID_AHA_4944U 0x8678900400000000ull 126 #define ID_AHA_2940UB 0x8178900478819004ull 127 #define ID_AHA_2930U 0x8878900478889004ull 128 #define ID_AHA_2940U_PRO 0x8778900478879004ull 129 #define ID_AHA_2940U_CN 0x0078900478009004ull 130 131 #define ID_AIC7895 0x7895900478959004ull 132 #define ID_AIC7895_ARO 0x7890900478939004ull 133 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 134 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 135 #define ID_AHA_3940AU 0x7895900478929004ull 136 #define ID_AHA_3944AU 0x7895900478949004ull 137 138 #define ID_AIC7890 0x001F9005000F9005ull 139 #define ID_AIC7890_ARO 0x00139005000F9005ull 140 #define ID_AAA_131U2 0x0013900500039005ull 141 #define ID_AHA_2930U2 0x0011900501819005ull 142 #define ID_AHA_2940U2B 0x00109005A1009005ull 143 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 144 #define ID_AHA_2940U2 0x00109005A1809005ull 145 #define ID_AHA_2950U2B 0x00109005E1009005ull 146 147 #define ID_AIC7892 0x008F9005FFFF9005ull 148 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 149 #define ID_AHA_2915LP 0x0082900502109005ull 150 #define ID_AHA_29160 0x00809005E2A09005ull 151 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 152 #define ID_AHA_29160N 0x0080900562A09005ull 153 #define ID_AHA_29160C 0x0080900562209005ull 154 #define ID_AHA_29160B 0x00809005E2209005ull 155 #define ID_AHA_19160B 0x0081900562A19005ull 156 157 #define ID_AIC7896 0x005F9005FFFF9005ull 158 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 159 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 160 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 161 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 162 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 163 164 #define ID_AIC7899 0x00CF9005FFFF9005ull 165 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 166 #define ID_AHA_3960D 0x00C09005F6209005ull 167 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 168 169 #define ID_AIC7810 0x1078900400000000ull 170 #define ID_AIC7815 0x7815900400000000ull 171 172 #define DEVID_9005_TYPE(id) ((id) & 0xF) 173 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 174 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 175 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 176 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 177 178 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 179 #define DEVID_9005_MAXRATE_U160 0x0 180 #define DEVID_9005_MAXRATE_ULTRA2 0x1 181 #define DEVID_9005_MAXRATE_ULTRA 0x2 182 #define DEVID_9005_MAXRATE_FAST 0x3 183 184 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 185 186 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 187 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 188 189 #define SUBID_9005_TYPE(id) ((id) & 0xF) 190 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 191 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 192 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 193 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 194 195 #define SUBID_9005_TYPE_KNOWN(id) \ 196 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 197 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 198 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 199 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 200 201 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 202 #define SUBID_9005_MAXRATE_ULTRA2 0x0 203 #define SUBID_9005_MAXRATE_ULTRA 0x1 204 #define SUBID_9005_MAXRATE_U160 0x2 205 #define SUBID_9005_MAXRATE_RESERVED 0x3 206 207 #define SUBID_9005_SEEPTYPE(id) \ 208 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 209 ? ((id) & 0xC0) >> 6 \ 210 : ((id) & 0x300) >> 8) 211 #define SUBID_9005_SEEPTYPE_NONE 0x0 212 #define SUBID_9005_SEEPTYPE_1K 0x1 213 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 214 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 215 #define SUBID_9005_AUTOTERM(id) \ 216 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 217 ? (((id) & 0x400) >> 10) == 0 \ 218 : (((id) & 0x40) >> 6) == 0) 219 220 #define SUBID_9005_NUMCHAN(id) \ 221 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 222 ? ((id) & 0x300) >> 8 \ 223 : ((id) & 0xC00) >> 10) 224 225 #define SUBID_9005_LEGACYCONN(id) \ 226 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 227 ? 0 \ 228 : ((id) & 0x80) >> 7) 229 230 #define SUBID_9005_MFUNCENB(id) \ 231 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 232 ? ((id) & 0x800) >> 11 \ 233 : ((id) & 0x1000) >> 12) 234 /* 235 * Informational only. Should use chip register to be 236 * certain, but may be use in identification strings. 237 */ 238 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 239 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 240 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 241 242 static ahc_device_setup_t ahc_aic785X_setup; 243 static ahc_device_setup_t ahc_aic7860_setup; 244 static ahc_device_setup_t ahc_apa1480_setup; 245 static ahc_device_setup_t ahc_aic7870_setup; 246 static ahc_device_setup_t ahc_aha394X_setup; 247 static ahc_device_setup_t ahc_aha494X_setup; 248 static ahc_device_setup_t ahc_aha398X_setup; 249 static ahc_device_setup_t ahc_aic7880_setup; 250 static ahc_device_setup_t ahc_aha2940Pro_setup; 251 static ahc_device_setup_t ahc_aha394XU_setup; 252 static ahc_device_setup_t ahc_aha398XU_setup; 253 static ahc_device_setup_t ahc_aic7890_setup; 254 static ahc_device_setup_t ahc_aic7892_setup; 255 static ahc_device_setup_t ahc_aic7895_setup; 256 static ahc_device_setup_t ahc_aic7896_setup; 257 static ahc_device_setup_t ahc_aic7899_setup; 258 static ahc_device_setup_t ahc_aha29160C_setup; 259 static ahc_device_setup_t ahc_raid_setup; 260 static ahc_device_setup_t ahc_aha394XX_setup; 261 static ahc_device_setup_t ahc_aha494XX_setup; 262 static ahc_device_setup_t ahc_aha398XX_setup; 263 264 struct ahc_pci_identity ahc_pci_ident_table [] = 265 { 266 /* aic7850 based controllers */ 267 { 268 ID_AHA_2902_04_10_15_20_30C, 269 ID_ALL_MASK, 270 ahc_aic785X_setup 271 }, 272 /* aic7860 based controllers */ 273 { 274 ID_AHA_2930CU, 275 ID_ALL_MASK, 276 ahc_aic7860_setup 277 }, 278 { 279 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 280 ID_DEV_VENDOR_MASK, 281 ahc_apa1480_setup 282 }, 283 { 284 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 285 ID_DEV_VENDOR_MASK, 286 ahc_aic7860_setup 287 }, 288 { 289 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 290 ID_DEV_VENDOR_MASK, 291 ahc_aic7860_setup 292 }, 293 { 294 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 295 ID_DEV_VENDOR_MASK, 296 ahc_aic7860_setup 297 }, 298 /* aic7870 based controllers */ 299 { 300 ID_AHA_2940, 301 ID_ALL_MASK, 302 ahc_aic7870_setup 303 }, 304 { 305 ID_AHA_3940, 306 ID_ALL_MASK, 307 ahc_aha394X_setup 308 }, 309 { 310 ID_AHA_398X, 311 ID_ALL_MASK, 312 ahc_aha398X_setup 313 }, 314 { 315 ID_AHA_2944, 316 ID_ALL_MASK, 317 ahc_aic7870_setup 318 }, 319 { 320 ID_AHA_3944, 321 ID_ALL_MASK, 322 ahc_aha394X_setup 323 }, 324 { 325 ID_AHA_4944, 326 ID_ALL_MASK, 327 ahc_aha494X_setup 328 }, 329 /* aic7880 based controllers */ 330 { 331 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 332 ID_DEV_VENDOR_MASK, 333 ahc_aic7880_setup 334 }, 335 { 336 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 337 ID_DEV_VENDOR_MASK, 338 ahc_aha394XU_setup 339 }, 340 { 341 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 342 ID_DEV_VENDOR_MASK, 343 ahc_aic7880_setup 344 }, 345 { 346 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 347 ID_DEV_VENDOR_MASK, 348 ahc_aha394XU_setup 349 }, 350 { 351 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 352 ID_DEV_VENDOR_MASK, 353 ahc_aha398XU_setup 354 }, 355 { 356 /* 357 * XXX Don't know the slot numbers 358 * so we can't identify channels 359 */ 360 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 361 ID_DEV_VENDOR_MASK, 362 ahc_aic7880_setup 363 }, 364 { 365 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 366 ID_DEV_VENDOR_MASK, 367 ahc_aic7880_setup 368 }, 369 { 370 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 371 ID_DEV_VENDOR_MASK, 372 ahc_aha2940Pro_setup 373 }, 374 { 375 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 ahc_aic7880_setup 378 }, 379 /* Ignore all SISL (AAC on MB) based controllers. */ 380 { 381 ID_9005_SISL_ID, 382 ID_9005_SISL_MASK, 383 NULL 384 }, 385 /* aic7890 based controllers */ 386 { 387 ID_AHA_2930U2, 388 ID_ALL_MASK, 389 ahc_aic7890_setup 390 }, 391 { 392 ID_AHA_2940U2B, 393 ID_ALL_MASK, 394 ahc_aic7890_setup 395 }, 396 { 397 ID_AHA_2940U2_OEM, 398 ID_ALL_MASK, 399 ahc_aic7890_setup 400 }, 401 { 402 ID_AHA_2940U2, 403 ID_ALL_MASK, 404 ahc_aic7890_setup 405 }, 406 { 407 ID_AHA_2950U2B, 408 ID_ALL_MASK, 409 ahc_aic7890_setup 410 }, 411 { 412 ID_AIC7890_ARO, 413 ID_ALL_MASK, 414 ahc_aic7890_setup 415 }, 416 { 417 ID_AAA_131U2, 418 ID_ALL_MASK, 419 ahc_aic7890_setup 420 }, 421 /* aic7892 based controllers */ 422 { 423 ID_AHA_29160, 424 ID_ALL_MASK, 425 ahc_aic7892_setup 426 }, 427 { 428 ID_AHA_29160_CPQ, 429 ID_ALL_MASK, 430 ahc_aic7892_setup 431 }, 432 { 433 ID_AHA_29160N, 434 ID_ALL_MASK, 435 ahc_aic7892_setup 436 }, 437 { 438 ID_AHA_29160C, 439 ID_ALL_MASK, 440 ahc_aha29160C_setup 441 }, 442 { 443 ID_AHA_29160B, 444 ID_ALL_MASK, 445 ahc_aic7892_setup 446 }, 447 { 448 ID_AHA_19160B, 449 ID_ALL_MASK, 450 ahc_aic7892_setup 451 }, 452 { 453 ID_AIC7892_ARO, 454 ID_ALL_MASK, 455 ahc_aic7892_setup 456 }, 457 { 458 ID_AHA_2915LP, 459 ID_ALL_MASK, 460 ahc_aic7892_setup 461 }, 462 /* aic7895 based controllers */ 463 { 464 ID_AHA_2940U_DUAL, 465 ID_ALL_MASK, 466 ahc_aic7895_setup 467 }, 468 { 469 ID_AHA_3940AU, 470 ID_ALL_MASK, 471 ahc_aic7895_setup 472 }, 473 { 474 ID_AHA_3944AU, 475 ID_ALL_MASK, 476 ahc_aic7895_setup 477 }, 478 { 479 ID_AIC7895_ARO, 480 ID_AIC7895_ARO_MASK, 481 ahc_aic7895_setup 482 }, 483 /* aic7896/97 based controllers */ 484 { 485 ID_AHA_3950U2B_0, 486 ID_ALL_MASK, 487 ahc_aic7896_setup 488 }, 489 { 490 ID_AHA_3950U2B_1, 491 ID_ALL_MASK, 492 ahc_aic7896_setup 493 }, 494 { 495 ID_AHA_3950U2D_0, 496 ID_ALL_MASK, 497 ahc_aic7896_setup 498 }, 499 { 500 ID_AHA_3950U2D_1, 501 ID_ALL_MASK, 502 ahc_aic7896_setup 503 }, 504 { 505 ID_AIC7896_ARO, 506 ID_ALL_MASK, 507 ahc_aic7896_setup 508 }, 509 /* aic7899 based controllers */ 510 { 511 ID_AHA_3960D, 512 ID_ALL_MASK, 513 ahc_aic7899_setup 514 }, 515 { 516 ID_AHA_3960D_CPQ, 517 ID_ALL_MASK, 518 ahc_aic7899_setup 519 }, 520 { 521 ID_AIC7899_ARO, 522 ID_ALL_MASK, 523 ahc_aic7899_setup 524 }, 525 /* Generic chip probes for devices we don't know 'exactly' */ 526 { 527 ID_AIC7850 & ID_DEV_VENDOR_MASK, 528 ID_DEV_VENDOR_MASK, 529 ahc_aic785X_setup 530 }, 531 { 532 ID_AIC7855 & ID_DEV_VENDOR_MASK, 533 ID_DEV_VENDOR_MASK, 534 ahc_aic785X_setup 535 }, 536 { 537 ID_AIC7859 & ID_DEV_VENDOR_MASK, 538 ID_DEV_VENDOR_MASK, 539 ahc_aic7860_setup 540 }, 541 { 542 ID_AIC7860 & ID_DEV_VENDOR_MASK, 543 ID_DEV_VENDOR_MASK, 544 ahc_aic7860_setup 545 }, 546 { 547 ID_AIC7870 & ID_DEV_VENDOR_MASK, 548 ID_DEV_VENDOR_MASK, 549 ahc_aic7870_setup 550 }, 551 { 552 ID_AIC7880 & ID_DEV_VENDOR_MASK, 553 ID_DEV_VENDOR_MASK, 554 ahc_aic7880_setup 555 }, 556 { 557 ID_AIC7890 & ID_9005_GENERIC_MASK, 558 ID_9005_GENERIC_MASK, 559 ahc_aic7890_setup 560 }, 561 { 562 ID_AIC7892 & ID_9005_GENERIC_MASK, 563 ID_9005_GENERIC_MASK, 564 ahc_aic7892_setup 565 }, 566 { 567 ID_AIC7895 & ID_DEV_VENDOR_MASK, 568 ID_DEV_VENDOR_MASK, 569 ahc_aic7895_setup 570 }, 571 { 572 ID_AIC7896 & ID_9005_GENERIC_MASK, 573 ID_9005_GENERIC_MASK, 574 ahc_aic7896_setup 575 }, 576 { 577 ID_AIC7899 & ID_9005_GENERIC_MASK, 578 ID_9005_GENERIC_MASK, 579 ahc_aic7899_setup 580 }, 581 { 582 ID_AIC7810 & ID_DEV_VENDOR_MASK, 583 ID_DEV_VENDOR_MASK, 584 ahc_raid_setup 585 }, 586 { 587 ID_AIC7815 & ID_DEV_VENDOR_MASK, 588 ID_DEV_VENDOR_MASK, 589 ahc_raid_setup 590 } 591 }; 592 593 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 594 595 #define AHC_394X_SLOT_CHANNEL_A 4 596 #define AHC_394X_SLOT_CHANNEL_B 5 597 598 #define AHC_398X_SLOT_CHANNEL_A 4 599 #define AHC_398X_SLOT_CHANNEL_B 8 600 #define AHC_398X_SLOT_CHANNEL_C 12 601 602 #define AHC_494X_SLOT_CHANNEL_A 4 603 #define AHC_494X_SLOT_CHANNEL_B 5 604 #define AHC_494X_SLOT_CHANNEL_C 6 605 #define AHC_494X_SLOT_CHANNEL_D 7 606 607 #define DEVCONFIG 0x40 608 #define PCIERRGENDIS 0x80000000ul 609 #define SCBSIZE32 0x00010000ul /* aic789X only */ 610 #define REXTVALID 0x00001000ul /* ultra cards only */ 611 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 612 #define RAMPSM 0x00000200ul /* aic7870+ only */ 613 #define VOLSENSE 0x00000100ul 614 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 615 #define SCBRAMSEL 0x00000080ul 616 #define MRDCEN 0x00000040ul 617 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 618 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 619 #define BERREN 0x00000008ul 620 #define DACEN 0x00000004ul 621 #define STPWLEVEL 0x00000002ul 622 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 623 624 #define CSIZE_LATTIME 0x0c 625 #define CACHESIZE 0x0000003ful /* only 5 bits */ 626 #define LATTIME 0x0000ff00ul 627 628 /* PCI STATUS definitions */ 629 #define DPE 0x80 630 #define SSE 0x40 631 #define RMA 0x20 632 #define RTA 0x10 633 #define STA 0x08 634 #define DPR 0x01 635 636 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 637 uint16_t subvendor, uint16_t subdevice); 638 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 639 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 640 int pcheck, int fast, int large); 641 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 642 643 int ahc_pci_probe(struct device *, void *, void *); 644 void ahc_pci_attach(struct device *, struct device *, void *); 645 646 647 struct cfattach ahc_pci_ca = { 648 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 649 }; 650 651 const struct ahc_pci_identity * 652 ahc_find_pci_device(id, subid, func) 653 pcireg_t id, subid; 654 u_int func; 655 { 656 u_int64_t full_id; 657 const struct ahc_pci_identity *entry; 658 u_int i; 659 660 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 661 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 662 663 /* 664 * If the second function is not hooked up, ignore it. 665 * Unfortunately, not all MB vendors implement the 666 * subdevice ID as per the Adaptec spec, so do our best 667 * to sanity check it prior to accepting the subdevice 668 * ID as valid. 669 */ 670 if (func > 0 671 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 672 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 673 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 674 return (NULL); 675 676 for (i = 0; i < ahc_num_pci_devs; i++) { 677 entry = &ahc_pci_ident_table[i]; 678 if (entry->full_id == (full_id & entry->id_mask)) 679 return (entry); 680 } 681 return (NULL); 682 } 683 684 int 685 ahc_pci_probe(parent, match, aux) 686 struct device *parent; 687 void *match, *aux; 688 { 689 struct pci_attach_args *pa = aux; 690 const struct ahc_pci_identity *entry; 691 pcireg_t subid; 692 693 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 694 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 695 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 696 } 697 698 void 699 ahc_pci_attach(parent, self, aux) 700 struct device *parent, *self; 701 void *aux; 702 { 703 struct pci_attach_args *pa = aux; 704 const struct ahc_pci_identity *entry; 705 struct ahc_softc *ahc = (void *)self; 706 pcireg_t command; 707 u_int our_id = 0; 708 u_int sxfrctl1; 709 u_int scsiseq; 710 u_int sblkctl; 711 uint8_t dscommand0; 712 uint32_t devconfig; 713 int error; 714 pcireg_t subid; 715 int ioh_valid, memh_valid; 716 bus_space_tag_t st, iot; 717 bus_space_handle_t sh, ioh; 718 #ifdef AHC_ALLOW_MEMIO 719 bus_space_tag_t memt; 720 bus_space_handle_t memh; 721 pcireg_t memtype; 722 #endif 723 pci_intr_handle_t ih; 724 const char *intrstr; 725 struct ahc_pci_busdata *bd; 726 727 ahc->dev_softc = pa; 728 729 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 730 ahc->parent_dmat = pa->pa_dmat; 731 732 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 733 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 734 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 735 if (entry == NULL) 736 return; 737 738 /* Keep information about the PCI bus */ 739 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 740 if (bd == NULL) { 741 printf("%s: unable to allocate bus-specific data\n", ahc_name(ahc)); 742 return; 743 } 744 memset(bd, 0, sizeof(struct ahc_pci_busdata)); 745 746 bd->pc = pa->pa_pc; 747 bd->tag = pa->pa_tag; 748 bd->func = pa->pa_function; 749 bd->dev = pa->pa_device; 750 bd->class = pa->pa_class; 751 752 ahc->bd = bd; 753 754 error = entry->setup(ahc); 755 if (error != 0) 756 return; 757 758 ioh_valid = memh_valid = 0; 759 760 #ifdef AHC_ALLOW_MEMIO 761 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 762 switch (memtype) { 763 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 764 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 765 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 766 memtype, 0, &memt, &memh, NULL, NULL, 0) == 0); 767 break; 768 default: 769 memh_valid = 0; 770 } 771 #endif 772 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 773 PCI_MAPREG_TYPE_IO, 0, &iot, 774 &ioh, NULL, NULL, 0) == 0); 775 #if 0 776 printf("%s: mem mapping: memt 0x%x, memh 0x%x, iot 0x%x, ioh 0x%lx\n", 777 ahc_name(ahc), memt, (u_int32_t)memh, (u_int32_t)iot, ioh); 778 #endif 779 780 if (ioh_valid) { 781 st = iot; 782 sh = ioh; 783 #ifdef AHC_ALLOW_MEMIO 784 } else if (memh_valid) { 785 st = memt; 786 sh = memh; 787 #endif 788 } else { 789 printf(": unable to map registers\n"); 790 return; 791 } 792 ahc->tag = st; 793 ahc->bsh = sh; 794 795 ahc->chip |= AHC_PCI; 796 /* 797 * Before we continue probing the card, ensure that 798 * its interrupts are *disabled*. We don't want 799 * a misstep to hang the machine in an interrupt 800 * storm. 801 */ 802 ahc_intr_enable(ahc, FALSE); 803 804 /* 805 * XXX somehow reading this once fails on some sparc64 systems. 806 * This may be a problem in the sparc64 PCI code. Doing it 807 * twice works around it. 808 */ 809 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 810 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 811 812 /* 813 * If we need to support high memory, enable dual 814 * address cycles. This bit must be set to enable 815 * high address bit generation even if we are on a 816 * 64bit bus (PCI64BIT set in devconfig). 817 */ 818 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 819 820 if (1/*bootverbose*/) 821 printf("%s: Enabling 39Bit Addressing\n", 822 ahc_name(ahc)); 823 devconfig |= DACEN; 824 } 825 826 /* Ensure that pci error generation, a test feature, is disabled. */ 827 devconfig |= PCIERRGENDIS; 828 829 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 830 831 /* Ensure busmastering is enabled */ 832 command |= PCI_COMMAND_MASTER_ENABLE;; 833 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 834 835 /* 836 * Disable PCI parity error reporting. Users typically 837 * do this to work around broken PCI chipsets that get 838 * the parity timing wrong and thus generate lots of spurious 839 * errors. 840 */ 841 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 842 command &= ~PCI_COMMAND_PARITY_ENABLE; 843 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 844 845 /* On all PCI adapters, we allow SCB paging */ 846 ahc->flags |= AHC_PAGESCBS; 847 error = ahc_softc_init(ahc); 848 if (error != 0) 849 goto error_out; 850 851 ahc->bus_intr = ahc_pci_intr; 852 853 /* Remember how the card was setup in case there is no SEEPROM */ 854 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 855 ahc_pause(ahc); 856 if ((ahc->features & AHC_ULTRA2) != 0) 857 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 858 else 859 our_id = ahc_inb(ahc, SCSIID) & OID; 860 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 861 scsiseq = ahc_inb(ahc, SCSISEQ); 862 } else { 863 sxfrctl1 = STPWEN; 864 our_id = 7; 865 scsiseq = 0; 866 } 867 868 error = ahc_reset(ahc); 869 if (error != 0) 870 goto error_out; 871 872 if ((ahc->features & AHC_DT) != 0) { 873 u_int sfunct; 874 875 /* Perform ALT-Mode Setup */ 876 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 877 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 878 ahc_outb(ahc, OPTIONMODE, 879 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 880 ahc_outb(ahc, SFUNCT, sfunct); 881 882 /* Normal mode setup */ 883 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 884 |TARGCRCENDEN); 885 } 886 887 if (pci_intr_map(pa, &ih)) { 888 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 889 ahc_free(ahc); 890 return; 891 } 892 intrstr = pci_intr_string(pa->pa_pc, ih); 893 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 894 ahc_platform_intr, ahc, ahc->sc_dev.dv_xname); 895 if (ahc->ih == NULL) { 896 printf(": couldn't establish interrupt"); 897 if (intrstr != NULL) 898 printf(" at %s", intrstr); 899 printf("\n"); 900 ahc_free(ahc); 901 return; 902 } else 903 printf(": %s\n", intrstr ? intrstr : "?"); 904 905 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 906 dscommand0 |= MPARCKEN|CACHETHEN; 907 if ((ahc->features & AHC_ULTRA2) != 0) { 908 909 /* 910 * DPARCKEN doesn't work correctly on 911 * some MBs so don't use it. 912 */ 913 dscommand0 &= ~DPARCKEN; 914 } 915 916 /* 917 * Handle chips that must have cache line 918 * streaming (dis/en)abled. 919 */ 920 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 921 dscommand0 |= CACHETHEN; 922 923 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 924 dscommand0 &= ~CACHETHEN; 925 926 ahc_outb(ahc, DSCOMMAND0, dscommand0); 927 928 ahc->pci_cachesize = 929 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 930 ahc->pci_cachesize *= 4; 931 932 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 933 && ahc->pci_cachesize == 4) { 934 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 935 ahc->pci_cachesize = 0; 936 } 937 938 /* 939 * We cannot perform ULTRA speeds without the presence 940 * of the external precision resistor. 941 */ 942 if ((ahc->features & AHC_ULTRA) != 0) { 943 uint32_t devconfig; 944 945 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 946 if ((devconfig & REXTVALID) == 0) 947 ahc->features &= ~AHC_ULTRA; 948 } 949 950 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 951 M_DEVBUF, M_NOWAIT); 952 if (ahc->seep_config == NULL) 953 goto error_out; 954 955 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); 956 957 /* See if we have a SEEPROM and perform auto-term */ 958 ahc_check_extport(ahc, &sxfrctl1); 959 960 /* 961 * Take the LED out of diagnostic mode 962 */ 963 sblkctl = ahc_inb(ahc, SBLKCTL); 964 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 965 966 if ((ahc->features & AHC_ULTRA2) != 0) { 967 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 968 } else { 969 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 970 } 971 972 if (ahc->flags & AHC_USEDEFAULTS) { 973 /* 974 * PCI Adapter default setup 975 * Should only be used if the adapter does not have 976 * a SEEPROM. 977 */ 978 /* See if someone else set us up already */ 979 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 980 && scsiseq != 0) { 981 printf("%s: Using left over BIOS settings\n", 982 ahc_name(ahc)); 983 ahc->flags &= ~AHC_USEDEFAULTS; 984 ahc->flags |= AHC_BIOS_ENABLED; 985 } else { 986 /* 987 * Assume only one connector and always turn 988 * on termination. 989 */ 990 our_id = 0x07; 991 sxfrctl1 = STPWEN; 992 } 993 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 994 995 ahc->our_id = our_id; 996 } 997 998 /* 999 * Take a look to see if we have external SRAM. 1000 * We currently do not attempt to use SRAM that is 1001 * shared among multiple controllers. 1002 */ 1003 ahc_probe_ext_scbram(ahc); 1004 1005 /* 1006 * Record our termination setting for the 1007 * generic initialization routine. 1008 */ 1009 if ((sxfrctl1 & STPWEN) != 0) 1010 ahc->flags |= AHC_TERM_ENB_A; 1011 1012 if (ahc_init(ahc)) 1013 goto error_out; 1014 1015 ahc_attach(ahc); 1016 1017 return; 1018 1019 error_out: 1020 ahc_free(ahc); 1021 return; 1022 } 1023 1024 static int 1025 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1026 uint16_t subdevice, uint16_t subvendor) 1027 { 1028 int result; 1029 1030 /* Default to invalid. */ 1031 result = 0; 1032 if (vendor == 0x9005 1033 && subvendor == 0x9005 1034 && subdevice != device 1035 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1036 1037 switch (SUBID_9005_TYPE(subdevice)) { 1038 case SUBID_9005_TYPE_MB: 1039 break; 1040 case SUBID_9005_TYPE_CARD: 1041 case SUBID_9005_TYPE_LCCARD: 1042 /* 1043 * Currently only trust Adaptec cards to 1044 * get the sub device info correct. 1045 */ 1046 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1047 result = 1; 1048 break; 1049 case SUBID_9005_TYPE_RAID: 1050 break; 1051 default: 1052 break; 1053 } 1054 } 1055 return (result); 1056 } 1057 1058 1059 /* 1060 * Test for the presense of external sram in an 1061 * "unshared" configuration. 1062 */ 1063 static int 1064 ahc_ext_scbram_present(struct ahc_softc *ahc) 1065 { 1066 u_int chip; 1067 int ramps; 1068 int single_user; 1069 uint32_t devconfig; 1070 1071 chip = ahc->chip & AHC_CHIPID_MASK; 1072 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1073 single_user = (devconfig & MPORTMODE) != 0; 1074 1075 if ((ahc->features & AHC_ULTRA2) != 0) 1076 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1077 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1078 /* 1079 * External SCBRAM arbitration is flakey 1080 * on these chips. Unfortunately this means 1081 * we don't use the extra SCB ram space on the 1082 * 3940AUW. 1083 */ 1084 ramps = 0; 1085 else if (chip >= AHC_AIC7870) 1086 ramps = (devconfig & RAMPSM) != 0; 1087 else 1088 ramps = 0; 1089 1090 if (ramps && single_user) 1091 return (1); 1092 return (0); 1093 } 1094 1095 /* 1096 * Enable external scbram. 1097 */ 1098 static void 1099 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1100 int fast, int large) 1101 { 1102 uint32_t devconfig; 1103 1104 if (ahc->features & AHC_MULTI_FUNC) { 1105 /* 1106 * Set the SCB Base addr (highest address bit) 1107 * depending on which channel we are. 1108 */ 1109 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1110 } 1111 1112 ahc->flags &= ~AHC_LSCBS_ENABLED; 1113 if (large) 1114 ahc->flags |= AHC_LSCBS_ENABLED; 1115 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1116 if ((ahc->features & AHC_ULTRA2) != 0) { 1117 u_int dscommand0; 1118 1119 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1120 if (enable) 1121 dscommand0 &= ~INTSCBRAMSEL; 1122 else 1123 dscommand0 |= INTSCBRAMSEL; 1124 if (large) 1125 dscommand0 &= ~USCBSIZE32; 1126 else 1127 dscommand0 |= USCBSIZE32; 1128 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1129 } else { 1130 if (fast) 1131 devconfig &= ~EXTSCBTIME; 1132 else 1133 devconfig |= EXTSCBTIME; 1134 if (enable) 1135 devconfig &= ~SCBRAMSEL; 1136 else 1137 devconfig |= SCBRAMSEL; 1138 if (large) 1139 devconfig &= ~SCBSIZE32; 1140 else 1141 devconfig |= SCBSIZE32; 1142 } 1143 if (pcheck) 1144 devconfig |= EXTSCBPEN; 1145 else 1146 devconfig &= ~EXTSCBPEN; 1147 1148 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1149 } 1150 1151 /* 1152 * Take a look to see if we have external SRAM. 1153 * We currently do not attempt to use SRAM that is 1154 * shared among multiple controllers. 1155 */ 1156 static void 1157 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1158 { 1159 int num_scbs; 1160 int test_num_scbs; 1161 int enable; 1162 int pcheck; 1163 int fast; 1164 int large; 1165 1166 enable = FALSE; 1167 pcheck = FALSE; 1168 fast = FALSE; 1169 large = FALSE; 1170 num_scbs = 0; 1171 1172 if (ahc_ext_scbram_present(ahc) == 0) 1173 goto done; 1174 1175 /* 1176 * Probe for the best parameters to use. 1177 */ 1178 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1179 num_scbs = ahc_probe_scbs(ahc); 1180 if (num_scbs == 0) { 1181 /* The SRAM wasn't really present. */ 1182 goto done; 1183 } 1184 enable = TRUE; 1185 1186 /* 1187 * Clear any outstanding parity error 1188 * and ensure that parity error reporting 1189 * is enabled. 1190 */ 1191 ahc_outb(ahc, SEQCTL, 0); 1192 ahc_outb(ahc, CLRINT, CLRPARERR); 1193 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1194 1195 /* Now see if we can do parity */ 1196 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1197 num_scbs = ahc_probe_scbs(ahc); 1198 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1199 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1200 pcheck = TRUE; 1201 1202 /* Clear any resulting parity error */ 1203 ahc_outb(ahc, CLRINT, CLRPARERR); 1204 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1205 1206 /* Now see if we can do fast timing */ 1207 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1208 test_num_scbs = ahc_probe_scbs(ahc); 1209 if (test_num_scbs == num_scbs 1210 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1211 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1212 fast = TRUE; 1213 1214 /* 1215 * See if we can use large SCBs and still maintain 1216 * the same overall count of SCBs. 1217 */ 1218 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1219 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1220 test_num_scbs = ahc_probe_scbs(ahc); 1221 if (test_num_scbs >= num_scbs) { 1222 large = TRUE; 1223 num_scbs = test_num_scbs; 1224 if (num_scbs >= 64) { 1225 /* 1226 * We have enough space to move the 1227 * "busy targets table" into SCB space 1228 * and make it qualify all the way to the 1229 * lun level. 1230 */ 1231 ahc->flags |= AHC_SCB_BTT; 1232 } 1233 } 1234 } 1235 done: 1236 /* 1237 * Disable parity error reporting until we 1238 * can load instruction ram. 1239 */ 1240 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1241 /* Clear any latched parity error */ 1242 ahc_outb(ahc, CLRINT, CLRPARERR); 1243 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1244 if (1/*bootverbose*/ && enable) { 1245 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1246 ahc_name(ahc), fast ? "fast" : "slow", 1247 pcheck ? ", parity checking enabled" : "", 1248 large ? 64 : 32); 1249 } 1250 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1251 } 1252 1253 #if 0 1254 /* 1255 * Perform some simple tests that should catch situations where 1256 * our registers are invalidly mapped. 1257 */ 1258 int 1259 ahc_pci_test_register_access(struct ahc_softc *ahc) 1260 { 1261 int error; 1262 u_int status1; 1263 uint32_t cmd; 1264 uint8_t hcntrl; 1265 1266 error = EIO; 1267 1268 /* 1269 * Enable PCI error interrupt status, but suppress NMIs 1270 * generated by SERR raised due to target aborts. 1271 */ 1272 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1273 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1274 cmd & ~PCIM_CMD_SERRESPEN); 1275 1276 /* 1277 * First a simple test to see if any 1278 * registers can be read. Reading 1279 * HCNTRL has no side effects and has 1280 * at least one bit that is guaranteed to 1281 * be zero so it is a good register to 1282 * use for this test. 1283 */ 1284 hcntrl = ahc_inb(ahc, HCNTRL); 1285 if (hcntrl == 0xFF) 1286 goto fail; 1287 1288 /* 1289 * Next create a situation where write combining 1290 * or read prefetching could be initiated by the 1291 * CPU or host bridge. Our device does not support 1292 * either, so look for data corruption and/or flagged 1293 * PCI errors. 1294 */ 1295 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1296 while (ahc_is_paused(ahc) == 0) 1297 ; 1298 ahc_outb(ahc, SEQCTL, PERRORDIS); 1299 ahc_outb(ahc, SCBPTR, 0); 1300 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1301 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1302 goto fail; 1303 1304 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1305 PCI_COMMAND_STATUS_REG + 1); 1306 if ((status1 & STA) != 0) 1307 goto fail; 1308 1309 error = 0; 1310 1311 fail: 1312 /* Silently clear any latched errors. */ 1313 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1); 1314 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1315 status1, /*bytes*/1); 1316 ahc_outb(ahc, CLRINT, CLRPARERR); 1317 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1318 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1319 return (error); 1320 } 1321 #endif 1322 1323 void 1324 ahc_pci_intr(struct ahc_softc *ahc) 1325 { 1326 u_int error; 1327 u_int status1; 1328 1329 error = ahc_inb(ahc, ERROR); 1330 if ((error & PCIERRSTAT) == 0) 1331 return; 1332 1333 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1334 1335 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1336 ahc_name(ahc), 1337 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1338 1339 if (status1 & DPE) { 1340 printf("%s: Data Parity Error Detected during address " 1341 "or write data phase\n", ahc_name(ahc)); 1342 } 1343 if (status1 & SSE) { 1344 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1345 } 1346 if (status1 & RMA) { 1347 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1348 } 1349 if (status1 & RTA) { 1350 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1351 } 1352 if (status1 & STA) { 1353 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1354 } 1355 if (status1 & DPR) { 1356 printf("%s: Data Parity Error has been reported via PERR#\n", 1357 ahc_name(ahc)); 1358 } 1359 1360 /* Clear latched errors. */ 1361 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, status1); 1362 1363 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1364 printf("%s: Latched PCIERR interrupt with " 1365 "no status bits set\n", ahc_name(ahc)); 1366 } else { 1367 ahc_outb(ahc, CLRINT, CLRPARERR); 1368 } 1369 1370 ahc_unpause(ahc); 1371 } 1372 1373 static int 1374 ahc_aic785X_setup(struct ahc_softc *ahc) 1375 { 1376 uint8_t rev; 1377 1378 ahc->channel = 'A'; 1379 ahc->chip = AHC_AIC7850; 1380 ahc->features = AHC_AIC7850_FE; 1381 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1382 rev = PCI_REVISION(ahc->bd->class); 1383 if (rev >= 1) 1384 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1385 return (0); 1386 } 1387 1388 static int 1389 ahc_aic7860_setup(struct ahc_softc *ahc) 1390 { 1391 uint8_t rev; 1392 1393 ahc->channel = 'A'; 1394 ahc->chip = AHC_AIC7860; 1395 ahc->features = AHC_AIC7860_FE; 1396 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1397 rev = PCI_REVISION(ahc->bd->class); 1398 if (rev >= 1) 1399 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1400 return (0); 1401 } 1402 1403 static int 1404 ahc_apa1480_setup(struct ahc_softc *ahc) 1405 { 1406 int error; 1407 1408 error = ahc_aic7860_setup(ahc); 1409 if (error != 0) 1410 return (error); 1411 ahc->features |= AHC_REMOVABLE; 1412 return (0); 1413 } 1414 1415 static int 1416 ahc_aic7870_setup(struct ahc_softc *ahc) 1417 { 1418 1419 ahc->channel = 'A'; 1420 ahc->chip = AHC_AIC7870; 1421 ahc->features = AHC_AIC7870_FE; 1422 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1423 return (0); 1424 } 1425 1426 static int 1427 ahc_aha394X_setup(struct ahc_softc *ahc) 1428 { 1429 int error; 1430 1431 error = ahc_aic7870_setup(ahc); 1432 if (error == 0) 1433 error = ahc_aha394XX_setup(ahc); 1434 return (error); 1435 } 1436 1437 static int 1438 ahc_aha398X_setup(struct ahc_softc *ahc) 1439 { 1440 int error; 1441 1442 error = ahc_aic7870_setup(ahc); 1443 if (error == 0) 1444 error = ahc_aha398XX_setup(ahc); 1445 return (error); 1446 } 1447 1448 static int 1449 ahc_aha494X_setup(struct ahc_softc *ahc) 1450 { 1451 int error; 1452 1453 error = ahc_aic7870_setup(ahc); 1454 if (error == 0) 1455 error = ahc_aha494XX_setup(ahc); 1456 return (error); 1457 } 1458 1459 static int 1460 ahc_aic7880_setup(struct ahc_softc *ahc) 1461 { 1462 uint8_t rev; 1463 1464 ahc->channel = 'A'; 1465 ahc->chip = AHC_AIC7880; 1466 ahc->features = AHC_AIC7880_FE; 1467 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1468 rev = PCI_REVISION(ahc->bd->class); 1469 if (rev >= 1) { 1470 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1471 } else { 1472 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1473 } 1474 return (0); 1475 } 1476 1477 static int 1478 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1479 { 1480 1481 ahc->flags |= AHC_INT50_SPEEDFLEX; 1482 return (ahc_aic7880_setup(ahc)); 1483 } 1484 1485 static int 1486 ahc_aha394XU_setup(struct ahc_softc *ahc) 1487 { 1488 int error; 1489 1490 error = ahc_aic7880_setup(ahc); 1491 if (error == 0) 1492 error = ahc_aha394XX_setup(ahc); 1493 return (error); 1494 } 1495 1496 static int 1497 ahc_aha398XU_setup(struct ahc_softc *ahc) 1498 { 1499 int error; 1500 1501 error = ahc_aic7880_setup(ahc); 1502 if (error == 0) 1503 error = ahc_aha398XX_setup(ahc); 1504 return (error); 1505 } 1506 1507 static int 1508 ahc_aic7890_setup(struct ahc_softc *ahc) 1509 { 1510 uint8_t rev; 1511 1512 ahc->channel = 'A'; 1513 ahc->chip = AHC_AIC7890; 1514 ahc->features = AHC_AIC7890_FE; 1515 ahc->flags |= AHC_NEWEEPROM_FMT; 1516 rev = PCI_REVISION(ahc->bd->class); 1517 if (rev == 0) 1518 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1519 return (0); 1520 } 1521 1522 static int 1523 ahc_aic7892_setup(struct ahc_softc *ahc) 1524 { 1525 1526 ahc->channel = 'A'; 1527 ahc->chip = AHC_AIC7892; 1528 ahc->features = AHC_AIC7892_FE; 1529 ahc->flags |= AHC_NEWEEPROM_FMT; 1530 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1531 return (0); 1532 } 1533 1534 static int 1535 ahc_aic7895_setup(struct ahc_softc *ahc) 1536 { 1537 uint8_t rev; 1538 1539 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1540 /* 1541 * The 'C' revision of the aic7895 has a few additional features. 1542 */ 1543 rev = PCI_REVISION(ahc->bd->class); 1544 if (rev >= 4) { 1545 ahc->chip = AHC_AIC7895C; 1546 ahc->features = AHC_AIC7895C_FE; 1547 } else { 1548 u_int command; 1549 1550 ahc->chip = AHC_AIC7895; 1551 ahc->features = AHC_AIC7895_FE; 1552 1553 /* 1554 * The BIOS disables the use of MWI transactions 1555 * since it does not have the MWI bug work around 1556 * we have. Disabling MWI reduces performance, so 1557 * turn it on again. 1558 */ 1559 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1560 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1561 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command); 1562 ahc->bugs |= AHC_PCI_MWI_BUG; 1563 } 1564 /* 1565 * XXX Does CACHETHEN really not work??? What about PCI retry? 1566 * on C level chips. Need to test, but for now, play it safe. 1567 */ 1568 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1569 | AHC_CACHETHEN_BUG; 1570 1571 #if 0 1572 uint32_t devconfig; 1573 1574 /* 1575 * Cachesize must also be zero due to stray DAC 1576 * problem when sitting behind some bridges. 1577 */ 1578 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1579 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1580 devconfig |= MRDCEN; 1581 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1582 #endif 1583 ahc->flags |= AHC_NEWEEPROM_FMT; 1584 return (0); 1585 } 1586 1587 static int 1588 ahc_aic7896_setup(struct ahc_softc *ahc) 1589 { 1590 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1591 ahc->chip = AHC_AIC7896; 1592 ahc->features = AHC_AIC7896_FE; 1593 ahc->flags |= AHC_NEWEEPROM_FMT; 1594 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1595 return (0); 1596 } 1597 1598 static int 1599 ahc_aic7899_setup(struct ahc_softc *ahc) 1600 { 1601 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1602 ahc->chip = AHC_AIC7899; 1603 ahc->features = AHC_AIC7899_FE; 1604 ahc->flags |= AHC_NEWEEPROM_FMT; 1605 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1606 return (0); 1607 } 1608 1609 static int 1610 ahc_aha29160C_setup(struct ahc_softc *ahc) 1611 { 1612 int error; 1613 1614 error = ahc_aic7899_setup(ahc); 1615 if (error != 0) 1616 return (error); 1617 ahc->features |= AHC_REMOVABLE; 1618 return (0); 1619 } 1620 1621 static int 1622 ahc_raid_setup(struct ahc_softc *ahc) 1623 { 1624 printf("RAID functionality unsupported\n"); 1625 return (ENXIO); 1626 } 1627 1628 static int 1629 ahc_aha394XX_setup(struct ahc_softc *ahc) 1630 { 1631 1632 switch (ahc->bd->dev) { 1633 case AHC_394X_SLOT_CHANNEL_A: 1634 ahc->channel = 'A'; 1635 break; 1636 case AHC_394X_SLOT_CHANNEL_B: 1637 ahc->channel = 'B'; 1638 break; 1639 default: 1640 printf("adapter at unexpected slot %d\n" 1641 "unable to map to a channel\n", 1642 ahc->bd->dev); 1643 ahc->channel = 'A'; 1644 } 1645 return (0); 1646 } 1647 1648 static int 1649 ahc_aha398XX_setup(struct ahc_softc *ahc) 1650 { 1651 1652 switch (ahc->bd->dev) { 1653 case AHC_398X_SLOT_CHANNEL_A: 1654 ahc->channel = 'A'; 1655 break; 1656 case AHC_398X_SLOT_CHANNEL_B: 1657 ahc->channel = 'B'; 1658 break; 1659 case AHC_398X_SLOT_CHANNEL_C: 1660 ahc->channel = 'C'; 1661 break; 1662 default: 1663 printf("adapter at unexpected slot %d\n" 1664 "unable to map to a channel\n", 1665 ahc->bd->dev); 1666 ahc->channel = 'A'; 1667 break; 1668 } 1669 ahc->flags |= AHC_LARGE_SEEPROM; 1670 return (0); 1671 } 1672 1673 static int 1674 ahc_aha494XX_setup(struct ahc_softc *ahc) 1675 { 1676 1677 switch (ahc->bd->dev) { 1678 case AHC_494X_SLOT_CHANNEL_A: 1679 ahc->channel = 'A'; 1680 break; 1681 case AHC_494X_SLOT_CHANNEL_B: 1682 ahc->channel = 'B'; 1683 break; 1684 case AHC_494X_SLOT_CHANNEL_C: 1685 ahc->channel = 'C'; 1686 break; 1687 case AHC_494X_SLOT_CHANNEL_D: 1688 ahc->channel = 'D'; 1689 break; 1690 default: 1691 printf("adapter at unexpected slot %d\n" 1692 "unable to map to a channel\n", 1693 ahc->bd->dev); 1694 ahc->channel = 'A'; 1695 } 1696 ahc->flags |= AHC_LARGE_SEEPROM; 1697 return (0); 1698 } 1699