1 /* $OpenBSD: ahc_pci.c,v 1.38 2003/07/25 09:49:21 henning Exp $ */ 2 /* $NetBSD: ahc_pci.c,v 1.9 1996/10/21 22:56:24 thorpej Exp $ */ 3 4 /* 5 * Product specific probe and attach routines for: 6 * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1995, 1996 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/queue.h> 41 #include <sys/device.h> 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <scsi/scsi_all.h> 46 #include <scsi/scsiconf.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 53 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 54 55 #include <dev/ic/aic7xxxreg.h> 56 #include <dev/ic/aic7xxx_openbsd.h> 57 #include <dev/ic/aic7xxx_inline.h> 58 #include <dev/ic/smc93cx6var.h> 59 60 /* 61 * XXX memory-mapped is busted on some i386 on-board chips. 62 * for i386, we don't even try it. Also, suppress the damn 63 * PCI bus errors messages on i386. They are not fatal, and are 64 * usually caused by some other device on the PCI bus. But some 65 * ahc cards won't work without ACKing them. So just ACK and go! 66 * XXX- smurph 67 */ 68 #ifndef i386 69 #define AHC_ALLOW_MEMIO 70 #define AHC_SHOW_PCI_ERRORS 71 #endif 72 73 /* 74 * Under normal circumstances, these messages are unnecessary 75 * and not terribly cosmetic. 76 */ 77 #ifdef DEBUG 78 #define bootverbose 1 79 #else 80 #define bootverbose 0 81 #endif 82 83 #define PCI_BASEADR0 PCI_MAPREG_START 84 85 #define AHC_394X_SLOT_CHANNEL_A 4 86 #define AHC_394X_SLOT_CHANNEL_B 5 87 88 #define AHC_398X_SLOT_CHANNEL_A 4 89 #define AHC_398X_SLOT_CHANNEL_B 8 90 #define AHC_398X_SLOT_CHANNEL_C 12 91 92 #define EXROMBADR 0x30 93 #define EXROMEN 0x00000001UL /* External Rom Enable */ 94 95 #define DEVCONFIG 0x40 96 #define SCBSIZE32 0x00010000UL /* aic789X only */ 97 #define REXTVALID 0x00001000UL /* ultra cards only */ 98 #define MPORTMODE 0x00000400UL /* aic7870+ only */ 99 #define RAMPSM 0x00000200UL /* aic7870+ only */ 100 #define VOLSENSE 0x00000100UL 101 #define PCI64BIT 0x00000080UL /* 64Bit PCI bus (Ultra2 Only)*/ 102 #define SCBRAMSEL 0x00000080UL 103 #define MRDCEN 0x00000040UL 104 #define EXTSCBTIME 0x00000020UL /* aic7870 only */ 105 #define EXTSCBPEN 0x00000010UL /* aic7870 only */ 106 #define BERREN 0x00000008UL 107 #define DACEN 0x00000004UL 108 #define STPWLEVEL 0x00000002UL 109 #define DIFACTNEGEN 0x00000001UL /* aic7870 only */ 110 111 #define CSIZE_LATTIME 0x0c 112 #define CACHESIZE 0x0000003fUL /* only 5 bits */ 113 #define LATTIME 0x0000ff00UL 114 115 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 116 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 117 int pcheck, int fast, int large); 118 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 119 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 120 static void configure_termination(struct ahc_softc *ahc, 121 struct seeprom_descriptor *sd, 122 u_int adapter_control, 123 u_int *sxfrctl1); 124 static void ahc_new_term_detect(struct ahc_softc *ahc, 125 int *enableSEC_low, 126 int *enableSEC_high, 127 int *enablePRI_low, 128 int *enablePRI_high, 129 int *eeprom_present); 130 static void aic787X_cable_detect(struct ahc_softc *ahc, 131 int *internal50_present, 132 int *internal68_present, 133 int *externalcable_present, 134 int *eeprom_present); 135 static void aic785X_cable_detect(struct ahc_softc *ahc, 136 int *internal50_present, 137 int *externalcable_present, 138 int *eeprom_present); 139 static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 140 static u_int8_t read_brdctl(struct ahc_softc *ahc); 141 142 int ahc_do_pci_config(struct ahc_softc *ahc); 143 144 void load_seeprom(struct ahc_softc *ahc); 145 static int acquire_seeprom(struct ahc_softc *ahc, 146 struct seeprom_descriptor *sd); 147 static void release_seeprom(struct seeprom_descriptor *sd); 148 int ahc_probe_scbs(struct ahc_softc *ahc); 149 150 static u_char aic3940_count; 151 152 int ahc_pci_probe(struct device *, void *, void *); 153 void ahc_pci_attach(struct device *, struct device *, void *); 154 155 struct cfattach ahc_pci_ca = { 156 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 157 }; 158 159 const struct pci_matchid ahc_pci_devices[] = { 160 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7810 }, 161 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7850 }, 162 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7855 }, 163 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7860 }, 164 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940AU }, 165 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7870 }, 166 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2930CU }, 167 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940 }, 168 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940 }, 169 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3985 }, 170 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944 }, 171 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7880 }, 172 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940U }, 173 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940U }, 174 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_398XU }, 175 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944U }, 176 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940UWPro }, 177 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_7895 }, 178 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7890 }, 179 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_2940U2 }, 180 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_2930U2 }, 181 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7892 }, 182 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_29160 }, 183 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_19160B }, 184 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_3950U2B }, 185 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_3950U2D }, 186 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7896 }, 187 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7899B }, 188 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7899D }, 189 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7899F }, 190 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7899 }, 191 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_3960D }, 192 }; 193 194 int 195 ahc_pci_probe(parent, match, aux) 196 struct device *parent; 197 void *match, *aux; 198 { 199 return (pci_matchbyid((struct pci_attach_args *)aux, ahc_pci_devices, 200 sizeof(ahc_pci_devices)/sizeof(ahc_pci_devices[0]))); 201 } 202 203 void 204 ahc_pci_attach(parent, self, aux) 205 struct device *parent, *self; 206 void *aux; 207 { 208 struct pci_attach_args *pa = aux; 209 struct ahc_softc *ahc = (void *)self; 210 pcireg_t devconfig; 211 pcireg_t command; 212 213 /* setup the PCI stuff */ 214 ahc->dev_softc = pa; 215 216 /* 217 * We really don't allocate our softc, but 218 * we need to do the initialization. And this 219 * also allocates the platform_data structure. 220 */ 221 ahc_alloc(ahc, NULL); 222 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 223 ahc_set_unit(ahc, ahc->sc_dev.dv_unit); 224 225 /* set dma tags */ 226 ahc->parent_dmat = pa->pa_dmat; 227 ahc->buffer_dmat = pa->pa_dmat; 228 ahc->shared_data_dmat = pa->pa_dmat; 229 230 /* card specific setup */ 231 switch (PCI_VENDOR(pa->pa_id)) { 232 case PCI_VENDOR_ADP: 233 switch (PCI_PRODUCT(pa->pa_id)) { 234 case PCI_PRODUCT_ADP_7895: 235 ahc->channel = pa->pa_function == 1 ? 'B' : 'A'; 236 /* The 'C' revision of the aic7895 237 has a few additional features */ 238 if (PCI_REVISION(pa->pa_class) >= 4){ 239 ahc->chip |= AHC_AIC7895C; 240 } else { 241 ahc->chip |= AHC_AIC7895; 242 } 243 break; 244 case PCI_PRODUCT_ADP_3940U: 245 case PCI_PRODUCT_ADP_3940: 246 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADP_3940U) { 247 ahc->chip |= AHC_AIC7880; 248 } else { 249 ahc->chip |= AHC_AIC7870; 250 } 251 aic3940_count++; 252 if (!(aic3940_count & 0x01)) 253 /* Even count implies second channel */ 254 ahc->channel = 'B'; 255 break; 256 case PCI_PRODUCT_ADP_2940UWPro: 257 ahc->flags |= AHC_INT50_SPEEDFLEX; 258 /* fall through */ 259 case PCI_PRODUCT_ADP_AIC7880: 260 case PCI_PRODUCT_ADP_398XU: /* XXX */ 261 case PCI_PRODUCT_ADP_2944U: 262 case PCI_PRODUCT_ADP_2940U: 263 ahc->chip |= AHC_AIC7880; 264 break; 265 case PCI_PRODUCT_ADP_AIC7870: 266 case PCI_PRODUCT_ADP_2944: 267 case PCI_PRODUCT_ADP_2940: 268 ahc->chip |= AHC_AIC7870; 269 break; 270 case PCI_PRODUCT_ADP_AIC7860: 271 case PCI_PRODUCT_ADP_2940AU: 272 ahc->chip |= AHC_AIC7860; 273 break; 274 case PCI_PRODUCT_ADP_AIC7855: 275 case PCI_PRODUCT_ADP_AIC7850: 276 ahc->chip |= AHC_AIC7850; 277 break; 278 default: 279 /* TTT */ 280 break; 281 } 282 break; 283 case PCI_VENDOR_ADP2: 284 switch (PCI_PRODUCT(pa->pa_id)) { 285 case PCI_PRODUCT_ADP2_AIC7890: 286 case PCI_PRODUCT_ADP2_2940U2: 287 case PCI_PRODUCT_ADP2_2930U2: 288 ahc->chip |= AHC_AIC7890; 289 break; 290 case PCI_PRODUCT_ADP2_AIC7892: 291 case PCI_PRODUCT_ADP2_29160: 292 case PCI_PRODUCT_ADP2_19160B: 293 ahc->chip |= AHC_AIC7892; 294 break; 295 case PCI_PRODUCT_ADP2_3950U2B: 296 case PCI_PRODUCT_ADP2_3950U2D: 297 case PCI_PRODUCT_ADP2_AIC7896: 298 ahc->chip |= AHC_AIC7896; 299 ahc->channel = pa->pa_function == 1 ? 'B' : 'A'; 300 devconfig = ahc_pci_read_config(ahc->dev_softc, 301 DEVCONFIG, 4); 302 /* turn off 64 bit for now XXX smurph */ 303 devconfig &= ~PCI64BIT; 304 ahc_pci_write_config(ahc->dev_softc, 305 DEVCONFIG, devconfig, 4); 306 break; 307 case PCI_PRODUCT_ADP2_AIC7899: 308 case PCI_PRODUCT_ADP2_3960D: 309 ahc->chip |= AHC_AIC7899; 310 ahc->channel = pa->pa_function == 1 ? 'B' : 'A'; 311 break; 312 default: 313 /* TTT */ 314 break; 315 } 316 } 317 318 /* chip specific setup */ 319 switch(ahc->chip){ 320 case AHC_AIC7850: 321 case AHC_AIC7855: 322 case AHC_AIC7859: 323 ahc->features = AHC_AIC7850_FE; 324 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 325 if (PCI_REVISION(pa->pa_class) >= 1) 326 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 327 break; 328 case AHC_AIC7860: 329 ahc->features = AHC_AIC7860_FE; 330 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 331 if (PCI_REVISION(pa->pa_class) >= 1) 332 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 333 break; 334 case AHC_AIC7870: 335 ahc->features = AHC_AIC7870_FE; 336 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 337 break; 338 case AHC_AIC7880: 339 ahc->features = AHC_AIC7880_FE; 340 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 341 if (PCI_REVISION(pa->pa_class) >= 1) { 342 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 343 } else { 344 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 345 } 346 break; 347 case AHC_AIC7895: 348 ahc->features = AHC_AIC7895_FE; 349 ahc->flags |= AHC_NEWEEPROM_FMT; 350 /* 351 * The BIOS disables the use of MWI transactions 352 * since it does not have the MWI bug work around 353 * we have. Disabling MWI reduces performance, so 354 * turn it on again. 355 */ 356 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 357 PCI_COMMAND_STATUS_REG); 358 command |= PCI_COMMAND_INVALIDATE_ENABLE; 359 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 360 command); 361 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 362 | AHC_CACHETHEN_BUG | AHC_PCI_MWI_BUG; 363 break; 364 case AHC_AIC7895C: 365 ahc->features = AHC_AIC7895C_FE; 366 ahc->flags |= AHC_NEWEEPROM_FMT; 367 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 368 | AHC_CACHETHEN_BUG; 369 break; 370 case AHC_AIC7890: 371 ahc->features = AHC_AIC7890_FE; 372 ahc->flags |= AHC_NEWEEPROM_FMT; 373 if (PCI_REVISION(pa->pa_class) == 0) 374 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 375 break; 376 case AHC_AIC7892: 377 ahc->features = AHC_AIC7892_FE; 378 ahc->flags |= AHC_NEWEEPROM_FMT; 379 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 380 break; 381 case AHC_AIC7896: 382 ahc->features = AHC_AIC7896_FE; 383 ahc->flags |= AHC_NEWEEPROM_FMT; 384 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 385 break; 386 case AHC_AIC7899: 387 ahc->features = AHC_AIC7899_FE; 388 ahc->flags |= AHC_NEWEEPROM_FMT; 389 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 390 break; 391 default: 392 break; 393 } 394 395 /* setup the PCI interrupt */ 396 ahc->bus_intr = ahc_pci_intr; 397 ahc->unsolicited_ints = 0; 398 399 if(ahc_do_pci_config(ahc)){ 400 ahc_free(ahc); 401 return; 402 } 403 404 ahc_attach(ahc); 405 } 406 407 int 408 ahc_pci_map_registers(ahc) 409 struct ahc_softc *ahc; 410 { 411 pcireg_t command; 412 int ioh_valid; 413 bus_space_tag_t iot; 414 bus_space_handle_t ioh; 415 struct pci_attach_args *pa = ahc->dev_softc; 416 417 command = ahc_pci_read_config(ahc->dev_softc, 418 PCI_COMMAND_STATUS_REG, 4); 419 #ifdef AHC_ALLOW_MEMIO 420 /* 421 * attempt to use memory mapping on hardware that supports it. 422 * e.g powerpc XXX - smurph 423 * 424 * Note: If this fails, IO mapping is used. 425 */ 426 if ((command & PCI_COMMAND_MEM_ENABLE) != 0) { 427 pcireg_t memtype; 428 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 429 switch (memtype) { 430 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 431 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 432 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 433 memtype, 0, &iot, &ioh, NULL, NULL, 0) == 0); 434 break; 435 default: 436 ioh_valid = 0; 437 } 438 if (ioh_valid) { 439 /* 440 * Do a quick test to see if memory mapped 441 * I/O is functioning correctly. 442 */ 443 ahc->tag = iot; 444 ahc->bsh = ioh; 445 if (ahc_inb(ahc, HCNTRL) == 0xFF) { 446 /* nope, use I/O mapping */ 447 ioh_valid = 0; 448 } else { 449 /* Using memory mapping, disable I/O mapping */ 450 command &= ~PCI_COMMAND_IO_ENABLE; 451 ahc_pci_write_config(ahc->dev_softc, 452 PCI_COMMAND_STATUS_REG, 453 command, 4); 454 } 455 } 456 } 457 458 if (!ioh_valid) /* try to drop back to IO mapping */ 459 #endif 460 { 461 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 462 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0); 463 464 /* Using I/O mapping, disable memory mapping */ 465 command &= ~PCI_COMMAND_MEM_ENABLE; 466 ahc_pci_write_config(ahc->dev_softc, 467 PCI_COMMAND_STATUS_REG, 468 command, 4); 469 } 470 471 if (!ioh_valid) { 472 /* Game Over. Insert coin... */ 473 printf(": unable to map registers\n"); 474 return (1); 475 } 476 ahc->tag = iot; 477 ahc->bsh = ioh; 478 return (0); 479 } 480 481 int 482 ahc_do_pci_config(ahc) 483 struct ahc_softc *ahc; 484 { 485 pcireg_t command; 486 u_int our_id = 0; 487 u_int sxfrctl1; 488 u_int scsiseq; 489 u_int dscommand0; 490 int error; 491 int opri; 492 uint8_t sblkctl; 493 494 495 ahc->chip |= AHC_PCI; 496 #if 0 497 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 498 #endif 499 error = ahc_pci_map_registers(ahc); 500 if (error != 0) 501 return (error); 502 /* 503 * Registers are mapped. Now it is safe to use 504 * the ahc_inb and ahc_outb macros. 505 */ 506 507 /* 508 * Before we continue probing the card, ensure that 509 * its interrupts are *disabled*. We don't want 510 * a misstep to hang the machine in an interrupt 511 * storm. 512 */ 513 ahc_intr_enable(ahc, FALSE); 514 515 /* 516 * If we need to support high memory, enable dual 517 * address cycles. This bit must be set to enable 518 * high address bit generation even if we are on a 519 * 64bit bus (PCI64BIT set in devconfig). 520 */ 521 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 522 pcireg_t devconfig; 523 524 if (bootverbose) 525 printf("%s: Enabling 39Bit Addressing\n", 526 ahc_name(ahc)); 527 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, 4); 528 devconfig |= DACEN; 529 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, 4); 530 } 531 532 /* Ensure busmastering is enabled */ 533 command = ahc_pci_read_config(ahc->dev_softc, PCI_COMMAND_STATUS_REG, 4); 534 command |= PCI_COMMAND_MASTER_ENABLE; 535 536 ahc_pci_write_config(ahc->dev_softc, PCI_COMMAND_STATUS_REG, command, 4); 537 538 /* On all PCI adapters, we allow SCB paging */ 539 ahc->flags |= AHC_PAGESCBS; 540 541 error = ahc_softc_init(ahc); 542 if (error != 0) 543 return (error); 544 545 /* Remember how the card was setup in case there is no SEEPROM */ 546 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 547 ahc_pause(ahc); 548 if ((ahc->features & AHC_ULTRA2) != 0) 549 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 550 else 551 our_id = ahc_inb(ahc, SCSIID) & OID; 552 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 553 scsiseq = ahc_inb(ahc, SCSISEQ); 554 } else { 555 sxfrctl1 = STPWEN; 556 our_id = 7; 557 scsiseq = 0; 558 } 559 560 error = ahc_reset(ahc); 561 if (error != 0) 562 return (ENXIO); 563 564 if ((ahc->features & AHC_DT) != 0) { 565 u_int sfunct; 566 567 /* Perform ALT-Mode Setup */ 568 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 569 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 570 ahc_outb(ahc, OPTIONMODE, 571 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 572 ahc_outb(ahc, SFUNCT, sfunct); 573 574 /* Normal mode setup */ 575 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 576 |TARGCRCENDEN); 577 } 578 579 /* 580 * Protect ourself from spurrious interrupts during 581 * initialization. 582 */ 583 opri = splbio(); 584 585 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 586 dscommand0 |= MPARCKEN|CACHETHEN; 587 if ((ahc->features & AHC_ULTRA2) != 0) { 588 589 /* 590 * DPARCKEN doesn't work correctly on 591 * some MBs so don't use it. 592 */ 593 dscommand0 &= ~DPARCKEN; 594 } 595 596 /* 597 * Handle chips that must have cache line 598 * streaming (dis/en)abled. 599 */ 600 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 601 dscommand0 |= CACHETHEN; 602 603 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 604 dscommand0 &= ~CACHETHEN; 605 606 ahc_outb(ahc, DSCOMMAND0, dscommand0); 607 608 ahc->pci_cachesize = ahc_pci_read_config(ahc->dev_softc, 609 CSIZE_LATTIME, 4) & CACHESIZE; 610 ahc->pci_cachesize *= 4; 611 612 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 613 && ahc->pci_cachesize == 4) { 614 u_int csl = ahc_pci_read_config(ahc->dev_softc, 615 CSIZE_LATTIME, 4); 616 csl &= ~CACHESIZE; 617 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, csl, 4); 618 ahc->pci_cachesize = 0; 619 } 620 621 /* 622 * We cannot perform ULTRA speeds without the presense 623 * of the external precision resistor. 624 */ 625 if ((ahc->features & AHC_ULTRA) != 0) { 626 uint32_t devconfig; 627 628 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, 4); 629 if ((devconfig & REXTVALID) == 0) 630 ahc->features &= ~AHC_ULTRA; 631 } 632 633 /* See if we have a SEEPROM and perform auto-term */ 634 check_extport(ahc, &sxfrctl1); 635 636 /* 637 * Take the LED out of diagnostic mode 638 */ 639 sblkctl = ahc_inb(ahc, SBLKCTL); 640 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 641 642 if ((ahc->features & AHC_ULTRA2) != 0) { 643 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 644 } else { 645 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 646 } 647 648 if (ahc->flags & AHC_USEDEFAULTS) { 649 /* 650 * PCI Adapter default setup 651 * Should only be used if the adapter does not have 652 * a SEEPROM. 653 */ 654 /* See if someone else set us up already */ 655 if (scsiseq != 0) { 656 printf("%s: Using left over BIOS settings\n", 657 ahc_name(ahc)); 658 ahc->flags &= ~AHC_USEDEFAULTS; 659 ahc->flags |= AHC_BIOS_ENABLED; 660 } else { 661 /* 662 * Assume only one connector and always turn 663 * on termination. 664 */ 665 our_id = 0x07; 666 sxfrctl1 = STPWEN; 667 } 668 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 669 670 ahc->our_id = our_id; 671 } 672 673 /* 674 * Take a look to see if we have external SRAM. 675 * We currently do not attempt to use SRAM that is 676 * shared among multiple controllers. 677 */ 678 ahc_probe_ext_scbram(ahc); 679 680 /* 681 * Record our termination setting for the 682 * generic initialization routine. 683 */ 684 if ((sxfrctl1 & STPWEN) != 0) 685 ahc->flags |= AHC_TERM_ENB_A; 686 687 /* Core initialization */ 688 error = ahc_init(ahc); 689 if (error != 0) 690 return (error); 691 692 /* Special func to force negotiation */ 693 ahc_force_neg(ahc); 694 695 /* 696 * Link this softc in with all other ahc instances. 697 */ 698 ahc_softc_insert(ahc); 699 700 /* 701 * Allow interrupts now that we are completely setup. 702 */ 703 error = ahc_pci_map_int(ahc); 704 if (error != 0) 705 return (error); 706 707 ahc_intr_enable(ahc, TRUE); 708 splx(opri); 709 710 return (0); 711 } 712 713 int 714 ahc_pci_map_int(ahc) 715 struct ahc_softc *ahc; 716 { 717 const char *intrstr = NULL; 718 pci_intr_handle_t ih; 719 struct pci_attach_args *pa = ahc->dev_softc; 720 721 if (pci_intr_map(pa, &ih)) { 722 printf(": couldn't map interrupt\n"); 723 return 1; 724 } 725 intrstr = pci_intr_string(pa->pa_pc, ih); 726 727 ahc->platform_data->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 728 ahc_platform_intr, ahc, 729 ahc->sc_dev.dv_xname); 730 731 if (ahc->platform_data->ih == NULL) { 732 printf(": couldn't establish interrupt"); 733 if (intrstr != NULL) 734 printf(" at %s", intrstr); 735 printf("\n"); 736 return 1; 737 } 738 739 if (intrstr != NULL) 740 printf(": %s\n", intrstr); 741 return 0; 742 } 743 744 /* 745 * Test for the presense of external sram in an 746 * "unshared" configuration. 747 */ 748 static int 749 ahc_ext_scbram_present(struct ahc_softc *ahc) 750 { 751 u_int chip; 752 int ramps; 753 int single_user; 754 uint32_t devconfig; 755 756 chip = ahc->chip & AHC_CHIPID_MASK; 757 758 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, 4); 759 760 single_user = (devconfig & MPORTMODE) != 0; 761 762 if ((ahc->features & AHC_ULTRA2) != 0) 763 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 764 else if (chip >= AHC_AIC7870) 765 ramps = (devconfig & RAMPSM) != 0; 766 else 767 ramps = 0; 768 769 if (ramps && single_user) 770 return (1); 771 return (0); 772 } 773 774 /* 775 * Enable external scbram. 776 */ 777 static void 778 ahc_scbram_config(ahc, enable, pcheck, fast, large) 779 struct ahc_softc *ahc; 780 int enable; 781 int pcheck; 782 int fast; 783 int large; 784 { 785 pcireg_t devconfig; 786 787 if (ahc->features & AHC_MULTI_FUNC) { 788 /* 789 * Set the SCB Base addr (highest address bit) 790 * depending on which channel we are. 791 */ 792 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 793 } 794 795 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, 4); 796 if ((ahc->features & AHC_ULTRA2) != 0) { 797 u_int dscommand0; 798 799 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 800 if (enable) 801 dscommand0 &= ~INTSCBRAMSEL; 802 else 803 dscommand0 |= INTSCBRAMSEL; 804 if (large) 805 dscommand0 &= ~USCBSIZE32; 806 else 807 dscommand0 |= USCBSIZE32; 808 ahc_outb(ahc, DSCOMMAND0, dscommand0); 809 } else { 810 if (fast) 811 devconfig &= ~EXTSCBTIME; 812 else 813 devconfig |= EXTSCBTIME; 814 if (enable) 815 devconfig &= ~SCBRAMSEL; 816 else 817 devconfig |= SCBRAMSEL; 818 if (large) 819 devconfig &= ~SCBSIZE32; 820 else 821 devconfig |= SCBSIZE32; 822 } 823 if (pcheck) 824 devconfig |= EXTSCBPEN; 825 else 826 devconfig &= ~EXTSCBPEN; 827 828 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, 4); 829 } 830 831 /* 832 * Take a look to see if we have external SRAM. 833 * We currently do not attempt to use SRAM that is 834 * shared among multiple controllers. 835 */ 836 static void 837 ahc_probe_ext_scbram(ahc) 838 struct ahc_softc *ahc; 839 { 840 int num_scbs; 841 int test_num_scbs; 842 int enable; 843 int pcheck; 844 int fast; 845 int large; 846 847 enable = FALSE; 848 pcheck = FALSE; 849 fast = FALSE; 850 large = FALSE; 851 num_scbs = 0; 852 853 if (ahc_ext_scbram_present(ahc) == 0) 854 goto done; 855 856 /* 857 * Probe for the best parameters to use. 858 */ 859 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 860 num_scbs = ahc_probe_scbs(ahc); 861 if (num_scbs == 0) { 862 /* The SRAM wasn't really present. */ 863 goto done; 864 } 865 enable = TRUE; 866 867 /* 868 * Clear any outstanding parity error 869 * and ensure that parity error reporting 870 * is enabled. 871 */ 872 ahc_outb(ahc, SEQCTL, 0); 873 ahc_outb(ahc, CLRINT, CLRPARERR); 874 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 875 876 /* Now see if we can do parity */ 877 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 878 num_scbs = ahc_probe_scbs(ahc); 879 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 880 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 881 pcheck = TRUE; 882 883 /* Clear any resulting parity error */ 884 ahc_outb(ahc, CLRINT, CLRPARERR); 885 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 886 887 /* Now see if we can do fast timing */ 888 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 889 test_num_scbs = ahc_probe_scbs(ahc); 890 if (test_num_scbs == num_scbs 891 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 892 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 893 fast = TRUE; 894 895 /* 896 * See if we can use large SCBs and still maintain 897 * the same overall count of SCBs. 898 */ 899 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 900 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 901 test_num_scbs = ahc_probe_scbs(ahc); 902 if (test_num_scbs >= num_scbs) { 903 large = TRUE; 904 num_scbs = test_num_scbs; 905 if (num_scbs >= 64) { 906 /* 907 * We have enough space to move the 908 * "busy targets table" into SCB space 909 * and make it qualify all the way to the 910 * lun level. 911 */ 912 ahc->flags |= AHC_SCB_BTT; 913 } 914 } 915 } 916 done: 917 /* 918 * Disable parity error reporting until we 919 * can load instruction ram. 920 */ 921 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 922 /* Clear any latched parity error */ 923 ahc_outb(ahc, CLRINT, CLRPARERR); 924 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 925 if (bootverbose && enable) { 926 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 927 ahc_name(ahc), fast ? "fast" : "slow", 928 pcheck ? ", parity checking enabled" : "", 929 large ? 64 : 32); 930 } 931 ahc_scbram_config(ahc, enable, pcheck, fast, large); 932 } 933 934 /* 935 * Check the external port logic for a serial eeprom 936 * and termination/cable detection contrls. 937 */ 938 static void 939 check_extport(ahc, sxfrctl1) 940 struct ahc_softc *ahc; 941 u_int *sxfrctl1; 942 { 943 struct seeprom_descriptor sd; 944 struct seeprom_config sc; 945 u_int scsi_conf; 946 u_int adapter_control; 947 int have_seeprom; 948 int have_autoterm; 949 950 sd.sd_ahc = ahc; 951 sd.sd_control_offset = SEECTL; 952 sd.sd_status_offset = SEECTL; 953 sd.sd_dataout_offset = SEECTL; 954 955 /* 956 * For some multi-channel devices, the c46 is simply too 957 * small to work. For the other controller types, we can 958 * get our information from either SEEPROM type. Set the 959 * type to start our probe with accordingly. 960 */ 961 if (ahc->flags & AHC_LARGE_SEEPROM) 962 sd.sd_chip = C56_66; 963 else 964 sd.sd_chip = C46; 965 966 sd.sd_MS = SEEMS; 967 sd.sd_RDY = SEERDY; 968 sd.sd_CS = SEECS; 969 sd.sd_CK = SEECK; 970 sd.sd_DO = SEEDO; 971 sd.sd_DI = SEEDI; 972 973 have_seeprom = acquire_seeprom(ahc, &sd); 974 if (have_seeprom) { 975 976 if (bootverbose) 977 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 978 979 for (;;) { 980 u_int start_addr; 981 982 start_addr = 32 * (ahc->channel - 'A'); 983 984 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 985 start_addr, sizeof(sc)/2); 986 987 if (have_seeprom) 988 have_seeprom = verify_cksum(&sc); 989 990 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 991 if (bootverbose) { 992 if (have_seeprom == 0) 993 printf ("checksum error\n"); 994 else 995 printf ("done.\n"); 996 } 997 break; 998 } 999 sd.sd_chip = C56_66; 1000 } 1001 release_seeprom(&sd); 1002 } 1003 1004 if (!have_seeprom) { 1005 /* 1006 * Pull scratch ram settings and treat them as 1007 * if they are the contents of an seeprom if 1008 * the 'ADPT' signature is found in SCB2. 1009 * We manually compose the data as 16bit values 1010 * to avoid endian issues. 1011 */ 1012 ahc_outb(ahc, SCBPTR, 2); 1013 if (ahc_inb(ahc, SCB_BASE) == 'A' 1014 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1015 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1016 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1017 uint16_t *sc_data; 1018 int i; 1019 1020 sc_data = (uint16_t *)≻ 1021 for (i = 0; i < 32; i++) { 1022 uint16_t val; 1023 int j; 1024 1025 j = i * 2; 1026 val = ahc_inb(ahc, SRAM_BASE + j) 1027 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1028 } 1029 have_seeprom = verify_cksum(&sc); 1030 } 1031 /* 1032 * Clear any SCB parity errors in case this data and 1033 * its associated parity was not initialized by the BIOS 1034 */ 1035 ahc_outb(ahc, CLRINT, CLRPARERR); 1036 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1037 } 1038 1039 if (!have_seeprom) { 1040 if (bootverbose) 1041 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1042 ahc->flags |= AHC_USEDEFAULTS; 1043 } else { 1044 /* 1045 * Put the data we've collected down into SRAM 1046 * where ahc_init will find it. 1047 */ 1048 int i; 1049 int max_targ = sc.max_targets & CFMAXTARG; 1050 uint16_t discenable; 1051 uint16_t ultraenb; 1052 1053 discenable = 0; 1054 ultraenb = 0; 1055 if ((sc.adapter_control & CFULTRAEN) != 0) { 1056 /* 1057 * Determine if this adapter has a "newstyle" 1058 * SEEPROM format. 1059 */ 1060 for (i = 0; i < max_targ; i++) { 1061 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1062 ahc->flags |= AHC_NEWEEPROM_FMT; 1063 break; 1064 } 1065 } 1066 } 1067 1068 for (i = 0; i < max_targ; i++) { 1069 u_int scsirate; 1070 uint16_t target_mask; 1071 1072 target_mask = 0x01 << i; 1073 if (sc.device_flags[i] & CFDISC) 1074 discenable |= target_mask; 1075 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1076 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1077 ultraenb |= target_mask; 1078 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1079 ultraenb |= target_mask; 1080 } 1081 if ((sc.device_flags[i] & CFXFER) == 0x04 1082 && (ultraenb & target_mask) != 0) { 1083 /* Treat 10MHz as a non-ultra speed */ 1084 sc.device_flags[i] &= ~CFXFER; 1085 ultraenb &= ~target_mask; 1086 } 1087 if ((ahc->features & AHC_ULTRA2) != 0) { 1088 u_int offset; 1089 1090 if (sc.device_flags[i] & CFSYNCH) 1091 offset = MAX_OFFSET_ULTRA2; 1092 else 1093 offset = 0; 1094 ahc_outb(ahc, TARG_OFFSET + i, offset); 1095 1096 /* 1097 * The ultra enable bits contain the 1098 * high bit of the ultra2 sync rate 1099 * field. 1100 */ 1101 scsirate = (sc.device_flags[i] & CFXFER) 1102 | ((ultraenb & target_mask) 1103 ? 0x8 : 0x0); 1104 if (sc.device_flags[i] & CFWIDEB) 1105 scsirate |= WIDEXFER; 1106 } else { 1107 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1108 if (sc.device_flags[i] & CFSYNCH) 1109 scsirate |= SOFS; 1110 if (sc.device_flags[i] & CFWIDEB) 1111 scsirate |= WIDEXFER; 1112 } 1113 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1114 } 1115 ahc->our_id = sc.brtime_id & CFSCSIID; 1116 1117 scsi_conf = (ahc->our_id & 0x7); 1118 if (sc.adapter_control & CFSPARITY) 1119 scsi_conf |= ENSPCHK; 1120 if (sc.adapter_control & CFRESETB) 1121 scsi_conf |= RESET_SCSI; 1122 1123 ahc->flags |= 1124 (sc.adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1125 1126 if (sc.bios_control & CFEXTEND) 1127 ahc->flags |= AHC_EXTENDED_TRANS_A; 1128 1129 if (sc.bios_control & CFBIOSEN) 1130 ahc->flags |= AHC_BIOS_ENABLED; 1131 if (ahc->features & AHC_ULTRA 1132 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1133 /* Should we enable Ultra mode? */ 1134 if (!(sc.adapter_control & CFULTRAEN)) 1135 /* Treat us as a non-ultra card */ 1136 ultraenb = 0; 1137 } 1138 1139 if (sc.signature == CFSIGNATURE 1140 || sc.signature == CFSIGNATURE2) { 1141 pcireg_t devconfig; 1142 1143 /* Honor the STPWLEVEL settings */ 1144 devconfig = ahc_pci_read_config(ahc->dev_softc, 1145 DEVCONFIG, 4); 1146 devconfig &= ~STPWLEVEL; 1147 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1148 devconfig |= STPWLEVEL; 1149 ahc_pci_write_config(ahc->dev_softc, 1150 DEVCONFIG, devconfig, 4); 1151 } 1152 /* Set SCSICONF info */ 1153 ahc_outb(ahc, SCSICONF, scsi_conf); 1154 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1155 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1156 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1157 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1158 } 1159 1160 /* 1161 * Cards that have the external logic necessary to talk to 1162 * a SEEPROM, are almost certain to have the remaining logic 1163 * necessary for auto-termination control. This assumption 1164 * hasn't failed yet... 1165 */ 1166 have_autoterm = have_seeprom; 1167 if (have_seeprom) 1168 adapter_control = sc.adapter_control; 1169 else 1170 adapter_control = CFAUTOTERM; 1171 1172 /* 1173 * Some low-cost chips have SEEPROM and auto-term control built 1174 * in, instead of using a GAL. They can tell us directly 1175 * if the termination logic is enabled. 1176 */ 1177 if ((ahc->features & AHC_SPIOCAP) != 0) { 1178 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1179 have_autoterm = TRUE; 1180 else 1181 have_autoterm = FALSE; 1182 } 1183 1184 if (have_autoterm) { 1185 acquire_seeprom(ahc, &sd); 1186 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1187 release_seeprom(&sd); 1188 } 1189 } 1190 1191 static void 1192 configure_termination(struct ahc_softc *ahc, 1193 struct seeprom_descriptor *sd, 1194 u_int adapter_control, 1195 u_int *sxfrctl1) 1196 { 1197 uint8_t brddat; 1198 1199 brddat = 0; 1200 1201 /* 1202 * Update the settings in sxfrctl1 to match the 1203 * termination settings 1204 */ 1205 *sxfrctl1 = 0; 1206 1207 /* 1208 * SEECS must be on for the GALS to latch 1209 * the data properly. Be sure to leave MS 1210 * on or we will release the seeprom. 1211 */ 1212 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1213 if ((adapter_control & CFAUTOTERM) != 0 1214 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1215 int internal50_present; 1216 int internal68_present; 1217 int externalcable_present; 1218 int eeprom_present; 1219 int enableSEC_low; 1220 int enableSEC_high; 1221 int enablePRI_low; 1222 int enablePRI_high; 1223 int sum; 1224 1225 enableSEC_low = 0; 1226 enableSEC_high = 0; 1227 enablePRI_low = 0; 1228 enablePRI_high = 0; 1229 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1230 ahc_new_term_detect(ahc, &enableSEC_low, 1231 &enableSEC_high, 1232 &enablePRI_low, 1233 &enablePRI_high, 1234 &eeprom_present); 1235 if ((adapter_control & CFSEAUTOTERM) == 0) { 1236 if (bootverbose) 1237 printf("%s: Manual SE Termination\n", 1238 ahc_name(ahc)); 1239 enableSEC_low = (adapter_control & CFSELOWTERM); 1240 enableSEC_high = 1241 (adapter_control & CFSEHIGHTERM); 1242 } 1243 if ((adapter_control & CFAUTOTERM) == 0) { 1244 if (bootverbose) 1245 printf("%s: Manual LVD Termination\n", 1246 ahc_name(ahc)); 1247 enablePRI_low = (adapter_control & CFSTERM); 1248 enablePRI_high = (adapter_control & CFWSTERM); 1249 } 1250 /* Make the table calculations below happy */ 1251 internal50_present = 0; 1252 internal68_present = 1; 1253 externalcable_present = 1; 1254 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1255 aic785X_cable_detect(ahc, &internal50_present, 1256 &externalcable_present, 1257 &eeprom_present); 1258 } else { 1259 aic787X_cable_detect(ahc, &internal50_present, 1260 &internal68_present, 1261 &externalcable_present, 1262 &eeprom_present); 1263 } 1264 1265 if ((ahc->features & AHC_WIDE) == 0) 1266 internal68_present = 0; 1267 1268 if (bootverbose 1269 && (ahc->features & AHC_ULTRA2) == 0) { 1270 printf("%s: internal 50 cable %s present", 1271 ahc_name(ahc), 1272 internal50_present ? "is":"not"); 1273 1274 if ((ahc->features & AHC_WIDE) != 0) 1275 printf(", internal 68 cable %s present", 1276 internal68_present ? "is":"not"); 1277 printf("\n%s: external cable %s present\n", 1278 ahc_name(ahc), 1279 externalcable_present ? "is":"not"); 1280 } 1281 if (bootverbose) 1282 printf("%s: BIOS eeprom %s present\n", 1283 ahc_name(ahc), eeprom_present ? "is" : "not"); 1284 1285 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1286 /* 1287 * The 50 pin connector is a separate bus, 1288 * so force it to always be terminated. 1289 * In the future, perform current sensing 1290 * to determine if we are in the middle of 1291 * a properly terminated bus. 1292 */ 1293 internal50_present = 0; 1294 } 1295 1296 /* 1297 * Now set the termination based on what 1298 * we found. 1299 * Flash Enable = BRDDAT7 1300 * Secondary High Term Enable = BRDDAT6 1301 * Secondary Low Term Enable = BRDDAT5 (7890) 1302 * Primary High Term Enable = BRDDAT4 (7890) 1303 */ 1304 if ((ahc->features & AHC_ULTRA2) == 0 1305 && (internal50_present != 0) 1306 && (internal68_present != 0) 1307 && (externalcable_present != 0)) { 1308 printf("%s: Illegal cable configuration!!. " 1309 "Only two connectors on the " 1310 "adapter may be used at a " 1311 "time!\n", ahc_name(ahc)); 1312 1313 /* 1314 * Pretend there are no cables in the hope 1315 * that having all of the termination on 1316 * gives us a more stable bus. 1317 */ 1318 internal50_present = 0; 1319 internal68_present = 0; 1320 externalcable_present = 0; 1321 } 1322 1323 if ((ahc->features & AHC_WIDE) != 0 1324 && ((externalcable_present == 0) 1325 || (internal68_present == 0) 1326 || (enableSEC_high != 0))) { 1327 brddat |= BRDDAT6; 1328 if (bootverbose) { 1329 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1330 printf("%s: 68 pin termination " 1331 "Enabled\n", ahc_name(ahc)); 1332 else 1333 printf("%s: %sHigh byte termination " 1334 "Enabled\n", ahc_name(ahc), 1335 enableSEC_high ? "Secondary " 1336 : ""); 1337 } 1338 } 1339 1340 sum = internal50_present + internal68_present 1341 + externalcable_present; 1342 if (sum < 2 || (enableSEC_low != 0)) { 1343 if ((ahc->features & AHC_ULTRA2) != 0) 1344 brddat |= BRDDAT5; 1345 else 1346 *sxfrctl1 |= STPWEN; 1347 if (bootverbose) { 1348 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1349 printf("%s: 50 pin termination " 1350 "Enabled\n", ahc_name(ahc)); 1351 else 1352 printf("%s: %sLow byte termination " 1353 "Enabled\n", ahc_name(ahc), 1354 enableSEC_low ? "Secondary " 1355 : ""); 1356 } 1357 } 1358 1359 if (enablePRI_low != 0) { 1360 *sxfrctl1 |= STPWEN; 1361 if (bootverbose) 1362 printf("%s: Primary Low Byte termination " 1363 "Enabled\n", ahc_name(ahc)); 1364 } 1365 1366 /* 1367 * Setup STPWEN before setting up the rest of 1368 * the termination per the tech note on the U160 cards. 1369 */ 1370 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1371 1372 if (enablePRI_high != 0) { 1373 brddat |= BRDDAT4; 1374 if (bootverbose) 1375 printf("%s: Primary High Byte " 1376 "termination Enabled\n", 1377 ahc_name(ahc)); 1378 } 1379 1380 write_brdctl(ahc, brddat); 1381 1382 } else { 1383 if ((adapter_control & CFSTERM) != 0) { 1384 *sxfrctl1 |= STPWEN; 1385 1386 if (bootverbose) 1387 printf("%s: %sLow byte termination Enabled\n", 1388 ahc_name(ahc), 1389 (ahc->features & AHC_ULTRA2) ? "Primary " 1390 : ""); 1391 } 1392 1393 if ((adapter_control & CFWSTERM) != 0 1394 && (ahc->features & AHC_WIDE) != 0) { 1395 brddat |= BRDDAT6; 1396 if (bootverbose) 1397 printf("%s: %sHigh byte termination Enabled\n", 1398 ahc_name(ahc), 1399 (ahc->features & AHC_ULTRA2) 1400 ? "Secondary " : ""); 1401 } 1402 1403 /* 1404 * Setup STPWEN before setting up the rest of 1405 * the termination per the tech note on the U160 cards. 1406 */ 1407 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1408 1409 if ((ahc->features & AHC_WIDE) != 0) 1410 write_brdctl(ahc, brddat); 1411 } 1412 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1413 } 1414 1415 static void 1416 ahc_new_term_detect(ahc, enableSEC_low, enableSEC_high, enablePRI_low, 1417 enablePRI_high, eeprom_present) 1418 struct ahc_softc *ahc; 1419 int *enableSEC_low; 1420 int *enableSEC_high; 1421 int *enablePRI_low; 1422 int *enablePRI_high; 1423 int *eeprom_present; 1424 { 1425 u_int8_t brdctl; 1426 1427 /* 1428 * BRDDAT7 = Eeprom 1429 * BRDDAT6 = Enable Secondary High Byte termination 1430 * BRDDAT5 = Enable Secondary Low Byte termination 1431 * BRDDAT4 = Enable Primary high byte termination 1432 * BRDDAT3 = Enable Primary low byte termination 1433 */ 1434 brdctl = read_brdctl(ahc); 1435 *eeprom_present = brdctl & BRDDAT7; 1436 *enableSEC_high = (brdctl & BRDDAT6); 1437 *enableSEC_low = (brdctl & BRDDAT5); 1438 *enablePRI_high = (brdctl & BRDDAT4); 1439 *enablePRI_low = (brdctl & BRDDAT3); 1440 } 1441 1442 static void 1443 aic787X_cable_detect(ahc, internal50_present, internal68_present, 1444 externalcable_present, eeprom_present) 1445 struct ahc_softc *ahc; 1446 int *internal50_present; 1447 int *internal68_present; 1448 int *externalcable_present; 1449 int *eeprom_present; 1450 { 1451 u_int8_t brdctl; 1452 1453 /* 1454 * First read the status of our cables. 1455 * Set the rom bank to 0 since the 1456 * bank setting serves as a multiplexor 1457 * for the cable detection logic. 1458 * BRDDAT5 controls the bank switch. 1459 */ 1460 write_brdctl(ahc, 0); 1461 1462 /* 1463 * Now read the state of the internal 1464 * connectors. BRDDAT6 is INT50 and 1465 * BRDDAT7 is INT68. 1466 */ 1467 brdctl = read_brdctl(ahc); 1468 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1469 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1470 1471 /* 1472 * Set the rom bank to 1 and determine 1473 * the other signals. 1474 */ 1475 write_brdctl(ahc, BRDDAT5); 1476 1477 /* 1478 * Now read the state of the external 1479 * connectors. BRDDAT6 is EXT68 and 1480 * BRDDAT7 is EPROMPS. 1481 */ 1482 brdctl = read_brdctl(ahc); 1483 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1484 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1485 } 1486 1487 static void 1488 aic785X_cable_detect(ahc, internal50_present, externalcable_present, 1489 eeprom_present) 1490 struct ahc_softc *ahc; 1491 int *internal50_present; 1492 int *externalcable_present; 1493 int *eeprom_present; 1494 { 1495 u_int8_t brdctl; 1496 1497 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1498 ahc_outb(ahc, BRDCTL, 0); 1499 brdctl = ahc_inb(ahc, BRDCTL); 1500 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1501 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1502 1503 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1504 } 1505 1506 static void 1507 write_brdctl(ahc, value) 1508 struct ahc_softc *ahc; 1509 u_int8_t value; 1510 { 1511 u_int8_t brdctl; 1512 1513 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1514 brdctl = BRDSTB; 1515 if (ahc->channel == 'B') 1516 brdctl |= BRDCS; 1517 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1518 brdctl = 0; 1519 } else { 1520 brdctl = BRDSTB|BRDCS; 1521 } 1522 ahc_outb(ahc, BRDCTL, brdctl); 1523 ahc_flush_device_writes(ahc); 1524 brdctl |= value; 1525 ahc_outb(ahc, BRDCTL, brdctl); 1526 ahc_flush_device_writes(ahc); 1527 if ((ahc->features & AHC_ULTRA2) != 0) 1528 brdctl |= BRDSTB_ULTRA2; 1529 else 1530 brdctl &= ~BRDSTB; 1531 ahc_outb(ahc, BRDCTL, brdctl); 1532 ahc_flush_device_writes(ahc); 1533 if ((ahc->features & AHC_ULTRA2) != 0) 1534 brdctl = 0; 1535 else 1536 brdctl &= ~BRDCS; 1537 ahc_outb(ahc, BRDCTL, brdctl); 1538 } 1539 1540 static u_int8_t 1541 read_brdctl(ahc) 1542 struct ahc_softc *ahc; 1543 { 1544 u_int8_t brdctl; 1545 u_int8_t value; 1546 1547 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1548 brdctl = BRDRW; 1549 if (ahc->channel == 'B') 1550 brdctl |= BRDCS; 1551 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1552 brdctl = BRDRW_ULTRA2; 1553 } else { 1554 brdctl = BRDRW|BRDCS; 1555 } 1556 ahc_outb(ahc, BRDCTL, brdctl); 1557 ahc_flush_device_writes(ahc); 1558 value = ahc_inb(ahc, BRDCTL); 1559 ahc_outb(ahc, BRDCTL, 0); 1560 return (value); 1561 } 1562 1563 static int 1564 acquire_seeprom(ahc, sd) 1565 struct ahc_softc *ahc; 1566 struct seeprom_descriptor *sd; 1567 { 1568 int wait; 1569 1570 if ((ahc->features & AHC_SPIOCAP) != 0 1571 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1572 return (0); 1573 1574 /* 1575 * Request access of the memory port. When access is 1576 * granted, SEERDY will go high. We use a 1 second 1577 * timeout which should be near 1 second more than 1578 * is needed. Reason: after the chip reset, there 1579 * should be no contention. 1580 */ 1581 SEEPROM_OUTB(sd, sd->sd_MS); 1582 wait = 1000; /* 1 second timeout in msec */ 1583 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1584 DELAY(1000); /* delay 1 msec */ 1585 } 1586 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1587 SEEPROM_OUTB(sd, 0); 1588 return (0); 1589 } 1590 return (1); 1591 } 1592 1593 static void 1594 release_seeprom(sd) 1595 struct seeprom_descriptor *sd; 1596 { 1597 /* Release access to the memory port and the serial EEPROM. */ 1598 SEEPROM_OUTB(sd, 0); 1599 } 1600 1601 #define DPE PCI_STATUS_PARITY_DETECT 1602 #define SSE PCI_STATUS_SPECIAL_ERROR 1603 #define RMA PCI_STATUS_MASTER_ABORT 1604 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 1605 #define STA PCI_STATUS_TARGET_TARGET_ABORT 1606 #define DPR PCI_STATUS_PARITY_ERROR 1607 1608 #define PCIDEBUG 1609 #ifdef PCIDEBUG 1610 #define PCI_PRINT(Printstuff) printf Printstuff 1611 #else 1612 #define PCI_PRINT(Printstuff) 1613 #endif 1614 1615 void 1616 ahc_pci_intr(ahc) 1617 struct ahc_softc *ahc; 1618 { 1619 pcireg_t status1; 1620 1621 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1622 return; 1623 PCI_PRINT(("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1624 ahc_name(ahc), 1625 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8))); 1626 1627 status1 = ahc_pci_read_config(ahc->dev_softc, PCI_COMMAND_STATUS_REG, 4); 1628 1629 /* define AHC_SHOW_PCI_ERRORS to get painful errors on your i386 console */ 1630 #ifdef AHC_SHOW_PCI_ERRORS 1631 if (status1 & DPE) { 1632 PCI_PRINT(("%s: Data Parity Error Detected during address " 1633 "or write data phase\n", ahc_name(ahc))); 1634 } 1635 #endif 1636 if (status1 & SSE) { 1637 PCI_PRINT(("%s: Signal System Error Detected\n", ahc_name(ahc))); 1638 } 1639 if (status1 & RMA) { 1640 PCI_PRINT(("%s: Received a Master Abort\n", ahc_name(ahc))); 1641 } 1642 if (status1 & RTA) { 1643 PCI_PRINT(("%s: Received a Target Abort\n", ahc_name(ahc))); 1644 } 1645 if (status1 & STA) { 1646 PCI_PRINT(("%s: Signaled a Target Abort\n", ahc_name(ahc))); 1647 } 1648 if (status1 & DPR) { 1649 PCI_PRINT(("%s: Data Parity Error has been reported via PERR#\n", 1650 ahc_name(ahc))); 1651 } 1652 1653 ahc_pci_write_config(ahc->dev_softc, PCI_COMMAND_STATUS_REG, status1, 4); 1654 1655 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1656 printf("%s: Latched PCIERR interrupt with " 1657 "no status bits set\n", ahc_name(ahc)); 1658 } else { 1659 ahc_outb(ahc, CLRINT, CLRPARERR); 1660 } 1661 1662 ahc_unpause(ahc); 1663 1664 return; 1665 } 1666