1 /* $OpenBSD: ahc_pci.c,v 1.50 2006/07/11 18:48:27 kettenis Exp $ */ 2 /* 3 * Product specific probe and attach routines for: 4 * 3940, 2940, aic7895, aic7890, aic7880, 5 * aic7870, aic7860 and aic7850 SCSI controllers 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2001 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * $Id: ahc_pci.c,v 1.50 2006/07/11 18:48:27 kettenis Exp $ 44 * 45 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $ 46 * 47 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $ 48 */ 49 /* 50 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003 51 */ 52 53 #include <sys/cdefs.h> 54 /* __KERNEL_RCSID(0, "$NetBSD: ahc_pci.c,v 1.43 2003/08/18 09:16:22 taca Exp $"); */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/queue.h> 61 #include <sys/device.h> 62 #include <sys/reboot.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 71 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 72 73 #include <dev/ic/aic7xxx_openbsd.h> 74 #include <dev/ic/aic7xxx_inline.h> 75 76 #include <dev/ic/smc93cx6var.h> 77 78 #ifndef __i386__ 79 #define AHC_ALLOW_MEMIO 80 #endif 81 82 static __inline uint64_t 83 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 84 { 85 uint64_t id; 86 87 id = subvendor 88 | (subdevice << 16) 89 | ((uint64_t)vendor << 32) 90 | ((uint64_t)device << 48); 91 92 return (id); 93 } 94 95 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 96 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 97 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 98 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull 99 #define ID_9005_SISL_ID 0x0005900500000000ull 100 #define ID_AIC7850 0x5078900400000000ull 101 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull 102 #define ID_AIC7855 0x5578900400000000ull 103 #define ID_AIC7859 0x3860900400000000ull 104 #define ID_AHA_2930CU 0x3860900438699004ull 105 #define ID_AIC7860 0x6078900400000000ull 106 #define ID_AIC7860C 0x6078900478609004ull 107 #define ID_AHA_1480A 0x6075900400000000ull 108 #define ID_AHA_2940AU_0 0x6178900400000000ull 109 #define ID_AHA_2940AU_1 0x6178900478619004ull 110 #define ID_AHA_2940AU_CN 0x2178900478219004ull 111 #define ID_AHA_2930C_VAR 0x6038900438689004ull 112 113 #define ID_AIC7870 0x7078900400000000ull 114 #define ID_AHA_2940 0x7178900400000000ull 115 #define ID_AHA_3940 0x7278900400000000ull 116 #define ID_AHA_398X 0x7378900400000000ull 117 #define ID_AHA_2944 0x7478900400000000ull 118 #define ID_AHA_3944 0x7578900400000000ull 119 #define ID_AHA_4944 0x7678900400000000ull 120 121 #define ID_AIC7880 0x8078900400000000ull 122 #define ID_AIC7880_B 0x8078900478809004ull 123 #define ID_AHA_2940U 0x8178900400000000ull 124 #define ID_AHA_3940U 0x8278900400000000ull 125 #define ID_AHA_2944U 0x8478900400000000ull 126 #define ID_AHA_3944U 0x8578900400000000ull 127 #define ID_AHA_398XU 0x8378900400000000ull 128 #define ID_AHA_4944U 0x8678900400000000ull 129 #define ID_AHA_2940UB 0x8178900478819004ull 130 #define ID_AHA_2930U 0x8878900478889004ull 131 #define ID_AHA_2940U_PRO 0x8778900478879004ull 132 #define ID_AHA_2940U_CN 0x0078900478009004ull 133 134 #define ID_AIC7895 0x7895900478959004ull 135 #define ID_AIC7895_ARO 0x7890900478939004ull 136 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull 137 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 138 #define ID_AHA_3940AU 0x7895900478929004ull 139 #define ID_AHA_3944AU 0x7895900478949004ull 140 141 #define ID_AIC7890 0x001F9005000F9005ull 142 #define ID_AIC7890_ARO 0x00139005000F9005ull 143 #define ID_AAA_131U2 0x0013900500039005ull 144 #define ID_AHA_2930U2 0x0011900501819005ull 145 #define ID_AHA_2940U2B 0x00109005A1009005ull 146 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 147 #define ID_AHA_2940U2 0x00109005A1809005ull 148 #define ID_AHA_2950U2B 0x00109005E1009005ull 149 150 #define ID_AIC7892 0x008F9005FFFF9005ull 151 #define ID_AIC7892_ARO 0x00839005FFFF9005ull 152 #define ID_AHA_2915LP 0x0082900502109005ull 153 #define ID_AHA_29160 0x00809005E2A09005ull 154 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 155 #define ID_AHA_29160N 0x0080900562A09005ull 156 #define ID_AHA_29160C 0x0080900562209005ull 157 #define ID_AHA_29160B 0x00809005E2209005ull 158 #define ID_AHA_19160B 0x0081900562A19005ull 159 160 #define ID_AIC7896 0x005F9005FFFF9005ull 161 #define ID_AIC7896_ARO 0x00539005FFFF9005ull 162 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 163 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 164 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 165 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 166 167 #define ID_AIC7899 0x00CF9005FFFF9005ull 168 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull 169 #define ID_AHA_3960D 0x00C09005F6209005ull 170 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 171 172 #define ID_AIC7810 0x1078900400000000ull 173 #define ID_AIC7815 0x7815900400000000ull 174 175 #define DEVID_9005_TYPE(id) ((id) & 0xF) 176 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 177 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 178 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 179 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 180 181 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 182 #define DEVID_9005_MAXRATE_U160 0x0 183 #define DEVID_9005_MAXRATE_ULTRA2 0x1 184 #define DEVID_9005_MAXRATE_ULTRA 0x2 185 #define DEVID_9005_MAXRATE_FAST 0x3 186 187 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 188 189 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 190 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 191 192 #define SUBID_9005_TYPE(id) ((id) & 0xF) 193 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 194 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 195 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 196 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 197 198 #define SUBID_9005_TYPE_KNOWN(id) \ 199 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 200 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 201 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 202 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 203 204 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 205 #define SUBID_9005_MAXRATE_ULTRA2 0x0 206 #define SUBID_9005_MAXRATE_ULTRA 0x1 207 #define SUBID_9005_MAXRATE_U160 0x2 208 #define SUBID_9005_MAXRATE_RESERVED 0x3 209 210 #define SUBID_9005_SEEPTYPE(id) \ 211 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 212 ? ((id) & 0xC0) >> 6 \ 213 : ((id) & 0x300) >> 8) 214 #define SUBID_9005_SEEPTYPE_NONE 0x0 215 #define SUBID_9005_SEEPTYPE_1K 0x1 216 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 217 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 218 #define SUBID_9005_AUTOTERM(id) \ 219 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 220 ? (((id) & 0x400) >> 10) == 0 \ 221 : (((id) & 0x40) >> 6) == 0) 222 223 #define SUBID_9005_NUMCHAN(id) \ 224 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 225 ? ((id) & 0x300) >> 8 \ 226 : ((id) & 0xC00) >> 10) 227 228 #define SUBID_9005_LEGACYCONN(id) \ 229 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 230 ? 0 \ 231 : ((id) & 0x80) >> 7) 232 233 #define SUBID_9005_MFUNCENB(id) \ 234 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 235 ? ((id) & 0x800) >> 11 \ 236 : ((id) & 0x1000) >> 12) 237 /* 238 * Informational only. Should use chip register to be 239 * certain, but may be use in identification strings. 240 */ 241 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 242 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 243 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 244 245 static ahc_device_setup_t ahc_aic785X_setup; 246 static ahc_device_setup_t ahc_aic7860_setup; 247 static ahc_device_setup_t ahc_apa1480_setup; 248 static ahc_device_setup_t ahc_aic7870_setup; 249 static ahc_device_setup_t ahc_aha394X_setup; 250 static ahc_device_setup_t ahc_aha494X_setup; 251 static ahc_device_setup_t ahc_aha398X_setup; 252 static ahc_device_setup_t ahc_aic7880_setup; 253 static ahc_device_setup_t ahc_aha2940Pro_setup; 254 static ahc_device_setup_t ahc_aha394XU_setup; 255 static ahc_device_setup_t ahc_aha398XU_setup; 256 static ahc_device_setup_t ahc_aic7890_setup; 257 static ahc_device_setup_t ahc_aic7892_setup; 258 static ahc_device_setup_t ahc_aic7895_setup; 259 static ahc_device_setup_t ahc_aic7896_setup; 260 static ahc_device_setup_t ahc_aic7899_setup; 261 static ahc_device_setup_t ahc_aha29160C_setup; 262 static ahc_device_setup_t ahc_raid_setup; 263 static ahc_device_setup_t ahc_aha394XX_setup; 264 static ahc_device_setup_t ahc_aha494XX_setup; 265 static ahc_device_setup_t ahc_aha398XX_setup; 266 267 struct ahc_pci_identity ahc_pci_ident_table [] = 268 { 269 /* aic7850 based controllers */ 270 { 271 ID_AHA_2902_04_10_15_20_30C, 272 ID_ALL_MASK, 273 ahc_aic785X_setup 274 }, 275 /* aic7860 based controllers */ 276 { 277 ID_AHA_2930CU, 278 ID_ALL_MASK, 279 ahc_aic7860_setup 280 }, 281 { 282 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 283 ID_DEV_VENDOR_MASK, 284 ahc_apa1480_setup 285 }, 286 { 287 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 288 ID_DEV_VENDOR_MASK, 289 ahc_aic7860_setup 290 }, 291 { 292 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 ahc_aic7860_setup 295 }, 296 { 297 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 298 ID_DEV_VENDOR_MASK, 299 ahc_aic7860_setup 300 }, 301 /* aic7870 based controllers */ 302 { 303 ID_AHA_2940, 304 ID_ALL_MASK, 305 ahc_aic7870_setup 306 }, 307 { 308 ID_AHA_3940, 309 ID_ALL_MASK, 310 ahc_aha394X_setup 311 }, 312 { 313 ID_AHA_398X, 314 ID_ALL_MASK, 315 ahc_aha398X_setup 316 }, 317 { 318 ID_AHA_2944, 319 ID_ALL_MASK, 320 ahc_aic7870_setup 321 }, 322 { 323 ID_AHA_3944, 324 ID_ALL_MASK, 325 ahc_aha394X_setup 326 }, 327 { 328 ID_AHA_4944, 329 ID_ALL_MASK, 330 ahc_aha494X_setup 331 }, 332 /* aic7880 based controllers */ 333 { 334 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 335 ID_DEV_VENDOR_MASK, 336 ahc_aic7880_setup 337 }, 338 { 339 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 340 ID_DEV_VENDOR_MASK, 341 ahc_aha394XU_setup 342 }, 343 { 344 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 345 ID_DEV_VENDOR_MASK, 346 ahc_aic7880_setup 347 }, 348 { 349 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 350 ID_DEV_VENDOR_MASK, 351 ahc_aha394XU_setup 352 }, 353 { 354 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 355 ID_DEV_VENDOR_MASK, 356 ahc_aha398XU_setup 357 }, 358 { 359 /* 360 * XXX Don't know the slot numbers 361 * so we can't identify channels 362 */ 363 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 364 ID_DEV_VENDOR_MASK, 365 ahc_aic7880_setup 366 }, 367 { 368 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 369 ID_DEV_VENDOR_MASK, 370 ahc_aic7880_setup 371 }, 372 { 373 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 374 ID_DEV_VENDOR_MASK, 375 ahc_aha2940Pro_setup 376 }, 377 { 378 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 379 ID_DEV_VENDOR_MASK, 380 ahc_aic7880_setup 381 }, 382 /* Ignore all SISL (AAC on MB) based controllers. */ 383 { 384 ID_9005_SISL_ID, 385 ID_9005_SISL_MASK, 386 NULL 387 }, 388 /* aic7890 based controllers */ 389 { 390 ID_AHA_2930U2, 391 ID_ALL_MASK, 392 ahc_aic7890_setup 393 }, 394 { 395 ID_AHA_2940U2B, 396 ID_ALL_MASK, 397 ahc_aic7890_setup 398 }, 399 { 400 ID_AHA_2940U2_OEM, 401 ID_ALL_MASK, 402 ahc_aic7890_setup 403 }, 404 { 405 ID_AHA_2940U2, 406 ID_ALL_MASK, 407 ahc_aic7890_setup 408 }, 409 { 410 ID_AHA_2950U2B, 411 ID_ALL_MASK, 412 ahc_aic7890_setup 413 }, 414 { 415 ID_AIC7890_ARO, 416 ID_ALL_MASK, 417 ahc_aic7890_setup 418 }, 419 { 420 ID_AAA_131U2, 421 ID_ALL_MASK, 422 ahc_aic7890_setup 423 }, 424 /* aic7892 based controllers */ 425 { 426 ID_AHA_29160, 427 ID_ALL_MASK, 428 ahc_aic7892_setup 429 }, 430 { 431 ID_AHA_29160_CPQ, 432 ID_ALL_MASK, 433 ahc_aic7892_setup 434 }, 435 { 436 ID_AHA_29160N, 437 ID_ALL_MASK, 438 ahc_aic7892_setup 439 }, 440 { 441 ID_AHA_29160C, 442 ID_ALL_MASK, 443 ahc_aha29160C_setup 444 }, 445 { 446 ID_AHA_29160B, 447 ID_ALL_MASK, 448 ahc_aic7892_setup 449 }, 450 { 451 ID_AHA_19160B, 452 ID_ALL_MASK, 453 ahc_aic7892_setup 454 }, 455 { 456 ID_AIC7892_ARO, 457 ID_ALL_MASK, 458 ahc_aic7892_setup 459 }, 460 { 461 ID_AHA_2915LP, 462 ID_ALL_MASK, 463 ahc_aic7892_setup 464 }, 465 /* aic7895 based controllers */ 466 { 467 ID_AHA_2940U_DUAL, 468 ID_ALL_MASK, 469 ahc_aic7895_setup 470 }, 471 { 472 ID_AHA_3940AU, 473 ID_ALL_MASK, 474 ahc_aic7895_setup 475 }, 476 { 477 ID_AHA_3944AU, 478 ID_ALL_MASK, 479 ahc_aic7895_setup 480 }, 481 { 482 ID_AIC7895_ARO, 483 ID_AIC7895_ARO_MASK, 484 ahc_aic7895_setup 485 }, 486 /* aic7896/97 based controllers */ 487 { 488 ID_AHA_3950U2B_0, 489 ID_ALL_MASK, 490 ahc_aic7896_setup 491 }, 492 { 493 ID_AHA_3950U2B_1, 494 ID_ALL_MASK, 495 ahc_aic7896_setup 496 }, 497 { 498 ID_AHA_3950U2D_0, 499 ID_ALL_MASK, 500 ahc_aic7896_setup 501 }, 502 { 503 ID_AHA_3950U2D_1, 504 ID_ALL_MASK, 505 ahc_aic7896_setup 506 }, 507 { 508 ID_AIC7896_ARO, 509 ID_ALL_MASK, 510 ahc_aic7896_setup 511 }, 512 /* aic7899 based controllers */ 513 { 514 ID_AHA_3960D, 515 ID_ALL_MASK, 516 ahc_aic7899_setup 517 }, 518 { 519 ID_AHA_3960D_CPQ, 520 ID_ALL_MASK, 521 ahc_aic7899_setup 522 }, 523 { 524 ID_AIC7899_ARO, 525 ID_ALL_MASK, 526 ahc_aic7899_setup 527 }, 528 /* Generic chip probes for devices we don't know 'exactly' */ 529 { 530 ID_AIC7850 & ID_DEV_VENDOR_MASK, 531 ID_DEV_VENDOR_MASK, 532 ahc_aic785X_setup 533 }, 534 { 535 ID_AIC7855 & ID_DEV_VENDOR_MASK, 536 ID_DEV_VENDOR_MASK, 537 ahc_aic785X_setup 538 }, 539 { 540 ID_AIC7859 & ID_DEV_VENDOR_MASK, 541 ID_DEV_VENDOR_MASK, 542 ahc_aic7860_setup 543 }, 544 { 545 ID_AIC7860 & ID_DEV_VENDOR_MASK, 546 ID_DEV_VENDOR_MASK, 547 ahc_aic7860_setup 548 }, 549 { 550 ID_AIC7870 & ID_DEV_VENDOR_MASK, 551 ID_DEV_VENDOR_MASK, 552 ahc_aic7870_setup 553 }, 554 { 555 ID_AIC7880 & ID_DEV_VENDOR_MASK, 556 ID_DEV_VENDOR_MASK, 557 ahc_aic7880_setup 558 }, 559 { 560 ID_AIC7890 & ID_9005_GENERIC_MASK, 561 ID_9005_GENERIC_MASK, 562 ahc_aic7890_setup 563 }, 564 { 565 ID_AIC7892 & ID_9005_GENERIC_MASK, 566 ID_9005_GENERIC_MASK, 567 ahc_aic7892_setup 568 }, 569 { 570 ID_AIC7895 & ID_DEV_VENDOR_MASK, 571 ID_DEV_VENDOR_MASK, 572 ahc_aic7895_setup 573 }, 574 { 575 ID_AIC7896 & ID_9005_GENERIC_MASK, 576 ID_9005_GENERIC_MASK, 577 ahc_aic7896_setup 578 }, 579 { 580 ID_AIC7899 & ID_9005_GENERIC_MASK, 581 ID_9005_GENERIC_MASK, 582 ahc_aic7899_setup 583 }, 584 { 585 ID_AIC7810 & ID_DEV_VENDOR_MASK, 586 ID_DEV_VENDOR_MASK, 587 ahc_raid_setup 588 }, 589 { 590 ID_AIC7815 & ID_DEV_VENDOR_MASK, 591 ID_DEV_VENDOR_MASK, 592 ahc_raid_setup 593 } 594 }; 595 596 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 597 598 #define AHC_394X_SLOT_CHANNEL_A 4 599 #define AHC_394X_SLOT_CHANNEL_B 5 600 601 #define AHC_398X_SLOT_CHANNEL_A 4 602 #define AHC_398X_SLOT_CHANNEL_B 8 603 #define AHC_398X_SLOT_CHANNEL_C 12 604 605 #define AHC_494X_SLOT_CHANNEL_A 4 606 #define AHC_494X_SLOT_CHANNEL_B 5 607 #define AHC_494X_SLOT_CHANNEL_C 6 608 #define AHC_494X_SLOT_CHANNEL_D 7 609 610 #define DEVCONFIG 0x40 611 #define PCIERRGENDIS 0x80000000ul 612 #define SCBSIZE32 0x00010000ul /* aic789X only */ 613 #define REXTVALID 0x00001000ul /* ultra cards only */ 614 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 615 #define RAMPSM 0x00000200ul /* aic7870+ only */ 616 #define VOLSENSE 0x00000100ul 617 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 618 #define SCBRAMSEL 0x00000080ul 619 #define MRDCEN 0x00000040ul 620 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 621 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 622 #define BERREN 0x00000008ul 623 #define DACEN 0x00000004ul 624 #define STPWLEVEL 0x00000002ul 625 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 626 627 #define CSIZE_LATTIME 0x0c 628 #define CACHESIZE 0x0000003ful /* only 5 bits */ 629 #define LATTIME 0x0000ff00ul 630 631 /* PCI STATUS definitions */ 632 #define DPE 0x80 633 #define SSE 0x40 634 #define RMA 0x20 635 #define RTA 0x10 636 #define STA 0x08 637 #define DPR 0x01 638 639 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 640 uint16_t subvendor, uint16_t subdevice); 641 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 642 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 643 int pcheck, int fast, int large); 644 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 645 static int ahc_pci_chip_init(struct ahc_softc *ahc); 646 647 int ahc_pci_probe(struct device *, void *, void *); 648 void ahc_pci_attach(struct device *, struct device *, void *); 649 650 651 struct cfattach ahc_pci_ca = { 652 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 653 }; 654 655 const struct ahc_pci_identity * 656 ahc_find_pci_device(id, subid, func) 657 pcireg_t id, subid; 658 u_int func; 659 { 660 u_int64_t full_id; 661 const struct ahc_pci_identity *entry; 662 u_int i; 663 664 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id), 665 PCI_PRODUCT(subid), PCI_VENDOR(subid)); 666 667 /* 668 * If the second function is not hooked up, ignore it. 669 * Unfortunately, not all MB vendors implement the 670 * subdevice ID as per the Adaptec spec, so do our best 671 * to sanity check it prior to accepting the subdevice 672 * ID as valid. 673 */ 674 if (func > 0 675 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), 676 PCI_VENDOR(subid), PCI_PRODUCT(subid)) 677 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) 678 return (NULL); 679 680 for (i = 0; i < ahc_num_pci_devs; i++) { 681 entry = &ahc_pci_ident_table[i]; 682 if (entry->full_id == (full_id & entry->id_mask)) 683 return (entry); 684 } 685 return (NULL); 686 } 687 688 int 689 ahc_pci_probe(parent, match, aux) 690 struct device *parent; 691 void *match, *aux; 692 { 693 struct pci_attach_args *pa = aux; 694 const struct ahc_pci_identity *entry; 695 pcireg_t subid; 696 697 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 698 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 699 return (entry != NULL && entry->setup != NULL) ? 1 : 0; 700 } 701 702 void 703 ahc_pci_attach(parent, self, aux) 704 struct device *parent, *self; 705 void *aux; 706 { 707 struct pci_attach_args *pa = aux; 708 const struct ahc_pci_identity *entry; 709 struct ahc_softc *ahc = (void *)self; 710 pcireg_t command; 711 u_int our_id = 0; 712 u_int sxfrctl1; 713 u_int scsiseq; 714 u_int sblkctl; 715 uint8_t dscommand0; 716 uint32_t devconfig; 717 int error; 718 pcireg_t subid; 719 int ioh_valid; 720 bus_space_tag_t st, iot; 721 bus_space_handle_t sh, ioh; 722 #ifdef AHC_ALLOW_MEMIO 723 int memh_valid; 724 bus_space_tag_t memt; 725 bus_space_handle_t memh; 726 pcireg_t memtype; 727 #endif 728 pci_intr_handle_t ih; 729 const char *intrstr; 730 struct ahc_pci_busdata *bd; 731 int i; 732 733 /* 734 * Instead of ahc_alloc() as in FreeBSD, do the few relevant 735 * initializations manually. 736 */ 737 LIST_INIT(&ahc->pending_scbs); 738 ahc->channel = 'A'; 739 ahc->seqctl = FASTMODE; 740 for (i = 0; i < AHC_NUM_TARGETS; i++) 741 TAILQ_INIT(&ahc->untagged_queues[i]); 742 743 /* 744 * SCSI_IS_SCSIBUS_B() must returns false until sc_channel_b 745 * has been properly initialized. XXX Breaks if >254 scsi buses. 746 */ 747 ahc->sc_channel_b.scsibus = 0xff; 748 749 ahc->dev_softc = pa; 750 751 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 752 ahc->parent_dmat = pa->pa_dmat; 753 754 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function); 756 if (entry == NULL) 757 return; 758 759 /* Keep information about the PCI bus */ 760 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF, M_NOWAIT); 761 if (bd == NULL) { 762 printf("%s: unable to allocate bus-specific data\n", ahc_name(ahc)); 763 return; 764 } 765 memset(bd, 0, sizeof(struct ahc_pci_busdata)); 766 767 bd->pc = pa->pa_pc; 768 bd->tag = pa->pa_tag; 769 bd->func = pa->pa_function; 770 bd->dev = pa->pa_device; 771 bd->class = pa->pa_class; 772 773 ahc->bd = bd; 774 775 error = entry->setup(ahc); 776 if (error != 0) 777 return; 778 779 ioh_valid = 0; 780 781 #ifdef AHC_ALLOW_MEMIO 782 memh_valid = 0; 783 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 784 switch (memtype) { 785 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 786 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 787 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 788 memtype, 0, &memt, &memh, NULL, NULL, 0) == 0); 789 break; 790 default: 791 memh_valid = 0; 792 } 793 if (memh_valid == 0) 794 #endif 795 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 796 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0); 797 #if 0 798 printf("%s: mem mapping: memt 0x%x, memh 0x%x, iot 0x%x, ioh 0x%lx\n", 799 ahc_name(ahc), memt, (u_int32_t)memh, (u_int32_t)iot, ioh); 800 #endif 801 802 if (ioh_valid) { 803 st = iot; 804 sh = ioh; 805 #ifdef AHC_ALLOW_MEMIO 806 } else if (memh_valid) { 807 st = memt; 808 sh = memh; 809 #endif 810 } else { 811 printf(": unable to map registers\n"); 812 return; 813 } 814 ahc->tag = st; 815 ahc->bsh = sh; 816 817 ahc->chip |= AHC_PCI; 818 /* 819 * Before we continue probing the card, ensure that 820 * its interrupts are *disabled*. We don't want 821 * a misstep to hang the machine in an interrupt 822 * storm. 823 */ 824 ahc_intr_enable(ahc, FALSE); 825 826 /* 827 * XXX somehow reading this once fails on some sparc64 systems. 828 * This may be a problem in the sparc64 PCI code. Doing it 829 * twice works around it. 830 */ 831 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 832 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 833 834 /* 835 * If we need to support high memory, enable dual 836 * address cycles. This bit must be set to enable 837 * high address bit generation even if we are on a 838 * 64bit bus (PCI64BIT set in devconfig). 839 */ 840 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 841 842 if (1/*bootverbose*/) 843 printf("%s: Enabling 39Bit Addressing\n", 844 ahc_name(ahc)); 845 devconfig |= DACEN; 846 } 847 848 /* Ensure that pci error generation, a test feature, is disabled. */ 849 devconfig |= PCIERRGENDIS; 850 851 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); 852 853 /* 854 * Disable PCI parity error reporting. Users typically 855 * do this to work around broken PCI chipsets that get 856 * the parity timing wrong and thus generate lots of spurious 857 * errors. 858 */ 859 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) { 860 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 861 PCI_COMMAND_STATUS_REG); 862 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 863 command & ~PCI_COMMAND_PARITY_ENABLE); 864 } 865 866 /* On all PCI adapters, we allow SCB paging */ 867 ahc->flags |= AHC_PAGESCBS; 868 error = ahc_softc_init(ahc); 869 if (error != 0) 870 goto error_out; 871 872 ahc->bus_intr = ahc_pci_intr; 873 ahc->bus_chip_init = ahc_pci_chip_init; 874 875 /* Remember how the card was setup in case there is no SEEPROM */ 876 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 877 ahc_pause(ahc); 878 if ((ahc->features & AHC_ULTRA2) != 0) 879 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 880 else 881 our_id = ahc_inb(ahc, SCSIID) & OID; 882 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 883 scsiseq = ahc_inb(ahc, SCSISEQ); 884 } else { 885 sxfrctl1 = STPWEN; 886 our_id = 7; 887 scsiseq = 0; 888 } 889 890 error = ahc_reset(ahc, /*reinit*/FALSE); 891 if (error != 0) 892 goto error_out; 893 894 if ((ahc->features & AHC_DT) != 0) { 895 u_int sfunct; 896 897 /* Perform ALT-Mode Setup */ 898 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 899 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 900 ahc_outb(ahc, OPTIONMODE, 901 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 902 ahc_outb(ahc, SFUNCT, sfunct); 903 904 /* Normal mode setup */ 905 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 906 |TARGCRCENDEN); 907 } 908 909 if (pci_intr_map(pa, &ih)) { 910 printf("%s: couldn't map interrupt\n", ahc_name(ahc)); 911 ahc_free(ahc); 912 return; 913 } 914 intrstr = pci_intr_string(pa->pa_pc, ih); 915 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 916 ahc_platform_intr, ahc, ahc->sc_dev.dv_xname); 917 if (ahc->ih == NULL) { 918 printf(": couldn't establish interrupt"); 919 if (intrstr != NULL) 920 printf(" at %s", intrstr); 921 printf("\n"); 922 ahc_free(ahc); 923 return; 924 } else 925 printf(": %s\n", intrstr ? intrstr : "?"); 926 927 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 928 dscommand0 |= MPARCKEN|CACHETHEN; 929 if ((ahc->features & AHC_ULTRA2) != 0) { 930 931 /* 932 * DPARCKEN doesn't work correctly on 933 * some MBs so don't use it. 934 */ 935 dscommand0 &= ~DPARCKEN; 936 } 937 938 /* 939 * Handle chips that must have cache line 940 * streaming (dis/en)abled. 941 */ 942 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 943 dscommand0 |= CACHETHEN; 944 945 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 946 dscommand0 &= ~CACHETHEN; 947 948 ahc_outb(ahc, DSCOMMAND0, dscommand0); 949 950 ahc->pci_cachesize = 951 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE; 952 ahc->pci_cachesize *= 4; 953 954 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 955 && ahc->pci_cachesize == 4) { 956 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0); 957 ahc->pci_cachesize = 0; 958 } 959 960 /* 961 * We cannot perform ULTRA speeds without the presence 962 * of the external precision resistor. 963 */ 964 if ((ahc->features & AHC_ULTRA) != 0) { 965 uint32_t devconfig; 966 967 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 968 if ((devconfig & REXTVALID) == 0) 969 ahc->features &= ~AHC_ULTRA; 970 } 971 972 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 973 M_DEVBUF, M_NOWAIT); 974 if (ahc->seep_config == NULL) 975 goto error_out; 976 977 memset(ahc->seep_config, 0, sizeof(*ahc->seep_config)); 978 979 /* See if we have a SEEPROM and perform auto-term */ 980 ahc_check_extport(ahc, &sxfrctl1); 981 982 /* 983 * Take the LED out of diagnostic mode 984 */ 985 sblkctl = ahc_inb(ahc, SBLKCTL); 986 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 987 988 if ((ahc->features & AHC_ULTRA2) != 0) { 989 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 990 } else { 991 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 992 } 993 994 if (ahc->flags & AHC_USEDEFAULTS) { 995 /* 996 * PCI Adapter default setup 997 * Should only be used if the adapter does not have 998 * a SEEPROM. 999 */ 1000 /* See if someone else set us up already */ 1001 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 1002 && scsiseq != 0) { 1003 printf("%s: Using left over BIOS settings\n", 1004 ahc_name(ahc)); 1005 ahc->flags &= ~AHC_USEDEFAULTS; 1006 ahc->flags |= AHC_BIOS_ENABLED; 1007 } else { 1008 /* 1009 * Assume only one connector and always turn 1010 * on termination. 1011 */ 1012 our_id = 0x07; 1013 sxfrctl1 = STPWEN; 1014 } 1015 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 1016 1017 ahc->our_id = our_id; 1018 } 1019 1020 /* 1021 * Take a look to see if we have external SRAM. 1022 * We currently do not attempt to use SRAM that is 1023 * shared among multiple controllers. 1024 */ 1025 ahc_probe_ext_scbram(ahc); 1026 1027 /* 1028 * Record our termination setting for the 1029 * generic initialization routine. 1030 */ 1031 if ((sxfrctl1 & STPWEN) != 0) 1032 ahc->flags |= AHC_TERM_ENB_A; 1033 1034 /* 1035 * Save chip register configuration data for chip resets 1036 * that occur during runtime and resume events. 1037 */ 1038 ahc->bus_softc.pci_softc.devconfig = 1039 pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); 1040 ahc->bus_softc.pci_softc.command = 1041 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1042 ahc->bus_softc.pci_softc.csize_lattime = 1043 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME); 1044 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1045 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 1046 if ((ahc->features & AHC_DT) != 0) { 1047 u_int sfunct; 1048 1049 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1050 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1051 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 1052 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 1053 ahc_outb(ahc, SFUNCT, sfunct); 1054 ahc->bus_softc.pci_softc.crccontrol1 = 1055 ahc_inb(ahc, CRCCONTROL1); 1056 } 1057 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1058 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 1059 1060 if ((ahc->features & AHC_ULTRA2) != 0) 1061 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 1062 1063 /* Core initialization */ 1064 if (ahc_init(ahc)) 1065 goto error_out; 1066 1067 ahc_attach(ahc); 1068 1069 return; 1070 1071 error_out: 1072 ahc_free(ahc); 1073 return; 1074 } 1075 1076 static int 1077 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 1078 uint16_t subdevice, uint16_t subvendor) 1079 { 1080 int result; 1081 1082 /* Default to invalid. */ 1083 result = 0; 1084 if (vendor == 0x9005 1085 && subvendor == 0x9005 1086 && subdevice != device 1087 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 1088 1089 switch (SUBID_9005_TYPE(subdevice)) { 1090 case SUBID_9005_TYPE_MB: 1091 break; 1092 case SUBID_9005_TYPE_CARD: 1093 case SUBID_9005_TYPE_LCCARD: 1094 /* 1095 * Currently only trust Adaptec cards to 1096 * get the sub device info correct. 1097 */ 1098 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 1099 result = 1; 1100 break; 1101 case SUBID_9005_TYPE_RAID: 1102 break; 1103 default: 1104 break; 1105 } 1106 } 1107 return (result); 1108 } 1109 1110 1111 /* 1112 * Test for the presense of external sram in an 1113 * "unshared" configuration. 1114 */ 1115 static int 1116 ahc_ext_scbram_present(struct ahc_softc *ahc) 1117 { 1118 u_int chip; 1119 int ramps; 1120 int single_user; 1121 uint32_t devconfig; 1122 1123 chip = ahc->chip & AHC_CHIPID_MASK; 1124 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1125 single_user = (devconfig & MPORTMODE) != 0; 1126 1127 if ((ahc->features & AHC_ULTRA2) != 0) 1128 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 1129 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 1130 /* 1131 * External SCBRAM arbitration is flakey 1132 * on these chips. Unfortunately this means 1133 * we don't use the extra SCB ram space on the 1134 * 3940AUW. 1135 */ 1136 ramps = 0; 1137 else if (chip >= AHC_AIC7870) 1138 ramps = (devconfig & RAMPSM) != 0; 1139 else 1140 ramps = 0; 1141 1142 if (ramps && single_user) 1143 return (1); 1144 return (0); 1145 } 1146 1147 /* 1148 * Enable external scbram. 1149 */ 1150 static void 1151 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1152 int fast, int large) 1153 { 1154 uint32_t devconfig; 1155 1156 if (ahc->features & AHC_MULTI_FUNC) { 1157 /* 1158 * Set the SCB Base addr (highest address bit) 1159 * depending on which channel we are. 1160 */ 1161 ahc_outb(ahc, SCBBADDR, ahc->bd->func); 1162 } 1163 1164 ahc->flags &= ~AHC_LSCBS_ENABLED; 1165 if (large) 1166 ahc->flags |= AHC_LSCBS_ENABLED; 1167 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1168 if ((ahc->features & AHC_ULTRA2) != 0) { 1169 u_int dscommand0; 1170 1171 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1172 if (enable) 1173 dscommand0 &= ~INTSCBRAMSEL; 1174 else 1175 dscommand0 |= INTSCBRAMSEL; 1176 if (large) 1177 dscommand0 &= ~USCBSIZE32; 1178 else 1179 dscommand0 |= USCBSIZE32; 1180 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1181 } else { 1182 if (fast) 1183 devconfig &= ~EXTSCBTIME; 1184 else 1185 devconfig |= EXTSCBTIME; 1186 if (enable) 1187 devconfig &= ~SCBRAMSEL; 1188 else 1189 devconfig |= SCBRAMSEL; 1190 if (large) 1191 devconfig &= ~SCBSIZE32; 1192 else 1193 devconfig |= SCBSIZE32; 1194 } 1195 if (pcheck) 1196 devconfig |= EXTSCBPEN; 1197 else 1198 devconfig &= ~EXTSCBPEN; 1199 1200 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1201 } 1202 1203 /* 1204 * Take a look to see if we have external SRAM. 1205 * We currently do not attempt to use SRAM that is 1206 * shared among multiple controllers. 1207 */ 1208 static void 1209 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1210 { 1211 int num_scbs; 1212 int test_num_scbs; 1213 int enable; 1214 int pcheck; 1215 int fast; 1216 int large; 1217 1218 enable = FALSE; 1219 pcheck = FALSE; 1220 fast = FALSE; 1221 large = FALSE; 1222 num_scbs = 0; 1223 1224 if (ahc_ext_scbram_present(ahc) == 0) 1225 goto done; 1226 1227 /* 1228 * Probe for the best parameters to use. 1229 */ 1230 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1231 num_scbs = ahc_probe_scbs(ahc); 1232 if (num_scbs == 0) { 1233 /* The SRAM wasn't really present. */ 1234 goto done; 1235 } 1236 enable = TRUE; 1237 1238 /* 1239 * Clear any outstanding parity error 1240 * and ensure that parity error reporting 1241 * is enabled. 1242 */ 1243 ahc_outb(ahc, SEQCTL, 0); 1244 ahc_outb(ahc, CLRINT, CLRPARERR); 1245 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1246 1247 /* Now see if we can do parity */ 1248 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1249 num_scbs = ahc_probe_scbs(ahc); 1250 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1251 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1252 pcheck = TRUE; 1253 1254 /* Clear any resulting parity error */ 1255 ahc_outb(ahc, CLRINT, CLRPARERR); 1256 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1257 1258 /* Now see if we can do fast timing */ 1259 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1260 test_num_scbs = ahc_probe_scbs(ahc); 1261 if (test_num_scbs == num_scbs 1262 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1263 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1264 fast = TRUE; 1265 1266 /* 1267 * See if we can use large SCBs and still maintain 1268 * the same overall count of SCBs. 1269 */ 1270 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1271 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1272 test_num_scbs = ahc_probe_scbs(ahc); 1273 if (test_num_scbs >= num_scbs) { 1274 large = TRUE; 1275 num_scbs = test_num_scbs; 1276 if (num_scbs >= 64) { 1277 /* 1278 * We have enough space to move the 1279 * "busy targets table" into SCB space 1280 * and make it qualify all the way to the 1281 * lun level. 1282 */ 1283 ahc->flags |= AHC_SCB_BTT; 1284 } 1285 } 1286 } 1287 done: 1288 /* 1289 * Disable parity error reporting until we 1290 * can load instruction ram. 1291 */ 1292 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1293 /* Clear any latched parity error */ 1294 ahc_outb(ahc, CLRINT, CLRPARERR); 1295 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1296 if (1/*bootverbose*/ && enable) { 1297 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1298 ahc_name(ahc), fast ? "fast" : "slow", 1299 pcheck ? ", parity checking enabled" : "", 1300 large ? 64 : 32); 1301 } 1302 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1303 } 1304 1305 #if 0 1306 /* 1307 * Perform some simple tests that should catch situations where 1308 * our registers are invalidly mapped. 1309 */ 1310 int 1311 ahc_pci_test_register_access(struct ahc_softc *ahc) 1312 { 1313 int error; 1314 u_int status1; 1315 uint32_t cmd; 1316 uint8_t hcntrl; 1317 1318 error = EIO; 1319 1320 /* 1321 * Enable PCI error interrupt status, but suppress NMIs 1322 * generated by SERR raised due to target aborts. 1323 */ 1324 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND); 1325 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND, 1326 cmd & ~PCIM_CMD_SERRESPEN); 1327 1328 /* 1329 * First a simple test to see if any 1330 * registers can be read. Reading 1331 * HCNTRL has no side effects and has 1332 * at least one bit that is guaranteed to 1333 * be zero so it is a good register to 1334 * use for this test. 1335 */ 1336 hcntrl = ahc_inb(ahc, HCNTRL); 1337 if (hcntrl == 0xFF) 1338 goto fail; 1339 1340 /* 1341 * Next create a situation where write combining 1342 * or read prefetching could be initiated by the 1343 * CPU or host bridge. Our device does not support 1344 * either, so look for data corruption and/or flagged 1345 * PCI errors. 1346 */ 1347 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1348 while (ahc_is_paused(ahc) == 0) 1349 ; 1350 ahc_outb(ahc, SEQCTL, PERRORDIS); 1351 ahc_outb(ahc, SCBPTR, 0); 1352 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1353 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1354 goto fail; 1355 1356 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, 1357 PCI_COMMAND_STATUS_REG + 1); 1358 if ((status1 & STA) != 0) 1359 goto fail; 1360 1361 error = 0; 1362 1363 fail: 1364 /* Silently clear any latched errors. */ 1365 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1); 1366 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1367 status1, /*bytes*/1); 1368 ahc_outb(ahc, CLRINT, CLRPARERR); 1369 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1370 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1371 return (error); 1372 } 1373 #endif 1374 1375 void 1376 ahc_pci_intr(struct ahc_softc *ahc) 1377 { 1378 u_int error; 1379 u_int status1; 1380 1381 error = ahc_inb(ahc, ERROR); 1382 if ((error & PCIERRSTAT) == 0) 1383 return; 1384 1385 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1386 1387 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1388 ahc_name(ahc), 1389 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1390 1391 if (status1 & DPE) { 1392 printf("%s: Data Parity Error Detected during address " 1393 "or write data phase\n", ahc_name(ahc)); 1394 } 1395 if (status1 & SSE) { 1396 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1397 } 1398 if (status1 & RMA) { 1399 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1400 } 1401 if (status1 & RTA) { 1402 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1403 } 1404 if (status1 & STA) { 1405 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1406 } 1407 if (status1 & DPR) { 1408 printf("%s: Data Parity Error has been reported via PERR#\n", 1409 ahc_name(ahc)); 1410 } 1411 1412 /* Clear latched errors. */ 1413 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, status1); 1414 1415 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1416 printf("%s: Latched PCIERR interrupt with " 1417 "no status bits set\n", ahc_name(ahc)); 1418 } else { 1419 ahc_outb(ahc, CLRINT, CLRPARERR); 1420 } 1421 1422 ahc_unpause(ahc); 1423 } 1424 1425 static int 1426 ahc_pci_chip_init(struct ahc_softc *ahc) 1427 { 1428 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 1429 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 1430 if ((ahc->features & AHC_DT) != 0) { 1431 u_int sfunct; 1432 1433 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1434 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1435 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 1436 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 1437 ahc_outb(ahc, SFUNCT, sfunct); 1438 ahc_outb(ahc, CRCCONTROL1, 1439 ahc->bus_softc.pci_softc.crccontrol1); 1440 } 1441 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1442 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 1443 1444 if ((ahc->features & AHC_ULTRA2) != 0) 1445 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 1446 1447 return (ahc_chip_init(ahc)); 1448 } 1449 1450 static int 1451 ahc_aic785X_setup(struct ahc_softc *ahc) 1452 { 1453 uint8_t rev; 1454 1455 ahc->channel = 'A'; 1456 ahc->chip = AHC_AIC7850; 1457 ahc->features = AHC_AIC7850_FE; 1458 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1459 rev = PCI_REVISION(ahc->bd->class); 1460 if (rev >= 1) 1461 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1462 ahc->instruction_ram_size = 512; 1463 return (0); 1464 } 1465 1466 static int 1467 ahc_aic7860_setup(struct ahc_softc *ahc) 1468 { 1469 uint8_t rev; 1470 1471 ahc->channel = 'A'; 1472 ahc->chip = AHC_AIC7860; 1473 ahc->features = AHC_AIC7860_FE; 1474 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1475 rev = PCI_REVISION(ahc->bd->class); 1476 if (rev >= 1) 1477 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1478 ahc->instruction_ram_size = 512; 1479 return (0); 1480 } 1481 1482 static int 1483 ahc_apa1480_setup(struct ahc_softc *ahc) 1484 { 1485 int error; 1486 1487 error = ahc_aic7860_setup(ahc); 1488 if (error != 0) 1489 return (error); 1490 ahc->features |= AHC_REMOVABLE; 1491 return (0); 1492 } 1493 1494 static int 1495 ahc_aic7870_setup(struct ahc_softc *ahc) 1496 { 1497 1498 ahc->channel = 'A'; 1499 ahc->chip = AHC_AIC7870; 1500 ahc->features = AHC_AIC7870_FE; 1501 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1502 ahc->instruction_ram_size = 512; 1503 return (0); 1504 } 1505 1506 static int 1507 ahc_aha394X_setup(struct ahc_softc *ahc) 1508 { 1509 int error; 1510 1511 error = ahc_aic7870_setup(ahc); 1512 if (error == 0) 1513 error = ahc_aha394XX_setup(ahc); 1514 return (error); 1515 } 1516 1517 static int 1518 ahc_aha398X_setup(struct ahc_softc *ahc) 1519 { 1520 int error; 1521 1522 error = ahc_aic7870_setup(ahc); 1523 if (error == 0) 1524 error = ahc_aha398XX_setup(ahc); 1525 return (error); 1526 } 1527 1528 static int 1529 ahc_aha494X_setup(struct ahc_softc *ahc) 1530 { 1531 int error; 1532 1533 error = ahc_aic7870_setup(ahc); 1534 if (error == 0) 1535 error = ahc_aha494XX_setup(ahc); 1536 return (error); 1537 } 1538 1539 static int 1540 ahc_aic7880_setup(struct ahc_softc *ahc) 1541 { 1542 uint8_t rev; 1543 1544 ahc->channel = 'A'; 1545 ahc->chip = AHC_AIC7880; 1546 ahc->features = AHC_AIC7880_FE; 1547 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 1548 rev = PCI_REVISION(ahc->bd->class); 1549 if (rev >= 1) { 1550 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 1551 } else { 1552 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 1553 } 1554 ahc->instruction_ram_size = 512; 1555 return (0); 1556 } 1557 1558 static int 1559 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 1560 { 1561 1562 ahc->flags |= AHC_INT50_SPEEDFLEX; 1563 return (ahc_aic7880_setup(ahc)); 1564 } 1565 1566 static int 1567 ahc_aha394XU_setup(struct ahc_softc *ahc) 1568 { 1569 int error; 1570 1571 error = ahc_aic7880_setup(ahc); 1572 if (error == 0) 1573 error = ahc_aha394XX_setup(ahc); 1574 return (error); 1575 } 1576 1577 static int 1578 ahc_aha398XU_setup(struct ahc_softc *ahc) 1579 { 1580 int error; 1581 1582 error = ahc_aic7880_setup(ahc); 1583 if (error == 0) 1584 error = ahc_aha398XX_setup(ahc); 1585 return (error); 1586 } 1587 1588 static int 1589 ahc_aic7890_setup(struct ahc_softc *ahc) 1590 { 1591 uint8_t rev; 1592 1593 ahc->channel = 'A'; 1594 ahc->chip = AHC_AIC7890; 1595 ahc->features = AHC_AIC7890_FE; 1596 ahc->flags |= AHC_NEWEEPROM_FMT; 1597 rev = PCI_REVISION(ahc->bd->class); 1598 if (rev == 0) 1599 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 1600 ahc->instruction_ram_size = 768; 1601 return (0); 1602 } 1603 1604 static int 1605 ahc_aic7892_setup(struct ahc_softc *ahc) 1606 { 1607 1608 ahc->channel = 'A'; 1609 ahc->chip = AHC_AIC7892; 1610 ahc->features = AHC_AIC7892_FE; 1611 ahc->flags |= AHC_NEWEEPROM_FMT; 1612 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1613 ahc->instruction_ram_size = 1024; 1614 return (0); 1615 } 1616 1617 static int 1618 ahc_aic7895_setup(struct ahc_softc *ahc) 1619 { 1620 uint8_t rev; 1621 1622 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1623 /* 1624 * The 'C' revision of the aic7895 has a few additional features. 1625 */ 1626 rev = PCI_REVISION(ahc->bd->class); 1627 if (rev >= 4) { 1628 ahc->chip = AHC_AIC7895C; 1629 ahc->features = AHC_AIC7895C_FE; 1630 } else { 1631 u_int command; 1632 1633 ahc->chip = AHC_AIC7895; 1634 ahc->features = AHC_AIC7895_FE; 1635 1636 /* 1637 * The BIOS disables the use of MWI transactions 1638 * since it does not have the MWI bug work around 1639 * we have. Disabling MWI reduces performance, so 1640 * turn it on again. 1641 */ 1642 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG); 1643 command |= PCI_COMMAND_INVALIDATE_ENABLE; 1644 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command); 1645 ahc->bugs |= AHC_PCI_MWI_BUG; 1646 } 1647 /* 1648 * XXX Does CACHETHEN really not work??? What about PCI retry? 1649 * on C level chips. Need to test, but for now, play it safe. 1650 */ 1651 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 1652 | AHC_CACHETHEN_BUG; 1653 1654 #if 0 1655 uint32_t devconfig; 1656 1657 /* 1658 * Cachesize must also be zero due to stray DAC 1659 * problem when sitting behind some bridges. 1660 */ 1661 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0); 1662 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG); 1663 devconfig |= MRDCEN; 1664 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig); 1665 #endif 1666 ahc->flags |= AHC_NEWEEPROM_FMT; 1667 ahc->instruction_ram_size = 512; 1668 return (0); 1669 } 1670 1671 static int 1672 ahc_aic7896_setup(struct ahc_softc *ahc) 1673 { 1674 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1675 ahc->chip = AHC_AIC7896; 1676 ahc->features = AHC_AIC7896_FE; 1677 ahc->flags |= AHC_NEWEEPROM_FMT; 1678 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 1679 ahc->instruction_ram_size = 768; 1680 return (0); 1681 } 1682 1683 static int 1684 ahc_aic7899_setup(struct ahc_softc *ahc) 1685 { 1686 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A'; 1687 ahc->chip = AHC_AIC7899; 1688 ahc->features = AHC_AIC7899_FE; 1689 ahc->flags |= AHC_NEWEEPROM_FMT; 1690 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 1691 ahc->instruction_ram_size = 1024; 1692 return (0); 1693 } 1694 1695 static int 1696 ahc_aha29160C_setup(struct ahc_softc *ahc) 1697 { 1698 int error; 1699 1700 error = ahc_aic7899_setup(ahc); 1701 if (error != 0) 1702 return (error); 1703 ahc->features |= AHC_REMOVABLE; 1704 return (0); 1705 } 1706 1707 static int 1708 ahc_raid_setup(struct ahc_softc *ahc) 1709 { 1710 printf("RAID functionality unsupported\n"); 1711 return (ENXIO); 1712 } 1713 1714 static int 1715 ahc_aha394XX_setup(struct ahc_softc *ahc) 1716 { 1717 1718 switch (ahc->bd->dev) { 1719 case AHC_394X_SLOT_CHANNEL_A: 1720 ahc->channel = 'A'; 1721 break; 1722 case AHC_394X_SLOT_CHANNEL_B: 1723 ahc->channel = 'B'; 1724 break; 1725 default: 1726 printf("adapter at unexpected slot %d\n" 1727 "unable to map to a channel\n", 1728 ahc->bd->dev); 1729 ahc->channel = 'A'; 1730 } 1731 return (0); 1732 } 1733 1734 static int 1735 ahc_aha398XX_setup(struct ahc_softc *ahc) 1736 { 1737 1738 switch (ahc->bd->dev) { 1739 case AHC_398X_SLOT_CHANNEL_A: 1740 ahc->channel = 'A'; 1741 break; 1742 case AHC_398X_SLOT_CHANNEL_B: 1743 ahc->channel = 'B'; 1744 break; 1745 case AHC_398X_SLOT_CHANNEL_C: 1746 ahc->channel = 'C'; 1747 break; 1748 default: 1749 printf("adapter at unexpected slot %d\n" 1750 "unable to map to a channel\n", 1751 ahc->bd->dev); 1752 ahc->channel = 'A'; 1753 break; 1754 } 1755 ahc->flags |= AHC_LARGE_SEEPROM; 1756 return (0); 1757 } 1758 1759 static int 1760 ahc_aha494XX_setup(struct ahc_softc *ahc) 1761 { 1762 1763 switch (ahc->bd->dev) { 1764 case AHC_494X_SLOT_CHANNEL_A: 1765 ahc->channel = 'A'; 1766 break; 1767 case AHC_494X_SLOT_CHANNEL_B: 1768 ahc->channel = 'B'; 1769 break; 1770 case AHC_494X_SLOT_CHANNEL_C: 1771 ahc->channel = 'C'; 1772 break; 1773 case AHC_494X_SLOT_CHANNEL_D: 1774 ahc->channel = 'D'; 1775 break; 1776 default: 1777 printf("adapter at unexpected slot %d\n" 1778 "unable to map to a channel\n", 1779 ahc->bd->dev); 1780 ahc->channel = 'A'; 1781 } 1782 ahc->flags |= AHC_LARGE_SEEPROM; 1783 return (0); 1784 } 1785