1 /* $OpenBSD: ahc_pci.c,v 1.23 2001/07/10 11:07:23 espie Exp $ */ 2 /* $NetBSD: ahc_pci.c,v 1.9 1996/10/21 22:56:24 thorpej Exp $ */ 3 4 /* 5 * Product specific probe and attach routines for: 6 * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1995, 1996 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/queue.h> 41 #include <sys/device.h> 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <scsi/scsi_all.h> 46 #include <scsi/scsiconf.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 53 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 54 55 #include <dev/ic/aic7xxxreg.h> 56 #include <dev/ic/aic7xxxvar.h> 57 #include <dev/ic/smc93cx6var.h> 58 59 /* 60 * XXX memory-mapped is busted on some i386 on-board chips. 61 * for i386, we don't even try it. Also, suppress the damn 62 * PCI bus errors messages on i386. They are not fatal, and are 63 * usually caused by some other device on the PCI bus. But some 64 * ahc cards won't work without ACKing them. So just ACK and go! 65 * XXX- smurph 66 */ 67 #ifndef i386 68 #define AHC_ALLOW_MEMIO 69 #define AHC_SHOW_PCI_ERRORS 70 #endif 71 72 /* 73 * Under normal circumstances, these messages are unnecessary 74 * and not terribly cosmetic. 75 */ 76 #ifdef DEBUG 77 #define bootverbose 1 78 #else 79 #define bootverbose 0 80 #endif 81 82 #define PCI_BASEADR0 PCI_MAPREG_START 83 84 #define AHC_394X_SLOT_CHANNEL_A 4 85 #define AHC_394X_SLOT_CHANNEL_B 5 86 87 #define AHC_398X_SLOT_CHANNEL_A 4 88 #define AHC_398X_SLOT_CHANNEL_B 8 89 #define AHC_398X_SLOT_CHANNEL_C 12 90 91 #define DEVCONFIG 0x40 92 #define SCBSIZE32 0x00010000UL /* aic789X only */ 93 #define MPORTMODE 0x00000400UL /* aic7870 only */ 94 #define RAMPSM 0x00000200UL /* aic7870 only */ 95 #define VOLSENSE 0x00000100UL 96 #define SCBRAMSEL 0x00000080UL 97 #define PCI64 0x00000080UL /* aic7891 & aic7897 only */ 98 #define MRDCEN 0x00000040UL 99 #define EXTSCBTIME 0x00000020UL /* aic7870 only */ 100 #define EXTSCBPEN 0x00000010UL /* aic7870 & aic7890 only */ 101 #define BERREN 0x00000008UL 102 #define DACEN 0x00000004UL 103 #define STPWLEVEL 0x00000002UL 104 #define DIFACTNEGEN 0x00000001UL /* aic7870 only */ 105 106 #define CSIZE_LATTIME 0x0c 107 #define CACHESIZE 0x0000003ful /* only 5 bits */ 108 #define LATTIME 0x0000ff00ul 109 110 int ahc_pci_intr __P((struct ahc_softc *ahc)); 111 static int ahc_ext_scbram_present __P((struct ahc_softc *ahc)); 112 static void ahc_ext_scbram_config __P((struct ahc_softc *ahc, int enable, 113 int pcheck, int fast)); 114 static void ahc_probe_ext_scbram __P((struct ahc_softc *ahc)); 115 static void check_extport __P((struct ahc_softc *ahc, u_int *sxfrctl1)); 116 static void configure_termination __P((struct ahc_softc *ahc, 117 struct seeprom_descriptor *sd, 118 u_int adapter_control, 119 u_int *sxfrctl1)); 120 static void ahc_new_term_detect __P((struct ahc_softc *ahc, 121 int *enableSEC_low, 122 int *enableSEC_high, 123 int *enablePRI_low, 124 int *enablePRI_high, 125 int *eeprom_present)); 126 static void aic787X_cable_detect __P((struct ahc_softc *ahc, 127 int *internal50_present, 128 int *internal68_present, 129 int *externalcable_present, 130 int *eeprom_present)); 131 static void aic785X_cable_detect __P((struct ahc_softc *ahc, 132 int *internal50_present, 133 int *externalcable_present, 134 int *eeprom_present)); 135 static void write_brdctl __P((struct ahc_softc *ahc, u_int8_t value)); 136 static u_int8_t read_brdctl __P((struct ahc_softc *ahc)); 137 138 void load_seeprom __P((struct ahc_softc *ahc)); 139 static int acquire_seeprom __P((struct ahc_softc *ahc, 140 struct seeprom_descriptor *sd)); 141 static void release_seeprom __P((struct seeprom_descriptor *sd)); 142 int ahc_probe_scbs __P((struct ahc_softc *ahc)); 143 144 static u_char aic3940_count; 145 146 int ahc_pci_probe __P((struct device *, void *, void *)); 147 void ahc_pci_attach __P((struct device *, struct device *, void *)); 148 149 struct cfattach ahc_pci_ca = { 150 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 151 }; 152 153 struct ahc_pci_data { 154 pci_chipset_tag_t pc; 155 pcitag_t tag; 156 u_int function; 157 }; 158 159 int 160 ahc_pci_probe(parent, match, aux) 161 struct device *parent; 162 void *match, *aux; 163 { 164 struct pci_attach_args *pa = aux; 165 166 switch (PCI_VENDOR(pa->pa_id)) { 167 case PCI_VENDOR_ADP: 168 switch (PCI_PRODUCT(pa->pa_id)) { 169 case PCI_PRODUCT_ADP_AIC7810: 170 case PCI_PRODUCT_ADP_AIC7850: 171 case PCI_PRODUCT_ADP_AIC7855: 172 case PCI_PRODUCT_ADP_AIC5900: 173 case PCI_PRODUCT_ADP_AIC5905: 174 case PCI_PRODUCT_ADP_AIC7860: 175 case PCI_PRODUCT_ADP_2940AU: 176 case PCI_PRODUCT_ADP_AIC7870: 177 case PCI_PRODUCT_ADP_2930CU: 178 case PCI_PRODUCT_ADP_2940: 179 case PCI_PRODUCT_ADP_3940: 180 case PCI_PRODUCT_ADP_3985: 181 case PCI_PRODUCT_ADP_2944: 182 case PCI_PRODUCT_ADP_AIC7880: 183 case PCI_PRODUCT_ADP_2940U: 184 case PCI_PRODUCT_ADP_3940U: 185 case PCI_PRODUCT_ADP_398XU: 186 case PCI_PRODUCT_ADP_2944U: 187 case PCI_PRODUCT_ADP_2940UWPro: 188 case PCI_PRODUCT_ADP_7895: 189 return (1); 190 } 191 break; 192 case PCI_VENDOR_ADP2: 193 switch (PCI_PRODUCT(pa->pa_id)) { 194 case PCI_PRODUCT_ADP2_AIC7890: 195 case PCI_PRODUCT_ADP2_2940U2: 196 case PCI_PRODUCT_ADP2_2930U2: 197 case PCI_PRODUCT_ADP2_AIC7892: 198 case PCI_PRODUCT_ADP2_29160: 199 case PCI_PRODUCT_ADP2_19160B: 200 case PCI_PRODUCT_ADP2_3950U2B: 201 case PCI_PRODUCT_ADP2_3950U2D: 202 case PCI_PRODUCT_ADP2_AIC7896: 203 case PCI_PRODUCT_ADP2_AIC7899: 204 case PCI_PRODUCT_ADP2_3960D: 205 return (1); 206 } 207 break; 208 } 209 return (0); 210 } 211 212 void 213 ahc_pci_attach(parent, self, aux) 214 struct device *parent, *self; 215 void *aux; 216 { 217 struct pci_attach_args *pa = aux; 218 struct ahc_softc *ahc = (void *)self; 219 bus_space_tag_t iot; 220 bus_space_handle_t ioh; 221 pci_intr_handle_t ih; 222 pcireg_t command; 223 const char *intrstr; 224 unsigned opri = 0; 225 ahc_chip ahc_c = AHC_PCI; /* we are a PCI controller */ 226 ahc_flag ahc_flags = AHC_FNONE; 227 ahc_feature ahc_f = AHC_FENONE; 228 int ioh_valid; 229 230 u_char ultra_enb = 0; 231 u_char our_id = 0; 232 u_char channel = 'A'; 233 u_int sxfrctl1; 234 u_int scsiseq; 235 /* So we can access PCI configuration space after init */ 236 struct ahc_pci_data *pd; 237 238 ahc->sc_dmat = pa->pa_dmat; 239 240 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 241 PCI_COMMAND_STATUS_REG); 242 243 switch (PCI_VENDOR(pa->pa_id)) { 244 case PCI_VENDOR_ADP: 245 switch (PCI_PRODUCT(pa->pa_id)) { 246 case PCI_PRODUCT_ADP_7895: 247 { 248 pcireg_t devconfig; 249 channel = pa->pa_function == 1 ? 'B' : 'A'; 250 ahc_c |= AHC_AIC7895; 251 /* The 'C' revision of the aic7895 252 has a few additional features */ 253 if (PCI_REVISION(pa->pa_class) >= 4) 254 ahc_f = AHC_AIC7895C_FE; 255 else 256 ahc_f = AHC_AIC7895_FE; 257 ahc_flags |= AHC_NEWEEPROM_FMT; 258 devconfig = pci_conf_read(pa->pa_pc, 259 pa->pa_tag, 260 DEVCONFIG); 261 devconfig &= ~SCBSIZE32; 262 pci_conf_write(pa->pa_pc, pa->pa_tag, 263 DEVCONFIG, devconfig); 264 } 265 break; 266 case PCI_PRODUCT_ADP_3940U: 267 case PCI_PRODUCT_ADP_3940: 268 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADP_3940U) { 269 ahc_c |= AHC_AIC7880; 270 ahc_f = AHC_AIC7880_FE; 271 } else { 272 ahc_c |= AHC_AIC7870; 273 ahc_f = AHC_AIC7870_FE; 274 } 275 aic3940_count++; 276 if (!(aic3940_count & 0x01)) 277 /* Even count implies second channel */ 278 channel = 'B'; 279 break; 280 case PCI_PRODUCT_ADP_2940UWPro: 281 ahc_c |= AHC_AIC7880; 282 ahc_f = AHC_AIC7880_FE; 283 ahc_f |= AHC_INT50_SPEEDFLEX; 284 case PCI_PRODUCT_ADP_2944U: 285 case PCI_PRODUCT_ADP_2940U: 286 ahc_c |= AHC_AIC7880; 287 ahc_f = AHC_AIC7880_FE; 288 break; 289 case PCI_PRODUCT_ADP_2944: 290 case PCI_PRODUCT_ADP_2940: 291 ahc_c |= AHC_AIC7870; 292 ahc_f = AHC_AIC7870_FE; 293 break; 294 case PCI_PRODUCT_ADP_2940AU: 295 ahc_c |= AHC_AIC7860; 296 ahc_f = AHC_AIC7860_FE; 297 break; 298 case PCI_PRODUCT_ADP_398XU: /* XXX */ 299 case PCI_PRODUCT_ADP_AIC7880: 300 ahc_c |= AHC_AIC7880; 301 ahc_f = AHC_AIC7880_FE; 302 break; 303 case PCI_PRODUCT_ADP_AIC7870: 304 ahc_c |= AHC_AIC7870; 305 ahc_f = AHC_AIC7870_FE; 306 break; 307 case PCI_PRODUCT_ADP_AIC7860: 308 ahc_c |= AHC_AIC7860; 309 ahc_f = AHC_AIC7860_FE; 310 break; 311 case PCI_PRODUCT_ADP_AIC7855: 312 case PCI_PRODUCT_ADP_AIC7850: 313 ahc_c |= AHC_AIC7850; 314 ahc_f = AHC_AIC7850_FE; 315 break; 316 default: 317 /* TTT */ 318 break; 319 } 320 break; 321 case PCI_VENDOR_ADP2: 322 switch (PCI_PRODUCT(pa->pa_id)) { 323 case PCI_PRODUCT_ADP2_AIC7890: 324 case PCI_PRODUCT_ADP2_2940U2: 325 case PCI_PRODUCT_ADP2_2930U2: 326 ahc_c |= AHC_AIC7890; 327 ahc_f = AHC_AIC7890_FE; 328 ahc_flags |= AHC_NEWEEPROM_FMT; 329 break; 330 case PCI_PRODUCT_ADP2_AIC7892: 331 case PCI_PRODUCT_ADP2_29160: 332 case PCI_PRODUCT_ADP2_19160B: 333 ahc_c |= AHC_AIC7892; 334 ahc_f = AHC_AIC7892_FE; 335 ahc_flags |= AHC_NEWEEPROM_FMT; 336 break; 337 case PCI_PRODUCT_ADP2_3950U2B: 338 case PCI_PRODUCT_ADP2_3950U2D: 339 case PCI_PRODUCT_ADP2_AIC7896: 340 { 341 pcireg_t devconfig; 342 channel = pa->pa_function == 1 ? 'B' : 'A'; 343 ahc_c |= AHC_AIC7896; 344 ahc_f = AHC_AIC7896_FE; 345 ahc_flags |= AHC_NEWEEPROM_FMT; 346 devconfig = pci_conf_read(pa->pa_pc, 347 pa->pa_tag, 348 DEVCONFIG); 349 /* turn off 64 bit for now XXX smurph */ 350 devconfig &= ~PCI64; 351 pci_conf_write(pa->pa_pc, pa->pa_tag, 352 DEVCONFIG, devconfig); 353 } 354 break; 355 case PCI_PRODUCT_ADP2_AIC7899: 356 case PCI_PRODUCT_ADP2_3960D: 357 ahc_c |= AHC_AIC7899; 358 ahc_f = AHC_AIC7899_FE; 359 ahc_flags |= AHC_NEWEEPROM_FMT; 360 break; 361 default: 362 /* TTT */ 363 break; 364 } 365 } 366 367 #ifdef AHC_ALLOW_MEMIO 368 /* 369 * attempt to use memory mapping on hardware that supports it. 370 * e.g powerpc XXX - smurph 371 * 372 * Note: If this fails, IO mapping is used. 373 */ 374 if ((command & PCI_COMMAND_MEM_ENABLE) != 0) { 375 pcireg_t memtype; 376 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 377 switch (memtype) { 378 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 379 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 380 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 381 memtype, 0, &iot, &ioh, NULL, NULL, 0) == 0); 382 break; 383 default: 384 ioh_valid = 0; 385 } 386 } 387 388 if (!ioh_valid) /* try to drop back to IO mapping */ 389 #endif 390 { 391 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 392 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0); 393 } 394 395 if (!ioh_valid) { 396 /* Game Over. Insert coin... */ 397 printf(": unable to map registers\n"); 398 return; 399 } 400 401 /* Ensure busmastering is enabled */ 402 command |= PCI_COMMAND_MASTER_ENABLE; 403 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 404 405 pd = malloc(sizeof (struct ahc_pci_data), M_DEVBUF, M_NOWAIT); 406 if (pd == NULL) { 407 printf(": error allocating pci data\n"); 408 return; 409 } 410 411 pd->pc = pa->pa_pc; 412 pd->tag = pa->pa_tag; 413 pd->function = pa->pa_function; 414 415 /* setup the PCI stuff */ 416 ahc->pci_data = pd; 417 ahc->pci_intr_func = ahc_pci_intr; 418 419 420 /* On all PCI adapters, we allow SCB paging */ 421 ahc_flags |= AHC_PAGESCBS; 422 423 ahc_construct(ahc, pa->pa_iot, ioh, ahc_c, ahc_flags, ahc_f, channel); 424 /* Now we can use the ahc_inb and ahc_outb macros */ 425 426 /* setup the PCI error interrupt handler */ 427 ahc->pci_intr_func = &ahc_pci_intr; 428 429 /* Remeber how the card was setup in case there is no SEEPROM */ 430 ahc_outb(ahc, HCNTRL, ahc->pause); 431 if ((ahc->features & AHC_ULTRA2) != 0) 432 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 433 else 434 our_id = ahc_inb(ahc, SCSIID) & OID; 435 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 436 scsiseq = ahc_inb(ahc, SCSISEQ); 437 438 if (ahc_reset(ahc) != 0) { 439 /* Failed */ 440 ahc_free(ahc); 441 return; 442 } 443 444 if (ahc->features & AHC_ULTRA) 445 ultra_enb = bus_space_read_1(pa->pa_iot, ioh, SXFRCTL0) & 446 FAST20; 447 448 if ((ahc->features & AHC_DT) != 0) { 449 u_int optionmode; 450 u_int sfunct; 451 452 /* Perform ALT-Mode Setup */ 453 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 454 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 455 optionmode = ahc_inb(ahc, OPTIONMODE); 456 if (bootverbose) 457 printf("%s: OptionMode = %x\n", ahc_name(ahc), optionmode); 458 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 459 /* Send CRC info in target mode every 4K */ 460 ahc_outb(ahc, TARGCRCCNT, 0); 461 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 462 ahc_outb(ahc, SFUNCT, sfunct); 463 464 /* Normal mode setup */ 465 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 466 |TARGCRCENDEN|TARGCRCCNTEN); 467 } 468 469 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 470 pa->pa_intrline, &ih)) { 471 printf(": couldn't map interrupt\n", ahc->sc_dev.dv_xname); 472 ahc_free(ahc); 473 return; 474 } 475 intrstr = pci_intr_string(pa->pa_pc, ih); 476 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc, 477 ahc->sc_dev.dv_xname); 478 479 if (ahc->sc_ih == NULL) { 480 printf(": couldn't establish interrupt"); 481 if (intrstr != NULL) 482 printf(" at %s", intrstr); 483 printf("\n"); 484 ahc_free(ahc); 485 return; 486 } 487 if (intrstr != NULL) 488 printf(": %s\n", intrstr); 489 490 /* 491 * Protect ourself from spurrious interrupts during 492 * intialization. 493 */ 494 opri = splbio(); 495 496 /* 497 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 498 */ 499 { 500 u_int8_t sblkctl; 501 u_int dscommand0; 502 503 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 504 dscommand0 |= MPARCKEN; 505 if ((ahc->features & AHC_ULTRA2) != 0) { 506 507 /* 508 * DPARCKEN doesn't work correctly on 509 * some MBs so don't use it. 510 */ 511 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 512 dscommand0 |= CACHETHEN; 513 } 514 515 ahc_outb(ahc, DSCOMMAND0, dscommand0); 516 517 /* See if we have an SEEPROM and perform auto-term */ 518 check_extport(ahc, &sxfrctl1); 519 520 /* 521 * Take the LED out of diagnostic mode 522 */ 523 sblkctl = ahc_inb(ahc, SBLKCTL); 524 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 525 526 /* 527 * I don't know where this is set in the SEEPROM or by the 528 * BIOS, so we default to 100% on Ultra or slower controllers 529 * and 75% on ULTRA2 controllers. 530 */ 531 if ((ahc->features & AHC_ULTRA2) != 0) { 532 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 533 } else { 534 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 535 } 536 537 if (ahc->flags & AHC_USEDEFAULTS) { 538 /* 539 * PCI Adapter default setup 540 * Should only be used if the adapter does not have 541 * an SEEPROM. 542 */ 543 /* See if someone else set us up already */ 544 if (scsiseq != 0) { 545 printf("%s: Using left over BIOS settings\n", 546 ahc_name(ahc)); 547 ahc->flags &= ~AHC_USEDEFAULTS; 548 } else { 549 /* 550 * Assume only one connector and always turn 551 * on termination. 552 */ 553 our_id = 0x07; 554 sxfrctl1 = STPWEN; 555 } 556 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 557 558 ahc->our_id = our_id; 559 } 560 } 561 562 /* 563 * Take a look to see if we have external SRAM. 564 * We currently do not attempt to use SRAM that is 565 * shared among multiple controllers. 566 */ 567 ahc_probe_ext_scbram(ahc); 568 569 printf("%s: ", ahc_name(ahc)); 570 571 /* 572 * Record our termination setting for the 573 * generic initialization routine. 574 */ 575 if ((sxfrctl1 & STPWEN) != 0) 576 ahc->flags |= AHC_TERM_ENB_A; 577 578 if (ahc_init(ahc)) { 579 ahc_free(ahc); 580 splx(opri); 581 return; /* XXX PCI code should take return status */ 582 } 583 splx(opri); 584 585 ahc_attach(ahc); 586 } 587 588 /* 589 * Test for the presense of external sram in an 590 * "unshared" configuration. 591 */ 592 static int 593 ahc_ext_scbram_present(ahc) 594 struct ahc_softc *ahc; 595 { 596 int ramps; 597 int single_user; 598 pcireg_t devconfig; 599 struct ahc_pci_data *pd = ahc->pci_data; 600 601 devconfig = pci_conf_read(pd->pc, pd->tag, DEVCONFIG); 602 single_user = (devconfig & MPORTMODE) != 0; 603 604 if ((ahc->features & AHC_ULTRA2) != 0) 605 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 606 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 607 ramps = (devconfig & RAMPSM) != 0; 608 else 609 ramps = 0; 610 611 if (ramps && single_user) 612 return (1); 613 return (0); 614 } 615 616 /* 617 * Enable external scbram. 618 */ 619 static void 620 ahc_ext_scbram_config(ahc, enable, pcheck, fast) 621 struct ahc_softc *ahc; 622 int enable; 623 int pcheck; 624 int fast; 625 { 626 pcireg_t devconfig; 627 struct ahc_pci_data *pd = ahc->pci_data; 628 629 if (ahc->features & AHC_MULTI_FUNC) { 630 u_char channel; 631 /* 632 * Set the SCB Base addr (highest address bit) 633 * depending on which channel we are. 634 */ 635 channel = pd->function == 1 ? 1 : 0; 636 ahc_outb(ahc, SCBBADDR, channel); 637 } 638 639 devconfig = pci_conf_read(pd->pc, pd->tag, DEVCONFIG); 640 641 if ((ahc->features & AHC_ULTRA2) != 0) { 642 u_int dscommand0; 643 644 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 645 if (enable) 646 dscommand0 &= ~INTSCBRAMSEL; 647 else 648 dscommand0 |= INTSCBRAMSEL; 649 ahc_outb(ahc, DSCOMMAND0, dscommand0); 650 } else { 651 if (fast) 652 devconfig &= ~EXTSCBTIME; 653 else 654 devconfig |= EXTSCBTIME; 655 if (enable) 656 devconfig &= ~SCBRAMSEL; 657 else 658 devconfig |= SCBRAMSEL; 659 } 660 if (pcheck) 661 devconfig |= EXTSCBPEN; 662 else 663 devconfig &= ~EXTSCBPEN; 664 665 pci_conf_write(pd->pc, pd->tag, DEVCONFIG, devconfig); 666 } 667 668 /* 669 * Take a look to see if we have external SRAM. 670 * We currently do not attempt to use SRAM that is 671 * shared among multiple controllers. 672 */ 673 static void 674 ahc_probe_ext_scbram(ahc) 675 struct ahc_softc *ahc; 676 { 677 int num_scbs; 678 int test_num_scbs; 679 int enable; 680 int pcheck; 681 int fast; 682 683 if (ahc_ext_scbram_present(ahc) == 0) 684 return; 685 686 /* 687 * Probe for the best parameters to use. 688 */ 689 enable = 0; 690 pcheck = 0; 691 fast = 0; 692 ahc_ext_scbram_config(ahc, /*enable*/1, pcheck, fast); 693 num_scbs = ahc_probe_scbs(ahc); 694 if (num_scbs == 0) { 695 /* The SRAM wasn't really present. */ 696 goto done; 697 } 698 enable = 1; 699 700 /* Now see if we can do parity */ 701 ahc_ext_scbram_config(ahc, enable, /*pcheck*/1, fast); 702 num_scbs = ahc_probe_scbs(ahc); 703 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 704 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 705 pcheck = 1; 706 707 /* Clear any resulting parity error */ 708 ahc_outb(ahc, CLRINT, CLRPARERR); 709 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 710 711 /* Now see if we can do fast timing */ 712 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/1); 713 test_num_scbs = ahc_probe_scbs(ahc); 714 if (test_num_scbs == num_scbs 715 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 716 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 717 fast = 1; 718 719 done: 720 /* Clear any resulting parity error */ 721 ahc_outb(ahc, CLRINT, CLRPARERR); 722 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 723 if (bootverbose && enable) { 724 printf("%s: External SRAM, %dns access%s\n", 725 ahc_name(ahc), fast ? 10 : 20, 726 pcheck ? ", parity checking enabled" : ""); 727 728 } 729 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 730 } 731 732 /* 733 * Check the external port logic for a serial eeprom 734 * and termination/cable detection contrls. 735 */ 736 static void 737 check_extport(ahc, sxfrctl1) 738 struct ahc_softc *ahc; 739 u_int *sxfrctl1; 740 { 741 struct seeprom_descriptor sd; 742 struct seeprom_config sc; 743 u_int scsi_conf; 744 u_int adapter_control; 745 int have_seeprom; 746 int have_autoterm; 747 748 sd.sd_tag = ahc->sc_iot; 749 sd.sd_bsh = ahc->sc_ioh; 750 sd.sd_control_offset = SEECTL; 751 sd.sd_status_offset = SEECTL; 752 sd.sd_dataout_offset = SEECTL; 753 754 /* 755 * For some multi-channel devices, the c46 is simply too 756 * small to work. For the other controller types, we can 757 * get our information from either SEEPROM type. Set the 758 * type to start our probe with accordingly. 759 */ 760 if (ahc->flags & AHC_LARGE_SEEPROM) 761 sd.sd_chip = C56_66; 762 else 763 sd.sd_chip = C46; 764 765 sd.sd_MS = SEEMS; 766 sd.sd_RDY = SEERDY; 767 sd.sd_CS = SEECS; 768 sd.sd_CK = SEECK; 769 sd.sd_DO = SEEDO; 770 sd.sd_DI = SEEDI; 771 772 have_seeprom = acquire_seeprom(ahc, &sd); 773 if (have_seeprom) { 774 775 if (bootverbose) 776 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 777 778 for (;;) { 779 bus_size_t start_addr; 780 781 start_addr = 32 * (ahc->channel - 'A'); 782 783 have_seeprom = read_seeprom(&sd, 784 (u_int16_t *)&sc, 785 start_addr, 786 sizeof(sc)/2); 787 788 if (have_seeprom) { 789 /* Check checksum */ 790 int i; 791 int maxaddr; 792 u_int32_t checksum; 793 u_int16_t *scarray; 794 795 maxaddr = (sizeof(sc)/2) - 1; 796 checksum = 0; 797 scarray = (u_int16_t *)≻ 798 799 for (i = 0; i < maxaddr; i++) 800 checksum = checksum + scarray[i]; 801 if (checksum == 0 802 || (checksum & 0xFFFF) != sc.checksum) { 803 if (bootverbose && sd.sd_chip == C56_66) 804 printf ("checksum error\n"); 805 have_seeprom = 0; 806 } else { 807 if (bootverbose) 808 printf("done.\n"); 809 break; 810 } 811 } 812 813 if (sd.sd_chip == C56_66) 814 break; 815 sd.sd_chip = C56_66; 816 } 817 } 818 819 if (!have_seeprom) { 820 if (bootverbose) 821 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 822 ahc->flags |= AHC_USEDEFAULTS; 823 } else { 824 /* 825 * Put the data we've collected down into SRAM 826 * where ahc_init will find it. 827 */ 828 int i; 829 int max_targ = sc.max_targets & CFMAXTARG; 830 u_int16_t discenable; 831 u_int16_t ultraenb; 832 833 discenable = 0; 834 ultraenb = 0; 835 if ((sc.adapter_control & CFULTRAEN) != 0) { 836 /* 837 * Determine if this adapter has a "newstyle" 838 * SEEPROM format. 839 */ 840 for (i = 0; i < max_targ; i++) { 841 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) { 842 ahc->flags |= AHC_NEWEEPROM_FMT; 843 break; 844 } 845 } 846 } 847 848 for (i = 0; i < max_targ; i++) { 849 u_int scsirate; 850 u_int16_t target_mask; 851 852 target_mask = 0x01 << i; 853 if (sc.device_flags[i] & CFDISC) 854 discenable |= target_mask; 855 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 856 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 857 ultraenb |= target_mask; 858 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 859 ultraenb |= target_mask; 860 } 861 if ((sc.device_flags[i] & CFXFER) == 0x04 862 && (ultraenb & target_mask) != 0) { 863 /* Treat 10MHz as a non-ultra speed */ 864 sc.device_flags[i] &= ~CFXFER; 865 ultraenb &= ~target_mask; 866 } 867 if ((ahc->features & AHC_ULTRA2) != 0) { 868 u_int offset; 869 870 if (sc.device_flags[i] & CFSYNCH) 871 offset = MAX_OFFSET_ULTRA2; 872 else 873 offset = 0; 874 ahc_outb(ahc, TARG_OFFSET + i, offset); 875 876 scsirate = (sc.device_flags[i] & CFXFER) 877 | ((ultraenb & target_mask) ? 0x8 : 0x0); 878 if (sc.device_flags[i] & CFWIDEB) 879 scsirate |= WIDEXFER; 880 } else { 881 scsirate = (sc.device_flags[i] & CFXFER) << 4; 882 if (sc.device_flags[i] & CFSYNCH) 883 scsirate |= SOFS; 884 if (sc.device_flags[i] & CFWIDEB) 885 scsirate |= WIDEXFER; 886 } 887 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 888 } 889 ahc->our_id = sc.brtime_id & CFSCSIID; 890 891 scsi_conf = (ahc->our_id & 0x7); 892 if (sc.adapter_control & CFSPARITY) 893 scsi_conf |= ENSPCHK; 894 if (sc.adapter_control & CFRESETB) 895 scsi_conf |= RESET_SCSI; 896 897 if (sc.bios_control & CFEXTEND) 898 ahc->flags |= AHC_EXTENDED_TRANS_A; 899 if (ahc->features & AHC_ULTRA 900 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 901 /* Should we enable Ultra mode? */ 902 if (!(sc.adapter_control & CFULTRAEN)) 903 /* Treat us as a non-ultra card */ 904 ultraenb = 0; 905 } 906 /* Set SCSICONF info */ 907 ahc_outb(ahc, SCSICONF, scsi_conf); 908 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 909 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 910 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 911 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 912 } 913 914 /* 915 * Cards that have the external logic necessary to talk to 916 * a SEEPROM, are almost certain to have the remaining logic 917 * necessary for auto-termination control. This assumption 918 * hasn't failed yet... 919 */ 920 have_autoterm = have_seeprom; 921 if (have_seeprom) 922 adapter_control = sc.adapter_control; 923 else 924 adapter_control = CFAUTOTERM; 925 926 /* 927 * Some low-cost chips have SEEPROM and auto-term control built 928 * in, instead of using a GAL. They can tell us directly 929 * if the termination logic is enabled. 930 */ 931 if ((ahc->features & AHC_SPIOCAP) != 0) { 932 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 933 have_autoterm = 1; 934 else 935 have_autoterm = 0; 936 } 937 938 if (have_autoterm) 939 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 940 941 release_seeprom(&sd); 942 } 943 944 static void 945 configure_termination(ahc, sd, adapter_control, sxfrctl1) 946 struct ahc_softc *ahc; 947 struct seeprom_descriptor *sd; 948 u_int adapter_control; 949 u_int *sxfrctl1; 950 { 951 u_int8_t brddat; 952 953 brddat = 0; 954 955 /* 956 * Update the settings in sxfrctl1 to match the 957 * termination settings 958 */ 959 *sxfrctl1 = 0; 960 961 /* 962 * SEECS must be on for the GALS to latch 963 * the data properly. Be sure to leave MS 964 * on or we will release the seeprom. 965 */ 966 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 967 if ((adapter_control & CFAUTOTERM) != 0 968 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 969 int internal50_present; 970 int internal68_present; 971 int externalcable_present; 972 int eeprom_present; 973 int enableSEC_low; 974 int enableSEC_high; 975 int enablePRI_low; 976 int enablePRI_high; 977 978 enableSEC_low = 0; 979 enableSEC_high = 0; 980 enablePRI_low = 0; 981 enablePRI_high = 0; 982 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 983 ahc_new_term_detect(ahc, &enableSEC_low, 984 &enableSEC_high, 985 &enablePRI_low, 986 &enablePRI_high, 987 &eeprom_present); 988 if ((adapter_control & CFSEAUTOTERM) == 0) { 989 if (bootverbose) 990 printf("%s: Manual SE Termination\n", 991 ahc_name(ahc)); 992 enableSEC_low = (adapter_control & CFSTERM); 993 enableSEC_high = (adapter_control & CFWSTERM); 994 } 995 if ((adapter_control & CFAUTOTERM) == 0) { 996 if (bootverbose) 997 printf("%s: Manual LVD Termination\n", 998 ahc_name(ahc)); 999 enablePRI_low = enablePRI_high = 1000 (adapter_control & CFLVDSTERM); 1001 } 1002 /* Make the table calculations below happy */ 1003 internal50_present = 0; 1004 internal68_present = 1; 1005 externalcable_present = 1; 1006 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1007 aic785X_cable_detect(ahc, &internal50_present, 1008 &externalcable_present, 1009 &eeprom_present); 1010 } else { 1011 aic787X_cable_detect(ahc, &internal50_present, 1012 &internal68_present, 1013 &externalcable_present, 1014 &eeprom_present); 1015 } 1016 1017 if ((ahc->features & AHC_WIDE) == 0) 1018 internal68_present = 0; 1019 1020 if (bootverbose) { 1021 if ((ahc->features & AHC_ULTRA2) == 0) { 1022 printf("%s: internal 50 cable %s present, " 1023 "internal 68 cable %s present\n", 1024 ahc_name(ahc), 1025 internal50_present ? "is":"not", 1026 internal68_present ? "is":"not"); 1027 1028 printf("%s: external cable %s present\n", 1029 ahc_name(ahc), 1030 externalcable_present ? "is":"not"); 1031 } 1032 printf("%s: BIOS eeprom %s present\n", 1033 ahc_name(ahc), eeprom_present ? "is" : "not"); 1034 } 1035 1036 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1037 /* 1038 * The 50 pin connector is a separate bus, 1039 * so force it to always be terminated. 1040 * In the future, perform current sensing 1041 * to determine if we are in the middle of 1042 * a properly terminated bus. 1043 */ 1044 internal50_present = 0; 1045 } 1046 1047 /* 1048 * Now set the termination based on what 1049 * we found. 1050 * Flash Enable = BRDDAT7 1051 * Secondary High Term Enable = BRDDAT6 1052 * Secondary Low Term Enable = BRDDAT5 (7890) 1053 * Primary High Term Enable = BRDDAT4 (7890) 1054 */ 1055 if ((ahc->features & AHC_ULTRA2) == 0 1056 && (internal50_present != 0) 1057 && (internal68_present != 0) 1058 && (externalcable_present != 0)) { 1059 printf("%s: Illegal cable configuration!!. " 1060 "Only two connectors on the " 1061 "adapter may be used at a " 1062 "time!\n", ahc_name(ahc)); 1063 } 1064 1065 if ((ahc->features & AHC_WIDE) != 0 1066 && ((externalcable_present == 0) 1067 || (internal68_present == 0) 1068 || (enableSEC_high != 0))) { 1069 brddat |= BRDDAT6; 1070 if (bootverbose) { 1071 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1072 printf("%s: 68 pin termination " 1073 "Enabled\n", ahc_name(ahc)); 1074 else 1075 printf("%s: %sHigh byte termination " 1076 "Enabled\n", ahc_name(ahc), 1077 enableSEC_high ? "Secondary " 1078 : ""); 1079 } 1080 } 1081 1082 if (((internal50_present ? 1 : 0) 1083 + (internal68_present ? 1 : 0) 1084 + (externalcable_present ? 1 : 0)) <= 1 1085 || (enableSEC_low != 0)) { 1086 if ((ahc->features & AHC_ULTRA2) != 0) 1087 brddat |= BRDDAT5; 1088 else 1089 *sxfrctl1 |= STPWEN; 1090 if (bootverbose) { 1091 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1092 printf("%s: 50 pin termination " 1093 "Enabled\n", ahc_name(ahc)); 1094 else 1095 printf("%s: %sLow byte termination " 1096 "Enabled\n", ahc_name(ahc), 1097 enableSEC_low ? "Secondary " 1098 : ""); 1099 } 1100 } 1101 1102 if (enablePRI_low != 0) { 1103 *sxfrctl1 |= STPWEN; 1104 if (bootverbose) 1105 printf("%s: Primary Low Byte termination " 1106 "Enabled\n", ahc_name(ahc)); 1107 } 1108 1109 /* 1110 * Setup STPWEN before setting up the rest of 1111 * the termination per the tech note on the U160 cards. 1112 */ 1113 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1114 1115 if (enablePRI_high != 0) { 1116 brddat |= BRDDAT4; 1117 if (bootverbose) 1118 printf("%s: Primary High Byte " 1119 "termination Enabled\n", 1120 ahc_name(ahc)); 1121 } 1122 1123 write_brdctl(ahc, brddat); 1124 1125 } else { 1126 if ((adapter_control & CFSTERM) != 0) { 1127 *sxfrctl1 |= STPWEN; 1128 1129 if (bootverbose) 1130 printf("%s: %sLow byte termination Enabled\n", 1131 ahc_name(ahc), 1132 (ahc->features & AHC_ULTRA2) 1133 ? "Primary " : ""); 1134 } 1135 1136 if ((adapter_control & CFWSTERM) != 0) { 1137 brddat |= BRDDAT6; 1138 if (bootverbose) 1139 printf("%s: %sHigh byte termination Enabled\n", 1140 ahc_name(ahc), 1141 (ahc->features & AHC_ULTRA2) 1142 ? "Secondary " : ""); 1143 } 1144 1145 /* 1146 * Setup STPWEN before setting up the rest of 1147 * the termination per the tech note on the U160 cards. 1148 */ 1149 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1150 1151 write_brdctl(ahc, brddat); 1152 } 1153 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1154 } 1155 1156 static void 1157 ahc_new_term_detect(ahc, enableSEC_low, enableSEC_high, enablePRI_low, 1158 enablePRI_high, eeprom_present) 1159 struct ahc_softc *ahc; 1160 int *enableSEC_low; 1161 int *enableSEC_high; 1162 int *enablePRI_low; 1163 int *enablePRI_high; 1164 int *eeprom_present; 1165 { 1166 u_int8_t brdctl; 1167 1168 /* 1169 * BRDDAT7 = Eeprom 1170 * BRDDAT6 = Enable Secondary High Byte termination 1171 * BRDDAT5 = Enable Secondary Low Byte termination 1172 * BRDDAT4 = Enable Primary high byte termination 1173 * BRDDAT3 = Enable Primary low byte termination 1174 */ 1175 brdctl = read_brdctl(ahc); 1176 *eeprom_present = brdctl & BRDDAT7; 1177 *enableSEC_high = (brdctl & BRDDAT6); 1178 *enableSEC_low = (brdctl & BRDDAT5); 1179 *enablePRI_high = (brdctl & BRDDAT4); 1180 *enablePRI_low = (brdctl & BRDDAT3); 1181 } 1182 1183 static void 1184 aic787X_cable_detect(ahc, internal50_present, internal68_present, 1185 externalcable_present, eeprom_present) 1186 struct ahc_softc *ahc; 1187 int *internal50_present; 1188 int *internal68_present; 1189 int *externalcable_present; 1190 int *eeprom_present; 1191 { 1192 u_int8_t brdctl; 1193 1194 /* 1195 * First read the status of our cables. 1196 * Set the rom bank to 0 since the 1197 * bank setting serves as a multiplexor 1198 * for the cable detection logic. 1199 * BRDDAT5 controls the bank switch. 1200 */ 1201 write_brdctl(ahc, 0); 1202 1203 /* 1204 * Now read the state of the internal 1205 * connectors. BRDDAT6 is INT50 and 1206 * BRDDAT7 is INT68. 1207 */ 1208 brdctl = read_brdctl(ahc); 1209 *internal50_present = !(brdctl & BRDDAT6); 1210 *internal68_present = !(brdctl & BRDDAT7); 1211 1212 /* 1213 * Set the rom bank to 1 and determine 1214 * the other signals. 1215 */ 1216 write_brdctl(ahc, BRDDAT5); 1217 1218 /* 1219 * Now read the state of the external 1220 * connectors. BRDDAT6 is EXT68 and 1221 * BRDDAT7 is EPROMPS. 1222 */ 1223 brdctl = read_brdctl(ahc); 1224 *externalcable_present = !(brdctl & BRDDAT6); 1225 *eeprom_present = brdctl & BRDDAT7; 1226 } 1227 1228 static void 1229 aic785X_cable_detect(ahc, internal50_present, externalcable_present, 1230 eeprom_present) 1231 struct ahc_softc *ahc; 1232 int *internal50_present; 1233 int *externalcable_present; 1234 int *eeprom_present; 1235 { 1236 u_int8_t brdctl; 1237 1238 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1239 ahc_outb(ahc, BRDCTL, 0); 1240 brdctl = ahc_inb(ahc, BRDCTL); 1241 *internal50_present = !(brdctl & BRDDAT5); 1242 *externalcable_present = !(brdctl & BRDDAT6); 1243 1244 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1245 } 1246 1247 static void 1248 write_brdctl(ahc, value) 1249 struct ahc_softc *ahc; 1250 u_int8_t value; 1251 { 1252 u_int8_t brdctl; 1253 1254 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1255 brdctl = BRDSTB; 1256 if (ahc->channel == 'B') 1257 brdctl |= BRDCS; 1258 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1259 brdctl = 0; 1260 } else { 1261 brdctl = BRDSTB|BRDCS; 1262 } 1263 ahc_outb(ahc, BRDCTL, brdctl); 1264 DELAY(20); 1265 brdctl |= value; 1266 ahc_outb(ahc, BRDCTL, brdctl); 1267 DELAY(20); 1268 if ((ahc->features & AHC_ULTRA2) != 0) 1269 brdctl |= BRDSTB_ULTRA2; 1270 else 1271 brdctl &= ~BRDSTB; 1272 ahc_outb(ahc, BRDCTL, brdctl); 1273 DELAY(20); 1274 if ((ahc->features & AHC_ULTRA2) != 0) 1275 brdctl = 0; 1276 else 1277 brdctl &= ~BRDCS; 1278 ahc_outb(ahc, BRDCTL, brdctl); 1279 } 1280 1281 static u_int8_t 1282 read_brdctl(ahc) 1283 struct ahc_softc *ahc; 1284 { 1285 u_int8_t brdctl; 1286 u_int8_t value; 1287 1288 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1289 brdctl = BRDRW; 1290 if (ahc->channel == 'B') 1291 brdctl |= BRDCS; 1292 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1293 brdctl = BRDRW_ULTRA2; 1294 } else { 1295 brdctl = BRDRW|BRDCS; 1296 } 1297 ahc_outb(ahc, BRDCTL, brdctl); 1298 DELAY(20); 1299 value = ahc_inb(ahc, BRDCTL); 1300 ahc_outb(ahc, BRDCTL, 0); 1301 return (value); 1302 } 1303 1304 static int 1305 acquire_seeprom(ahc, sd) 1306 struct ahc_softc *ahc; 1307 struct seeprom_descriptor *sd; 1308 { 1309 int wait; 1310 1311 if ((ahc->features & AHC_SPIOCAP) != 0 1312 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1313 return (0); 1314 1315 /* 1316 * Request access of the memory port. When access is 1317 * granted, SEERDY will go high. We use a 1 second 1318 * timeout which should be near 1 second more than 1319 * is needed. Reason: after the chip reset, there 1320 * should be no contention. 1321 */ 1322 SEEPROM_OUTB(sd, sd->sd_MS); 1323 wait = 1000; /* 1 second timeout in msec */ 1324 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1325 DELAY(1000); /* delay 1 msec */ 1326 } 1327 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1328 SEEPROM_OUTB(sd, 0); 1329 return (0); 1330 } 1331 return (1); 1332 } 1333 1334 static void 1335 release_seeprom(sd) 1336 struct seeprom_descriptor *sd; 1337 { 1338 /* Release access to the memory port and the serial EEPROM. */ 1339 SEEPROM_OUTB(sd, 0); 1340 } 1341 1342 #define DPE PCI_STATUS_PARITY_DETECT 1343 #define SSE PCI_STATUS_SPECIAL_ERROR 1344 #define RMA PCI_STATUS_MASTER_ABORT 1345 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 1346 #define STA PCI_STATUS_TARGET_TARGET_ABORT 1347 #define DPR PCI_STATUS_PARITY_ERROR 1348 1349 int 1350 ahc_pci_intr(ahc) 1351 struct ahc_softc *ahc; 1352 { 1353 pcireg_t status1; 1354 struct ahc_pci_data *pd = ahc->pci_data; 1355 1356 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1357 return 0; 1358 1359 status1 = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1360 1361 /* define AHC_SHOW_PCI_ERRORS to get painful errors on your i386 console */ 1362 #ifdef AHC_SHOW_PCI_ERRORS 1363 if (status1 & DPE) { 1364 printf("%s: Data Parity Error Detected during address " 1365 "or write data phase\n", ahc_name(ahc)); 1366 } 1367 #endif 1368 if (status1 & SSE) { 1369 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1370 } 1371 if (status1 & RMA) { 1372 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1373 } 1374 if (status1 & RTA) { 1375 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1376 } 1377 if (status1 & STA) { 1378 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1379 } 1380 if (status1 & DPR) { 1381 printf("%s: Data Parity Error has been reported via PERR#\n", 1382 ahc_name(ahc)); 1383 } 1384 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1385 printf("%s: Latched PCIERR interrupt with " 1386 "no status bits set\n", ahc_name(ahc)); 1387 } 1388 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, status1); 1389 1390 if (status1 & (DPR|RMA|RTA)) { 1391 ahc_outb(ahc, CLRINT, CLRPARERR); 1392 } 1393 1394 return 1; 1395 } 1396