1 /* $OpenBSD: ahc_pci.c,v 1.41 2003/09/25 07:11:15 deraadt Exp $ */ 2 /* $NetBSD: ahc_pci.c,v 1.9 1996/10/21 22:56:24 thorpej Exp $ */ 3 4 /* 5 * Product specific probe and attach routines for: 6 * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1995, 1996 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/queue.h> 41 #include <sys/device.h> 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <scsi/scsi_all.h> 46 #include <scsi/scsiconf.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 53 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 54 55 #include <dev/ic/aic7xxxreg.h> 56 #include <dev/ic/aic7xxx_openbsd.h> 57 #include <dev/ic/aic7xxx_inline.h> 58 #include <dev/ic/smc93cx6var.h> 59 60 /* 61 * XXX memory-mapped is busted on some i386 on-board chips. 62 * for i386, we don't even try it. Also, suppress the damn 63 * PCI bus errors messages on i386. They are not fatal, and are 64 * usually caused by some other device on the PCI bus. But some 65 * ahc cards won't work without ACKing them. So just ACK and go! 66 * XXX- smurph 67 */ 68 #ifndef i386 69 #define AHC_ALLOW_MEMIO 70 #define AHC_SHOW_PCI_ERRORS 71 #endif 72 73 /* 74 * Under normal circumstances, these messages are unnecessary 75 * and not terribly cosmetic. 76 */ 77 #ifdef DEBUG 78 #define bootverbose 1 79 #else 80 #define bootverbose 0 81 #endif 82 83 #define PCI_BASEADR0 PCI_MAPREG_START 84 85 #define AHC_394X_SLOT_CHANNEL_A 4 86 #define AHC_394X_SLOT_CHANNEL_B 5 87 88 #define AHC_398X_SLOT_CHANNEL_A 4 89 #define AHC_398X_SLOT_CHANNEL_B 8 90 #define AHC_398X_SLOT_CHANNEL_C 12 91 92 #define EXROMBADR 0x30 93 #define EXROMEN 0x00000001UL /* External Rom Enable */ 94 95 #define DEVCONFIG 0x40 96 #define SCBSIZE32 0x00010000UL /* aic789X only */ 97 #define REXTVALID 0x00001000UL /* ultra cards only */ 98 #define MPORTMODE 0x00000400UL /* aic7870+ only */ 99 #define RAMPSM 0x00000200UL /* aic7870+ only */ 100 #define VOLSENSE 0x00000100UL 101 #define PCI64BIT 0x00000080UL /* 64Bit PCI bus (Ultra2 Only)*/ 102 #define SCBRAMSEL 0x00000080UL 103 #define MRDCEN 0x00000040UL 104 #define EXTSCBTIME 0x00000020UL /* aic7870 only */ 105 #define EXTSCBPEN 0x00000010UL /* aic7870 only */ 106 #define BERREN 0x00000008UL 107 #define DACEN 0x00000004UL 108 #define STPWLEVEL 0x00000002UL 109 #define DIFACTNEGEN 0x00000001UL /* aic7870 only */ 110 111 #define CSIZE_LATTIME 0x0c 112 #define CACHESIZE 0x0000003fUL /* only 5 bits */ 113 #define LATTIME 0x0000ff00UL 114 115 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 116 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 117 int pcheck, int fast, int large); 118 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 119 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 120 static void configure_termination(struct ahc_softc *ahc, 121 struct seeprom_descriptor *sd, 122 u_int adapter_control, 123 u_int *sxfrctl1); 124 static void ahc_new_term_detect(struct ahc_softc *ahc, 125 int *enableSEC_low, 126 int *enableSEC_high, 127 int *enablePRI_low, 128 int *enablePRI_high, 129 int *eeprom_present); 130 static void aic787X_cable_detect(struct ahc_softc *ahc, 131 int *internal50_present, 132 int *internal68_present, 133 int *externalcable_present, 134 int *eeprom_present); 135 static void aic785X_cable_detect(struct ahc_softc *ahc, 136 int *internal50_present, 137 int *externalcable_present, 138 int *eeprom_present); 139 static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 140 static u_int8_t read_brdctl(struct ahc_softc *ahc); 141 142 int ahc_do_pci_config(struct ahc_softc *ahc); 143 144 void load_seeprom(struct ahc_softc *ahc); 145 static int acquire_seeprom(struct ahc_softc *ahc, 146 struct seeprom_descriptor *sd); 147 static void release_seeprom(struct seeprom_descriptor *sd); 148 static int verify_cksum(struct seeprom_config *); 149 int ahc_probe_scbs(struct ahc_softc *ahc); 150 151 static u_char aic3940_count; 152 153 int ahc_pci_probe(struct device *, void *, void *); 154 void ahc_pci_attach(struct device *, struct device *, void *); 155 156 struct cfattach ahc_pci_ca = { 157 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 158 }; 159 160 const struct pci_matchid ahc_pci_devices[] = { 161 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7810 }, 162 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7850 }, 163 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7855 }, 164 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7860 }, 165 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940AU }, 166 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7870 }, 167 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2930CU }, 168 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940 }, 169 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940 }, 170 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3985 }, 171 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944 }, 172 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC7880 }, 173 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940U }, 174 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_3940U }, 175 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_398XU }, 176 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2944U }, 177 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_2940UWPro }, 178 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_7895 }, 179 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AAA131U2 }, 180 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7890 }, 181 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_2940U2 }, 182 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_2930U2 }, 183 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7892 }, 184 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_29160 }, 185 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_19160B }, 186 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_3950U2B }, 187 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_3950U2D }, 188 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7896 }, 189 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7899B }, 190 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7899D }, 191 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7899F }, 192 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_AIC7899 }, 193 { PCI_VENDOR_ADP2, PCI_PRODUCT_ADP2_3960D }, 194 }; 195 196 int 197 ahc_pci_probe(parent, match, aux) 198 struct device *parent; 199 void *match, *aux; 200 { 201 return (pci_matchbyid((struct pci_attach_args *)aux, ahc_pci_devices, 202 sizeof(ahc_pci_devices)/sizeof(ahc_pci_devices[0]))); 203 } 204 205 void 206 ahc_pci_attach(parent, self, aux) 207 struct device *parent, *self; 208 void *aux; 209 { 210 struct pci_attach_args *pa = aux; 211 struct ahc_softc *ahc = (void *)self; 212 pcireg_t devconfig; 213 pcireg_t command; 214 215 /* setup the PCI stuff */ 216 ahc->dev_softc = pa; 217 218 /* 219 * We really don't allocate our softc, but 220 * we need to do the initialization. And this 221 * also allocates the platform_data structure. 222 */ 223 ahc_alloc(ahc, NULL); 224 ahc_set_name(ahc, ahc->sc_dev.dv_xname); 225 ahc_set_unit(ahc, ahc->sc_dev.dv_unit); 226 227 /* set dma tags */ 228 ahc->parent_dmat = pa->pa_dmat; 229 ahc->buffer_dmat = pa->pa_dmat; 230 ahc->shared_data_dmat = pa->pa_dmat; 231 232 /* card specific setup */ 233 switch (PCI_VENDOR(pa->pa_id)) { 234 case PCI_VENDOR_ADP: 235 switch (PCI_PRODUCT(pa->pa_id)) { 236 case PCI_PRODUCT_ADP_7895: 237 ahc->channel = pa->pa_function == 1 ? 'B' : 'A'; 238 /* The 'C' revision of the aic7895 239 has a few additional features */ 240 if (PCI_REVISION(pa->pa_class) >= 4){ 241 ahc->chip |= AHC_AIC7895C; 242 } else { 243 ahc->chip |= AHC_AIC7895; 244 } 245 break; 246 case PCI_PRODUCT_ADP_3940U: 247 case PCI_PRODUCT_ADP_3940: 248 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADP_3940U) { 249 ahc->chip |= AHC_AIC7880; 250 } else { 251 ahc->chip |= AHC_AIC7870; 252 } 253 aic3940_count++; 254 if (!(aic3940_count & 0x01)) 255 /* Even count implies second channel */ 256 ahc->channel = 'B'; 257 break; 258 case PCI_PRODUCT_ADP_2940UWPro: 259 ahc->flags |= AHC_INT50_SPEEDFLEX; 260 /* fall through */ 261 case PCI_PRODUCT_ADP_AIC7880: 262 case PCI_PRODUCT_ADP_398XU: /* XXX */ 263 case PCI_PRODUCT_ADP_2944U: 264 case PCI_PRODUCT_ADP_2940U: 265 ahc->chip |= AHC_AIC7880; 266 break; 267 case PCI_PRODUCT_ADP_AIC7870: 268 case PCI_PRODUCT_ADP_2944: 269 case PCI_PRODUCT_ADP_2940: 270 ahc->chip |= AHC_AIC7870; 271 break; 272 case PCI_PRODUCT_ADP_AIC7860: 273 case PCI_PRODUCT_ADP_2940AU: 274 ahc->chip |= AHC_AIC7860; 275 break; 276 case PCI_PRODUCT_ADP_AIC7855: 277 case PCI_PRODUCT_ADP_AIC7850: 278 ahc->chip |= AHC_AIC7850; 279 break; 280 default: 281 /* TTT */ 282 break; 283 } 284 break; 285 case PCI_VENDOR_ADP2: 286 switch (PCI_PRODUCT(pa->pa_id)) { 287 case PCI_PRODUCT_ADP2_AIC7890: 288 case PCI_PRODUCT_ADP2_2940U2: 289 case PCI_PRODUCT_ADP2_2930U2: 290 case PCI_PRODUCT_ADP2_AAA131U2: 291 ahc->chip |= AHC_AIC7890; 292 break; 293 case PCI_PRODUCT_ADP2_AIC7892: 294 case PCI_PRODUCT_ADP2_29160: 295 case PCI_PRODUCT_ADP2_19160B: 296 ahc->chip |= AHC_AIC7892; 297 break; 298 case PCI_PRODUCT_ADP2_3950U2B: 299 case PCI_PRODUCT_ADP2_3950U2D: 300 case PCI_PRODUCT_ADP2_AIC7896: 301 ahc->chip |= AHC_AIC7896; 302 ahc->channel = pa->pa_function == 1 ? 'B' : 'A'; 303 devconfig = ahc_pci_read_config(ahc->dev_softc, 304 DEVCONFIG, 4); 305 /* turn off 64 bit for now XXX smurph */ 306 devconfig &= ~PCI64BIT; 307 ahc_pci_write_config(ahc->dev_softc, 308 DEVCONFIG, devconfig, 4); 309 break; 310 case PCI_PRODUCT_ADP2_AIC7899: 311 case PCI_PRODUCT_ADP2_3960D: 312 ahc->chip |= AHC_AIC7899; 313 ahc->channel = pa->pa_function == 1 ? 'B' : 'A'; 314 break; 315 default: 316 /* TTT */ 317 break; 318 } 319 } 320 321 /* chip specific setup */ 322 switch(ahc->chip){ 323 case AHC_AIC7850: 324 case AHC_AIC7855: 325 case AHC_AIC7859: 326 ahc->features = AHC_AIC7850_FE; 327 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 328 if (PCI_REVISION(pa->pa_class) >= 1) 329 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 330 break; 331 case AHC_AIC7860: 332 ahc->features = AHC_AIC7860_FE; 333 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 334 if (PCI_REVISION(pa->pa_class) >= 1) 335 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 336 break; 337 case AHC_AIC7870: 338 ahc->features = AHC_AIC7870_FE; 339 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 340 break; 341 case AHC_AIC7880: 342 ahc->features = AHC_AIC7880_FE; 343 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 344 if (PCI_REVISION(pa->pa_class) >= 1) { 345 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 346 } else { 347 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 348 } 349 break; 350 case AHC_AIC7895: 351 ahc->features = AHC_AIC7895_FE; 352 ahc->flags |= AHC_NEWEEPROM_FMT; 353 /* 354 * The BIOS disables the use of MWI transactions 355 * since it does not have the MWI bug work around 356 * we have. Disabling MWI reduces performance, so 357 * turn it on again. 358 */ 359 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 360 PCI_COMMAND_STATUS_REG); 361 command |= PCI_COMMAND_INVALIDATE_ENABLE; 362 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 363 command); 364 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 365 | AHC_CACHETHEN_BUG | AHC_PCI_MWI_BUG; 366 break; 367 case AHC_AIC7895C: 368 ahc->features = AHC_AIC7895C_FE; 369 ahc->flags |= AHC_NEWEEPROM_FMT; 370 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 371 | AHC_CACHETHEN_BUG; 372 break; 373 case AHC_AIC7890: 374 ahc->features = AHC_AIC7890_FE; 375 ahc->flags |= AHC_NEWEEPROM_FMT; 376 if (PCI_REVISION(pa->pa_class) == 0) 377 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 378 break; 379 case AHC_AIC7892: 380 ahc->features = AHC_AIC7892_FE; 381 ahc->flags |= AHC_NEWEEPROM_FMT; 382 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 383 break; 384 case AHC_AIC7896: 385 ahc->features = AHC_AIC7896_FE; 386 ahc->flags |= AHC_NEWEEPROM_FMT; 387 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 388 break; 389 case AHC_AIC7899: 390 ahc->features = AHC_AIC7899_FE; 391 ahc->flags |= AHC_NEWEEPROM_FMT; 392 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 393 break; 394 default: 395 break; 396 } 397 398 /* setup the PCI interrupt */ 399 ahc->bus_intr = ahc_pci_intr; 400 ahc->unsolicited_ints = 0; 401 402 if(ahc_do_pci_config(ahc)){ 403 ahc_free(ahc); 404 return; 405 } 406 407 ahc_attach(ahc); 408 } 409 410 int 411 ahc_pci_map_registers(ahc) 412 struct ahc_softc *ahc; 413 { 414 pcireg_t command; 415 int ioh_valid; 416 bus_space_tag_t iot; 417 bus_space_handle_t ioh; 418 struct pci_attach_args *pa = ahc->dev_softc; 419 420 command = ahc_pci_read_config(ahc->dev_softc, 421 PCI_COMMAND_STATUS_REG, 4); 422 #ifdef AHC_ALLOW_MEMIO 423 /* 424 * attempt to use memory mapping on hardware that supports it. 425 * e.g powerpc XXX - smurph 426 * 427 * Note: If this fails, IO mapping is used. 428 */ 429 if ((command & PCI_COMMAND_MEM_ENABLE) != 0) { 430 pcireg_t memtype; 431 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 432 switch (memtype) { 433 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 434 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 435 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 436 memtype, 0, &iot, &ioh, NULL, NULL, 0) == 0); 437 break; 438 default: 439 ioh_valid = 0; 440 } 441 if (ioh_valid) { 442 /* 443 * Do a quick test to see if memory mapped 444 * I/O is functioning correctly. 445 */ 446 ahc->tag = iot; 447 ahc->bsh = ioh; 448 if (ahc_inb(ahc, HCNTRL) == 0xFF) { 449 /* nope, use I/O mapping */ 450 ioh_valid = 0; 451 } else { 452 /* Using memory mapping, disable I/O mapping */ 453 command &= ~PCI_COMMAND_IO_ENABLE; 454 ahc_pci_write_config(ahc->dev_softc, 455 PCI_COMMAND_STATUS_REG, 456 command, 4); 457 } 458 } 459 } 460 461 if (!ioh_valid) /* try to drop back to IO mapping */ 462 #endif 463 { 464 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 465 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0); 466 467 /* Using I/O mapping, disable memory mapping */ 468 command &= ~PCI_COMMAND_MEM_ENABLE; 469 ahc_pci_write_config(ahc->dev_softc, 470 PCI_COMMAND_STATUS_REG, 471 command, 4); 472 } 473 474 if (!ioh_valid) { 475 /* Game Over. Insert coin... */ 476 printf(": unable to map registers\n"); 477 return (1); 478 } 479 ahc->tag = iot; 480 ahc->bsh = ioh; 481 return (0); 482 } 483 484 int 485 ahc_do_pci_config(ahc) 486 struct ahc_softc *ahc; 487 { 488 pcireg_t command; 489 u_int our_id = 0; 490 u_int sxfrctl1; 491 u_int scsiseq; 492 u_int dscommand0; 493 int error; 494 int opri; 495 uint8_t sblkctl; 496 497 498 ahc->chip |= AHC_PCI; 499 #if 0 500 ahc_power_state_change(ahc, AHC_POWER_STATE_D0); 501 #endif 502 error = ahc_pci_map_registers(ahc); 503 if (error != 0) 504 return (error); 505 /* 506 * Registers are mapped. Now it is safe to use 507 * the ahc_inb and ahc_outb macros. 508 */ 509 510 /* 511 * Before we continue probing the card, ensure that 512 * its interrupts are *disabled*. We don't want 513 * a misstep to hang the machine in an interrupt 514 * storm. 515 */ 516 ahc_intr_enable(ahc, FALSE); 517 518 /* 519 * If we need to support high memory, enable dual 520 * address cycles. This bit must be set to enable 521 * high address bit generation even if we are on a 522 * 64bit bus (PCI64BIT set in devconfig). 523 */ 524 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 525 pcireg_t devconfig; 526 527 if (bootverbose) 528 printf("%s: Enabling 39Bit Addressing\n", 529 ahc_name(ahc)); 530 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, 4); 531 devconfig |= DACEN; 532 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, 4); 533 } 534 535 /* Ensure busmastering is enabled */ 536 command = ahc_pci_read_config(ahc->dev_softc, PCI_COMMAND_STATUS_REG, 4); 537 command |= PCI_COMMAND_MASTER_ENABLE; 538 539 ahc_pci_write_config(ahc->dev_softc, PCI_COMMAND_STATUS_REG, command, 4); 540 541 /* On all PCI adapters, we allow SCB paging */ 542 ahc->flags |= AHC_PAGESCBS; 543 544 error = ahc_softc_init(ahc); 545 if (error != 0) 546 return (error); 547 548 /* Remember how the card was setup in case there is no SEEPROM */ 549 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 550 ahc_pause(ahc); 551 if ((ahc->features & AHC_ULTRA2) != 0) 552 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 553 else 554 our_id = ahc_inb(ahc, SCSIID) & OID; 555 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 556 scsiseq = ahc_inb(ahc, SCSISEQ); 557 } else { 558 sxfrctl1 = STPWEN; 559 our_id = 7; 560 scsiseq = 0; 561 } 562 563 error = ahc_reset(ahc); 564 if (error != 0) 565 return (ENXIO); 566 567 if ((ahc->features & AHC_DT) != 0) { 568 u_int sfunct; 569 570 /* Perform ALT-Mode Setup */ 571 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 572 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 573 ahc_outb(ahc, OPTIONMODE, 574 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 575 ahc_outb(ahc, SFUNCT, sfunct); 576 577 /* Normal mode setup */ 578 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 579 |TARGCRCENDEN); 580 } 581 582 /* 583 * Protect ourself from spurrious interrupts during 584 * initialization. 585 */ 586 opri = splbio(); 587 588 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 589 dscommand0 |= MPARCKEN|CACHETHEN; 590 if ((ahc->features & AHC_ULTRA2) != 0) { 591 592 /* 593 * DPARCKEN doesn't work correctly on 594 * some MBs so don't use it. 595 */ 596 dscommand0 &= ~DPARCKEN; 597 } 598 599 /* 600 * Handle chips that must have cache line 601 * streaming (dis/en)abled. 602 */ 603 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 604 dscommand0 |= CACHETHEN; 605 606 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 607 dscommand0 &= ~CACHETHEN; 608 609 ahc_outb(ahc, DSCOMMAND0, dscommand0); 610 611 ahc->pci_cachesize = ahc_pci_read_config(ahc->dev_softc, 612 CSIZE_LATTIME, 4) & CACHESIZE; 613 ahc->pci_cachesize *= 4; 614 615 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 616 && ahc->pci_cachesize == 4) { 617 u_int csl = ahc_pci_read_config(ahc->dev_softc, 618 CSIZE_LATTIME, 4); 619 csl &= ~CACHESIZE; 620 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, csl, 4); 621 ahc->pci_cachesize = 0; 622 } 623 624 /* 625 * We cannot perform ULTRA speeds without the presense 626 * of the external precision resistor. 627 */ 628 if ((ahc->features & AHC_ULTRA) != 0) { 629 uint32_t devconfig; 630 631 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, 4); 632 if ((devconfig & REXTVALID) == 0) 633 ahc->features &= ~AHC_ULTRA; 634 } 635 636 /* See if we have a SEEPROM and perform auto-term */ 637 check_extport(ahc, &sxfrctl1); 638 639 /* 640 * Take the LED out of diagnostic mode 641 */ 642 sblkctl = ahc_inb(ahc, SBLKCTL); 643 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 644 645 if ((ahc->features & AHC_ULTRA2) != 0) { 646 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 647 } else { 648 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 649 } 650 651 if (ahc->flags & AHC_USEDEFAULTS) { 652 /* 653 * PCI Adapter default setup 654 * Should only be used if the adapter does not have 655 * a SEEPROM. 656 */ 657 /* See if someone else set us up already */ 658 if (scsiseq != 0) { 659 printf("%s: Using left over BIOS settings\n", 660 ahc_name(ahc)); 661 ahc->flags &= ~AHC_USEDEFAULTS; 662 ahc->flags |= AHC_BIOS_ENABLED; 663 } else { 664 /* 665 * Assume only one connector and always turn 666 * on termination. 667 */ 668 our_id = 0x07; 669 sxfrctl1 = STPWEN; 670 } 671 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 672 673 ahc->our_id = our_id; 674 } 675 676 /* 677 * Take a look to see if we have external SRAM. 678 * We currently do not attempt to use SRAM that is 679 * shared among multiple controllers. 680 */ 681 ahc_probe_ext_scbram(ahc); 682 683 /* 684 * Record our termination setting for the 685 * generic initialization routine. 686 */ 687 if ((sxfrctl1 & STPWEN) != 0) 688 ahc->flags |= AHC_TERM_ENB_A; 689 690 /* Core initialization */ 691 error = ahc_init(ahc); 692 if (error != 0) 693 return (error); 694 695 /* Special func to force negotiation */ 696 ahc_force_neg(ahc); 697 698 /* 699 * Link this softc in with all other ahc instances. 700 */ 701 ahc_softc_insert(ahc); 702 703 /* 704 * Allow interrupts now that we are completely setup. 705 */ 706 error = ahc_pci_map_int(ahc); 707 if (error != 0) 708 return (error); 709 710 ahc_intr_enable(ahc, TRUE); 711 splx(opri); 712 713 return (0); 714 } 715 716 int 717 ahc_pci_map_int(ahc) 718 struct ahc_softc *ahc; 719 { 720 const char *intrstr = NULL; 721 pci_intr_handle_t ih; 722 struct pci_attach_args *pa = ahc->dev_softc; 723 724 if (pci_intr_map(pa, &ih)) { 725 printf(": couldn't map interrupt\n"); 726 return 1; 727 } 728 intrstr = pci_intr_string(pa->pa_pc, ih); 729 730 ahc->platform_data->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 731 ahc_platform_intr, ahc, 732 ahc->sc_dev.dv_xname); 733 734 if (ahc->platform_data->ih == NULL) { 735 printf(": couldn't establish interrupt"); 736 if (intrstr != NULL) 737 printf(" at %s", intrstr); 738 printf("\n"); 739 return 1; 740 } 741 742 if (intrstr != NULL) 743 printf(": %s\n", intrstr); 744 return 0; 745 } 746 747 /* 748 * Test for the presense of external sram in an 749 * "unshared" configuration. 750 */ 751 static int 752 ahc_ext_scbram_present(struct ahc_softc *ahc) 753 { 754 u_int chip; 755 int ramps; 756 int single_user; 757 uint32_t devconfig; 758 759 chip = ahc->chip & AHC_CHIPID_MASK; 760 761 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, 4); 762 763 single_user = (devconfig & MPORTMODE) != 0; 764 765 if ((ahc->features & AHC_ULTRA2) != 0) 766 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 767 else if (chip >= AHC_AIC7870) 768 ramps = (devconfig & RAMPSM) != 0; 769 else 770 ramps = 0; 771 772 if (ramps && single_user) 773 return (1); 774 return (0); 775 } 776 777 /* 778 * Enable external scbram. 779 */ 780 static void 781 ahc_scbram_config(ahc, enable, pcheck, fast, large) 782 struct ahc_softc *ahc; 783 int enable; 784 int pcheck; 785 int fast; 786 int large; 787 { 788 pcireg_t devconfig; 789 790 if (ahc->features & AHC_MULTI_FUNC) { 791 /* 792 * Set the SCB Base addr (highest address bit) 793 * depending on which channel we are. 794 */ 795 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 796 } 797 798 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, 4); 799 if ((ahc->features & AHC_ULTRA2) != 0) { 800 u_int dscommand0; 801 802 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 803 if (enable) 804 dscommand0 &= ~INTSCBRAMSEL; 805 else 806 dscommand0 |= INTSCBRAMSEL; 807 if (large) 808 dscommand0 &= ~USCBSIZE32; 809 else 810 dscommand0 |= USCBSIZE32; 811 ahc_outb(ahc, DSCOMMAND0, dscommand0); 812 } else { 813 if (fast) 814 devconfig &= ~EXTSCBTIME; 815 else 816 devconfig |= EXTSCBTIME; 817 if (enable) 818 devconfig &= ~SCBRAMSEL; 819 else 820 devconfig |= SCBRAMSEL; 821 if (large) 822 devconfig &= ~SCBSIZE32; 823 else 824 devconfig |= SCBSIZE32; 825 } 826 if (pcheck) 827 devconfig |= EXTSCBPEN; 828 else 829 devconfig &= ~EXTSCBPEN; 830 831 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, 4); 832 } 833 834 /* 835 * Take a look to see if we have external SRAM. 836 * We currently do not attempt to use SRAM that is 837 * shared among multiple controllers. 838 */ 839 static void 840 ahc_probe_ext_scbram(ahc) 841 struct ahc_softc *ahc; 842 { 843 int num_scbs; 844 int test_num_scbs; 845 int enable; 846 int pcheck; 847 int fast; 848 int large; 849 850 enable = FALSE; 851 pcheck = FALSE; 852 fast = FALSE; 853 large = FALSE; 854 num_scbs = 0; 855 856 if (ahc_ext_scbram_present(ahc) == 0) 857 goto done; 858 859 /* 860 * Probe for the best parameters to use. 861 */ 862 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 863 num_scbs = ahc_probe_scbs(ahc); 864 if (num_scbs == 0) { 865 /* The SRAM wasn't really present. */ 866 goto done; 867 } 868 enable = TRUE; 869 870 /* 871 * Clear any outstanding parity error 872 * and ensure that parity error reporting 873 * is enabled. 874 */ 875 ahc_outb(ahc, SEQCTL, 0); 876 ahc_outb(ahc, CLRINT, CLRPARERR); 877 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 878 879 /* Now see if we can do parity */ 880 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 881 num_scbs = ahc_probe_scbs(ahc); 882 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 883 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 884 pcheck = TRUE; 885 886 /* Clear any resulting parity error */ 887 ahc_outb(ahc, CLRINT, CLRPARERR); 888 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 889 890 /* Now see if we can do fast timing */ 891 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 892 test_num_scbs = ahc_probe_scbs(ahc); 893 if (test_num_scbs == num_scbs 894 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 895 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 896 fast = TRUE; 897 898 /* 899 * See if we can use large SCBs and still maintain 900 * the same overall count of SCBs. 901 */ 902 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 903 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 904 test_num_scbs = ahc_probe_scbs(ahc); 905 if (test_num_scbs >= num_scbs) { 906 large = TRUE; 907 num_scbs = test_num_scbs; 908 if (num_scbs >= 64) { 909 /* 910 * We have enough space to move the 911 * "busy targets table" into SCB space 912 * and make it qualify all the way to the 913 * lun level. 914 */ 915 ahc->flags |= AHC_SCB_BTT; 916 } 917 } 918 } 919 done: 920 /* 921 * Disable parity error reporting until we 922 * can load instruction ram. 923 */ 924 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 925 /* Clear any latched parity error */ 926 ahc_outb(ahc, CLRINT, CLRPARERR); 927 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 928 if (bootverbose && enable) { 929 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 930 ahc_name(ahc), fast ? "fast" : "slow", 931 pcheck ? ", parity checking enabled" : "", 932 large ? 64 : 32); 933 } 934 ahc_scbram_config(ahc, enable, pcheck, fast, large); 935 } 936 937 /* 938 * Check the external port logic for a serial eeprom 939 * and termination/cable detection contrls. 940 */ 941 static void 942 check_extport(ahc, sxfrctl1) 943 struct ahc_softc *ahc; 944 u_int *sxfrctl1; 945 { 946 struct seeprom_descriptor sd; 947 struct seeprom_config sc; 948 u_int scsi_conf; 949 u_int adapter_control; 950 int have_seeprom; 951 int have_autoterm; 952 953 sd.sd_tag = ahc->tag; 954 sd.sd_bsh = ahc->bsh; 955 sd.sd_regsize = 1; 956 sd.sd_control_offset = SEECTL; 957 sd.sd_status_offset = SEECTL; 958 sd.sd_dataout_offset = SEECTL; 959 960 /* 961 * For some multi-channel devices, the c46 is simply too 962 * small to work. For the other controller types, we can 963 * get our information from either SEEPROM type. Set the 964 * type to start our probe with accordingly. 965 */ 966 if (ahc->flags & AHC_LARGE_SEEPROM) 967 sd.sd_chip = C56_66; 968 else 969 sd.sd_chip = C46; 970 971 sd.sd_MS = SEEMS; 972 sd.sd_RDY = SEERDY; 973 sd.sd_CS = SEECS; 974 sd.sd_CK = SEECK; 975 sd.sd_DO = SEEDO; 976 sd.sd_DI = SEEDI; 977 978 have_seeprom = acquire_seeprom(ahc, &sd); 979 if (have_seeprom) { 980 981 if (bootverbose) 982 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 983 984 for (;;) { 985 u_int start_addr; 986 987 start_addr = 32 * (ahc->channel - 'A'); 988 989 have_seeprom = read_seeprom(&sd, (uint16_t *)&sc, 990 start_addr, sizeof(sc)/2); 991 992 if (have_seeprom) 993 have_seeprom = verify_cksum(&sc); 994 995 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 996 if (bootverbose) { 997 if (have_seeprom == 0) 998 printf ("checksum error\n"); 999 else 1000 printf ("done.\n"); 1001 } 1002 break; 1003 } 1004 sd.sd_chip = C56_66; 1005 } 1006 release_seeprom(&sd); 1007 } 1008 1009 if (!have_seeprom) { 1010 /* 1011 * Pull scratch ram settings and treat them as 1012 * if they are the contents of an seeprom if 1013 * the 'ADPT' signature is found in SCB2. 1014 * We manually compose the data as 16bit values 1015 * to avoid endian issues. 1016 */ 1017 ahc_outb(ahc, SCBPTR, 2); 1018 if (ahc_inb(ahc, SCB_BASE) == 'A' 1019 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1020 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1021 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1022 uint16_t *sc_data; 1023 int i; 1024 1025 sc_data = (uint16_t *)≻ 1026 for (i = 0; i < 32; i++) { 1027 uint16_t val; 1028 int j; 1029 1030 j = i * 2; 1031 val = ahc_inb(ahc, SRAM_BASE + j) 1032 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1033 } 1034 have_seeprom = verify_cksum(&sc); 1035 } 1036 /* 1037 * Clear any SCB parity errors in case this data and 1038 * its associated parity was not initialized by the BIOS 1039 */ 1040 ahc_outb(ahc, CLRINT, CLRPARERR); 1041 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1042 } 1043 1044 if (!have_seeprom) { 1045 if (bootverbose) 1046 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1047 ahc->flags |= AHC_USEDEFAULTS; 1048 } else { 1049 /* 1050 * Put the data we've collected down into SRAM 1051 * where ahc_init will find it. 1052 */ 1053 int i; 1054 int max_targ = sc.max_targets & CFMAXTARG; 1055 uint16_t discenable; 1056 uint16_t ultraenb; 1057 1058 discenable = 0; 1059 ultraenb = 0; 1060 if ((sc.adapter_control & CFULTRAEN) != 0) { 1061 /* 1062 * Determine if this adapter has a "newstyle" 1063 * SEEPROM format. 1064 */ 1065 for (i = 0; i < max_targ; i++) { 1066 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1067 ahc->flags |= AHC_NEWEEPROM_FMT; 1068 break; 1069 } 1070 } 1071 } 1072 1073 for (i = 0; i < max_targ; i++) { 1074 u_int scsirate; 1075 uint16_t target_mask; 1076 1077 target_mask = 0x01 << i; 1078 if (sc.device_flags[i] & CFDISC) 1079 discenable |= target_mask; 1080 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1081 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1082 ultraenb |= target_mask; 1083 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1084 ultraenb |= target_mask; 1085 } 1086 if ((sc.device_flags[i] & CFXFER) == 0x04 1087 && (ultraenb & target_mask) != 0) { 1088 /* Treat 10MHz as a non-ultra speed */ 1089 sc.device_flags[i] &= ~CFXFER; 1090 ultraenb &= ~target_mask; 1091 } 1092 if ((ahc->features & AHC_ULTRA2) != 0) { 1093 u_int offset; 1094 1095 if (sc.device_flags[i] & CFSYNCH) 1096 offset = MAX_OFFSET_ULTRA2; 1097 else 1098 offset = 0; 1099 ahc_outb(ahc, TARG_OFFSET + i, offset); 1100 1101 /* 1102 * The ultra enable bits contain the 1103 * high bit of the ultra2 sync rate 1104 * field. 1105 */ 1106 scsirate = (sc.device_flags[i] & CFXFER) 1107 | ((ultraenb & target_mask) 1108 ? 0x8 : 0x0); 1109 if (sc.device_flags[i] & CFWIDEB) 1110 scsirate |= WIDEXFER; 1111 } else { 1112 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1113 if (sc.device_flags[i] & CFSYNCH) 1114 scsirate |= SOFS; 1115 if (sc.device_flags[i] & CFWIDEB) 1116 scsirate |= WIDEXFER; 1117 } 1118 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1119 } 1120 ahc->our_id = sc.brtime_id & CFSCSIID; 1121 1122 scsi_conf = (ahc->our_id & 0x7); 1123 if (sc.adapter_control & CFSPARITY) 1124 scsi_conf |= ENSPCHK; 1125 if (sc.adapter_control & CFRESETB) 1126 scsi_conf |= RESET_SCSI; 1127 1128 ahc->flags |= 1129 (sc.adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1130 1131 if (sc.bios_control & CFEXTEND) 1132 ahc->flags |= AHC_EXTENDED_TRANS_A; 1133 1134 if (sc.bios_control & CFBIOSEN) 1135 ahc->flags |= AHC_BIOS_ENABLED; 1136 if (ahc->features & AHC_ULTRA 1137 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1138 /* Should we enable Ultra mode? */ 1139 if (!(sc.adapter_control & CFULTRAEN)) 1140 /* Treat us as a non-ultra card */ 1141 ultraenb = 0; 1142 } 1143 1144 if (sc.signature == CFSIGNATURE 1145 || sc.signature == CFSIGNATURE2) { 1146 pcireg_t devconfig; 1147 1148 /* Honor the STPWLEVEL settings */ 1149 devconfig = ahc_pci_read_config(ahc->dev_softc, 1150 DEVCONFIG, 4); 1151 devconfig &= ~STPWLEVEL; 1152 if ((sc.bios_control & CFSTPWLEVEL) != 0) 1153 devconfig |= STPWLEVEL; 1154 ahc_pci_write_config(ahc->dev_softc, 1155 DEVCONFIG, devconfig, 4); 1156 } 1157 /* Set SCSICONF info */ 1158 ahc_outb(ahc, SCSICONF, scsi_conf); 1159 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1160 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1161 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1162 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1163 } 1164 1165 /* 1166 * Cards that have the external logic necessary to talk to 1167 * a SEEPROM, are almost certain to have the remaining logic 1168 * necessary for auto-termination control. This assumption 1169 * hasn't failed yet... 1170 */ 1171 have_autoterm = have_seeprom; 1172 if (have_seeprom) 1173 adapter_control = sc.adapter_control; 1174 else 1175 adapter_control = CFAUTOTERM; 1176 1177 /* 1178 * Some low-cost chips have SEEPROM and auto-term control built 1179 * in, instead of using a GAL. They can tell us directly 1180 * if the termination logic is enabled. 1181 */ 1182 if ((ahc->features & AHC_SPIOCAP) != 0) { 1183 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1184 have_autoterm = TRUE; 1185 else 1186 have_autoterm = FALSE; 1187 } 1188 1189 if (have_autoterm) { 1190 acquire_seeprom(ahc, &sd); 1191 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1192 release_seeprom(&sd); 1193 } 1194 } 1195 1196 static void 1197 configure_termination(struct ahc_softc *ahc, 1198 struct seeprom_descriptor *sd, 1199 u_int adapter_control, 1200 u_int *sxfrctl1) 1201 { 1202 uint8_t brddat; 1203 1204 brddat = 0; 1205 1206 /* 1207 * Update the settings in sxfrctl1 to match the 1208 * termination settings 1209 */ 1210 *sxfrctl1 = 0; 1211 1212 /* 1213 * SEECS must be on for the GALS to latch 1214 * the data properly. Be sure to leave MS 1215 * on or we will release the seeprom. 1216 */ 1217 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1218 if ((adapter_control & CFAUTOTERM) != 0 1219 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1220 int internal50_present; 1221 int internal68_present; 1222 int externalcable_present; 1223 int eeprom_present; 1224 int enableSEC_low; 1225 int enableSEC_high; 1226 int enablePRI_low; 1227 int enablePRI_high; 1228 int sum; 1229 1230 enableSEC_low = 0; 1231 enableSEC_high = 0; 1232 enablePRI_low = 0; 1233 enablePRI_high = 0; 1234 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1235 ahc_new_term_detect(ahc, &enableSEC_low, 1236 &enableSEC_high, 1237 &enablePRI_low, 1238 &enablePRI_high, 1239 &eeprom_present); 1240 if ((adapter_control & CFSEAUTOTERM) == 0) { 1241 if (bootverbose) 1242 printf("%s: Manual SE Termination\n", 1243 ahc_name(ahc)); 1244 enableSEC_low = (adapter_control & CFSELOWTERM); 1245 enableSEC_high = 1246 (adapter_control & CFSEHIGHTERM); 1247 } 1248 if ((adapter_control & CFAUTOTERM) == 0) { 1249 if (bootverbose) 1250 printf("%s: Manual LVD Termination\n", 1251 ahc_name(ahc)); 1252 enablePRI_low = (adapter_control & CFSTERM); 1253 enablePRI_high = (adapter_control & CFWSTERM); 1254 } 1255 /* Make the table calculations below happy */ 1256 internal50_present = 0; 1257 internal68_present = 1; 1258 externalcable_present = 1; 1259 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1260 aic785X_cable_detect(ahc, &internal50_present, 1261 &externalcable_present, 1262 &eeprom_present); 1263 } else { 1264 aic787X_cable_detect(ahc, &internal50_present, 1265 &internal68_present, 1266 &externalcable_present, 1267 &eeprom_present); 1268 } 1269 1270 if ((ahc->features & AHC_WIDE) == 0) 1271 internal68_present = 0; 1272 1273 if (bootverbose 1274 && (ahc->features & AHC_ULTRA2) == 0) { 1275 printf("%s: internal 50 cable %s present", 1276 ahc_name(ahc), 1277 internal50_present ? "is":"not"); 1278 1279 if ((ahc->features & AHC_WIDE) != 0) 1280 printf(", internal 68 cable %s present", 1281 internal68_present ? "is":"not"); 1282 printf("\n%s: external cable %s present\n", 1283 ahc_name(ahc), 1284 externalcable_present ? "is":"not"); 1285 } 1286 if (bootverbose) 1287 printf("%s: BIOS eeprom %s present\n", 1288 ahc_name(ahc), eeprom_present ? "is" : "not"); 1289 1290 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1291 /* 1292 * The 50 pin connector is a separate bus, 1293 * so force it to always be terminated. 1294 * In the future, perform current sensing 1295 * to determine if we are in the middle of 1296 * a properly terminated bus. 1297 */ 1298 internal50_present = 0; 1299 } 1300 1301 /* 1302 * Now set the termination based on what 1303 * we found. 1304 * Flash Enable = BRDDAT7 1305 * Secondary High Term Enable = BRDDAT6 1306 * Secondary Low Term Enable = BRDDAT5 (7890) 1307 * Primary High Term Enable = BRDDAT4 (7890) 1308 */ 1309 if ((ahc->features & AHC_ULTRA2) == 0 1310 && (internal50_present != 0) 1311 && (internal68_present != 0) 1312 && (externalcable_present != 0)) { 1313 printf("%s: Illegal cable configuration!!. " 1314 "Only two connectors on the " 1315 "adapter may be used at a " 1316 "time!\n", ahc_name(ahc)); 1317 1318 /* 1319 * Pretend there are no cables in the hope 1320 * that having all of the termination on 1321 * gives us a more stable bus. 1322 */ 1323 internal50_present = 0; 1324 internal68_present = 0; 1325 externalcable_present = 0; 1326 } 1327 1328 if ((ahc->features & AHC_WIDE) != 0 1329 && ((externalcable_present == 0) 1330 || (internal68_present == 0) 1331 || (enableSEC_high != 0))) { 1332 brddat |= BRDDAT6; 1333 if (bootverbose) { 1334 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1335 printf("%s: 68 pin termination " 1336 "Enabled\n", ahc_name(ahc)); 1337 else 1338 printf("%s: %sHigh byte termination " 1339 "Enabled\n", ahc_name(ahc), 1340 enableSEC_high ? "Secondary " 1341 : ""); 1342 } 1343 } 1344 1345 sum = internal50_present + internal68_present 1346 + externalcable_present; 1347 if (sum < 2 || (enableSEC_low != 0)) { 1348 if ((ahc->features & AHC_ULTRA2) != 0) 1349 brddat |= BRDDAT5; 1350 else 1351 *sxfrctl1 |= STPWEN; 1352 if (bootverbose) { 1353 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1354 printf("%s: 50 pin termination " 1355 "Enabled\n", ahc_name(ahc)); 1356 else 1357 printf("%s: %sLow byte termination " 1358 "Enabled\n", ahc_name(ahc), 1359 enableSEC_low ? "Secondary " 1360 : ""); 1361 } 1362 } 1363 1364 if (enablePRI_low != 0) { 1365 *sxfrctl1 |= STPWEN; 1366 if (bootverbose) 1367 printf("%s: Primary Low Byte termination " 1368 "Enabled\n", ahc_name(ahc)); 1369 } 1370 1371 /* 1372 * Setup STPWEN before setting up the rest of 1373 * the termination per the tech note on the U160 cards. 1374 */ 1375 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1376 1377 if (enablePRI_high != 0) { 1378 brddat |= BRDDAT4; 1379 if (bootverbose) 1380 printf("%s: Primary High Byte " 1381 "termination Enabled\n", 1382 ahc_name(ahc)); 1383 } 1384 1385 write_brdctl(ahc, brddat); 1386 1387 } else { 1388 if ((adapter_control & CFSTERM) != 0) { 1389 *sxfrctl1 |= STPWEN; 1390 1391 if (bootverbose) 1392 printf("%s: %sLow byte termination Enabled\n", 1393 ahc_name(ahc), 1394 (ahc->features & AHC_ULTRA2) ? "Primary " 1395 : ""); 1396 } 1397 1398 if ((adapter_control & CFWSTERM) != 0 1399 && (ahc->features & AHC_WIDE) != 0) { 1400 brddat |= BRDDAT6; 1401 if (bootverbose) 1402 printf("%s: %sHigh byte termination Enabled\n", 1403 ahc_name(ahc), 1404 (ahc->features & AHC_ULTRA2) 1405 ? "Secondary " : ""); 1406 } 1407 1408 /* 1409 * Setup STPWEN before setting up the rest of 1410 * the termination per the tech note on the U160 cards. 1411 */ 1412 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1413 1414 if ((ahc->features & AHC_WIDE) != 0) 1415 write_brdctl(ahc, brddat); 1416 } 1417 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1418 } 1419 1420 static void 1421 ahc_new_term_detect(ahc, enableSEC_low, enableSEC_high, enablePRI_low, 1422 enablePRI_high, eeprom_present) 1423 struct ahc_softc *ahc; 1424 int *enableSEC_low; 1425 int *enableSEC_high; 1426 int *enablePRI_low; 1427 int *enablePRI_high; 1428 int *eeprom_present; 1429 { 1430 u_int8_t brdctl; 1431 1432 /* 1433 * BRDDAT7 = Eeprom 1434 * BRDDAT6 = Enable Secondary High Byte termination 1435 * BRDDAT5 = Enable Secondary Low Byte termination 1436 * BRDDAT4 = Enable Primary high byte termination 1437 * BRDDAT3 = Enable Primary low byte termination 1438 */ 1439 brdctl = read_brdctl(ahc); 1440 *eeprom_present = brdctl & BRDDAT7; 1441 *enableSEC_high = (brdctl & BRDDAT6); 1442 *enableSEC_low = (brdctl & BRDDAT5); 1443 *enablePRI_high = (brdctl & BRDDAT4); 1444 *enablePRI_low = (brdctl & BRDDAT3); 1445 } 1446 1447 static void 1448 aic787X_cable_detect(ahc, internal50_present, internal68_present, 1449 externalcable_present, eeprom_present) 1450 struct ahc_softc *ahc; 1451 int *internal50_present; 1452 int *internal68_present; 1453 int *externalcable_present; 1454 int *eeprom_present; 1455 { 1456 u_int8_t brdctl; 1457 1458 /* 1459 * First read the status of our cables. 1460 * Set the rom bank to 0 since the 1461 * bank setting serves as a multiplexor 1462 * for the cable detection logic. 1463 * BRDDAT5 controls the bank switch. 1464 */ 1465 write_brdctl(ahc, 0); 1466 1467 /* 1468 * Now read the state of the internal 1469 * connectors. BRDDAT6 is INT50 and 1470 * BRDDAT7 is INT68. 1471 */ 1472 brdctl = read_brdctl(ahc); 1473 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1474 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1475 1476 /* 1477 * Set the rom bank to 1 and determine 1478 * the other signals. 1479 */ 1480 write_brdctl(ahc, BRDDAT5); 1481 1482 /* 1483 * Now read the state of the external 1484 * connectors. BRDDAT6 is EXT68 and 1485 * BRDDAT7 is EPROMPS. 1486 */ 1487 brdctl = read_brdctl(ahc); 1488 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1489 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1490 } 1491 1492 static void 1493 aic785X_cable_detect(ahc, internal50_present, externalcable_present, 1494 eeprom_present) 1495 struct ahc_softc *ahc; 1496 int *internal50_present; 1497 int *externalcable_present; 1498 int *eeprom_present; 1499 { 1500 u_int8_t brdctl; 1501 1502 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1503 ahc_outb(ahc, BRDCTL, 0); 1504 brdctl = ahc_inb(ahc, BRDCTL); 1505 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1506 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1507 1508 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1509 } 1510 1511 static void 1512 write_brdctl(ahc, value) 1513 struct ahc_softc *ahc; 1514 u_int8_t value; 1515 { 1516 u_int8_t brdctl; 1517 1518 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1519 brdctl = BRDSTB; 1520 if (ahc->channel == 'B') 1521 brdctl |= BRDCS; 1522 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1523 brdctl = 0; 1524 } else { 1525 brdctl = BRDSTB|BRDCS; 1526 } 1527 ahc_outb(ahc, BRDCTL, brdctl); 1528 ahc_flush_device_writes(ahc); 1529 brdctl |= value; 1530 ahc_outb(ahc, BRDCTL, brdctl); 1531 ahc_flush_device_writes(ahc); 1532 if ((ahc->features & AHC_ULTRA2) != 0) 1533 brdctl |= BRDSTB_ULTRA2; 1534 else 1535 brdctl &= ~BRDSTB; 1536 ahc_outb(ahc, BRDCTL, brdctl); 1537 ahc_flush_device_writes(ahc); 1538 if ((ahc->features & AHC_ULTRA2) != 0) 1539 brdctl = 0; 1540 else 1541 brdctl &= ~BRDCS; 1542 ahc_outb(ahc, BRDCTL, brdctl); 1543 } 1544 1545 static u_int8_t 1546 read_brdctl(ahc) 1547 struct ahc_softc *ahc; 1548 { 1549 u_int8_t brdctl; 1550 u_int8_t value; 1551 1552 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1553 brdctl = BRDRW; 1554 if (ahc->channel == 'B') 1555 brdctl |= BRDCS; 1556 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1557 brdctl = BRDRW_ULTRA2; 1558 } else { 1559 brdctl = BRDRW|BRDCS; 1560 } 1561 ahc_outb(ahc, BRDCTL, brdctl); 1562 ahc_flush_device_writes(ahc); 1563 value = ahc_inb(ahc, BRDCTL); 1564 ahc_outb(ahc, BRDCTL, 0); 1565 return (value); 1566 } 1567 1568 static int 1569 acquire_seeprom(ahc, sd) 1570 struct ahc_softc *ahc; 1571 struct seeprom_descriptor *sd; 1572 { 1573 int wait; 1574 1575 if ((ahc->features & AHC_SPIOCAP) != 0 1576 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1577 return (0); 1578 1579 /* 1580 * Request access of the memory port. When access is 1581 * granted, SEERDY will go high. We use a 1 second 1582 * timeout which should be near 1 second more than 1583 * is needed. Reason: after the chip reset, there 1584 * should be no contention. 1585 */ 1586 SEEPROM_OUTB(sd, sd->sd_MS); 1587 wait = 1000; /* 1 second timeout in msec */ 1588 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1589 DELAY(1000); /* delay 1 msec */ 1590 } 1591 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1592 SEEPROM_OUTB(sd, 0); 1593 return (0); 1594 } 1595 return (1); 1596 } 1597 1598 static void 1599 release_seeprom(sd) 1600 struct seeprom_descriptor *sd; 1601 { 1602 /* Release access to the memory port and the serial EEPROM. */ 1603 SEEPROM_OUTB(sd, 0); 1604 } 1605 1606 #define DPE PCI_STATUS_PARITY_DETECT 1607 #define SSE PCI_STATUS_SPECIAL_ERROR 1608 #define RMA PCI_STATUS_MASTER_ABORT 1609 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 1610 #define STA PCI_STATUS_TARGET_TARGET_ABORT 1611 #define DPR PCI_STATUS_PARITY_ERROR 1612 1613 #define PCIDEBUG 1614 #ifdef PCIDEBUG 1615 #define PCI_PRINT(Printstuff) printf Printstuff 1616 #else 1617 #define PCI_PRINT(Printstuff) 1618 #endif 1619 1620 void 1621 ahc_pci_intr(ahc) 1622 struct ahc_softc *ahc; 1623 { 1624 pcireg_t status1; 1625 1626 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1627 return; 1628 PCI_PRINT(("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1629 ahc_name(ahc), 1630 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8))); 1631 1632 status1 = ahc_pci_read_config(ahc->dev_softc, PCI_COMMAND_STATUS_REG, 4); 1633 1634 /* define AHC_SHOW_PCI_ERRORS to get painful errors on your i386 console */ 1635 #ifdef AHC_SHOW_PCI_ERRORS 1636 if (status1 & DPE) { 1637 PCI_PRINT(("%s: Data Parity Error Detected during address " 1638 "or write data phase\n", ahc_name(ahc))); 1639 } 1640 #endif 1641 if (status1 & SSE) { 1642 PCI_PRINT(("%s: Signal System Error Detected\n", ahc_name(ahc))); 1643 } 1644 if (status1 & RMA) { 1645 PCI_PRINT(("%s: Received a Master Abort\n", ahc_name(ahc))); 1646 } 1647 if (status1 & RTA) { 1648 PCI_PRINT(("%s: Received a Target Abort\n", ahc_name(ahc))); 1649 } 1650 if (status1 & STA) { 1651 PCI_PRINT(("%s: Signaled a Target Abort\n", ahc_name(ahc))); 1652 } 1653 if (status1 & DPR) { 1654 PCI_PRINT(("%s: Data Parity Error has been reported via PERR#\n", 1655 ahc_name(ahc))); 1656 } 1657 1658 ahc_pci_write_config(ahc->dev_softc, PCI_COMMAND_STATUS_REG, status1, 4); 1659 1660 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1661 printf("%s: Latched PCIERR interrupt with " 1662 "no status bits set\n", ahc_name(ahc)); 1663 } else { 1664 ahc_outb(ahc, CLRINT, CLRPARERR); 1665 } 1666 1667 ahc_unpause(ahc); 1668 1669 return; 1670 } 1671 1672 static int 1673 verify_cksum(struct seeprom_config *sc) 1674 { 1675 int i; 1676 int maxaddr; 1677 u_int32_t checksum; 1678 u_int16_t *scarray; 1679 1680 maxaddr = (sizeof(*sc)/2) - 1; 1681 checksum = 0; 1682 scarray = (uint16_t *)sc; 1683 1684 for (i = 0; i < maxaddr; i++) 1685 checksum = checksum + scarray[i]; 1686 if (checksum == 0 || 1687 (checksum & 0xFFFF) != sc->checksum) { 1688 return (0); 1689 } else { 1690 return (1); 1691 } 1692 } 1693