1 /* $OpenBSD: ahc_pci.c,v 1.26 2001/09/21 17:55:43 miod Exp $ */ 2 /* $NetBSD: ahc_pci.c,v 1.9 1996/10/21 22:56:24 thorpej Exp $ */ 3 4 /* 5 * Product specific probe and attach routines for: 6 * 3940, 2940, aic7880, aic7870, aic7860 and aic7850 SCSI controllers 7 * 8 * Copyright (c) 1995, 1996 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice immediately at the beginning of the file, without modification, 16 * this list of conditions, and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/queue.h> 41 #include <sys/device.h> 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 45 #include <scsi/scsi_all.h> 46 #include <scsi/scsiconf.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcidevs.h> 51 52 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */ 53 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */ 54 55 #include <dev/ic/aic7xxxreg.h> 56 #include <dev/ic/aic7xxxvar.h> 57 #include <dev/ic/smc93cx6var.h> 58 59 /* 60 * XXX memory-mapped is busted on some i386 on-board chips. 61 * for i386, we don't even try it. Also, suppress the damn 62 * PCI bus errors messages on i386. They are not fatal, and are 63 * usually caused by some other device on the PCI bus. But some 64 * ahc cards won't work without ACKing them. So just ACK and go! 65 * XXX- smurph 66 */ 67 #ifndef i386 68 #define AHC_ALLOW_MEMIO 69 #define AHC_SHOW_PCI_ERRORS 70 #endif 71 72 /* 73 * Under normal circumstances, these messages are unnecessary 74 * and not terribly cosmetic. 75 */ 76 #ifdef DEBUG 77 #define bootverbose 1 78 #else 79 #define bootverbose 0 80 #endif 81 82 #define PCI_BASEADR0 PCI_MAPREG_START 83 84 #define AHC_394X_SLOT_CHANNEL_A 4 85 #define AHC_394X_SLOT_CHANNEL_B 5 86 87 #define AHC_398X_SLOT_CHANNEL_A 4 88 #define AHC_398X_SLOT_CHANNEL_B 8 89 #define AHC_398X_SLOT_CHANNEL_C 12 90 91 #define DEVCONFIG 0x40 92 #define SCBSIZE32 0x00010000UL /* aic789X only */ 93 #define MPORTMODE 0x00000400UL /* aic7870 only */ 94 #define RAMPSM 0x00000200UL /* aic7870 only */ 95 #define VOLSENSE 0x00000100UL 96 #define SCBRAMSEL 0x00000080UL 97 #define PCI64 0x00000080UL /* aic7891 & aic7897 only */ 98 #define MRDCEN 0x00000040UL 99 #define EXTSCBTIME 0x00000020UL /* aic7870 only */ 100 #define EXTSCBPEN 0x00000010UL /* aic7870 & aic7890 only */ 101 #define BERREN 0x00000008UL 102 #define DACEN 0x00000004UL 103 #define STPWLEVEL 0x00000002UL 104 #define DIFACTNEGEN 0x00000001UL /* aic7870 only */ 105 106 #define CSIZE_LATTIME 0x0c 107 #define CACHESIZE 0x0000003ful /* only 5 bits */ 108 #define LATTIME 0x0000ff00ul 109 110 int ahc_pci_intr __P((struct ahc_softc *ahc)); 111 static int ahc_ext_scbram_present __P((struct ahc_softc *ahc)); 112 static void ahc_ext_scbram_config __P((struct ahc_softc *ahc, int enable, 113 int pcheck, int fast)); 114 static void ahc_probe_ext_scbram __P((struct ahc_softc *ahc)); 115 static void check_extport __P((struct ahc_softc *ahc, u_int *sxfrctl1)); 116 static void configure_termination __P((struct ahc_softc *ahc, 117 struct seeprom_descriptor *sd, 118 u_int adapter_control, 119 u_int *sxfrctl1)); 120 static void ahc_new_term_detect __P((struct ahc_softc *ahc, 121 int *enableSEC_low, 122 int *enableSEC_high, 123 int *enablePRI_low, 124 int *enablePRI_high, 125 int *eeprom_present)); 126 static void aic787X_cable_detect __P((struct ahc_softc *ahc, 127 int *internal50_present, 128 int *internal68_present, 129 int *externalcable_present, 130 int *eeprom_present)); 131 static void aic785X_cable_detect __P((struct ahc_softc *ahc, 132 int *internal50_present, 133 int *externalcable_present, 134 int *eeprom_present)); 135 static void write_brdctl __P((struct ahc_softc *ahc, u_int8_t value)); 136 static u_int8_t read_brdctl __P((struct ahc_softc *ahc)); 137 138 void load_seeprom __P((struct ahc_softc *ahc)); 139 static int acquire_seeprom __P((struct ahc_softc *ahc, 140 struct seeprom_descriptor *sd)); 141 static void release_seeprom __P((struct seeprom_descriptor *sd)); 142 int ahc_probe_scbs __P((struct ahc_softc *ahc)); 143 144 static u_char aic3940_count; 145 146 int ahc_pci_probe __P((struct device *, void *, void *)); 147 void ahc_pci_attach __P((struct device *, struct device *, void *)); 148 149 struct cfattach ahc_pci_ca = { 150 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach 151 }; 152 153 struct ahc_pci_data { 154 pci_chipset_tag_t pc; 155 pcitag_t tag; 156 u_int function; 157 }; 158 159 int 160 ahc_pci_probe(parent, match, aux) 161 struct device *parent; 162 void *match, *aux; 163 { 164 struct pci_attach_args *pa = aux; 165 166 switch (PCI_VENDOR(pa->pa_id)) { 167 case PCI_VENDOR_ADP: 168 switch (PCI_PRODUCT(pa->pa_id)) { 169 case PCI_PRODUCT_ADP_AIC7810: 170 case PCI_PRODUCT_ADP_AIC7850: 171 case PCI_PRODUCT_ADP_AIC7855: 172 case PCI_PRODUCT_ADP_AIC5900: 173 case PCI_PRODUCT_ADP_AIC5905: 174 case PCI_PRODUCT_ADP_AIC7860: 175 case PCI_PRODUCT_ADP_2940AU: 176 case PCI_PRODUCT_ADP_AIC7870: 177 case PCI_PRODUCT_ADP_2930CU: 178 case PCI_PRODUCT_ADP_2940: 179 case PCI_PRODUCT_ADP_3940: 180 case PCI_PRODUCT_ADP_3985: 181 case PCI_PRODUCT_ADP_2944: 182 case PCI_PRODUCT_ADP_AIC7880: 183 case PCI_PRODUCT_ADP_2940U: 184 case PCI_PRODUCT_ADP_3940U: 185 case PCI_PRODUCT_ADP_398XU: 186 case PCI_PRODUCT_ADP_2944U: 187 case PCI_PRODUCT_ADP_2940UWPro: 188 case PCI_PRODUCT_ADP_7895: 189 return (1); 190 } 191 break; 192 case PCI_VENDOR_ADP2: 193 switch (PCI_PRODUCT(pa->pa_id)) { 194 case PCI_PRODUCT_ADP2_AIC7890: 195 case PCI_PRODUCT_ADP2_2940U2: 196 case PCI_PRODUCT_ADP2_2930U2: 197 case PCI_PRODUCT_ADP2_AIC7892: 198 case PCI_PRODUCT_ADP2_29160: 199 case PCI_PRODUCT_ADP2_19160B: 200 case PCI_PRODUCT_ADP2_3950U2B: 201 case PCI_PRODUCT_ADP2_3950U2D: 202 case PCI_PRODUCT_ADP2_AIC7896: 203 case PCI_PRODUCT_ADP2_AIC7899B: 204 case PCI_PRODUCT_ADP2_AIC7899D: 205 case PCI_PRODUCT_ADP2_AIC7899F: 206 case PCI_PRODUCT_ADP2_AIC7899: 207 case PCI_PRODUCT_ADP2_3960D: 208 return (1); 209 } 210 break; 211 } 212 return (0); 213 } 214 215 void 216 ahc_pci_attach(parent, self, aux) 217 struct device *parent, *self; 218 void *aux; 219 { 220 struct pci_attach_args *pa = aux; 221 struct ahc_softc *ahc = (void *)self; 222 bus_space_tag_t iot; 223 bus_space_handle_t ioh; 224 pci_intr_handle_t ih; 225 pcireg_t command; 226 const char *intrstr; 227 unsigned opri = 0; 228 ahc_chip ahc_c = AHC_PCI; /* we are a PCI controller */ 229 ahc_flag ahc_flags = AHC_FNONE; 230 ahc_feature ahc_f = AHC_FENONE; 231 int ioh_valid; 232 233 u_char ultra_enb = 0; 234 u_char our_id = 0; 235 u_char channel = 'A'; 236 u_int sxfrctl1; 237 u_int scsiseq; 238 /* So we can access PCI configuration space after init */ 239 struct ahc_pci_data *pd; 240 241 ahc->sc_dmat = pa->pa_dmat; 242 243 command = pci_conf_read(pa->pa_pc, pa->pa_tag, 244 PCI_COMMAND_STATUS_REG); 245 246 switch (PCI_VENDOR(pa->pa_id)) { 247 case PCI_VENDOR_ADP: 248 switch (PCI_PRODUCT(pa->pa_id)) { 249 case PCI_PRODUCT_ADP_7895: 250 { 251 pcireg_t devconfig; 252 channel = pa->pa_function == 1 ? 'B' : 'A'; 253 ahc_c |= AHC_AIC7895; 254 /* The 'C' revision of the aic7895 255 has a few additional features */ 256 if (PCI_REVISION(pa->pa_class) >= 4) 257 ahc_f = AHC_AIC7895C_FE; 258 else 259 ahc_f = AHC_AIC7895_FE; 260 ahc_flags |= AHC_NEWEEPROM_FMT; 261 devconfig = pci_conf_read(pa->pa_pc, 262 pa->pa_tag, 263 DEVCONFIG); 264 devconfig &= ~SCBSIZE32; 265 pci_conf_write(pa->pa_pc, pa->pa_tag, 266 DEVCONFIG, devconfig); 267 } 268 break; 269 case PCI_PRODUCT_ADP_3940U: 270 case PCI_PRODUCT_ADP_3940: 271 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADP_3940U) { 272 ahc_c |= AHC_AIC7880; 273 ahc_f = AHC_AIC7880_FE; 274 } else { 275 ahc_c |= AHC_AIC7870; 276 ahc_f = AHC_AIC7870_FE; 277 } 278 aic3940_count++; 279 if (!(aic3940_count & 0x01)) 280 /* Even count implies second channel */ 281 channel = 'B'; 282 break; 283 case PCI_PRODUCT_ADP_2940UWPro: 284 ahc_c |= AHC_AIC7880; 285 ahc_f = AHC_AIC7880_FE; 286 ahc_f |= AHC_INT50_SPEEDFLEX; 287 case PCI_PRODUCT_ADP_2944U: 288 case PCI_PRODUCT_ADP_2940U: 289 ahc_c |= AHC_AIC7880; 290 ahc_f = AHC_AIC7880_FE; 291 break; 292 case PCI_PRODUCT_ADP_2944: 293 case PCI_PRODUCT_ADP_2940: 294 ahc_c |= AHC_AIC7870; 295 ahc_f = AHC_AIC7870_FE; 296 break; 297 case PCI_PRODUCT_ADP_2940AU: 298 ahc_c |= AHC_AIC7860; 299 ahc_f = AHC_AIC7860_FE; 300 break; 301 case PCI_PRODUCT_ADP_398XU: /* XXX */ 302 case PCI_PRODUCT_ADP_AIC7880: 303 ahc_c |= AHC_AIC7880; 304 ahc_f = AHC_AIC7880_FE; 305 break; 306 case PCI_PRODUCT_ADP_AIC7870: 307 ahc_c |= AHC_AIC7870; 308 ahc_f = AHC_AIC7870_FE; 309 break; 310 case PCI_PRODUCT_ADP_AIC7860: 311 ahc_c |= AHC_AIC7860; 312 ahc_f = AHC_AIC7860_FE; 313 break; 314 case PCI_PRODUCT_ADP_AIC7855: 315 case PCI_PRODUCT_ADP_AIC7850: 316 ahc_c |= AHC_AIC7850; 317 ahc_f = AHC_AIC7850_FE; 318 break; 319 default: 320 /* TTT */ 321 break; 322 } 323 break; 324 case PCI_VENDOR_ADP2: 325 switch (PCI_PRODUCT(pa->pa_id)) { 326 case PCI_PRODUCT_ADP2_AIC7890: 327 case PCI_PRODUCT_ADP2_2940U2: 328 case PCI_PRODUCT_ADP2_2930U2: 329 ahc_c |= AHC_AIC7890; 330 ahc_f = AHC_AIC7890_FE; 331 ahc_flags |= AHC_NEWEEPROM_FMT; 332 break; 333 case PCI_PRODUCT_ADP2_AIC7892: 334 case PCI_PRODUCT_ADP2_29160: 335 case PCI_PRODUCT_ADP2_19160B: 336 ahc_c |= AHC_AIC7892; 337 ahc_f = AHC_AIC7892_FE; 338 ahc_flags |= AHC_NEWEEPROM_FMT; 339 break; 340 case PCI_PRODUCT_ADP2_3950U2B: 341 case PCI_PRODUCT_ADP2_3950U2D: 342 case PCI_PRODUCT_ADP2_AIC7896: 343 { 344 pcireg_t devconfig; 345 channel = pa->pa_function == 1 ? 'B' : 'A'; 346 ahc_c |= AHC_AIC7896; 347 ahc_f = AHC_AIC7896_FE; 348 ahc_flags |= AHC_NEWEEPROM_FMT; 349 devconfig = pci_conf_read(pa->pa_pc, 350 pa->pa_tag, 351 DEVCONFIG); 352 /* turn off 64 bit for now XXX smurph */ 353 devconfig &= ~PCI64; 354 pci_conf_write(pa->pa_pc, pa->pa_tag, 355 DEVCONFIG, devconfig); 356 } 357 break; 358 case PCI_PRODUCT_ADP2_AIC7899: 359 case PCI_PRODUCT_ADP2_3960D: 360 ahc_c |= AHC_AIC7899; 361 ahc_f = AHC_AIC7899_FE; 362 ahc_flags |= AHC_NEWEEPROM_FMT; 363 break; 364 default: 365 /* TTT */ 366 break; 367 } 368 } 369 370 #ifdef AHC_ALLOW_MEMIO 371 /* 372 * attempt to use memory mapping on hardware that supports it. 373 * e.g powerpc XXX - smurph 374 * 375 * Note: If this fails, IO mapping is used. 376 */ 377 if ((command & PCI_COMMAND_MEM_ENABLE) != 0) { 378 pcireg_t memtype; 379 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR); 380 switch (memtype) { 381 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 382 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 383 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR, 384 memtype, 0, &iot, &ioh, NULL, NULL, 0) == 0); 385 break; 386 default: 387 ioh_valid = 0; 388 } 389 } 390 391 if (!ioh_valid) /* try to drop back to IO mapping */ 392 #endif 393 { 394 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR, 395 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0); 396 } 397 398 if (!ioh_valid) { 399 /* Game Over. Insert coin... */ 400 printf(": unable to map registers\n"); 401 return; 402 } 403 404 /* Ensure busmastering is enabled */ 405 command |= PCI_COMMAND_MASTER_ENABLE; 406 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 407 408 pd = malloc(sizeof (struct ahc_pci_data), M_DEVBUF, M_NOWAIT); 409 if (pd == NULL) { 410 printf(": error allocating pci data\n"); 411 return; 412 } 413 414 pd->pc = pa->pa_pc; 415 pd->tag = pa->pa_tag; 416 pd->function = pa->pa_function; 417 418 /* setup the PCI stuff */ 419 ahc->pci_data = pd; 420 ahc->pci_intr_func = ahc_pci_intr; 421 422 423 /* On all PCI adapters, we allow SCB paging */ 424 ahc_flags |= AHC_PAGESCBS; 425 426 ahc_construct(ahc, pa->pa_iot, ioh, ahc_c, ahc_flags, ahc_f, channel); 427 /* Now we can use the ahc_inb and ahc_outb macros */ 428 429 /* setup the PCI error interrupt handler */ 430 ahc->pci_intr_func = &ahc_pci_intr; 431 432 /* Remeber how the card was setup in case there is no SEEPROM */ 433 ahc_outb(ahc, HCNTRL, ahc->pause); 434 if ((ahc->features & AHC_ULTRA2) != 0) 435 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 436 else 437 our_id = ahc_inb(ahc, SCSIID) & OID; 438 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 439 scsiseq = ahc_inb(ahc, SCSISEQ); 440 441 if (ahc_reset(ahc) != 0) { 442 /* Failed */ 443 ahc_free(ahc); 444 return; 445 } 446 447 if (ahc->features & AHC_ULTRA) 448 ultra_enb = bus_space_read_1(pa->pa_iot, ioh, SXFRCTL0) & 449 FAST20; 450 451 if ((ahc->features & AHC_DT) != 0) { 452 u_int optionmode; 453 u_int sfunct; 454 455 /* Perform ALT-Mode Setup */ 456 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 457 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 458 optionmode = ahc_inb(ahc, OPTIONMODE); 459 if (bootverbose) 460 printf("%s: OptionMode = %x\n", ahc_name(ahc), optionmode); 461 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 462 /* Send CRC info in target mode every 4K */ 463 ahc_outb(ahc, TARGCRCCNT, 0); 464 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 465 ahc_outb(ahc, SFUNCT, sfunct); 466 467 /* Normal mode setup */ 468 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 469 |TARGCRCENDEN|TARGCRCCNTEN); 470 } 471 472 if (pci_intr_map(pa, &ih)) { 473 printf(": couldn't map interrupt\n"); 474 ahc_free(ahc); 475 return; 476 } 477 intrstr = pci_intr_string(pa->pa_pc, ih); 478 ahc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ahc_intr, ahc, 479 ahc->sc_dev.dv_xname); 480 481 if (ahc->sc_ih == NULL) { 482 printf(": couldn't establish interrupt"); 483 if (intrstr != NULL) 484 printf(" at %s", intrstr); 485 printf("\n"); 486 ahc_free(ahc); 487 return; 488 } 489 if (intrstr != NULL) 490 printf(": %s\n", intrstr); 491 492 /* 493 * Protect ourself from spurrious interrupts during 494 * intialization. 495 */ 496 opri = splbio(); 497 498 /* 499 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 500 */ 501 { 502 u_int8_t sblkctl; 503 u_int dscommand0; 504 505 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 506 dscommand0 |= MPARCKEN; 507 if ((ahc->features & AHC_ULTRA2) != 0) { 508 509 /* 510 * DPARCKEN doesn't work correctly on 511 * some MBs so don't use it. 512 */ 513 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 514 dscommand0 |= CACHETHEN; 515 } 516 517 ahc_outb(ahc, DSCOMMAND0, dscommand0); 518 519 /* See if we have an SEEPROM and perform auto-term */ 520 check_extport(ahc, &sxfrctl1); 521 522 /* 523 * Take the LED out of diagnostic mode 524 */ 525 sblkctl = ahc_inb(ahc, SBLKCTL); 526 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 527 528 /* 529 * I don't know where this is set in the SEEPROM or by the 530 * BIOS, so we default to 100% on Ultra or slower controllers 531 * and 75% on ULTRA2 controllers. 532 */ 533 if ((ahc->features & AHC_ULTRA2) != 0) { 534 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 535 } else { 536 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 537 } 538 539 if (ahc->flags & AHC_USEDEFAULTS) { 540 /* 541 * PCI Adapter default setup 542 * Should only be used if the adapter does not have 543 * an SEEPROM. 544 */ 545 /* See if someone else set us up already */ 546 if (scsiseq != 0) { 547 printf("%s: Using left over BIOS settings\n", 548 ahc_name(ahc)); 549 ahc->flags &= ~AHC_USEDEFAULTS; 550 } else { 551 /* 552 * Assume only one connector and always turn 553 * on termination. 554 */ 555 our_id = 0x07; 556 sxfrctl1 = STPWEN; 557 } 558 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 559 560 ahc->our_id = our_id; 561 } 562 } 563 564 /* 565 * Take a look to see if we have external SRAM. 566 * We currently do not attempt to use SRAM that is 567 * shared among multiple controllers. 568 */ 569 ahc_probe_ext_scbram(ahc); 570 571 printf("%s: ", ahc_name(ahc)); 572 573 /* 574 * Record our termination setting for the 575 * generic initialization routine. 576 */ 577 if ((sxfrctl1 & STPWEN) != 0) 578 ahc->flags |= AHC_TERM_ENB_A; 579 580 if (ahc_init(ahc)) { 581 ahc_free(ahc); 582 splx(opri); 583 return; /* XXX PCI code should take return status */ 584 } 585 splx(opri); 586 587 ahc_attach(ahc); 588 } 589 590 /* 591 * Test for the presense of external sram in an 592 * "unshared" configuration. 593 */ 594 static int 595 ahc_ext_scbram_present(ahc) 596 struct ahc_softc *ahc; 597 { 598 int ramps; 599 int single_user; 600 pcireg_t devconfig; 601 struct ahc_pci_data *pd = ahc->pci_data; 602 603 devconfig = pci_conf_read(pd->pc, pd->tag, DEVCONFIG); 604 single_user = (devconfig & MPORTMODE) != 0; 605 606 if ((ahc->features & AHC_ULTRA2) != 0) 607 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 608 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 609 ramps = (devconfig & RAMPSM) != 0; 610 else 611 ramps = 0; 612 613 if (ramps && single_user) 614 return (1); 615 return (0); 616 } 617 618 /* 619 * Enable external scbram. 620 */ 621 static void 622 ahc_ext_scbram_config(ahc, enable, pcheck, fast) 623 struct ahc_softc *ahc; 624 int enable; 625 int pcheck; 626 int fast; 627 { 628 pcireg_t devconfig; 629 struct ahc_pci_data *pd = ahc->pci_data; 630 631 if (ahc->features & AHC_MULTI_FUNC) { 632 u_char channel; 633 /* 634 * Set the SCB Base addr (highest address bit) 635 * depending on which channel we are. 636 */ 637 channel = pd->function == 1 ? 1 : 0; 638 ahc_outb(ahc, SCBBADDR, channel); 639 } 640 641 devconfig = pci_conf_read(pd->pc, pd->tag, DEVCONFIG); 642 643 if ((ahc->features & AHC_ULTRA2) != 0) { 644 u_int dscommand0; 645 646 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 647 if (enable) 648 dscommand0 &= ~INTSCBRAMSEL; 649 else 650 dscommand0 |= INTSCBRAMSEL; 651 ahc_outb(ahc, DSCOMMAND0, dscommand0); 652 } else { 653 if (fast) 654 devconfig &= ~EXTSCBTIME; 655 else 656 devconfig |= EXTSCBTIME; 657 if (enable) 658 devconfig &= ~SCBRAMSEL; 659 else 660 devconfig |= SCBRAMSEL; 661 } 662 if (pcheck) 663 devconfig |= EXTSCBPEN; 664 else 665 devconfig &= ~EXTSCBPEN; 666 667 pci_conf_write(pd->pc, pd->tag, DEVCONFIG, devconfig); 668 } 669 670 /* 671 * Take a look to see if we have external SRAM. 672 * We currently do not attempt to use SRAM that is 673 * shared among multiple controllers. 674 */ 675 static void 676 ahc_probe_ext_scbram(ahc) 677 struct ahc_softc *ahc; 678 { 679 int num_scbs; 680 int test_num_scbs; 681 int enable; 682 int pcheck; 683 int fast; 684 685 if (ahc_ext_scbram_present(ahc) == 0) 686 return; 687 688 /* 689 * Probe for the best parameters to use. 690 */ 691 enable = 0; 692 pcheck = 0; 693 fast = 0; 694 ahc_ext_scbram_config(ahc, /*enable*/1, pcheck, fast); 695 num_scbs = ahc_probe_scbs(ahc); 696 if (num_scbs == 0) { 697 /* The SRAM wasn't really present. */ 698 goto done; 699 } 700 enable = 1; 701 702 /* Now see if we can do parity */ 703 ahc_ext_scbram_config(ahc, enable, /*pcheck*/1, fast); 704 num_scbs = ahc_probe_scbs(ahc); 705 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 706 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 707 pcheck = 1; 708 709 /* Clear any resulting parity error */ 710 ahc_outb(ahc, CLRINT, CLRPARERR); 711 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 712 713 /* Now see if we can do fast timing */ 714 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/1); 715 test_num_scbs = ahc_probe_scbs(ahc); 716 if (test_num_scbs == num_scbs 717 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 718 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 719 fast = 1; 720 721 done: 722 /* Clear any resulting parity error */ 723 ahc_outb(ahc, CLRINT, CLRPARERR); 724 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 725 if (bootverbose && enable) { 726 printf("%s: External SRAM, %dns access%s\n", 727 ahc_name(ahc), fast ? 10 : 20, 728 pcheck ? ", parity checking enabled" : ""); 729 730 } 731 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 732 } 733 734 /* 735 * Check the external port logic for a serial eeprom 736 * and termination/cable detection contrls. 737 */ 738 static void 739 check_extport(ahc, sxfrctl1) 740 struct ahc_softc *ahc; 741 u_int *sxfrctl1; 742 { 743 struct seeprom_descriptor sd; 744 struct seeprom_config sc; 745 u_int scsi_conf; 746 u_int adapter_control; 747 int have_seeprom; 748 int have_autoterm; 749 750 sd.sd_tag = ahc->sc_iot; 751 sd.sd_bsh = ahc->sc_ioh; 752 sd.sd_control_offset = SEECTL; 753 sd.sd_status_offset = SEECTL; 754 sd.sd_dataout_offset = SEECTL; 755 756 /* 757 * For some multi-channel devices, the c46 is simply too 758 * small to work. For the other controller types, we can 759 * get our information from either SEEPROM type. Set the 760 * type to start our probe with accordingly. 761 */ 762 if (ahc->flags & AHC_LARGE_SEEPROM) 763 sd.sd_chip = C56_66; 764 else 765 sd.sd_chip = C46; 766 767 sd.sd_MS = SEEMS; 768 sd.sd_RDY = SEERDY; 769 sd.sd_CS = SEECS; 770 sd.sd_CK = SEECK; 771 sd.sd_DO = SEEDO; 772 sd.sd_DI = SEEDI; 773 774 have_seeprom = acquire_seeprom(ahc, &sd); 775 if (have_seeprom) { 776 777 if (bootverbose) 778 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 779 780 for (;;) { 781 bus_size_t start_addr; 782 783 start_addr = 32 * (ahc->channel - 'A'); 784 785 have_seeprom = read_seeprom(&sd, 786 (u_int16_t *)&sc, 787 start_addr, 788 sizeof(sc)/2); 789 790 if (have_seeprom) { 791 /* Check checksum */ 792 int i; 793 int maxaddr; 794 u_int32_t checksum; 795 u_int16_t *scarray; 796 797 maxaddr = (sizeof(sc)/2) - 1; 798 checksum = 0; 799 scarray = (u_int16_t *)≻ 800 801 for (i = 0; i < maxaddr; i++) 802 checksum = checksum + scarray[i]; 803 if (checksum == 0 804 || (checksum & 0xFFFF) != sc.checksum) { 805 if (bootverbose && sd.sd_chip == C56_66) 806 printf ("checksum error\n"); 807 have_seeprom = 0; 808 } else { 809 if (bootverbose) 810 printf("done.\n"); 811 break; 812 } 813 } 814 815 if (sd.sd_chip == C56_66) 816 break; 817 sd.sd_chip = C56_66; 818 } 819 } 820 821 if (!have_seeprom) { 822 if (bootverbose) 823 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 824 ahc->flags |= AHC_USEDEFAULTS; 825 } else { 826 /* 827 * Put the data we've collected down into SRAM 828 * where ahc_init will find it. 829 */ 830 int i; 831 int max_targ = sc.max_targets & CFMAXTARG; 832 u_int16_t discenable; 833 u_int16_t ultraenb; 834 835 discenable = 0; 836 ultraenb = 0; 837 if ((sc.adapter_control & CFULTRAEN) != 0) { 838 /* 839 * Determine if this adapter has a "newstyle" 840 * SEEPROM format. 841 */ 842 for (i = 0; i < max_targ; i++) { 843 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) { 844 ahc->flags |= AHC_NEWEEPROM_FMT; 845 break; 846 } 847 } 848 } 849 850 for (i = 0; i < max_targ; i++) { 851 u_int scsirate; 852 u_int16_t target_mask; 853 854 target_mask = 0x01 << i; 855 if (sc.device_flags[i] & CFDISC) 856 discenable |= target_mask; 857 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 858 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 859 ultraenb |= target_mask; 860 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 861 ultraenb |= target_mask; 862 } 863 if ((sc.device_flags[i] & CFXFER) == 0x04 864 && (ultraenb & target_mask) != 0) { 865 /* Treat 10MHz as a non-ultra speed */ 866 sc.device_flags[i] &= ~CFXFER; 867 ultraenb &= ~target_mask; 868 } 869 if ((ahc->features & AHC_ULTRA2) != 0) { 870 u_int offset; 871 872 if (sc.device_flags[i] & CFSYNCH) 873 offset = MAX_OFFSET_ULTRA2; 874 else 875 offset = 0; 876 ahc_outb(ahc, TARG_OFFSET + i, offset); 877 878 scsirate = (sc.device_flags[i] & CFXFER) 879 | ((ultraenb & target_mask) ? 0x8 : 0x0); 880 if (sc.device_flags[i] & CFWIDEB) 881 scsirate |= WIDEXFER; 882 } else { 883 scsirate = (sc.device_flags[i] & CFXFER) << 4; 884 if (sc.device_flags[i] & CFSYNCH) 885 scsirate |= SOFS; 886 if (sc.device_flags[i] & CFWIDEB) 887 scsirate |= WIDEXFER; 888 } 889 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 890 } 891 ahc->our_id = sc.brtime_id & CFSCSIID; 892 893 scsi_conf = (ahc->our_id & 0x7); 894 if (sc.adapter_control & CFSPARITY) 895 scsi_conf |= ENSPCHK; 896 if (sc.adapter_control & CFRESETB) 897 scsi_conf |= RESET_SCSI; 898 899 if (sc.bios_control & CFEXTEND) 900 ahc->flags |= AHC_EXTENDED_TRANS_A; 901 if (ahc->features & AHC_ULTRA 902 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 903 /* Should we enable Ultra mode? */ 904 if (!(sc.adapter_control & CFULTRAEN)) 905 /* Treat us as a non-ultra card */ 906 ultraenb = 0; 907 } 908 /* Set SCSICONF info */ 909 ahc_outb(ahc, SCSICONF, scsi_conf); 910 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 911 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 912 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 913 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 914 } 915 916 /* 917 * Cards that have the external logic necessary to talk to 918 * a SEEPROM, are almost certain to have the remaining logic 919 * necessary for auto-termination control. This assumption 920 * hasn't failed yet... 921 */ 922 have_autoterm = have_seeprom; 923 if (have_seeprom) 924 adapter_control = sc.adapter_control; 925 else 926 adapter_control = CFAUTOTERM; 927 928 /* 929 * Some low-cost chips have SEEPROM and auto-term control built 930 * in, instead of using a GAL. They can tell us directly 931 * if the termination logic is enabled. 932 */ 933 if ((ahc->features & AHC_SPIOCAP) != 0) { 934 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 935 have_autoterm = 1; 936 else 937 have_autoterm = 0; 938 } 939 940 if (have_autoterm) 941 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 942 943 release_seeprom(&sd); 944 } 945 946 static void 947 configure_termination(ahc, sd, adapter_control, sxfrctl1) 948 struct ahc_softc *ahc; 949 struct seeprom_descriptor *sd; 950 u_int adapter_control; 951 u_int *sxfrctl1; 952 { 953 u_int8_t brddat; 954 955 brddat = 0; 956 957 /* 958 * Update the settings in sxfrctl1 to match the 959 * termination settings 960 */ 961 *sxfrctl1 = 0; 962 963 /* 964 * SEECS must be on for the GALS to latch 965 * the data properly. Be sure to leave MS 966 * on or we will release the seeprom. 967 */ 968 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 969 if ((adapter_control & CFAUTOTERM) != 0 970 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 971 int internal50_present; 972 int internal68_present; 973 int externalcable_present; 974 int eeprom_present; 975 int enableSEC_low; 976 int enableSEC_high; 977 int enablePRI_low; 978 int enablePRI_high; 979 980 enableSEC_low = 0; 981 enableSEC_high = 0; 982 enablePRI_low = 0; 983 enablePRI_high = 0; 984 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 985 ahc_new_term_detect(ahc, &enableSEC_low, 986 &enableSEC_high, 987 &enablePRI_low, 988 &enablePRI_high, 989 &eeprom_present); 990 if ((adapter_control & CFSEAUTOTERM) == 0) { 991 if (bootverbose) 992 printf("%s: Manual SE Termination\n", 993 ahc_name(ahc)); 994 enableSEC_low = (adapter_control & CFSTERM); 995 enableSEC_high = (adapter_control & CFWSTERM); 996 } 997 if ((adapter_control & CFAUTOTERM) == 0) { 998 if (bootverbose) 999 printf("%s: Manual LVD Termination\n", 1000 ahc_name(ahc)); 1001 enablePRI_low = enablePRI_high = 1002 (adapter_control & CFLVDSTERM); 1003 } 1004 /* Make the table calculations below happy */ 1005 internal50_present = 0; 1006 internal68_present = 1; 1007 externalcable_present = 1; 1008 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1009 aic785X_cable_detect(ahc, &internal50_present, 1010 &externalcable_present, 1011 &eeprom_present); 1012 } else { 1013 aic787X_cable_detect(ahc, &internal50_present, 1014 &internal68_present, 1015 &externalcable_present, 1016 &eeprom_present); 1017 } 1018 1019 if ((ahc->features & AHC_WIDE) == 0) 1020 internal68_present = 0; 1021 1022 if (bootverbose) { 1023 if ((ahc->features & AHC_ULTRA2) == 0) { 1024 printf("%s: internal 50 cable %s present, " 1025 "internal 68 cable %s present\n", 1026 ahc_name(ahc), 1027 internal50_present ? "is":"not", 1028 internal68_present ? "is":"not"); 1029 1030 printf("%s: external cable %s present\n", 1031 ahc_name(ahc), 1032 externalcable_present ? "is":"not"); 1033 } 1034 printf("%s: BIOS eeprom %s present\n", 1035 ahc_name(ahc), eeprom_present ? "is" : "not"); 1036 } 1037 1038 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1039 /* 1040 * The 50 pin connector is a separate bus, 1041 * so force it to always be terminated. 1042 * In the future, perform current sensing 1043 * to determine if we are in the middle of 1044 * a properly terminated bus. 1045 */ 1046 internal50_present = 0; 1047 } 1048 1049 /* 1050 * Now set the termination based on what 1051 * we found. 1052 * Flash Enable = BRDDAT7 1053 * Secondary High Term Enable = BRDDAT6 1054 * Secondary Low Term Enable = BRDDAT5 (7890) 1055 * Primary High Term Enable = BRDDAT4 (7890) 1056 */ 1057 if ((ahc->features & AHC_ULTRA2) == 0 1058 && (internal50_present != 0) 1059 && (internal68_present != 0) 1060 && (externalcable_present != 0)) { 1061 printf("%s: Illegal cable configuration!!. " 1062 "Only two connectors on the " 1063 "adapter may be used at a " 1064 "time!\n", ahc_name(ahc)); 1065 } 1066 1067 if ((ahc->features & AHC_WIDE) != 0 1068 && ((externalcable_present == 0) 1069 || (internal68_present == 0) 1070 || (enableSEC_high != 0))) { 1071 brddat |= BRDDAT6; 1072 if (bootverbose) { 1073 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1074 printf("%s: 68 pin termination " 1075 "Enabled\n", ahc_name(ahc)); 1076 else 1077 printf("%s: %sHigh byte termination " 1078 "Enabled\n", ahc_name(ahc), 1079 enableSEC_high ? "Secondary " 1080 : ""); 1081 } 1082 } 1083 1084 if (((internal50_present ? 1 : 0) 1085 + (internal68_present ? 1 : 0) 1086 + (externalcable_present ? 1 : 0)) <= 1 1087 || (enableSEC_low != 0)) { 1088 if ((ahc->features & AHC_ULTRA2) != 0) 1089 brddat |= BRDDAT5; 1090 else 1091 *sxfrctl1 |= STPWEN; 1092 if (bootverbose) { 1093 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1094 printf("%s: 50 pin termination " 1095 "Enabled\n", ahc_name(ahc)); 1096 else 1097 printf("%s: %sLow byte termination " 1098 "Enabled\n", ahc_name(ahc), 1099 enableSEC_low ? "Secondary " 1100 : ""); 1101 } 1102 } 1103 1104 if (enablePRI_low != 0) { 1105 *sxfrctl1 |= STPWEN; 1106 if (bootverbose) 1107 printf("%s: Primary Low Byte termination " 1108 "Enabled\n", ahc_name(ahc)); 1109 } 1110 1111 /* 1112 * Setup STPWEN before setting up the rest of 1113 * the termination per the tech note on the U160 cards. 1114 */ 1115 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1116 1117 if (enablePRI_high != 0) { 1118 brddat |= BRDDAT4; 1119 if (bootverbose) 1120 printf("%s: Primary High Byte " 1121 "termination Enabled\n", 1122 ahc_name(ahc)); 1123 } 1124 1125 write_brdctl(ahc, brddat); 1126 1127 } else { 1128 if ((adapter_control & CFSTERM) != 0) { 1129 *sxfrctl1 |= STPWEN; 1130 1131 if (bootverbose) 1132 printf("%s: %sLow byte termination Enabled\n", 1133 ahc_name(ahc), 1134 (ahc->features & AHC_ULTRA2) 1135 ? "Primary " : ""); 1136 } 1137 1138 if ((adapter_control & CFWSTERM) != 0) { 1139 brddat |= BRDDAT6; 1140 if (bootverbose) 1141 printf("%s: %sHigh byte termination Enabled\n", 1142 ahc_name(ahc), 1143 (ahc->features & AHC_ULTRA2) 1144 ? "Secondary " : ""); 1145 } 1146 1147 /* 1148 * Setup STPWEN before setting up the rest of 1149 * the termination per the tech note on the U160 cards. 1150 */ 1151 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1152 1153 write_brdctl(ahc, brddat); 1154 } 1155 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1156 } 1157 1158 static void 1159 ahc_new_term_detect(ahc, enableSEC_low, enableSEC_high, enablePRI_low, 1160 enablePRI_high, eeprom_present) 1161 struct ahc_softc *ahc; 1162 int *enableSEC_low; 1163 int *enableSEC_high; 1164 int *enablePRI_low; 1165 int *enablePRI_high; 1166 int *eeprom_present; 1167 { 1168 u_int8_t brdctl; 1169 1170 /* 1171 * BRDDAT7 = Eeprom 1172 * BRDDAT6 = Enable Secondary High Byte termination 1173 * BRDDAT5 = Enable Secondary Low Byte termination 1174 * BRDDAT4 = Enable Primary high byte termination 1175 * BRDDAT3 = Enable Primary low byte termination 1176 */ 1177 brdctl = read_brdctl(ahc); 1178 *eeprom_present = brdctl & BRDDAT7; 1179 *enableSEC_high = (brdctl & BRDDAT6); 1180 *enableSEC_low = (brdctl & BRDDAT5); 1181 *enablePRI_high = (brdctl & BRDDAT4); 1182 *enablePRI_low = (brdctl & BRDDAT3); 1183 } 1184 1185 static void 1186 aic787X_cable_detect(ahc, internal50_present, internal68_present, 1187 externalcable_present, eeprom_present) 1188 struct ahc_softc *ahc; 1189 int *internal50_present; 1190 int *internal68_present; 1191 int *externalcable_present; 1192 int *eeprom_present; 1193 { 1194 u_int8_t brdctl; 1195 1196 /* 1197 * First read the status of our cables. 1198 * Set the rom bank to 0 since the 1199 * bank setting serves as a multiplexor 1200 * for the cable detection logic. 1201 * BRDDAT5 controls the bank switch. 1202 */ 1203 write_brdctl(ahc, 0); 1204 1205 /* 1206 * Now read the state of the internal 1207 * connectors. BRDDAT6 is INT50 and 1208 * BRDDAT7 is INT68. 1209 */ 1210 brdctl = read_brdctl(ahc); 1211 *internal50_present = !(brdctl & BRDDAT6); 1212 *internal68_present = !(brdctl & BRDDAT7); 1213 1214 /* 1215 * Set the rom bank to 1 and determine 1216 * the other signals. 1217 */ 1218 write_brdctl(ahc, BRDDAT5); 1219 1220 /* 1221 * Now read the state of the external 1222 * connectors. BRDDAT6 is EXT68 and 1223 * BRDDAT7 is EPROMPS. 1224 */ 1225 brdctl = read_brdctl(ahc); 1226 *externalcable_present = !(brdctl & BRDDAT6); 1227 *eeprom_present = brdctl & BRDDAT7; 1228 } 1229 1230 static void 1231 aic785X_cable_detect(ahc, internal50_present, externalcable_present, 1232 eeprom_present) 1233 struct ahc_softc *ahc; 1234 int *internal50_present; 1235 int *externalcable_present; 1236 int *eeprom_present; 1237 { 1238 u_int8_t brdctl; 1239 1240 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1241 ahc_outb(ahc, BRDCTL, 0); 1242 brdctl = ahc_inb(ahc, BRDCTL); 1243 *internal50_present = !(brdctl & BRDDAT5); 1244 *externalcable_present = !(brdctl & BRDDAT6); 1245 1246 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1247 } 1248 1249 static void 1250 write_brdctl(ahc, value) 1251 struct ahc_softc *ahc; 1252 u_int8_t value; 1253 { 1254 u_int8_t brdctl; 1255 1256 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1257 brdctl = BRDSTB; 1258 if (ahc->channel == 'B') 1259 brdctl |= BRDCS; 1260 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1261 brdctl = 0; 1262 } else { 1263 brdctl = BRDSTB|BRDCS; 1264 } 1265 ahc_outb(ahc, BRDCTL, brdctl); 1266 DELAY(20); 1267 brdctl |= value; 1268 ahc_outb(ahc, BRDCTL, brdctl); 1269 DELAY(20); 1270 if ((ahc->features & AHC_ULTRA2) != 0) 1271 brdctl |= BRDSTB_ULTRA2; 1272 else 1273 brdctl &= ~BRDSTB; 1274 ahc_outb(ahc, BRDCTL, brdctl); 1275 DELAY(20); 1276 if ((ahc->features & AHC_ULTRA2) != 0) 1277 brdctl = 0; 1278 else 1279 brdctl &= ~BRDCS; 1280 ahc_outb(ahc, BRDCTL, brdctl); 1281 } 1282 1283 static u_int8_t 1284 read_brdctl(ahc) 1285 struct ahc_softc *ahc; 1286 { 1287 u_int8_t brdctl; 1288 u_int8_t value; 1289 1290 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1291 brdctl = BRDRW; 1292 if (ahc->channel == 'B') 1293 brdctl |= BRDCS; 1294 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1295 brdctl = BRDRW_ULTRA2; 1296 } else { 1297 brdctl = BRDRW|BRDCS; 1298 } 1299 ahc_outb(ahc, BRDCTL, brdctl); 1300 DELAY(20); 1301 value = ahc_inb(ahc, BRDCTL); 1302 ahc_outb(ahc, BRDCTL, 0); 1303 return (value); 1304 } 1305 1306 static int 1307 acquire_seeprom(ahc, sd) 1308 struct ahc_softc *ahc; 1309 struct seeprom_descriptor *sd; 1310 { 1311 int wait; 1312 1313 if ((ahc->features & AHC_SPIOCAP) != 0 1314 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1315 return (0); 1316 1317 /* 1318 * Request access of the memory port. When access is 1319 * granted, SEERDY will go high. We use a 1 second 1320 * timeout which should be near 1 second more than 1321 * is needed. Reason: after the chip reset, there 1322 * should be no contention. 1323 */ 1324 SEEPROM_OUTB(sd, sd->sd_MS); 1325 wait = 1000; /* 1 second timeout in msec */ 1326 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1327 DELAY(1000); /* delay 1 msec */ 1328 } 1329 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1330 SEEPROM_OUTB(sd, 0); 1331 return (0); 1332 } 1333 return (1); 1334 } 1335 1336 static void 1337 release_seeprom(sd) 1338 struct seeprom_descriptor *sd; 1339 { 1340 /* Release access to the memory port and the serial EEPROM. */ 1341 SEEPROM_OUTB(sd, 0); 1342 } 1343 1344 #define DPE PCI_STATUS_PARITY_DETECT 1345 #define SSE PCI_STATUS_SPECIAL_ERROR 1346 #define RMA PCI_STATUS_MASTER_ABORT 1347 #define RTA PCI_STATUS_MASTER_TARGET_ABORT 1348 #define STA PCI_STATUS_TARGET_TARGET_ABORT 1349 #define DPR PCI_STATUS_PARITY_ERROR 1350 1351 int 1352 ahc_pci_intr(ahc) 1353 struct ahc_softc *ahc; 1354 { 1355 pcireg_t status1; 1356 struct ahc_pci_data *pd = ahc->pci_data; 1357 1358 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) == 0) 1359 return 0; 1360 1361 status1 = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1362 1363 /* define AHC_SHOW_PCI_ERRORS to get painful errors on your i386 console */ 1364 #ifdef AHC_SHOW_PCI_ERRORS 1365 if (status1 & DPE) { 1366 printf("%s: Data Parity Error Detected during address " 1367 "or write data phase\n", ahc_name(ahc)); 1368 } 1369 #endif 1370 if (status1 & SSE) { 1371 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1372 } 1373 if (status1 & RMA) { 1374 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1375 } 1376 if (status1 & RTA) { 1377 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1378 } 1379 if (status1 & STA) { 1380 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1381 } 1382 if (status1 & DPR) { 1383 printf("%s: Data Parity Error has been reported via PERR#\n", 1384 ahc_name(ahc)); 1385 } 1386 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1387 printf("%s: Latched PCIERR interrupt with " 1388 "no status bits set\n", ahc_name(ahc)); 1389 } 1390 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, status1); 1391 1392 if (status1 & (DPR|RMA|RTA)) { 1393 ahc_outb(ahc, CLRINT, CLRPARERR); 1394 } 1395 1396 return 1; 1397 } 1398