1 /* $OpenBSD: agpreg.h,v 1.2 2003/03/19 20:06:28 millert Exp $ */ 2 /* $NetBSD: agpreg.h,v 1.1 2001/09/10 10:01:02 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Doug Rabson 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $ 30 */ 31 32 #ifndef _PCI_AGPREG_H_ 33 #define _PCI_AGPREG_H_ 34 35 /* 36 * Offsets for various AGP configuration registers. 37 */ 38 #define AGP_APBASE 0x10 39 40 /* 41 * Offsets from the AGP Capability pointer. 42 */ 43 #define AGP_CAPID 0x02 44 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 45 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 46 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 47 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 48 49 #define AGP_STATUS 0x4 50 #define AGP_COMMAND 0x8 51 52 /* 53 * Config offsets for Intel AGP chipsets. 54 */ 55 #define AGP_INTEL_NBXCFG 0x50 56 #define AGP_INTEL_STS 0x90 57 #define AGP_INTEL_AGPCTRL 0xb0 58 #define AGP_INTEL_APSIZE 0xb4 59 #define AGP_INTEL_ATTBASE 0xb8 60 61 /* 62 * Config offsets for VIA AGP chipsets. 63 */ 64 #define AGP_VIA_GARTCTRL 0x80 65 #define AGP_VIA_APSIZE 0x84 66 #define AGP_VIA_ATTBASE 0x88 67 68 /* 69 * Config offsets for SiS AGP chipsets. 70 */ 71 #define AGP_SIS_ATTBASE 0x90 72 #define AGP_SIS_WINCTRL 0x94 73 #define AGP_SIS_TLBCTRL 0x97 74 #define AGP_SIS_TLBFLUSH 0x98 75 76 /* 77 * Config offsets for Ali AGP chipsets. 78 */ 79 #define AGP_ALI_AGPCTRL 0xb8 80 #define AGP_ALI_ATTBASE 0xbc 81 #define AGP_ALI_TLBCTRL 0xc0 82 83 /* 84 * Config offsets for the AMD 751 chipset. 85 */ 86 #define AGP_AMD751_REGISTERS 0x14 87 #define AGP_AMD751_APCTRL 0xac 88 #define AGP_AMD751_MODECTRL 0xb0 89 #define AGP_AMD751_MODECTRL_SYNEN 0x80 90 #define AGP_AMD751_MODECTRL2 0xb2 91 #define AGP_AMD751_MODECTRL2_G1LM 0x01 92 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 93 #define AGP_AMD751_MODECTRL2_NGSE 0x08 94 95 /* 96 * Memory mapped register offsets for AMD 751 chipset. 97 */ 98 #define AGP_AMD751_CAPS 0x00 99 #define AGP_AMD751_CAPS_EHI 0x0800 100 #define AGP_AMD751_CAPS_P2P 0x0400 101 #define AGP_AMD751_CAPS_MPC 0x0200 102 #define AGP_AMD751_CAPS_VBE 0x0100 103 #define AGP_AMD751_CAPS_REV 0x00ff 104 #define AGP_AMD751_STATUS 0x02 105 #define AGP_AMD751_STATUS_P2PS 0x0800 106 #define AGP_AMD751_STATUS_GCS 0x0400 107 #define AGP_AMD751_STATUS_MPS 0x0200 108 #define AGP_AMD751_STATUS_VBES 0x0100 109 #define AGP_AMD751_STATUS_P2PE 0x0008 110 #define AGP_AMD751_STATUS_GCE 0x0004 111 #define AGP_AMD751_STATUS_VBEE 0x0001 112 #define AGP_AMD751_ATTBASE 0x04 113 #define AGP_AMD751_TLBCTRL 0x0c 114 115 /* 116 * Config registers for i810 device 0 117 */ 118 #define AGP_I810_SMRAM 0x70 119 #define AGP_I810_SMRAM_GMS 0xc0 120 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 121 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 122 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 123 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 124 #define AGP_I810_MISCC 0x72 125 #define AGP_I810_MISCC_WINSIZE 0x0001 126 #define AGP_I810_MISCC_WINSIZE_64 0x0000 127 #define AGP_I810_MISCC_WINSIZE_32 0x0001 128 #define AGP_I810_MISCC_PLCK 0x0008 129 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 130 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 131 #define AGP_I810_MISCC_WPTC 0x0030 132 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 133 #define AGP_I810_MISCC_WPTC_62 0x0010 134 #define AGP_I810_MISCC_WPTC_50 0x0020 135 #define AGP_I810_MISCC_WPTC_37 0x0030 136 #define AGP_I810_MISCC_RPTC 0x00c0 137 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 138 #define AGP_I810_MISCC_RPTC_62 0x0040 139 #define AGP_I810_MISCC_RPTC_50 0x0080 140 #define AGP_I810_MISCC_RPTC_37 0x00c0 141 142 /* 143 * Config registers for i810 device 1 144 */ 145 #define AGP_I810_GMADR 0x10 146 #define AGP_I810_MMADR 0x14 147 148 /* 149 * Memory mapped register offsets for i810 chipset. 150 */ 151 #define AGP_I810_PGTBL_CTL 0x2020 152 #define AGP_I810_DRT 0x3000 153 #define AGP_I810_DRT_UNPOPULATED 0x00 154 #define AGP_I810_DRT_POPULATED 0x01 155 #define AGP_I810_GTT 0x10000 156 157 /* 158 * Config registers for i830MG device 0 159 */ 160 #define AGP_I830_GCC0 0x50 161 #define AGP_I830_GCC1 0x52 162 #define AGP_I830_GCC1_DEV2 0x08 163 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 164 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 165 #define AGP_I830_GCC1_GMS 0x70 166 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 167 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 168 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 169 #define AGP_I830_GCC1_GMASIZE 0x01 170 #define AGP_I830_GCC1_GMASIZE_64 0x01 171 #define AGP_I830_GCC1_GMASIZE_128 0x00 172 173 #endif /* !_PCI_AGPREG_H_ */ 174