1 /* $OpenBSD: agpreg.h,v 1.12 2008/12/24 05:42:58 oga Exp $ */ 2 /* $NetBSD: agpreg.h,v 1.1 2001/09/10 10:01:02 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Doug Rabson 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $ 30 */ 31 32 #ifndef _PCI_AGPREG_H_ 33 #define _PCI_AGPREG_H_ 34 35 /* 36 * Offsets for various AGP configuration registers. 37 */ 38 #define AGP_APBASE 0x10 39 40 /* 41 * Offsets from the AGP Capability pointer. 42 */ 43 #define AGP_CAPID 0x02 44 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 45 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 46 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 47 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 48 49 #define AGP_STATUS 0x4 50 #define AGP_COMMAND 0x8 51 52 /* 53 * Config offsets for Intel AGP chipsets. 54 */ 55 /* i845/855PM */ 56 #define AGP_I845_AGPMISC 0x51 57 #define AGPMISC_AAGN (1U << 1) /* Aperture AccessEN */ 58 59 /* i840/850/850E */ 60 #define AGP_I840_MCHCFG 0x50 61 #define MCHCFG_AAGN (1U << 9) /* Aperture AccessEN */ 62 63 /* i82443LX/BX/GX */ 64 #define AGP_INTEL_NBXCFG 0x50 65 #define AGP_INTEL_STS 0x90 66 #define NBXCFG_APAE (1U << 10) /* AGPtoPCI AccessDIS */ 67 #define NBXCFG_AAGN (1U << 9) /* Aperture AccessEN */ 68 69 /* Error Status for i8XX Chipset */ 70 #define AGP_INTEL_I8XX_ERRSTS 0xc8 71 72 /* Common register */ 73 #define AGP_INTEL_ERRSTS 0x91 /* Not i8XX */ 74 #define AGP_INTEL_AGPCMD 0xa8 75 #define AGPCMD_SBA (1U << 9) 76 #define AGPCMD_AGPEN (1U << 8) 77 #define AGPCMD_FWEN (1U << 4) 78 #define AGPCMD_RATE_1X (1U << 1) 79 #define AGPCMD_RATE_2X (1U << 2) 80 #define AGPCMD_RATE_4X (1U << 3) 81 82 #define AGP_INTEL_AGPCTRL 0xb0 83 #define AGPCTRL_AGPRSE (1U << 13) /* AGPRSE (82443 only)*/ 84 #define AGPCTRL_GTLB (1U << 7) /* GTLB EN */ 85 86 #define AGP_INTEL_APSIZE 0xb4 87 #define APSIZE_MASK 0x3f 88 89 #define AGP_INTEL_ATTBASE 0xb8 90 91 /* 92 * Config offsets for VIA AGP 2.x chipsets. 93 */ 94 #define AGP_VIA_GARTCTRL 0x80 95 #define AGP_VIA_APSIZE 0x84 96 #define AGP_VIA_ATTBASE 0x88 97 98 /* 99 * Config offsets for VIA AGP 3.0 chipsets. 100 */ 101 #define AGP3_VIA_GARTCTRL 0x90 102 #define AGP3_VIA_APSIZE 0x94 103 #define AGP3_VIA_ATTBASE 0x98 104 #define AGP_VIA_AGPSEL 0xfd 105 106 /* 107 * Config offsets for SiS AGP chipsets. 108 */ 109 #define AGP_SIS_ATTBASE 0x90 110 #define AGP_SIS_WINCTRL 0x94 111 #define AGP_SIS_TLBCTRL 0x97 112 #define AGP_SIS_TLBFLUSH 0x98 113 114 /* 115 * Config offsets for Ali AGP chipsets. 116 */ 117 #define AGP_ALI_AGPCTRL 0xb8 118 #define AGP_ALI_ATTBASE 0xbc 119 #define AGP_ALI_TLBCTRL 0xc0 120 121 /* 122 * Config offsets for the AMD 751 chipset. 123 */ 124 #define AGP_AMD751_REGISTERS 0x14 125 #define AGP_AMD751_APCTRL 0xac 126 #define AGP_AMD751_MODECTRL 0xb0 127 #define AGP_AMD751_MODECTRL_SYNEN 0x80 128 #define AGP_AMD751_MODECTRL2 0xb2 129 #define AGP_AMD751_MODECTRL2_G1LM 0x01 130 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 131 #define AGP_AMD751_MODECTRL2_NGSE 0x08 132 133 /* 134 * Memory mapped register offsets for AMD 751 chipset. 135 */ 136 #define AGP_AMD751_CAPS 0x00 137 #define AGP_AMD751_CAPS_EHI 0x0800 138 #define AGP_AMD751_CAPS_P2P 0x0400 139 #define AGP_AMD751_CAPS_MPC 0x0200 140 #define AGP_AMD751_CAPS_VBE 0x0100 141 #define AGP_AMD751_CAPS_REV 0x00ff 142 #define AGP_AMD751_STATUS 0x02 143 #define AGP_AMD751_STATUS_P2PS 0x0800 144 #define AGP_AMD751_STATUS_GCS 0x0400 145 #define AGP_AMD751_STATUS_MPS 0x0200 146 #define AGP_AMD751_STATUS_VBES 0x0100 147 #define AGP_AMD751_STATUS_P2PE 0x0008 148 #define AGP_AMD751_STATUS_GCE 0x0004 149 #define AGP_AMD751_STATUS_VBEE 0x0001 150 #define AGP_AMD751_ATTBASE 0x04 151 #define AGP_AMD751_TLBCTRL 0x0c 152 153 /* 154 * Config registers for i810 device 0 155 */ 156 #define AGP_I810_SMRAM 0x70 157 #define AGP_I810_SMRAM_GMS 0xc0 158 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 159 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 160 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 161 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 162 #define AGP_I810_MISCC 0x72 163 #define AGP_I810_MISCC_WINSIZE 0x0001 164 #define AGP_I810_MISCC_WINSIZE_64 0x0000 165 #define AGP_I810_MISCC_WINSIZE_32 0x0001 166 #define AGP_I810_MISCC_PLCK 0x0008 167 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 168 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 169 #define AGP_I810_MISCC_WPTC 0x0030 170 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 171 #define AGP_I810_MISCC_WPTC_62 0x0010 172 #define AGP_I810_MISCC_WPTC_50 0x0020 173 #define AGP_I810_MISCC_WPTC_37 0x0030 174 #define AGP_I810_MISCC_RPTC 0x00c0 175 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 176 #define AGP_I810_MISCC_RPTC_62 0x0040 177 #define AGP_I810_MISCC_RPTC_50 0x0080 178 #define AGP_I810_MISCC_RPTC_37 0x00c0 179 180 /* 181 * Config registers for i810 device 1 182 */ 183 #define AGP_I810_GMADR 0x10 184 #define AGP_I810_MMADR 0x14 185 186 /* 187 * Memory mapped register offsets for i810 chipset. 188 */ 189 #define AGP_I810_PGTBL_CTL 0x2020 190 #define AGP_I810_PGTBL_SIZE_MASK 0x0000000e 191 #define AGP_I810_PGTBL_SIZE_512KB (0 << 1) 192 #define AGP_I810_PGTBL_SIZE_256KB (1 << 1) 193 #define AGP_I810_PGTBL_SIZE_128KB (2 << 1) 194 #define AGP_I810_DRT 0x3000 195 #define AGP_I810_DRT_UNPOPULATED 0x00 196 #define AGP_I810_DRT_POPULATED 0x01 197 #define AGP_I810_GTT 0x10000 198 199 /* 200 * Config registers for i830MG device 0 201 */ 202 #define AGP_I830_GCC0 0x50 203 #define AGP_I830_GCC1 0x52 204 #define AGP_I830_GCC1_DEV2 0x08 205 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 206 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 207 #define AGP_I830_GCC1_GMS 0xf0 208 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 209 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 210 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 211 #define AGP_I830_GCC1_GMASIZE 0x01 212 #define AGP_I830_GCC1_GMASIZE_64 0x01 213 #define AGP_I830_GCC1_GMASIZE_128 0x00 214 215 216 /* 217 * Config registers for 852GM/855GM/865G device 0 218 */ 219 #define AGP_I855_GCC1 0x50 220 #define AGP_I855_GCC1_DEV2 0x08 221 #define AGP_I855_GCC1_DEV2_ENABLED 0x00 222 #define AGP_I855_GCC1_DEV2_DISABLED 0x08 223 #define AGP_I855_GCC1_GMS 0xf0 224 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 225 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 226 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 227 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 228 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 229 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 230 231 /* 232 * 915G registers 233 */ 234 #define AGP_I915_GMADR 0x18 235 #define AGP_I915_MMADR 0x10 236 #define AGP_I915_GTTADR 0x1C 237 #define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 238 #define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 239 #define AGP_I915_DEVEN 0x54 240 #define AGP_I915_DEVEN_D2F0 0x08 241 #define AGP_I915_DEVEN_D2F0_ENABLED 0x08 242 #define AGP_I915_DEVEN_D2F0_DISABLED 0x00 243 #define AGP_I915_MSAC 0x62 244 #define AGP_I915_MSAC_GMASIZE 0x02 245 #define AGP_I915_MSAC_GMASIZE_128 0x02 246 #define AGP_I915_MSAC_GMASIZE_256 0x00 247 248 /* 249 * G965 registers 250 */ 251 #define AGP_I965_GMADR 0x18 252 #define AGP_I965_MMADR 0x10 253 #define AGP_I965_MSAC 0x62 254 #define AGP_I965_MSAC_GMASIZE 0x06 255 #define AGP_I965_MSAC_GMASIZE_128 0x00 256 #define AGP_I965_MSAC_GMASIZE_256 0x02 257 #define AGP_I965_MSAC_GMASIZE_512 0x06 258 #define AGP_I965_GTT 0x80000 259 260 /* 261 * G33 registers 262 */ 263 #define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 264 #define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 265 #define AGP_G33_PGTBL_SIZE_MASK (3U << 8) 266 #define AGP_G33_PGTBL_SIZE_1M (1U << 8) 267 #define AGP_G33_PGTBL_SIZE_2M (2U << 8) 268 269 /* 270 * Intel 4-series registers and values 271 */ 272 #define AGP_INTEL_GMCH_GMS_STOLEN_96M 0xa0 273 #define AGP_INTEL_GMCH_GMS_STOLEN_160M 0xb0 274 #define AGP_INTEL_GMCH_GMS_STOLEN_224M 0xc0 275 #define AGP_INTEL_GMCH_GMS_STOLEN_352M 0xd0 276 #define AGP_G4X_GTT 0x200000 277 278 #endif /* !_PCI_AGPREG_H_ */ 279