1 /* $OpenBSD: agpreg.h,v 1.15 2011/10/24 15:42:33 oga Exp $ */ 2 /* $NetBSD: agpreg.h,v 1.1 2001/09/10 10:01:02 fvdl Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Doug Rabson 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: src/sys/pci/agpreg.h,v 1.3 2000/07/12 10:13:04 dfr Exp $ 30 */ 31 32 #ifndef _PCI_AGPREG_H_ 33 #define _PCI_AGPREG_H_ 34 35 /* 36 * Offsets for various AGP configuration registers. 37 */ 38 #define AGP_APBASE 0x10 39 40 /* 41 * Offsets from the AGP Capability pointer. 42 */ 43 #define AGP_CAPID 0x02 44 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 45 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 46 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 47 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 48 49 #define AGP_STATUS 0x4 50 #define AGP_COMMAND 0x8 51 52 /* 53 * Config offsets for Intel AGP chipsets. 54 */ 55 /* i840/850/850E */ 56 #define AGP_I840_MCHCFG 0x50 57 #define MCHCFG_AAGN (1U << 9) /* Aperture AccessEN */ 58 59 /* i82443LX/BX/GX */ 60 #define AGP_INTEL_NBXCFG 0x50 61 #define AGP_INTEL_STS 0x90 62 #define NBXCFG_APAE (1U << 10) /* AGPtoPCI AccessDIS */ 63 #define NBXCFG_AAGN (1U << 9) /* Aperture AccessEN */ 64 65 /* Error Status for i8XX Chipset */ 66 #define AGP_INTEL_I8XX_ERRSTS 0xc8 67 68 /* Common register */ 69 #define AGP_INTEL_ERRCMD 0x90 /* Not i8XX, 8 bits 70 * ERRSTS is at + 1 and is 16 71 */ 72 #define AGP_INTEL_AGPCMD 0xa8 73 #define AGPCMD_SBA (1U << 9) 74 #define AGPCMD_AGPEN (1U << 8) 75 #define AGPCMD_FWEN (1U << 4) 76 #define AGPCMD_RATE_1X (1U << 1) 77 #define AGPCMD_RATE_2X (1U << 2) 78 #define AGPCMD_RATE_4X (1U << 3) 79 80 #define AGP_INTEL_AGPCTRL 0xb0 81 #define AGPCTRL_AGPRSE (1U << 13) /* AGPRSE (82443 only)*/ 82 #define AGPCTRL_GTLB (1U << 7) /* GTLB EN */ 83 84 #define AGP_INTEL_APSIZE 0xb4 85 #define APSIZE_MASK 0x3f 86 87 #define AGP_INTEL_ATTBASE 0xb8 88 89 /* 90 * Config offsets for VIA AGP 2.x chipsets. 91 */ 92 #define AGP_VIA_GARTCTRL 0x80 93 #define AGP_VIA_APSIZE 0x84 94 #define AGP_VIA_ATTBASE 0x88 95 96 /* 97 * Config offsets for VIA AGP 3.0 chipsets. 98 */ 99 #define AGP3_VIA_GARTCTRL 0x90 100 #define AGP3_VIA_APSIZE 0x94 101 #define AGP3_VIA_ATTBASE 0x98 102 #define AGP_VIA_AGPSEL_REG 0xfc 103 #define AGP_VIA_AGPSEL 0xfd 104 105 /* 106 * Config offsets for SiS AGP chipsets. 107 */ 108 #define AGP_SIS_ATTBASE 0x90 109 #define AGP_SIS_WINCTRL 0x94 110 #define AGP_SIS_TLBCTRL 0x97 111 #define AGP_SIS_TLBFLUSH 0x98 112 113 /* 114 * Config offsets for Ali AGP chipsets. 115 */ 116 #define AGP_ALI_AGPCTRL 0xb8 117 #define AGP_ALI_ATTBASE 0xbc 118 #define AGP_ALI_TLBCTRL 0xc0 119 120 /* 121 * Config offsets for the AMD 751 chipset. 122 */ 123 #define AGP_AMD751_REGISTERS 0x14 124 #define AGP_AMD751_APCTRL 0xac 125 #define AGP_AMD751_MODECTRL 0xb0 126 #define AGP_AMD751_MODECTRL_SYNEN 0x80 127 #define AGP_AMD751_MODECTRL2 0xb2 128 #define AGP_AMD751_MODECTRL2_G1LM 0x01 129 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 130 #define AGP_AMD751_MODECTRL2_NGSE 0x08 131 132 /* 133 * Memory mapped register offsets for AMD 751 chipset. 134 */ 135 #define AGP_AMD751_CAPS 0x00 136 #define AGP_AMD751_CAPS_EHI 0x0800 137 #define AGP_AMD751_CAPS_P2P 0x0400 138 #define AGP_AMD751_CAPS_MPC 0x0200 139 #define AGP_AMD751_CAPS_VBE 0x0100 140 #define AGP_AMD751_CAPS_REV 0x00ff 141 #define AGP_AMD751_STATUS 0x02 142 #define AGP_AMD751_STATUS_P2PS 0x0800 143 #define AGP_AMD751_STATUS_GCS 0x0400 144 #define AGP_AMD751_STATUS_MPS 0x0200 145 #define AGP_AMD751_STATUS_VBES 0x0100 146 #define AGP_AMD751_STATUS_P2PE 0x0008 147 #define AGP_AMD751_STATUS_GCE 0x0004 148 #define AGP_AMD751_STATUS_VBEE 0x0001 149 #define AGP_AMD751_ATTBASE 0x04 150 #define AGP_AMD751_TLBCTRL 0x0c 151 152 /* 153 * Config registers for i810 device 0 154 */ 155 #define AGP_I810_SMRAM 0x70 156 #define AGP_I810_SMRAM_GMS 0xc0 157 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 158 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 159 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 160 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 161 #define AGP_I810_MISCC 0x72 162 #define AGP_I810_MISCC_WINSIZE 0x0001 163 #define AGP_I810_MISCC_WINSIZE_64 0x0000 164 #define AGP_I810_MISCC_WINSIZE_32 0x0001 165 #define AGP_I810_MISCC_PLCK 0x0008 166 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 167 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 168 #define AGP_I810_MISCC_WPTC 0x0030 169 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 170 #define AGP_I810_MISCC_WPTC_62 0x0010 171 #define AGP_I810_MISCC_WPTC_50 0x0020 172 #define AGP_I810_MISCC_WPTC_37 0x0030 173 #define AGP_I810_MISCC_RPTC 0x00c0 174 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 175 #define AGP_I810_MISCC_RPTC_62 0x0040 176 #define AGP_I810_MISCC_RPTC_50 0x0080 177 #define AGP_I810_MISCC_RPTC_37 0x00c0 178 179 /* 180 * Config registers for i810 device 1 181 */ 182 #define AGP_I810_GMADR 0x10 183 #define AGP_I810_MMADR 0x14 184 185 /* 186 * Memory mapped register offsets for i810 chipset. 187 */ 188 #define AGP_I810_PGTBL_CTL 0x2020 189 #define AGP_I810_PGTBL_SIZE_MASK 0x0000000e 190 #define AGP_I810_PGTBL_SIZE_512KB (0 << 1) 191 #define AGP_I810_PGTBL_SIZE_256KB (1 << 1) 192 #define AGP_I810_PGTBL_SIZE_128KB (2 << 1) 193 #define AGP_I810_DRT 0x3000 194 #define AGP_I810_DRT_UNPOPULATED 0x00 195 #define AGP_I810_DRT_POPULATED 0x01 196 #define AGP_I810_GTT 0x10000 197 198 /* 199 * Config registers for i830MG device 0 200 */ 201 #define AGP_I830_GCC0 0x50 202 #define AGP_I830_GCC1 0x52 203 #define AGP_I830_GCC1_DEV2 0x08 204 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 205 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 206 #define AGP_I830_GCC1_GMS 0xf0 207 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 208 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 209 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 210 #define AGP_I830_GCC1_GMASIZE 0x01 211 #define AGP_I830_GCC1_GMASIZE_64 0x01 212 #define AGP_I830_GCC1_GMASIZE_128 0x00 213 214 215 /* 216 * Config registers for 852GM/855GM/865G device 0 217 */ 218 #define AGP_I855_GCC1 0x50 219 #define AGP_I855_GCC1_DEV2 0x08 220 #define AGP_I855_GCC1_DEV2_ENABLED 0x00 221 #define AGP_I855_GCC1_DEV2_DISABLED 0x08 222 #define AGP_I855_GCC1_GMS 0xf0 223 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 224 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 225 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 226 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 227 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 228 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 229 230 /* 231 * 915G registers 232 */ 233 #define AGP_I915_GMADR 0x18 234 #define AGP_I915_MMADR 0x10 235 #define AGP_I915_GTTADR 0x1C 236 #define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 237 #define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 238 #define AGP_I915_DEVEN 0x54 239 #define AGP_I915_DEVEN_D2F0 0x08 240 #define AGP_I915_DEVEN_D2F0_ENABLED 0x08 241 #define AGP_I915_DEVEN_D2F0_DISABLED 0x00 242 #define AGP_I915_MSAC 0x62 243 #define AGP_I915_MSAC_GMASIZE 0x02 244 #define AGP_I915_MSAC_GMASIZE_128 0x02 245 #define AGP_I915_MSAC_GMASIZE_256 0x00 246 247 /* 248 * G965 registers 249 */ 250 #define AGP_I965_GMADR 0x18 251 #define AGP_I965_MMADR 0x10 252 #define AGP_I965_MSAC 0x62 253 #define AGP_I965_MSAC_GMASIZE 0x06 254 #define AGP_I965_MSAC_GMASIZE_128 0x00 255 #define AGP_I965_MSAC_GMASIZE_256 0x02 256 #define AGP_I965_MSAC_GMASIZE_512 0x06 257 #define AGP_I965_GTT 0x80000 258 259 /* 260 * G33 registers 261 */ 262 #define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 263 #define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 264 #define AGP_G33_PGTBL_SIZE_MASK (3U << 8) 265 #define AGP_G33_PGTBL_SIZE_1M (1U << 8) 266 #define AGP_G33_PGTBL_SIZE_2M (2U << 8) 267 268 /* 269 * Intel 4-series registers and values 270 */ 271 #define AGP_INTEL_GMCH_GMS_STOLEN_96M 0xa0 272 #define AGP_INTEL_GMCH_GMS_STOLEN_160M 0xb0 273 #define AGP_INTEL_GMCH_GMS_STOLEN_224M 0xc0 274 #define AGP_INTEL_GMCH_GMS_STOLEN_352M 0xd0 275 #define AGP_G4X_GTT 0x200000 276 277 /* 278 * Intel Sandybridge registers and values 279 */ 280 #define AGP_INTEL_SNB_GMCH_CTRL 0x50 281 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_MASK 0xF8 282 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_32M (1 << 3) 283 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_64M (2 << 3) 284 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_96M (3 << 3) 285 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_128M (4 << 3) 286 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_160M (5 << 3) 287 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_192M (6 << 3) 288 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_224M (7 << 3) 289 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_256M (8 << 3) 290 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_288M (9 << 3) 291 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_320M (0xa << 3) 292 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_352M (0xb << 3) 293 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_384M (0xc << 3) 294 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_416M (0xd << 3) 295 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_448M (0xe << 3) 296 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_480M (0xf << 3) 297 #define AGP_INTEL_SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) 298 299 #endif /* !_PCI_AGPREG_H_ */ 300