1 /* $OpenBSD: agp_i810.c,v 1.87 2014/07/12 18:48:51 tedu Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/device.h> 35 #include <sys/rwlock.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/agpvar.h> 41 #include <dev/pci/agpreg.h> 42 #include <dev/pci/vga_pcivar.h> 43 44 #include <machine/bus.h> 45 46 #define READ1(off) bus_space_read_1(isc->map->bst, isc->map->bsh, off) 47 #define READ4(off) bus_space_read_4(isc->map->bst, isc->map->bsh, off) 48 #define WRITE4(off,v) bus_space_write_4(isc->map->bst, isc->map->bsh, off, v) 49 50 /* 51 * Intel IGP gtt bits. 52 */ 53 /* PTE is enabled */ 54 #define INTEL_ENABLED 0x1 55 /* I810/I815 only, memory is in dcache */ 56 #define INTEL_LOCAL 0x2 57 /* Memory is snooped, must not be accessed through gtt from the cpu. */ 58 #define INTEL_COHERENT 0x6 59 60 enum { 61 CHIP_NONE = 0, /* not integrated graphics */ 62 CHIP_I810 = 1, /* i810/i815 */ 63 CHIP_I830 = 2, /* i830/i845 */ 64 CHIP_I855 = 3, /* i852GM/i855GM/i865G */ 65 CHIP_I915 = 4, /* i915G/i915GM */ 66 CHIP_I965 = 5, /* i965/i965GM */ 67 CHIP_G33 = 6, /* G33/Q33/Q35 */ 68 CHIP_G4X = 7, /* G4X */ 69 CHIP_PINEVIEW = 8, /* Pineview/Pineview M */ 70 CHIP_IRONLAKE = 9, /* Clarkdale/Arrandale */ 71 }; 72 73 struct agp_i810_softc { 74 struct device dev; 75 bus_dma_segment_t scrib_seg; 76 struct agp_softc *agpdev; 77 struct agp_gatt *gatt; 78 struct vga_pci_bar *map; 79 struct vga_pci_bar *gtt_map; 80 bus_dmamap_t scrib_dmamap; 81 bus_addr_t isc_apaddr; 82 bus_size_t isc_apsize; /* current aperture size */ 83 int chiptype; /* i810-like or i830 */ 84 u_int32_t dcache_size; /* i810 only */ 85 u_int32_t stolen; /* number of i830/845 gtt 86 entries for stolen memory */ 87 }; 88 89 void agp_i810_attach(struct device *, struct device *, void *); 90 int agp_i810_activate(struct device *, int); 91 void agp_i810_configure(struct agp_i810_softc *); 92 int agp_i810_probe(struct device *, void *, void *); 93 int agp_i810_get_chiptype(struct pci_attach_args *); 94 void agp_i810_bind_page(void *, bus_size_t, paddr_t, int); 95 void agp_i810_unbind_page(void *, bus_size_t); 96 void agp_i810_flush_tlb(void *); 97 int agp_i810_enable(void *, u_int32_t mode); 98 struct agp_memory * agp_i810_alloc_memory(void *, int, vsize_t); 99 int agp_i810_free_memory(void *, struct agp_memory *); 100 int agp_i810_bind_memory(void *, struct agp_memory *, bus_size_t); 101 int agp_i810_unbind_memory(void *, struct agp_memory *); 102 void intagp_write_gtt(struct agp_i810_softc *, bus_size_t, paddr_t); 103 int intagp_gmch_match(struct pci_attach_args *); 104 105 extern void intagp_dma_sync(bus_dma_tag_t, bus_dmamap_t, 106 bus_addr_t, bus_size_t, int); 107 108 struct cfattach intagp_ca = { 109 sizeof(struct agp_i810_softc), agp_i810_probe, agp_i810_attach, 110 NULL, agp_i810_activate, 111 }; 112 113 struct cfdriver intagp_cd = { 114 NULL, "intagp", DV_DULL 115 }; 116 117 struct agp_methods agp_i810_methods = { 118 agp_i810_bind_page, 119 agp_i810_unbind_page, 120 agp_i810_flush_tlb, 121 agp_i810_enable, 122 agp_i810_alloc_memory, 123 agp_i810_free_memory, 124 agp_i810_bind_memory, 125 agp_i810_unbind_memory, 126 }; 127 128 int 129 agp_i810_get_chiptype(struct pci_attach_args *pa) 130 { 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_INTEL_82810_IGD: 133 case PCI_PRODUCT_INTEL_82810_DC100_IGD: 134 case PCI_PRODUCT_INTEL_82810E_IGD: 135 case PCI_PRODUCT_INTEL_82815_IGD: 136 return (CHIP_I810); 137 break; 138 case PCI_PRODUCT_INTEL_82830M_IGD: 139 case PCI_PRODUCT_INTEL_82845G_IGD: 140 return (CHIP_I830); 141 break; 142 case PCI_PRODUCT_INTEL_82854_IGD: 143 case PCI_PRODUCT_INTEL_82855GM_IGD: 144 case PCI_PRODUCT_INTEL_82865G_IGD: 145 return (CHIP_I855); 146 break; 147 case PCI_PRODUCT_INTEL_E7221_IGD: 148 case PCI_PRODUCT_INTEL_82915G_IGD_1: 149 case PCI_PRODUCT_INTEL_82915G_IGD_2: 150 case PCI_PRODUCT_INTEL_82915GM_IGD_1: 151 case PCI_PRODUCT_INTEL_82915GM_IGD_2: 152 case PCI_PRODUCT_INTEL_82945G_IGD_1: 153 case PCI_PRODUCT_INTEL_82945G_IGD_2: 154 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 155 case PCI_PRODUCT_INTEL_82945GM_IGD_2: 156 case PCI_PRODUCT_INTEL_82945GME_IGD_1: 157 return (CHIP_I915); 158 break; 159 case PCI_PRODUCT_INTEL_82946GZ_IGD_1: 160 case PCI_PRODUCT_INTEL_82946GZ_IGD_2: 161 case PCI_PRODUCT_INTEL_82Q965_IGD_1: 162 case PCI_PRODUCT_INTEL_82Q965_IGD_2: 163 case PCI_PRODUCT_INTEL_82G965_IGD_1: 164 case PCI_PRODUCT_INTEL_82G965_IGD_2: 165 case PCI_PRODUCT_INTEL_82GM965_IGD_1: 166 case PCI_PRODUCT_INTEL_82GM965_IGD_2: 167 case PCI_PRODUCT_INTEL_82GME965_IGD_1: 168 case PCI_PRODUCT_INTEL_82GME965_IGD_2: 169 case PCI_PRODUCT_INTEL_82G35_IGD_1: 170 case PCI_PRODUCT_INTEL_82G35_IGD_2: 171 return (CHIP_I965); 172 break; 173 case PCI_PRODUCT_INTEL_82G33_IGD_1: 174 case PCI_PRODUCT_INTEL_82G33_IGD_2: 175 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 176 case PCI_PRODUCT_INTEL_82Q35_IGD_2: 177 return (CHIP_G33); 178 break; 179 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 180 case PCI_PRODUCT_INTEL_4SERIES_IGD: 181 case PCI_PRODUCT_INTEL_82Q45_IGD_1: 182 case PCI_PRODUCT_INTEL_82G45_IGD_1: 183 case PCI_PRODUCT_INTEL_82G41_IGD_1: 184 case PCI_PRODUCT_INTEL_82B43_IGD_1: 185 case PCI_PRODUCT_INTEL_82B43_IGD_2: 186 return (CHIP_G4X); 187 break; 188 case PCI_PRODUCT_INTEL_PINEVIEW_IGC_1: 189 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGC_1: 190 return (CHIP_PINEVIEW); 191 break; 192 case PCI_PRODUCT_INTEL_CLARKDALE_IGD: 193 case PCI_PRODUCT_INTEL_ARRANDALE_IGD: 194 return (CHIP_IRONLAKE); 195 break; 196 } 197 198 return (CHIP_NONE); 199 } 200 201 /* 202 * We're intel IGD, bus 0 function 0 dev 0 should be the GMCH, so it should 203 * be Intel 204 */ 205 int 206 intagp_gmch_match(struct pci_attach_args *pa) 207 { 208 if (pa->pa_bus == 0 && pa->pa_device == 0 && pa->pa_function == 0 && 209 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 210 PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 211 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) 212 return (1); 213 return (0); 214 } 215 216 int 217 agp_i810_probe(struct device *parent, void *match, void *aux) 218 { 219 struct pci_attach_args *pa = aux; 220 221 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 222 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 223 return (0); 224 225 return (agp_i810_get_chiptype(pa) != CHIP_NONE); 226 } 227 228 void 229 agp_i810_attach(struct device *parent, struct device *self, void *aux) 230 { 231 struct agp_i810_softc *isc = (struct agp_i810_softc *)self; 232 struct agp_gatt *gatt; 233 struct pci_attach_args *pa = aux, bpa; 234 struct vga_pci_softc *vga = (struct vga_pci_softc *)parent; 235 bus_addr_t mmaddr, gmaddr, tmp; 236 pcireg_t memtype, reg; 237 u_int32_t stolen; 238 u_int16_t gcc1; 239 240 isc->chiptype = agp_i810_get_chiptype(pa); 241 242 switch (isc->chiptype) { 243 case CHIP_I915: 244 case CHIP_G33: 245 case CHIP_PINEVIEW: 246 gmaddr = AGP_I915_GMADR; 247 mmaddr = AGP_I915_MMADR; 248 memtype = PCI_MAPREG_TYPE_MEM; 249 break; 250 case CHIP_I965: 251 case CHIP_G4X: 252 case CHIP_IRONLAKE: 253 gmaddr = AGP_I965_GMADR; 254 mmaddr = AGP_I965_MMADR; 255 memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT; 256 break; 257 default: 258 gmaddr = AGP_APBASE; 259 mmaddr = AGP_I810_MMADR; 260 memtype = PCI_MAPREG_TYPE_MEM; 261 break; 262 } 263 264 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, gmaddr, memtype, 265 &isc->isc_apaddr, &isc->isc_apsize, NULL) != 0) { 266 printf("can't get aperture info\n"); 267 return; 268 } 269 270 isc->map = vga_pci_bar_map(vga, mmaddr, 0, BUS_SPACE_MAP_LINEAR); 271 if (isc->map == NULL) { 272 printf("can't map mmadr registers\n"); 273 return; 274 } 275 276 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33 || 277 isc->chiptype == CHIP_PINEVIEW) { 278 isc->gtt_map = vga_pci_bar_map(vga, AGP_I915_GTTADR, 0, 279 BUS_SPACE_MAP_LINEAR); 280 if (isc->gtt_map == NULL) { 281 printf("can't map gatt registers\n"); 282 goto out; 283 } 284 } 285 286 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT | M_ZERO); 287 if (gatt == NULL) { 288 printf("can't alloc gatt\n"); 289 goto out; 290 } 291 isc->gatt = gatt; 292 293 gatt->ag_entries = isc->isc_apsize >> AGP_PAGE_SHIFT; 294 295 /* 296 * Find the GMCH, some of the registers we need to read for 297 * configuration purposes are on there. it's always at 298 * 0/0/0 (bus/dev/func). 299 */ 300 if (pci_find_device(&bpa, intagp_gmch_match) == 0) { 301 printf("can't find GMCH\n"); 302 goto out; 303 } 304 305 switch (isc->chiptype) { 306 case CHIP_I810: 307 /* Some i810s have on-chip memory called dcache */ 308 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 309 isc->dcache_size = 4 * 1024 * 1024; 310 else 311 isc->dcache_size = 0; 312 313 /* According to the specs the gatt on the i810 must be 64k */ 314 if (agp_alloc_dmamem(pa->pa_dmat, 64 * 1024, &gatt->ag_dmamap, 315 &gatt->ag_physical, &gatt->ag_dmaseg) != 0) { 316 goto out; 317 } 318 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 319 320 if (bus_dmamem_map(pa->pa_dmat, &gatt->ag_dmaseg, 1, 64 * 1024, 321 (caddr_t *)&gatt->ag_virtual, BUS_DMA_NOWAIT) != 0) 322 goto out; 323 break; 324 325 case CHIP_I830: 326 /* The i830 automatically initializes the 128k gatt on boot. */ 327 328 reg = pci_conf_read(bpa.pa_pc, bpa.pa_tag, AGP_I830_GCC0); 329 gcc1 = (u_int16_t)(reg >> 16); 330 switch (gcc1 & AGP_I830_GCC1_GMS) { 331 case AGP_I830_GCC1_GMS_STOLEN_512: 332 isc->stolen = (512 - 132) * 1024 / 4096; 333 break; 334 case AGP_I830_GCC1_GMS_STOLEN_1024: 335 isc->stolen = (1024 - 132) * 1024 / 4096; 336 break; 337 case AGP_I830_GCC1_GMS_STOLEN_8192: 338 isc->stolen = (8192 - 132) * 1024 / 4096; 339 break; 340 default: 341 isc->stolen = 0; 342 printf("unknown memory configuration, disabling\n"); 343 goto out; 344 } 345 #ifdef DEBUG 346 if (isc->stolen > 0) { 347 printf(": detected %dk stolen memory", 348 isc->stolen * 4); 349 } else 350 printf(": no preallocated video memory\n"); 351 #endif 352 353 /* XXX */ 354 isc->stolen = 0; 355 356 /* GATT address is already in there, make sure it's enabled */ 357 gatt->ag_physical = READ4(AGP_I810_PGTBL_CTL) & ~1; 358 break; 359 360 case CHIP_I855: 361 /* FALLTHROUGH */ 362 case CHIP_I915: 363 /* FALLTHROUGH */ 364 case CHIP_I965: 365 /* FALLTHROUGH */ 366 case CHIP_G33: 367 /* FALLTHROUGH */ 368 case CHIP_G4X: 369 case CHIP_PINEVIEW: 370 case CHIP_IRONLAKE: 371 372 /* Stolen memory is set up at the beginning of the aperture by 373 * the BIOS, consisting of the GATT followed by 4kb for the 374 * BIOS display. 375 */ 376 377 reg = pci_conf_read(bpa.pa_pc, bpa.pa_tag, AGP_I855_GCC1); 378 gcc1 = (u_int16_t)(reg >> 16); 379 switch (isc->chiptype) { 380 case CHIP_I855: 381 /* The 855GM automatically initializes the 128k gatt on boot. */ 382 stolen = 128 + 4; 383 break; 384 case CHIP_I915: 385 /* The 915G automatically initializes the 256k gatt on boot. */ 386 stolen = 256 + 4; 387 break; 388 case CHIP_I965: 389 switch (READ4(AGP_I810_PGTBL_CTL) & 390 AGP_I810_PGTBL_SIZE_MASK) { 391 case AGP_I810_PGTBL_SIZE_512KB: 392 stolen = 512 + 4; 393 break; 394 case AGP_I810_PGTBL_SIZE_256KB: 395 stolen = 256 + 4; 396 break; 397 case AGP_I810_PGTBL_SIZE_128KB: 398 default: 399 stolen = 128 + 4; 400 break; 401 } 402 break; 403 case CHIP_G33: 404 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 405 case AGP_G33_PGTBL_SIZE_2M: 406 stolen = 2048 + 4; 407 break; 408 case AGP_G33_PGTBL_SIZE_1M: 409 default: 410 stolen = 1024 + 4; 411 break; 412 } 413 break; 414 case CHIP_G4X: 415 case CHIP_PINEVIEW: 416 case CHIP_IRONLAKE: 417 /* 418 * GTT stolen is separate from graphics stolen on 419 * 4 series hardware. so ignore it in stolen gtt entries 420 * counting. However, 4Kb of stolen memory isn't mapped 421 * to the GTT. 422 */ 423 stolen = 4; 424 break; 425 default: 426 printf("bad chiptype\n"); 427 goto out; 428 } 429 430 switch (gcc1 & AGP_I855_GCC1_GMS) { 431 case AGP_I855_GCC1_GMS_STOLEN_1M: 432 isc->stolen = (1024 - stolen) * 1024 / 4096; 433 break; 434 case AGP_I855_GCC1_GMS_STOLEN_4M: 435 isc->stolen = (4096 - stolen) * 1024 / 4096; 436 break; 437 case AGP_I855_GCC1_GMS_STOLEN_8M: 438 isc->stolen = (8192 - stolen) * 1024 / 4096; 439 break; 440 case AGP_I855_GCC1_GMS_STOLEN_16M: 441 isc->stolen = (16384 - stolen) * 1024 / 4096; 442 break; 443 case AGP_I855_GCC1_GMS_STOLEN_32M: 444 isc->stolen = (32768 - stolen) * 1024 / 4096; 445 break; 446 case AGP_I915_GCC1_GMS_STOLEN_48M: 447 isc->stolen = (49152 - stolen) * 1024 / 4096; 448 break; 449 case AGP_I915_GCC1_GMS_STOLEN_64M: 450 isc->stolen = (65536 - stolen) * 1024 / 4096; 451 break; 452 case AGP_G33_GCC1_GMS_STOLEN_128M: 453 isc->stolen = (131072 - stolen) * 1024 / 4096; 454 break; 455 case AGP_G33_GCC1_GMS_STOLEN_256M: 456 isc->stolen = (262144 - stolen) * 1024 / 4096; 457 break; 458 case AGP_INTEL_GMCH_GMS_STOLEN_96M: 459 isc->stolen = (98304 - stolen) * 1024 / 4096; 460 break; 461 case AGP_INTEL_GMCH_GMS_STOLEN_160M: 462 isc->stolen = (163840 - stolen) * 1024 / 4096; 463 break; 464 case AGP_INTEL_GMCH_GMS_STOLEN_224M: 465 isc->stolen = (229376 - stolen) * 1024 / 4096; 466 break; 467 case AGP_INTEL_GMCH_GMS_STOLEN_352M: 468 isc->stolen = (360448 - stolen) * 1024 / 4096; 469 break; 470 default: 471 isc->stolen = 0; 472 printf("unknown memory configuration, disabling\n"); 473 goto out; 474 } 475 #ifdef DEBUG 476 if (isc->stolen > 0) { 477 printf(": detected %dk stolen memory", 478 isc->stolen * 4); 479 } else 480 printf(": no preallocated video memory\n"); 481 #endif 482 483 /* XXX */ 484 isc->stolen = 0; 485 486 /* GATT address is already in there, make sure it's enabled */ 487 gatt->ag_physical = READ4(AGP_I810_PGTBL_CTL) & ~1; 488 break; 489 490 default: 491 printf(": unknown initialisation\n"); 492 return; 493 } 494 /* Intel recommends that you have a fake page bound to the gtt always */ 495 if (agp_alloc_dmamem(pa->pa_dmat, AGP_PAGE_SIZE, &isc->scrib_dmamap, 496 &tmp, &isc->scrib_seg) != 0) { 497 printf(": can't get scribble page\n"); 498 return; 499 } 500 agp_i810_configure(isc); 501 502 isc->agpdev = (struct agp_softc *)agp_attach_bus(pa, &agp_i810_methods, 503 isc->isc_apaddr, isc->isc_apsize, &isc->dev); 504 isc->agpdev->sc_stolen_entries = isc->stolen; 505 return; 506 out: 507 508 if (isc->gatt) { 509 if (isc->gatt->ag_size != 0) 510 agp_free_dmamem(pa->pa_dmat, isc->gatt->ag_size, 511 isc->gatt->ag_dmamap, &isc->gatt->ag_dmaseg); 512 free(isc->gatt, M_AGP, 0); 513 } 514 if (isc->gtt_map != NULL) 515 vga_pci_bar_unmap(isc->gtt_map); 516 if (isc->map != NULL) 517 vga_pci_bar_unmap(isc->map); 518 } 519 520 int 521 agp_i810_activate(struct device *arg, int act) 522 { 523 struct agp_i810_softc *isc = (struct agp_i810_softc *)arg; 524 525 /* 526 * Anything kept in agp over a suspend/resume cycle (and thus by X 527 * over a vt switch cycle) is undefined upon resume. 528 */ 529 switch (act) { 530 case DVACT_RESUME: 531 agp_i810_configure(isc); 532 break; 533 } 534 535 return (0); 536 } 537 538 void 539 agp_i810_configure(struct agp_i810_softc *isc) 540 { 541 bus_addr_t tmp; 542 543 tmp = isc->isc_apaddr; 544 if (isc->chiptype == CHIP_I810) { 545 tmp += isc->dcache_size; 546 } else { 547 tmp += isc->stolen << AGP_PAGE_SHIFT; 548 } 549 550 agp_flush_cache(); 551 /* Install the GATT. */ 552 WRITE4(AGP_I810_PGTBL_CTL, isc->gatt->ag_physical | 1); 553 554 /* initialise all gtt entries to point to scribble page */ 555 for (; tmp < (isc->isc_apaddr + isc->isc_apsize); 556 tmp += AGP_PAGE_SIZE) 557 agp_i810_unbind_page(isc, tmp); 558 /* XXX we'll need to restore the GTT contents when we go kms */ 559 560 /* 561 * Make sure the chipset can see everything. 562 */ 563 agp_flush_cache(); 564 } 565 566 void 567 agp_i810_bind_page(void *sc, bus_addr_t offset, paddr_t physical, int flags) 568 { 569 struct agp_i810_softc *isc = sc; 570 571 /* 572 * COHERENT mappings mean set the snoop bit. this should never be 573 * accessed by the gpu through the gtt. 574 */ 575 if (flags & BUS_DMA_COHERENT) 576 physical |= INTEL_COHERENT; 577 578 intagp_write_gtt(isc, offset - isc->isc_apaddr, physical); 579 } 580 581 void 582 agp_i810_unbind_page(void *sc, bus_size_t offset) 583 { 584 struct agp_i810_softc *isc = sc; 585 586 intagp_write_gtt(isc, offset - isc->isc_apaddr, 587 isc->scrib_dmamap->dm_segs[0].ds_addr); 588 } 589 590 /* 591 * Writing via memory mapped registers already flushes all TLBs. 592 */ 593 void 594 agp_i810_flush_tlb(void *sc) 595 { 596 } 597 598 int 599 agp_i810_enable(void *sc, u_int32_t mode) 600 { 601 return (0); 602 } 603 604 struct agp_memory * 605 agp_i810_alloc_memory(void *softc, int type, vsize_t size) 606 { 607 struct agp_i810_softc *isc = softc; 608 struct agp_softc *sc = isc->agpdev; 609 struct agp_memory *mem; 610 int error; 611 612 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 613 return (NULL); 614 615 if (sc->sc_allocated + size > sc->sc_maxmem) 616 return (NULL); 617 618 if (type == 1) { 619 /* 620 * Mapping local DRAM into GATT. 621 */ 622 if (isc->chiptype != CHIP_I810 || size != isc->dcache_size) 623 return (NULL); 624 } else if (type == 2) { 625 /* 626 * Bogus mapping of 1 or 4 pages for the hardware cursor. 627 */ 628 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) { 629 #ifdef DEBUG 630 printf("agp: trying to map %lu for hw cursor\n", size); 631 #endif 632 return (NULL); 633 } 634 } 635 636 mem = malloc(sizeof *mem, M_AGP, M_WAITOK | M_ZERO); 637 mem->am_id = sc->sc_nextid++; 638 mem->am_size = size; 639 mem->am_type = type; 640 641 if (type == 2) { 642 /* 643 * Allocate and wire down the pages now so that we can 644 * get their physical address. 645 */ 646 if ((mem->am_dmaseg = malloc(sizeof (*mem->am_dmaseg), M_AGP, 647 M_WAITOK | M_CANFAIL)) == NULL) { 648 free(mem, M_AGP, 0); 649 return (NULL); 650 } 651 652 if ((error = agp_alloc_dmamem(sc->sc_dmat, size, 653 &mem->am_dmamap, &mem->am_physical, mem->am_dmaseg)) != 0) { 654 free(mem->am_dmaseg, M_AGP, 0); 655 free(mem, M_AGP, 0); 656 printf("agp: agp_alloc_dmamem(%d)\n", error); 657 return (NULL); 658 } 659 } else if (type != 1) { 660 if ((error = bus_dmamap_create(sc->sc_dmat, size, 661 size / PAGE_SIZE + 1, size, 0, BUS_DMA_NOWAIT, 662 &mem->am_dmamap)) != 0) { 663 free(mem, M_AGP, 0); 664 printf("agp: bus_dmamap_create(%d)\n", error); 665 return (NULL); 666 } 667 } 668 669 TAILQ_INSERT_TAIL(&sc->sc_memory, mem, am_link); 670 sc->sc_allocated += size; 671 672 return (mem); 673 } 674 675 int 676 agp_i810_free_memory(void *softc, struct agp_memory *mem) 677 { 678 struct agp_i810_softc *isc = softc; 679 struct agp_softc *sc = isc->agpdev; 680 681 if (mem->am_is_bound) 682 return (EBUSY); 683 684 if (mem->am_type == 2) { 685 agp_free_dmamem(sc->sc_dmat, mem->am_size, mem->am_dmamap, 686 mem->am_dmaseg); 687 free(mem->am_dmaseg, M_AGP, 0); 688 } else if (mem->am_type != 1) { 689 bus_dmamap_destroy(sc->sc_dmat, mem->am_dmamap); 690 } 691 692 sc->sc_allocated -= mem->am_size; 693 TAILQ_REMOVE(&sc->sc_memory, mem, am_link); 694 free(mem, M_AGP, 0); 695 return (0); 696 } 697 698 int 699 agp_i810_bind_memory(void *sc, struct agp_memory *mem, bus_size_t offset) 700 { 701 struct agp_i810_softc *isc = sc; 702 u_int32_t regval, i; 703 704 if (mem->am_is_bound != 0) 705 return (EINVAL); 706 707 if (isc->chiptype != CHIP_I810 && (offset >> AGP_PAGE_SHIFT) < 708 isc->stolen) { 709 #ifdef DEBUG 710 printf("agp: trying to bind into stolen memory\n"); 711 #endif 712 return (EINVAL); 713 } 714 715 /* 716 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 717 * X server for mysterious reasons which leads to crashes if we write 718 * to the GTT through the MMIO window. 719 * Until the issue is solved, simply restore it. 720 */ 721 regval = READ4(AGP_I810_PGTBL_CTL); 722 if (regval != (isc->gatt->ag_physical | 1)) { 723 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 724 regval); 725 WRITE4(AGP_I810_PGTBL_CTL, isc->gatt->ag_physical | 726 INTEL_ENABLED); 727 } 728 729 if (mem->am_type == 2) { 730 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 731 agp_i810_bind_page(isc, isc->isc_apaddr + offset + i, 732 mem->am_physical + i, 0); 733 mem->am_offset = offset; 734 mem->am_is_bound = 1; 735 return (0); 736 } 737 738 if (mem->am_type != 1) 739 return (agp_generic_bind_memory(isc->agpdev, mem, offset)); 740 741 if (isc->chiptype != CHIP_I810) 742 return (EINVAL); 743 744 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 745 intagp_write_gtt(isc, i, i | INTEL_ENABLED | INTEL_LOCAL); 746 mem->am_is_bound = 1; 747 return (0); 748 } 749 750 int 751 agp_i810_unbind_memory(void *sc, struct agp_memory *mem) 752 { 753 struct agp_i810_softc *isc = sc; 754 u_int32_t i; 755 756 if (mem->am_is_bound == 0) 757 return (EINVAL); 758 759 if (mem->am_type == 2) { 760 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 761 agp_i810_unbind_page(isc, isc->isc_apaddr + 762 mem->am_offset + i); 763 mem->am_offset = 0; 764 mem->am_is_bound = 0; 765 return (0); 766 } 767 768 if (mem->am_type != 1) 769 return (agp_generic_unbind_memory(isc->agpdev, mem)); 770 771 if (isc->chiptype != CHIP_I810) 772 return (EINVAL); 773 774 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 775 intagp_write_gtt(isc, i, 0); 776 mem->am_is_bound = 0; 777 return (0); 778 } 779 780 void 781 intagp_write_gtt(struct agp_i810_softc *isc, bus_size_t off, paddr_t v) 782 { 783 u_int32_t pte = 0; 784 bus_size_t baseoff, wroff; 785 786 if (isc->chiptype != CHIP_I810 && 787 (off >> AGP_PAGE_SHIFT) < isc->stolen) { 788 printf("intagp: binding into stolen memory! (0x%lx)\n", 789 (off >> AGP_PAGE_SHIFT)); 790 } 791 792 if (v != 0) { 793 pte = v | INTEL_ENABLED; 794 /* 965+ can do 36-bit addressing, add in the extra bits */ 795 switch (isc->chiptype) { 796 case CHIP_I965: 797 case CHIP_G4X: 798 case CHIP_PINEVIEW: 799 case CHIP_G33: 800 case CHIP_IRONLAKE: 801 pte |= (v & 0x0000000f00000000ULL) >> 28; 802 break; 803 } 804 } 805 806 wroff = (off >> AGP_PAGE_SHIFT) * 4; 807 808 switch(isc->chiptype) { 809 case CHIP_I915: 810 /* FALLTHROUGH */ 811 case CHIP_G33: 812 case CHIP_PINEVIEW: 813 bus_space_write_4(isc->gtt_map->bst, isc->gtt_map->bsh, 814 wroff, pte); 815 return; 816 case CHIP_I965: 817 baseoff = AGP_I965_GTT; 818 break; 819 case CHIP_G4X: 820 case CHIP_IRONLAKE: 821 baseoff = AGP_G4X_GTT; 822 break; 823 default: 824 baseoff = AGP_I810_GTT; 825 break; 826 } 827 bus_space_write_4(isc->map->bst, isc->map->bsh, baseoff + wroff, pte); 828 } 829