1 /* $OpenBSD: agp_i810.c,v 1.46 2009/02/17 18:41:32 oga Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Doug Rabson 5 * Copyright (c) 2000 Ruslan Ermilov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/proc.h> 37 #include <sys/device.h> 38 #include <sys/conf.h> 39 #include <sys/agpio.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/agpvar.h> 45 #include <dev/pci/agpreg.h> 46 #include <dev/pci/vga_pcivar.h> 47 48 #include <machine/bus.h> 49 50 #define READ1(off) bus_space_read_1(isc->map->bst, isc->map->bsh, off) 51 #define READ4(off) bus_space_read_4(isc->map->bst, isc->map->bsh, off) 52 #define WRITE4(off,v) bus_space_write_4(isc->map->bst, isc->map->bsh, off, v) 53 54 #define WRITEGTT(off,v) bus_space_write_4(isc->gtt_map->bst, isc->gtt_map->bsh, off, v) 55 #define WRITE_GATT(off,v) agp_i810_write_gatt(isc, off, v) 56 57 enum { 58 CHIP_NONE = 0, /* not integrated graphics */ 59 CHIP_I810 = 1, /* i810/i815 */ 60 CHIP_I830 = 2, /* i830/i845 */ 61 CHIP_I855 = 3, /* i852GM/i855GM/i865G */ 62 CHIP_I915 = 4, /* i915G/i915GM */ 63 CHIP_I965 = 5, /* i965/i965GM */ 64 CHIP_G33 = 6, /* G33/Q33/Q35 */ 65 CHIP_G4X = 7 /* G4X */ 66 }; 67 68 struct agp_i810_softc { 69 struct device dev; 70 struct agp_softc *agpdev; 71 struct agp_gatt *gatt; 72 struct vga_pci_bar *map; 73 struct vga_pci_bar *gtt_map; 74 int chiptype; /* i810-like or i830 */ 75 bus_size_t aperture; /* current aperture size */ 76 u_int32_t dcache_size; /* i810 only */ 77 u_int32_t stolen; /* number of i830/845 gtt 78 entries for stolen memory */ 79 }; 80 81 void agp_i810_attach(struct device *, struct device *, void *); 82 int agp_i810_probe(struct device *, void *, void *); 83 int agp_i810_get_chiptype(struct pci_attach_args *); 84 bus_size_t agp_i810_get_aperture(void *); 85 int agp_i810_bind_page(void *, off_t, bus_addr_t); 86 int agp_i810_unbind_page(void *, off_t); 87 void agp_i810_flush_tlb(void *); 88 int agp_i810_enable(void *, u_int32_t mode); 89 struct agp_memory * agp_i810_alloc_memory(void *, int, vsize_t); 90 int agp_i810_free_memory(void *, struct agp_memory *); 91 int agp_i810_bind_memory(void *, struct agp_memory *, off_t); 92 int agp_i810_unbind_memory(void *, struct agp_memory *); 93 void agp_i810_write_gatt(struct agp_i810_softc *, bus_size_t, u_int32_t); 94 int intagp_gmch_match(struct pci_attach_args *); 95 96 struct cfattach intagp_ca = { 97 sizeof(struct agp_i810_softc), agp_i810_probe, agp_i810_attach 98 }; 99 100 struct cfdriver intagp_cd = { 101 NULL, "intagp", DV_DULL 102 }; 103 104 struct agp_methods agp_i810_methods = { 105 agp_i810_get_aperture, 106 agp_i810_bind_page, 107 agp_i810_unbind_page, 108 agp_i810_flush_tlb, 109 agp_i810_enable, 110 agp_i810_alloc_memory, 111 agp_i810_free_memory, 112 agp_i810_bind_memory, 113 agp_i810_unbind_memory, 114 }; 115 116 int 117 agp_i810_get_chiptype(struct pci_attach_args *pa) 118 { 119 switch (PCI_PRODUCT(pa->pa_id)) { 120 case PCI_PRODUCT_INTEL_82810_IGD: 121 case PCI_PRODUCT_INTEL_82810_DC100_IGD: 122 case PCI_PRODUCT_INTEL_82810E_IGD: 123 case PCI_PRODUCT_INTEL_82815_IGD: 124 return (CHIP_I810); 125 break; 126 case PCI_PRODUCT_INTEL_82830M_IGD: 127 case PCI_PRODUCT_INTEL_82845G_IGD: 128 return (CHIP_I830); 129 break; 130 case PCI_PRODUCT_INTEL_82855GM_IGD: 131 case PCI_PRODUCT_INTEL_82865G_IGD: 132 return (CHIP_I855); 133 break; 134 case PCI_PRODUCT_INTEL_82915G_IGD_1: 135 case PCI_PRODUCT_INTEL_82915G_IGD_2: 136 case PCI_PRODUCT_INTEL_82915GM_IGD_1: 137 case PCI_PRODUCT_INTEL_82915GM_IGD_2: 138 case PCI_PRODUCT_INTEL_82945G_IGD_1: 139 case PCI_PRODUCT_INTEL_82945G_IGD_2: 140 case PCI_PRODUCT_INTEL_82945GM_IGD_1: 141 case PCI_PRODUCT_INTEL_82945GM_IGD_2: 142 case PCI_PRODUCT_INTEL_82945GME_IGD_1: 143 return (CHIP_I915); 144 break; 145 case PCI_PRODUCT_INTEL_82946GZ_IGD_1: 146 case PCI_PRODUCT_INTEL_82946GZ_IGD_2: 147 case PCI_PRODUCT_INTEL_82Q965_IGD_1: 148 case PCI_PRODUCT_INTEL_82Q965_IGD_2: 149 case PCI_PRODUCT_INTEL_82G965_IGD_1: 150 case PCI_PRODUCT_INTEL_82G965_IGD_2: 151 case PCI_PRODUCT_INTEL_82GM965_IGD_1: 152 case PCI_PRODUCT_INTEL_82GM965_IGD_2: 153 case PCI_PRODUCT_INTEL_82GME965_IGD_1: 154 case PCI_PRODUCT_INTEL_82GME965_IGD_2: 155 case PCI_PRODUCT_INTEL_82G35_IGD_1: 156 case PCI_PRODUCT_INTEL_82G35_IGD_2: 157 return (CHIP_I965); 158 break; 159 case PCI_PRODUCT_INTEL_82G33_IGD_1: 160 case PCI_PRODUCT_INTEL_82G33_IGD_2: 161 case PCI_PRODUCT_INTEL_82Q35_IGD_1: 162 case PCI_PRODUCT_INTEL_82Q35_IGD_2: 163 return (CHIP_G33); 164 break; 165 case PCI_PRODUCT_INTEL_82GM45_IGD_1: 166 case PCI_PRODUCT_INTEL_82Q45_IGD_1: 167 case PCI_PRODUCT_INTEL_82G45_IGD_1: 168 return (CHIP_G4X); 169 break; 170 } 171 return (CHIP_NONE); 172 } 173 174 /* 175 * We're intel IGD, bus 0 function 0 dev 0 should be the GMCH, so it should 176 * be Intel 177 */ 178 int 179 intagp_gmch_match(struct pci_attach_args *pa) 180 { 181 if (pa->pa_bus == 0 && pa->pa_device == 0 && pa->pa_function == 0 && 182 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 183 PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 184 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) 185 return (1); 186 return (0); 187 } 188 189 int 190 agp_i810_probe(struct device *parent, void *match, void *aux) 191 { 192 struct pci_attach_args *pa = aux; 193 194 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY || 195 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) 196 return (0); 197 198 return (agp_i810_get_chiptype(pa) != CHIP_NONE); 199 } 200 201 void 202 agp_i810_attach(struct device *parent, struct device *self, void *aux) 203 { 204 struct agp_i810_softc *isc = (struct agp_i810_softc *)self; 205 struct agp_gatt *gatt; 206 struct pci_attach_args *pa = aux, bpa; 207 struct vga_pci_softc *vga = (struct vga_pci_softc *)parent; 208 bus_addr_t mmaddr, gmaddr; 209 pcireg_t memtype; 210 211 isc->chiptype = agp_i810_get_chiptype(pa); 212 213 switch (isc->chiptype) { 214 case CHIP_I915: 215 case CHIP_G33: 216 gmaddr = AGP_I915_GMADR; 217 mmaddr = AGP_I915_MMADR; 218 memtype = PCI_MAPREG_TYPE_MEM; 219 break; 220 case CHIP_I965: 221 case CHIP_G4X: 222 gmaddr = AGP_I965_GMADR; 223 mmaddr = AGP_I965_MMADR; 224 memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT; 225 break; 226 default: 227 gmaddr = AGP_APBASE; 228 mmaddr = AGP_I810_MMADR; 229 memtype = PCI_MAPREG_TYPE_MEM; 230 break; 231 } 232 233 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, gmaddr, memtype, 234 NULL, &isc->aperture, NULL) != 0) { 235 printf("can't get aperture size\n"); 236 return; 237 } 238 239 isc->map = vga_pci_bar_map(vga, mmaddr, 0, BUS_SPACE_MAP_LINEAR); 240 if (isc->map == NULL) { 241 printf("can't map mmadr registers\n"); 242 return; 243 } 244 245 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { 246 isc->gtt_map = vga_pci_bar_map(vga, AGP_I915_GTTADR, 0, 247 BUS_SPACE_MAP_LINEAR); 248 if (isc->gtt_map == NULL) { 249 printf("can't map gatt registers\n"); 250 goto out; 251 } 252 } 253 254 gatt = malloc(sizeof(*gatt), M_AGP, M_NOWAIT); 255 if (gatt == NULL) { 256 printf("can't alloc gatt\n"); 257 goto out; 258 } 259 isc->gatt = gatt; 260 261 gatt->ag_entries = isc->aperture >> AGP_PAGE_SHIFT; 262 263 /* 264 * Find the GMCH, some of the registers we need to read for 265 * configuration purposes are on there. it's always at 266 * 0/0/0 (bus/dev/func). 267 */ 268 if (pci_find_device(&bpa, intagp_gmch_match) == 0) { 269 printf("can't find GMCH\n"); 270 goto out; 271 } 272 273 if (isc->chiptype == CHIP_I810) { 274 int dummyseg; 275 /* Some i810s have on-chip memory called dcache */ 276 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 277 isc->dcache_size = 4 * 1024 * 1024; 278 else 279 isc->dcache_size = 0; 280 281 /* According to the specs the gatt on the i810 must be 64k */ 282 if (agp_alloc_dmamem(pa->pa_dmat, 64 * 1024, 283 0, &gatt->ag_dmamap, (caddr_t *)&gatt->ag_virtual, 284 &gatt->ag_physical, &gatt->ag_dmaseg, 1, &dummyseg) != 0) { 285 goto out; 286 } 287 288 gatt->ag_size = gatt->ag_entries * sizeof(u_int32_t); 289 memset(gatt->ag_virtual, 0, gatt->ag_size); 290 291 agp_flush_cache(); 292 /* Install the GATT. */ 293 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 294 } else if (isc->chiptype == CHIP_I830) { 295 /* The i830 automatically initializes the 128k gatt on boot. */ 296 pcireg_t reg; 297 u_int32_t pgtblctl; 298 u_int16_t gcc1; 299 300 reg = pci_conf_read(bpa.pa_pc, bpa.pa_tag, AGP_I830_GCC0); 301 gcc1 = (u_int16_t)(reg >> 16); 302 switch (gcc1 & AGP_I830_GCC1_GMS) { 303 case AGP_I830_GCC1_GMS_STOLEN_512: 304 isc->stolen = (512 - 132) * 1024 / 4096; 305 break; 306 case AGP_I830_GCC1_GMS_STOLEN_1024: 307 isc->stolen = (1024 - 132) * 1024 / 4096; 308 break; 309 case AGP_I830_GCC1_GMS_STOLEN_8192: 310 isc->stolen = (8192 - 132) * 1024 / 4096; 311 break; 312 default: 313 isc->stolen = 0; 314 printf("unknown memory configuration, disabling\n"); 315 goto out; 316 } 317 #ifdef DEBUG 318 if (isc->stolen > 0) { 319 printf(": detected %dk stolen memory", 320 isc->stolen * 4); 321 } else 322 printf(": no preallocated video memory\n"); 323 #endif 324 325 /* GATT address is already in there, make sure it's enabled */ 326 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 327 pgtblctl |= 1; 328 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 329 330 gatt->ag_physical = pgtblctl & ~1; 331 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 || 332 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 || 333 isc->chiptype == CHIP_G4X) { 334 pcireg_t reg; 335 u_int32_t pgtblctl, stolen; 336 u_int16_t gcc1; 337 338 /* Stolen memory is set up at the beginning of the aperture by 339 * the BIOS, consisting of the GATT followed by 4kb for the 340 * BIOS display. 341 */ 342 343 reg = pci_conf_read(bpa.pa_pc, bpa.pa_tag, AGP_I855_GCC1); 344 gcc1 = (u_int16_t)(reg >> 16); 345 switch (isc->chiptype) { 346 case CHIP_I855: 347 /* The 855GM automatically initializes the 128k gatt on boot. */ 348 stolen = 128 + 4; 349 break; 350 case CHIP_I915: 351 /* The 915G automatically initializes the 256k gatt on boot. */ 352 stolen = 256 + 4; 353 break; 354 case CHIP_I965: 355 switch (READ4(AGP_I810_PGTBL_CTL) & 356 AGP_I810_PGTBL_SIZE_MASK) { 357 case AGP_I810_PGTBL_SIZE_512KB: 358 stolen = 512 + 4; 359 break; 360 case AGP_I810_PGTBL_SIZE_256KB: 361 stolen = 256 + 4; 362 break; 363 case AGP_I810_PGTBL_SIZE_128KB: 364 default: 365 stolen = 128 + 4; 366 break; 367 } 368 break; 369 case CHIP_G33: 370 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) { 371 case AGP_G33_PGTBL_SIZE_2M: 372 stolen = 2048 + 4; 373 break; 374 case AGP_G33_PGTBL_SIZE_1M: 375 default: 376 stolen = 1024 + 4; 377 break; 378 } 379 break; 380 case CHIP_G4X: 381 /* 382 * GTT stolen is separate from graphics stolen on 383 * 4 series hardware. so ignore it in stolen gtt entries 384 * counting. However, 4Kb of stolen memory isn't mapped 385 * to the GTT. 386 */ 387 stolen = 4; 388 break; 389 default: 390 printf("bad chiptype\n"); 391 goto out; 392 } 393 394 switch (gcc1 & AGP_I855_GCC1_GMS) { 395 case AGP_I855_GCC1_GMS_STOLEN_1M: 396 isc->stolen = (1024 - stolen) * 1024 / 4096; 397 break; 398 case AGP_I855_GCC1_GMS_STOLEN_4M: 399 isc->stolen = (4096 - stolen) * 1024 / 4096; 400 break; 401 case AGP_I855_GCC1_GMS_STOLEN_8M: 402 isc->stolen = (8192 - stolen) * 1024 / 4096; 403 break; 404 case AGP_I855_GCC1_GMS_STOLEN_16M: 405 isc->stolen = (16384 - stolen) * 1024 / 4096; 406 break; 407 case AGP_I855_GCC1_GMS_STOLEN_32M: 408 isc->stolen = (32768 - stolen) * 1024 / 4096; 409 break; 410 case AGP_I915_GCC1_GMS_STOLEN_48M: 411 isc->stolen = (49152 - stolen) * 1024 / 4096; 412 break; 413 case AGP_I915_GCC1_GMS_STOLEN_64M: 414 isc->stolen = (65536 - stolen) * 1024 / 4096; 415 break; 416 case AGP_G33_GCC1_GMS_STOLEN_128M: 417 isc->stolen = (131072 - stolen) * 1024 / 4096; 418 break; 419 case AGP_G33_GCC1_GMS_STOLEN_256M: 420 isc->stolen = (262144 - stolen) * 1024 / 4096; 421 break; 422 case AGP_INTEL_GMCH_GMS_STOLEN_96M: 423 isc->stolen = (98304 - stolen) * 1024 / 4096; 424 break; 425 case AGP_INTEL_GMCH_GMS_STOLEN_160M: 426 isc->stolen = (163840 - stolen) * 1024 / 4096; 427 break; 428 case AGP_INTEL_GMCH_GMS_STOLEN_224M: 429 isc->stolen = (229376 - stolen) * 1024 / 4096; 430 break; 431 case AGP_INTEL_GMCH_GMS_STOLEN_352M: 432 isc->stolen = (360448 - stolen) * 1024 / 4096; 433 break; 434 default: 435 isc->stolen = 0; 436 printf("unknown memory configuration, disabling\n"); 437 goto out; 438 } 439 #ifdef DEBUG 440 if (isc->stolen > 0) { 441 printf(": detected %dk stolen memory", 442 isc->stolen * 4); 443 } else 444 printf(": no preallocated video memory\n"); 445 #endif 446 447 /* GATT address is already in there, make sure it's enabled */ 448 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 449 pgtblctl |= 1; 450 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 451 452 gatt->ag_physical = pgtblctl & ~1; 453 } 454 455 /* 456 * Make sure the chipset can see everything. 457 */ 458 agp_flush_cache(); 459 460 isc->agpdev = (struct agp_softc *)agp_attach_bus(pa, &agp_i810_methods, 461 gmaddr, memtype, &isc->dev); 462 return; 463 out: 464 if (isc->gatt) 465 free(isc->gatt, M_AGP); 466 if (isc->gtt_map != NULL) 467 vga_pci_bar_unmap(isc->gtt_map); 468 if (isc->map != NULL) 469 vga_pci_bar_unmap(isc->map); 470 } 471 472 #if 0 473 int 474 agp_i810_detach(struct agp_softc *sc) 475 { 476 int error; 477 struct agp_i810_softc *isc = sc->sc_chipc; 478 479 error = agp_generic_detach(sc); 480 if (error) 481 return (error); 482 483 /* Clear the GATT base. */ 484 if (sc->chiptype == CHIP_I810) { 485 WRITE4(AGP_I810_PGTBL_CTL, 0); 486 } else { 487 unsigned int pgtblctl; 488 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 489 pgtblctl &= ~1; 490 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 491 } 492 493 if (sc->chiptype == CHIP_I810) { 494 agp_free_dmamem(sc->sc_dmat, gatt->ag_size, gatt->ag_dmamap, 495 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1); 496 } 497 free(sc->gatt, M_AGP); 498 499 return (0); 500 } 501 #endif 502 503 bus_size_t 504 agp_i810_get_aperture(void *sc) 505 { 506 struct agp_i810_softc *isc = sc; 507 508 return (isc->aperture); 509 } 510 511 int 512 agp_i810_bind_page(void *sc, off_t offset, bus_addr_t physical) 513 { 514 struct agp_i810_softc *isc = sc; 515 516 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 517 #ifdef DEBUG 518 printf("agp: failed: offset 0x%08x, shift %d, entries %d\n", 519 (int)offset, AGP_PAGE_SHIFT, isc->gatt->ag_entries); 520 #endif 521 return (EINVAL); 522 } 523 524 if (isc->chiptype != CHIP_I810) { 525 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 526 #ifdef DEBUG 527 printf("agp: trying to bind into stolen memory\n"); 528 #endif 529 return (EINVAL); 530 } 531 } 532 533 WRITE_GATT(offset, physical); 534 return (0); 535 } 536 537 int 538 agp_i810_unbind_page(void *sc, off_t offset) 539 { 540 struct agp_i810_softc *isc = sc; 541 542 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT)) 543 return (EINVAL); 544 545 if (isc->chiptype != CHIP_I810 ) { 546 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) { 547 #ifdef DEBUG 548 printf("agp: trying to unbind from stolen memory\n"); 549 #endif 550 return (EINVAL); 551 } 552 } 553 554 WRITE_GATT(offset, 0); 555 return (0); 556 } 557 558 /* 559 * Writing via memory mapped registers already flushes all TLBs. 560 */ 561 void 562 agp_i810_flush_tlb(void *sc) 563 { 564 } 565 566 int 567 agp_i810_enable(void *sc, u_int32_t mode) 568 { 569 return (0); 570 } 571 572 struct agp_memory * 573 agp_i810_alloc_memory(void *softc, int type, vsize_t size) 574 { 575 struct agp_i810_softc *isc = softc; 576 struct agp_softc *sc = isc->agpdev; 577 struct agp_memory *mem; 578 int error; 579 580 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 581 return (NULL); 582 583 if (sc->sc_allocated + size > sc->sc_maxmem) 584 return (NULL); 585 586 if (type == 1) { 587 /* 588 * Mapping local DRAM into GATT. 589 */ 590 if (isc->chiptype != CHIP_I810 ) 591 return (NULL); 592 if (size != isc->dcache_size) 593 return (NULL); 594 } else if (type == 2) { 595 /* 596 * Bogus mapping of 1 or 4 pages for the hardware cursor. 597 */ 598 if (size != AGP_PAGE_SIZE && size != 4 * AGP_PAGE_SIZE) { 599 #ifdef DEBUG 600 printf("agp: trying to map %lu for hw cursor\n", size); 601 #endif 602 return (NULL); 603 } 604 } 605 606 mem = malloc(sizeof *mem, M_AGP, M_WAITOK | M_ZERO); 607 mem->am_id = sc->sc_nextid++; 608 mem->am_size = size; 609 mem->am_type = type; 610 611 if (type == 2) { 612 /* 613 * Allocate and wire down the pages now so that we can 614 * get their physical address. 615 */ 616 mem->am_dmaseg = malloc(sizeof *mem->am_dmaseg, M_AGP, 617 M_WAITOK); 618 if ((error = agp_alloc_dmamem(sc->sc_dmat, size, 0, 619 &mem->am_dmamap, &mem->am_virtual, &mem->am_physical, 620 mem->am_dmaseg, 1, &mem->am_nseg)) != 0) { 621 free(mem->am_dmaseg, M_AGP); 622 free(mem, M_AGP); 623 printf("agp: agp_alloc_dmamem(%d)\n", error); 624 return (NULL); 625 } 626 memset(mem->am_virtual, 0, size); 627 } else if (type != 1) { 628 if ((error = bus_dmamap_create(sc->sc_dmat, size, 629 size / PAGE_SIZE + 1, size, 0, BUS_DMA_NOWAIT, 630 &mem->am_dmamap)) != 0) { 631 free(mem, M_AGP); 632 printf("agp: bus_dmamap_create(%d)\n", error); 633 return (NULL); 634 } 635 } 636 637 TAILQ_INSERT_TAIL(&sc->sc_memory, mem, am_link); 638 sc->sc_allocated += size; 639 640 return (mem); 641 } 642 643 int 644 agp_i810_free_memory(void *softc, struct agp_memory *mem) 645 { 646 struct agp_i810_softc *isc = softc; 647 struct agp_softc *sc = isc->agpdev; 648 649 if (mem->am_is_bound) 650 return (EBUSY); 651 652 if (mem->am_type == 2) { 653 agp_free_dmamem(sc->sc_dmat, mem->am_size, mem->am_dmamap, 654 mem->am_virtual, mem->am_dmaseg, mem->am_nseg); 655 free(mem->am_dmaseg, M_AGP); 656 } else if (mem->am_type != 1) { 657 bus_dmamap_destroy(sc->sc_dmat, mem->am_dmamap); 658 } 659 660 sc->sc_allocated -= mem->am_size; 661 TAILQ_REMOVE(&sc->sc_memory, mem, am_link); 662 free(mem, M_AGP); 663 return (0); 664 } 665 666 int 667 agp_i810_bind_memory(void *sc, struct agp_memory *mem, off_t offset) 668 { 669 struct agp_i810_softc *isc = sc; 670 u_int32_t regval, i; 671 672 /* 673 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the 674 * X server for mysterious reasons which leads to crashes if we write 675 * to the GTT through the MMIO window. 676 * Until the issue is solved, simply restore it. 677 */ 678 regval = READ4(AGP_I810_PGTBL_CTL); 679 if (regval != (isc->gatt->ag_physical | 1)) { 680 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%x - fixing\n", 681 regval); 682 WRITE4(AGP_I810_PGTBL_CTL, isc->gatt->ag_physical | 1); 683 } 684 685 if (mem->am_type == 2) { 686 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 687 WRITE_GATT(offset + i, (mem->am_physical + i)); 688 } 689 mem->am_offset = offset; 690 mem->am_is_bound = 1; 691 return (0); 692 } 693 694 if (mem->am_type != 1) 695 return (agp_generic_bind_memory(isc->agpdev, mem, offset)); 696 697 if (isc->chiptype != CHIP_I810) 698 return (EINVAL); 699 700 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 701 WRITE4(AGP_I810_GTT + 702 (u_int32_t)(offset >> AGP_PAGE_SHIFT) * 4, i | 3); 703 mem->am_is_bound = 1; 704 return (0); 705 } 706 707 int 708 agp_i810_unbind_memory(void *sc, struct agp_memory *mem) 709 { 710 struct agp_i810_softc *isc = sc; 711 u_int32_t i; 712 713 if (mem->am_type == 2) { 714 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 715 WRITE_GATT(mem->am_offset + i, 0); 716 } 717 mem->am_offset = 0; 718 mem->am_is_bound = 0; 719 return (0); 720 } 721 722 if (mem->am_type != 1) 723 return (agp_generic_unbind_memory(isc->agpdev, mem)); 724 725 if (isc->chiptype != CHIP_I810) 726 return (EINVAL); 727 728 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 729 WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0); 730 mem->am_is_bound = 0; 731 return (0); 732 } 733 734 void 735 agp_i810_write_gatt(struct agp_i810_softc *isc, bus_size_t off, u_int32_t v) 736 { 737 u_int32_t d; 738 739 d = v | 1; 740 741 if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) 742 WRITEGTT((u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, v ? d : 0); 743 else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) { 744 d |= (v & 0x0000000f00000000ULL) >> 28; 745 WRITE4((isc->chiptype == CHIP_I965 ? AGP_I965_GTT : AGP_G4X_GTT) 746 + (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, 747 v ? d : 0); 748 } else 749 WRITE4(AGP_I810_GTT + (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4, 750 v ? d : 0); 751 } 752