1 /* $OpenBSD: ofw_misc.h,v 1.20 2021/04/07 17:12:22 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2017 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _DEV_OFW_MISC_H_ 19 #define _DEV_OFW_MISC_H_ 20 21 /* Register maps */ 22 23 void regmap_register(int, bus_space_tag_t, bus_space_handle_t, bus_size_t); 24 25 struct regmap; 26 struct regmap *regmap_bycompatible(char *); 27 struct regmap *regmap_bynode(int); 28 struct regmap *regmap_byphandle(uint32_t); 29 30 uint32_t regmap_read_4(struct regmap *, bus_size_t); 31 void regmap_write_4(struct regmap *, bus_size_t, uint32_t); 32 33 /* PHY support */ 34 35 #define PHY_NONE 0 36 #define PHY_TYPE_SATA 1 37 #define PHY_TYPE_PCIE 2 38 #define PHY_TYPE_USB2 3 39 #define PHY_TYPE_USB3 4 40 #define PHY_TYPE_UFS 5 41 42 struct phy_device { 43 int pd_node; 44 void *pd_cookie; 45 int (*pd_enable)(void *, uint32_t *); 46 47 LIST_ENTRY(phy_device) pd_list; 48 uint32_t pd_phandle; 49 uint32_t pd_cells; 50 }; 51 52 void phy_register(struct phy_device *); 53 54 int phy_enable_idx(int, int); 55 int phy_enable(int, const char *); 56 57 /* I2C support */ 58 59 struct i2c_controller; 60 struct i2c_bus { 61 int ib_node; 62 struct i2c_controller *ib_ic; 63 64 LIST_ENTRY(i2c_bus) ib_list; 65 uint32_t ib_phandle; 66 }; 67 68 void i2c_register(struct i2c_bus *); 69 70 struct i2c_controller *i2c_bynode(int); 71 struct i2c_controller *i2c_byphandle(uint32_t); 72 73 /* SFP support */ 74 75 struct if_sffpage; 76 struct sfp_device { 77 int sd_node; 78 void *sd_cookie; 79 int (*sd_enable)(void *, int); 80 int (*sd_get_sffpage)(void *, struct if_sffpage *); 81 82 LIST_ENTRY(sfp_device) sd_list; 83 uint32_t sd_phandle; 84 }; 85 86 void sfp_register(struct sfp_device *); 87 88 struct mii_data; 89 int sfp_enable(uint32_t); 90 int sfp_disable(uint32_t); 91 int sfp_add_media(uint32_t, struct mii_data *); 92 int sfp_get_sffpage(uint32_t, struct if_sffpage *); 93 94 /* PWM support */ 95 96 #define PWM_POLARITY_INVERTED 0x00000001 97 98 struct pwm_state { 99 uint32_t ps_period; 100 uint32_t ps_pulse_width; 101 uint32_t ps_flags; 102 int ps_enabled; 103 }; 104 105 struct pwm_device { 106 int pd_node; 107 void *pd_cookie; 108 int (*pd_get_state)(void *, uint32_t *, struct pwm_state *); 109 int (*pd_set_state)(void *, uint32_t *, struct pwm_state *); 110 111 LIST_ENTRY(pwm_device) pd_list; 112 uint32_t pd_phandle; 113 uint32_t pd_cells; 114 }; 115 116 void pwm_register(struct pwm_device *); 117 118 int pwm_init_state(uint32_t *cells, struct pwm_state *ps); 119 int pwm_get_state(uint32_t *cells, struct pwm_state *ps); 120 int pwm_set_state(uint32_t *cells, struct pwm_state *ps); 121 122 /* Non-volatile memory support */ 123 124 struct nvmem_device { 125 int nd_node; 126 void *nd_cookie; 127 int (*nd_read)(void *, bus_addr_t, void *, bus_size_t); 128 129 LIST_ENTRY(nvmem_device) nd_list; 130 uint32_t nd_phandle; 131 }; 132 133 void nvmem_register(struct nvmem_device *); 134 int nvmem_read(uint32_t, bus_addr_t, void *, bus_size_t); 135 int nvmem_read_cell(int, const char *name, void *, bus_size_t); 136 137 /* Port/endpoint interface support */ 138 139 struct endpoint; 140 141 struct device_ports { 142 int dp_node; 143 void *dp_cookie; 144 145 int (*dp_ep_activate)(void *, struct endpoint *, void *); 146 void *(*dp_ep_get_cookie)(void *, struct endpoint *); 147 148 LIST_HEAD(, device_port) dp_ports; 149 }; 150 151 struct device_port { 152 int dp_node; 153 uint32_t dp_phandle; 154 uint32_t dp_reg; 155 struct device_ports *dp_ports; 156 LIST_ENTRY(device_port) dp_list; 157 LIST_HEAD(, endpoint) dp_endpoints; 158 }; 159 160 enum endpoint_type { 161 EP_DRM_BRIDGE = 1, /* struct drm_bridge */ 162 EP_DRM_CONNECTOR, /* struct drm_connector */ 163 EP_DRM_CRTC, /* struct drm_crtc */ 164 EP_DRM_ENCODER, /* struct drm_encoder */ 165 EP_DRM_PANEL, /* struct drm_panel */ 166 EP_DAI_DEVICE, /* struct dai_device */ 167 }; 168 169 struct endpoint { 170 int ep_node; 171 uint32_t ep_phandle; 172 uint32_t ep_reg; 173 enum endpoint_type ep_type; 174 struct device_port *ep_port; 175 LIST_ENTRY(endpoint) ep_list; 176 LIST_ENTRY(endpoint) ep_plist; 177 }; 178 179 void device_ports_register(struct device_ports *, enum endpoint_type); 180 struct device_ports *device_ports_byphandle(uint32_t); 181 int device_port_activate(uint32_t, void *); 182 struct endpoint *endpoint_byreg(struct device_ports *, uint32_t, uint32_t); 183 struct endpoint *endpoint_remote(struct endpoint *); 184 int endpoint_activate(struct endpoint *, void *); 185 void *endpoint_get_cookie(struct endpoint *); 186 187 /* Digital audio interface support */ 188 189 struct dai_device { 190 int dd_node; 191 void *dd_cookie; 192 void *dd_hw_if; 193 int (*dd_set_format)(void *, uint32_t, uint32_t, uint32_t); 194 int (*dd_set_sysclk)(void *, uint32_t); 195 196 LIST_ENTRY(dai_device) dd_list; 197 uint32_t dd_phandle; 198 199 struct device_ports dd_ports; 200 }; 201 202 void dai_register(struct dai_device *); 203 struct dai_device *dai_byphandle(uint32_t); 204 205 #define DAI_FORMAT_I2S 0 206 #define DAI_FORMAT_RJ 1 207 #define DAI_FORMAT_LJ 2 208 #define DAI_FORMAT_DSPA 3 209 #define DAI_FORMAT_DSPB 4 210 #define DAI_FORMAT_AC97 5 211 #define DAI_FORMAT_PDM 6 212 #define DAI_FORMAT_MSB 7 213 #define DAI_FORMAT_LSB 8 214 215 #define DAI_POLARITY_NB (0 << 0) 216 #define DAI_POLARITY_IB (1 << 0) 217 #define DAI_POLARITY_NF (0 << 1) 218 #define DAI_POLARITY_IF (1 << 1) 219 220 #define DAI_CLOCK_CBS (0 << 0) 221 #define DAI_CLOCK_CBM (1 << 0) 222 #define DAI_CLOCK_CFS (0 << 1) 223 #define DAI_CLOCK_CFM (1 << 1) 224 225 /* MII support */ 226 227 struct mii_bus { 228 int md_node; 229 void *md_cookie; 230 int (*md_readreg)(struct device *, int, int); 231 void (*md_writereg)(struct device *, int, int, int); 232 233 LIST_ENTRY(mii_bus) md_list; 234 }; 235 236 void mii_register(struct mii_bus *); 237 struct mii_bus *mii_bynode(int); 238 struct mii_bus *mii_byphandle(uint32_t); 239 240 /* IOMMU support */ 241 242 struct iommu_device { 243 int id_node; 244 void *id_cookie; 245 bus_dma_tag_t (*id_map)(void *, uint32_t *, bus_dma_tag_t); 246 247 LIST_ENTRY(iommu_device) id_list; 248 uint32_t id_phandle; 249 }; 250 251 void iommu_device_register(struct iommu_device *); 252 bus_dma_tag_t iommu_device_map(int, bus_dma_tag_t); 253 bus_dma_tag_t iommu_device_map_pci(int, uint32_t, bus_dma_tag_t); 254 255 #endif /* _DEV_OFW_MISC_H_ */ 256