1 /* $OpenBSD: rgephy.c,v 1.38 2015/07/19 06:35:18 yuo Exp $ */ 2 /* 3 * Copyright (c) 2003 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: rgephy.c,v 1.5 2004/05/30 17:57:40 phk Exp $ 34 */ 35 36 /* 37 * Driver for the Realtek 8169S/8110S internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/socket.h> 45 #include <sys/errno.h> 46 47 #include <machine/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include <dev/mii/miidevs.h> 58 59 #include <dev/mii/rgephyreg.h> 60 61 #include <dev/ic/rtl81x9reg.h> 62 63 int rgephymatch(struct device *, void *, void *); 64 void rgephyattach(struct device *, struct device *, void *); 65 66 struct cfattach rgephy_ca = { sizeof(struct mii_softc), 67 rgephymatch, rgephyattach, mii_phy_detach, 68 }; 69 70 struct cfdriver rgephy_cd = { 71 NULL, "rgephy", DV_DULL 72 }; 73 74 int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 void rgephy_status(struct mii_softc *); 76 int rgephy_mii_phy_auto(struct mii_softc *); 77 void rgephy_reset(struct mii_softc *); 78 void rgephy_loop(struct mii_softc *); 79 void rgephy_load_dspcode(struct mii_softc *); 80 81 const struct mii_phy_funcs rgephy_funcs = { 82 rgephy_service, rgephy_status, rgephy_reset, 83 }; 84 85 static const struct mii_phydesc rgephys[] = { 86 { MII_OUI_REALTEK2, MII_MODEL_xxREALTEK_RTL8169S, 87 MII_STR_xxREALTEK_RTL8169S }, 88 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 89 MII_STR_xxREALTEK_RTL8169S }, 90 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8251, 91 MII_STR_xxREALTEK_RTL8251 }, 92 93 { 0, 0, 94 NULL }, 95 }; 96 97 int 98 rgephymatch(struct device *parent, void *match, void *aux) 99 { 100 struct mii_attach_args *ma = aux; 101 102 if (mii_phy_match(ma, rgephys) != NULL) 103 return (10); 104 105 return (0); 106 } 107 108 void 109 rgephyattach(struct device *parent, struct device *self, void *aux) 110 { 111 struct mii_softc *sc = (struct mii_softc *)self; 112 struct mii_attach_args *ma = aux; 113 struct mii_data *mii = ma->mii_data; 114 const struct mii_phydesc *mpd; 115 116 mpd = mii_phy_match(ma, rgephys); 117 printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 118 119 sc->mii_inst = mii->mii_instance; 120 sc->mii_phy = ma->mii_phyno; 121 sc->mii_funcs = &rgephy_funcs; 122 sc->mii_model = MII_MODEL(ma->mii_id2); 123 sc->mii_rev = MII_REV(ma->mii_id2); 124 sc->mii_pdata = mii; 125 sc->mii_flags = ma->mii_flags; 126 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 127 128 sc->mii_flags |= MIIF_NOISOLATE; 129 130 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 131 132 if (sc->mii_capabilities & BMSR_EXTSTAT) 133 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 134 if ((sc->mii_capabilities & BMSR_MEDIAMASK) || 135 (sc->mii_extcapabilities & EXTSR_MEDIAMASK)) 136 mii_phy_add_media(sc); 137 138 PHY_RESET(sc); 139 } 140 141 int 142 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 143 { 144 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 145 int anar, reg, speed, gig = 0; 146 char *devname; 147 148 devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name; 149 150 switch (cmd) { 151 case MII_POLLSTAT: 152 /* 153 * If we're not polling our PHY instance, just return. 154 */ 155 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 156 return (0); 157 break; 158 159 case MII_MEDIACHG: 160 /* 161 * If the media indicates a different PHY instance, 162 * isolate ourselves. 163 */ 164 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 165 reg = PHY_READ(sc, MII_BMCR); 166 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 167 return (0); 168 } 169 170 /* 171 * If the interface is not up, don't do anything. 172 */ 173 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 174 break; 175 176 PHY_RESET(sc); /* XXX hardware bug work-around */ 177 178 anar = PHY_READ(sc, MII_ANAR); 179 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10); 180 181 switch (IFM_SUBTYPE(ife->ifm_media)) { 182 case IFM_AUTO: 183 (void) rgephy_mii_phy_auto(sc); 184 break; 185 case IFM_1000_T: 186 speed = BMCR_S1000; 187 goto setit; 188 case IFM_100_TX: 189 speed = BMCR_S100; 190 anar |= ANAR_TX_FD | ANAR_TX; 191 goto setit; 192 case IFM_10_T: 193 speed = BMCR_S10; 194 anar |= ANAR_10_FD | ANAR_10; 195 setit: 196 rgephy_loop(sc); 197 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 198 speed |= BMCR_FDX; 199 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) 200 gig = GTCR_ADV_1000TFDX; 201 anar &= ~(ANAR_TX | ANAR_10); 202 } else { 203 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) 204 gig = GTCR_ADV_1000THDX; 205 anar &= 206 ~(ANAR_TX_FD | ANAR_10_FD); 207 } 208 209 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T && 210 mii->mii_media.ifm_media & IFM_ETH_MASTER) 211 gig |= GTCR_MAN_MS|GTCR_ADV_MS; 212 213 PHY_WRITE(sc, MII_100T2CR, gig); 214 PHY_WRITE(sc, MII_BMCR, speed | BMCR_AUTOEN | 215 BMCR_STARTNEG); 216 PHY_WRITE(sc, MII_ANAR, anar); 217 break; 218 #if 0 219 case IFM_NONE: 220 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 221 break; 222 #endif 223 default: 224 return (EINVAL); 225 } 226 break; 227 228 case MII_TICK: 229 /* 230 * If we're not currently selected, just return. 231 */ 232 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 233 return (0); 234 235 /* 236 * Is the interface even up? 237 */ 238 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 239 return (0); 240 241 /* 242 * Only used for autonegotiation. 243 */ 244 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 245 break; 246 247 /* 248 * Check to see if we have link. If we do, we don't 249 * need to restart the autonegotiation process. Read 250 * the BMSR twice in case it's latched. 251 */ 252 if (strcmp(devname, "re") == 0) { 253 reg = PHY_READ(sc, RL_GMEDIASTAT); 254 if (reg & RL_GMEDIASTAT_LINK) { 255 sc->mii_ticks = 0; 256 break; 257 } 258 } else { 259 reg = PHY_READ(sc, RGEPHY_SR); 260 if (reg & RGEPHY_SR_LINK) { 261 sc->mii_ticks = 0; 262 break; 263 } 264 } 265 266 /* 267 * Only retry autonegotiation every mii_anegticks seconds. 268 */ 269 if (++sc->mii_ticks <= sc->mii_anegticks) 270 break; 271 272 sc->mii_ticks = 0; 273 rgephy_mii_phy_auto(sc); 274 break; 275 } 276 277 /* Update the media status. */ 278 mii_phy_status(sc); 279 280 /* 281 * Callback if something changed. Note that we need to poke 282 * the DSP on the Realtek PHYs if the media changes. 283 * 284 */ 285 if (sc->mii_media_active != mii->mii_media_active || 286 sc->mii_media_status != mii->mii_media_status || 287 cmd == MII_MEDIACHG) 288 rgephy_load_dspcode(sc); 289 290 /* Callback if something changed. */ 291 mii_phy_update(sc, cmd); 292 293 return (0); 294 } 295 296 void 297 rgephy_status(struct mii_softc *sc) 298 { 299 struct mii_data *mii = sc->mii_pdata; 300 int bmsr, bmcr, gtsr; 301 char *devname; 302 303 devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name; 304 305 mii->mii_media_status = IFM_AVALID; 306 mii->mii_media_active = IFM_ETHER; 307 308 if (strcmp(devname, "re") == 0) { 309 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 310 if (bmsr & RL_GMEDIASTAT_LINK) 311 mii->mii_media_status |= IFM_ACTIVE; 312 } else { 313 bmsr = PHY_READ(sc, RGEPHY_SR); 314 if (bmsr & RGEPHY_SR_LINK) 315 mii->mii_media_status |= IFM_ACTIVE; 316 } 317 318 bmsr = PHY_READ(sc, MII_BMSR); 319 320 bmcr = PHY_READ(sc, MII_BMCR); 321 322 if (bmcr & BMCR_LOOP) 323 mii->mii_media_active |= IFM_LOOP; 324 325 if (bmcr & BMCR_AUTOEN) { 326 if ((bmsr & BMSR_ACOMP) == 0) { 327 /* Erg, still trying, I guess... */ 328 mii->mii_media_active |= IFM_NONE; 329 return; 330 } 331 } 332 333 if (strcmp(devname, "re") == 0) { 334 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 335 if (bmsr & RL_GMEDIASTAT_1000MBPS) 336 mii->mii_media_active |= IFM_1000_T; 337 else if (bmsr & RL_GMEDIASTAT_100MBPS) 338 mii->mii_media_active |= IFM_100_TX; 339 else if (bmsr & RL_GMEDIASTAT_10MBPS) 340 mii->mii_media_active |= IFM_10_T; 341 342 if (bmsr & RL_GMEDIASTAT_FDX) 343 mii->mii_media_active |= mii_phy_flowstatus(sc) | 344 IFM_FDX; 345 else 346 mii->mii_media_active |= IFM_HDX; 347 } else { 348 bmsr = PHY_READ(sc, RGEPHY_SR); 349 if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_1000MBPS) 350 mii->mii_media_active |= IFM_1000_T; 351 else if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_100MBPS) 352 mii->mii_media_active |= IFM_100_TX; 353 else if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_10MBPS) 354 mii->mii_media_active |= IFM_10_T; 355 356 if (bmsr & RGEPHY_SR_FDX) 357 mii->mii_media_active |= mii_phy_flowstatus(sc) | 358 IFM_FDX; 359 else 360 mii->mii_media_active |= IFM_HDX; 361 } 362 363 gtsr = PHY_READ(sc, MII_100T2SR); 364 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 365 gtsr & GTSR_MS_RES) 366 mii->mii_media_active |= IFM_ETH_MASTER; 367 } 368 369 370 int 371 rgephy_mii_phy_auto(struct mii_softc *sc) 372 { 373 int anar; 374 375 rgephy_loop(sc); 376 PHY_RESET(sc); 377 378 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 379 if (sc->mii_flags & MIIF_DOPAUSE) 380 anar |= ANAR_FC | ANAR_X_PAUSE_ASYM; 381 382 PHY_WRITE(sc, MII_ANAR, anar); 383 DELAY(1000); 384 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX); 385 DELAY(1000); 386 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 387 DELAY(100); 388 389 return (EJUSTRETURN); 390 } 391 392 void 393 rgephy_loop(struct mii_softc *sc) 394 { 395 u_int32_t bmsr; 396 int i; 397 398 if (sc->mii_model != MII_MODEL_xxREALTEK_RTL8251 && 399 sc->mii_rev < 2) { 400 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN); 401 DELAY(1000); 402 } 403 404 for (i = 0; i < 15000; i++) { 405 bmsr = PHY_READ(sc, MII_BMSR); 406 if (!(bmsr & BMSR_LINK)) 407 break; 408 DELAY(10); 409 } 410 } 411 412 #define PHY_SETBIT(x, y, z) \ 413 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 414 #define PHY_CLRBIT(x, y, z) \ 415 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 416 417 /* 418 * Initialize Realtek PHY per the datasheet. The DSP in the PHYs of 419 * existing revisions of the 8169S/8110S chips need to be tuned in 420 * order to reliably negotiate a 1000Mbps link. This is only needed 421 * for rev 0 and rev 1 of the PHY. Later versions work without 422 * any fixups. 423 */ 424 void 425 rgephy_load_dspcode(struct mii_softc *sc) 426 { 427 int val; 428 429 if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8251 || 430 sc->mii_rev > 1) 431 return; 432 433 PHY_WRITE(sc, 31, 0x0001); 434 PHY_WRITE(sc, 21, 0x1000); 435 PHY_WRITE(sc, 24, 0x65C7); 436 PHY_CLRBIT(sc, 4, 0x0800); 437 val = PHY_READ(sc, 4) & 0xFFF; 438 PHY_WRITE(sc, 4, val); 439 PHY_WRITE(sc, 3, 0x00A1); 440 PHY_WRITE(sc, 2, 0x0008); 441 PHY_WRITE(sc, 1, 0x1020); 442 PHY_WRITE(sc, 0, 0x1000); 443 PHY_SETBIT(sc, 4, 0x0800); 444 PHY_CLRBIT(sc, 4, 0x0800); 445 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 446 PHY_WRITE(sc, 4, val); 447 PHY_WRITE(sc, 3, 0xFF41); 448 PHY_WRITE(sc, 2, 0xDE60); 449 PHY_WRITE(sc, 1, 0x0140); 450 PHY_WRITE(sc, 0, 0x0077); 451 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 452 PHY_WRITE(sc, 4, val); 453 PHY_WRITE(sc, 3, 0xDF01); 454 PHY_WRITE(sc, 2, 0xDF20); 455 PHY_WRITE(sc, 1, 0xFF95); 456 PHY_WRITE(sc, 0, 0xFA00); 457 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 458 PHY_WRITE(sc, 4, val); 459 PHY_WRITE(sc, 3, 0xFF41); 460 PHY_WRITE(sc, 2, 0xDE20); 461 PHY_WRITE(sc, 1, 0x0140); 462 PHY_WRITE(sc, 0, 0x00BB); 463 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 464 PHY_WRITE(sc, 4, val); 465 PHY_WRITE(sc, 3, 0xDF01); 466 PHY_WRITE(sc, 2, 0xDF20); 467 PHY_WRITE(sc, 1, 0xFF95); 468 PHY_WRITE(sc, 0, 0xBF00); 469 PHY_SETBIT(sc, 4, 0x0800); 470 PHY_CLRBIT(sc, 4, 0x0800); 471 PHY_WRITE(sc, 31, 0x0000); 472 473 DELAY(40); 474 } 475 476 void 477 rgephy_reset(struct mii_softc *sc) 478 { 479 mii_phy_reset(sc); 480 DELAY(1000); 481 rgephy_load_dspcode(sc); 482 } 483