1 /* $OpenBSD: rgephy.c,v 1.33 2013/12/30 22:35:29 brad Exp $ */ 2 /* 3 * Copyright (c) 2003 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: rgephy.c,v 1.5 2004/05/30 17:57:40 phk Exp $ 34 */ 35 36 /* 37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/socket.h> 45 #include <sys/errno.h> 46 47 #include <machine/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include <dev/mii/miidevs.h> 58 59 #include <dev/mii/rgephyreg.h> 60 61 #include <dev/ic/rtl81x9reg.h> 62 63 int rgephymatch(struct device *, void *, void *); 64 void rgephyattach(struct device *, struct device *, void *); 65 66 struct cfattach rgephy_ca = { sizeof(struct mii_softc), 67 rgephymatch, rgephyattach, mii_phy_detach, 68 }; 69 70 struct cfdriver rgephy_cd = { 71 NULL, "rgephy", DV_DULL 72 }; 73 74 int rgephy_service(struct mii_softc *, struct mii_data *, int); 75 void rgephy_status(struct mii_softc *); 76 int rgephy_mii_phy_auto(struct mii_softc *); 77 void rgephy_reset(struct mii_softc *); 78 void rgephy_loop(struct mii_softc *); 79 void rgephy_load_dspcode(struct mii_softc *); 80 81 const struct mii_phy_funcs rgephy_funcs = { 82 rgephy_service, rgephy_status, rgephy_reset, 83 }; 84 85 static const struct mii_phydesc rgephys[] = { 86 { MII_OUI_REALTEK2, MII_MODEL_xxREALTEK_RTL8169S, 87 MII_STR_xxREALTEK_RTL8169S }, 88 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S, 89 MII_STR_xxREALTEK_RTL8169S }, 90 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8251, 91 MII_STR_xxREALTEK_RTL8251 }, 92 93 { 0, 0, 94 NULL }, 95 }; 96 97 int 98 rgephymatch(struct device *parent, void *match, void *aux) 99 { 100 struct mii_attach_args *ma = aux; 101 102 if (mii_phy_match(ma, rgephys) != NULL) 103 return (10); 104 105 return (0); 106 } 107 108 void 109 rgephyattach(struct device *parent, struct device *self, void *aux) 110 { 111 struct mii_softc *sc = (struct mii_softc *)self; 112 struct mii_attach_args *ma = aux; 113 struct mii_data *mii = ma->mii_data; 114 const struct mii_phydesc *mpd; 115 116 mpd = mii_phy_match(ma, rgephys); 117 printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 118 119 sc->mii_inst = mii->mii_instance; 120 sc->mii_phy = ma->mii_phyno; 121 sc->mii_funcs = &rgephy_funcs; 122 sc->mii_model = MII_MODEL(ma->mii_id2); 123 sc->mii_rev = MII_REV(ma->mii_id2); 124 sc->mii_pdata = mii; 125 sc->mii_flags = ma->mii_flags; 126 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 127 128 sc->mii_flags |= MIIF_NOISOLATE; 129 130 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 131 132 if (sc->mii_capabilities & BMSR_EXTSTAT) 133 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 134 if ((sc->mii_capabilities & BMSR_MEDIAMASK) || 135 (sc->mii_extcapabilities & EXTSR_MEDIAMASK)) 136 mii_phy_add_media(sc); 137 138 PHY_RESET(sc); 139 } 140 141 int 142 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 143 { 144 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 145 int anar, reg, speed, gig = 0; 146 char *devname; 147 148 devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name; 149 150 switch (cmd) { 151 case MII_POLLSTAT: 152 /* 153 * If we're not polling our PHY instance, just return. 154 */ 155 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 156 return (0); 157 break; 158 159 case MII_MEDIACHG: 160 /* 161 * If the media indicates a different PHY instance, 162 * isolate ourselves. 163 */ 164 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 165 reg = PHY_READ(sc, MII_BMCR); 166 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 167 return (0); 168 } 169 170 /* 171 * If the interface is not up, don't do anything. 172 */ 173 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 174 break; 175 176 PHY_RESET(sc); /* XXX hardware bug work-around */ 177 178 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 179 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 180 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 181 182 switch (IFM_SUBTYPE(ife->ifm_media)) { 183 case IFM_AUTO: 184 (void) rgephy_mii_phy_auto(sc); 185 break; 186 case IFM_1000_T: 187 speed = RGEPHY_S1000; 188 goto setit; 189 case IFM_100_TX: 190 speed = RGEPHY_S100; 191 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 192 goto setit; 193 case IFM_10_T: 194 speed = RGEPHY_S10; 195 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 196 setit: 197 rgephy_loop(sc); 198 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 199 speed |= RGEPHY_BMCR_FDX; 200 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) 201 gig = RGEPHY_1000CTL_AFD; 202 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 203 } else { 204 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) 205 gig = RGEPHY_1000CTL_AHD; 206 anar &= 207 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 208 } 209 210 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T && 211 mii->mii_media.ifm_media & IFM_ETH_MASTER) 212 gig |= RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC; 213 214 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 215 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed | 216 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 217 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 218 break; 219 #if 0 220 case IFM_NONE: 221 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 222 break; 223 #endif 224 default: 225 return (EINVAL); 226 } 227 break; 228 229 case MII_TICK: 230 /* 231 * If we're not currently selected, just return. 232 */ 233 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 234 return (0); 235 236 /* 237 * Is the interface even up? 238 */ 239 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 240 return (0); 241 242 /* 243 * Only used for autonegotiation. 244 */ 245 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 246 break; 247 248 /* 249 * Check to see if we have link. If we do, we don't 250 * need to restart the autonegotiation process. Read 251 * the BMSR twice in case it's latched. 252 */ 253 if (strcmp(devname, "re") == 0) { 254 reg = PHY_READ(sc, RL_GMEDIASTAT); 255 if (reg & RL_GMEDIASTAT_LINK) { 256 sc->mii_ticks = 0; 257 break; 258 } 259 } else { 260 reg = PHY_READ(sc, RGEPHY_SR); 261 if (reg & RGEPHY_SR_LINK) { 262 sc->mii_ticks = 0; 263 break; 264 } 265 } 266 267 /* 268 * Only retry autonegotiation every mii_anegticks seconds. 269 */ 270 if (++sc->mii_ticks <= sc->mii_anegticks) 271 break; 272 273 sc->mii_ticks = 0; 274 rgephy_mii_phy_auto(sc); 275 break; 276 } 277 278 /* Update the media status. */ 279 mii_phy_status(sc); 280 281 /* 282 * Callback if something changed. Note that we need to poke 283 * the DSP on the RealTek PHYs if the media changes. 284 * 285 */ 286 if (sc->mii_media_active != mii->mii_media_active || 287 sc->mii_media_status != mii->mii_media_status || 288 cmd == MII_MEDIACHG) 289 rgephy_load_dspcode(sc); 290 291 /* Callback if something changed. */ 292 mii_phy_update(sc, cmd); 293 294 return (0); 295 } 296 297 void 298 rgephy_status(struct mii_softc *sc) 299 { 300 struct mii_data *mii = sc->mii_pdata; 301 int bmsr, bmcr, gtsr; 302 char *devname; 303 304 devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name; 305 306 mii->mii_media_status = IFM_AVALID; 307 mii->mii_media_active = IFM_ETHER; 308 309 if (strcmp(devname, "re") == 0) { 310 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 311 if (bmsr & RL_GMEDIASTAT_LINK) 312 mii->mii_media_status |= IFM_ACTIVE; 313 } else { 314 bmsr = PHY_READ(sc, RGEPHY_SR); 315 if (bmsr & RGEPHY_SR_LINK) 316 mii->mii_media_status |= IFM_ACTIVE; 317 } 318 319 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 320 321 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 322 323 if (bmcr & RGEPHY_BMCR_LOOP) 324 mii->mii_media_active |= IFM_LOOP; 325 326 if (bmcr & RGEPHY_BMCR_AUTOEN) { 327 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 328 /* Erg, still trying, I guess... */ 329 mii->mii_media_active |= IFM_NONE; 330 return; 331 } 332 } 333 334 if (strcmp(devname, "re") == 0) { 335 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 336 if (bmsr & RL_GMEDIASTAT_1000MBPS) 337 mii->mii_media_active |= IFM_1000_T; 338 else if (bmsr & RL_GMEDIASTAT_100MBPS) 339 mii->mii_media_active |= IFM_100_TX; 340 else if (bmsr & RL_GMEDIASTAT_10MBPS) 341 mii->mii_media_active |= IFM_10_T; 342 343 if (bmsr & RL_GMEDIASTAT_FDX) 344 mii->mii_media_active |= mii_phy_flowstatus(sc) | 345 IFM_FDX; 346 else 347 mii->mii_media_active |= IFM_HDX; 348 } else { 349 bmsr = PHY_READ(sc, RGEPHY_SR); 350 if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_1000MBPS) 351 mii->mii_media_active |= IFM_1000_T; 352 else if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_100MBPS) 353 mii->mii_media_active |= IFM_100_TX; 354 else if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_10MBPS) 355 mii->mii_media_active |= IFM_10_T; 356 357 if (bmsr & RGEPHY_SR_FDX) 358 mii->mii_media_active |= mii_phy_flowstatus(sc) | 359 IFM_FDX; 360 else 361 mii->mii_media_active |= IFM_HDX; 362 } 363 364 gtsr = PHY_READ(sc, RGEPHY_MII_1000STS); 365 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 366 gtsr & RGEPHY_1000STS_MSR) 367 mii->mii_media_active |= IFM_ETH_MASTER; 368 } 369 370 371 int 372 rgephy_mii_phy_auto(struct mii_softc *sc) 373 { 374 int anar; 375 376 rgephy_loop(sc); 377 PHY_RESET(sc); 378 379 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 380 if (sc->mii_flags & MIIF_DOPAUSE) 381 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 382 383 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 384 DELAY(1000); 385 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 386 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 387 DELAY(1000); 388 PHY_WRITE(sc, RGEPHY_MII_BMCR, 389 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 390 DELAY(100); 391 392 return (EJUSTRETURN); 393 } 394 395 void 396 rgephy_loop(struct mii_softc *sc) 397 { 398 u_int32_t bmsr; 399 int i; 400 401 if (sc->mii_model != MII_MODEL_xxREALTEK_RTL8251 && 402 sc->mii_rev < 2) { 403 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 404 DELAY(1000); 405 } 406 407 for (i = 0; i < 15000; i++) { 408 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 409 if (!(bmsr & RGEPHY_BMSR_LINK)) 410 break; 411 DELAY(10); 412 } 413 } 414 415 #define PHY_SETBIT(x, y, z) \ 416 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 417 #define PHY_CLRBIT(x, y, z) \ 418 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 419 420 /* 421 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 422 * existing revisions of the 8169S/8110S chips need to be tuned in 423 * order to reliably negotiate a 1000Mbps link. This is only needed 424 * for rev 0 and rev 1 of the PHY. Later versions work without 425 * any fixups. 426 */ 427 void 428 rgephy_load_dspcode(struct mii_softc *sc) 429 { 430 int val; 431 432 if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8251 || 433 sc->mii_rev > 1) 434 return; 435 436 PHY_WRITE(sc, 31, 0x0001); 437 PHY_WRITE(sc, 21, 0x1000); 438 PHY_WRITE(sc, 24, 0x65C7); 439 PHY_CLRBIT(sc, 4, 0x0800); 440 val = PHY_READ(sc, 4) & 0xFFF; 441 PHY_WRITE(sc, 4, val); 442 PHY_WRITE(sc, 3, 0x00A1); 443 PHY_WRITE(sc, 2, 0x0008); 444 PHY_WRITE(sc, 1, 0x1020); 445 PHY_WRITE(sc, 0, 0x1000); 446 PHY_SETBIT(sc, 4, 0x0800); 447 PHY_CLRBIT(sc, 4, 0x0800); 448 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 449 PHY_WRITE(sc, 4, val); 450 PHY_WRITE(sc, 3, 0xFF41); 451 PHY_WRITE(sc, 2, 0xDE60); 452 PHY_WRITE(sc, 1, 0x0140); 453 PHY_WRITE(sc, 0, 0x0077); 454 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 455 PHY_WRITE(sc, 4, val); 456 PHY_WRITE(sc, 3, 0xDF01); 457 PHY_WRITE(sc, 2, 0xDF20); 458 PHY_WRITE(sc, 1, 0xFF95); 459 PHY_WRITE(sc, 0, 0xFA00); 460 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 461 PHY_WRITE(sc, 4, val); 462 PHY_WRITE(sc, 3, 0xFF41); 463 PHY_WRITE(sc, 2, 0xDE20); 464 PHY_WRITE(sc, 1, 0x0140); 465 PHY_WRITE(sc, 0, 0x00BB); 466 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 467 PHY_WRITE(sc, 4, val); 468 PHY_WRITE(sc, 3, 0xDF01); 469 PHY_WRITE(sc, 2, 0xDF20); 470 PHY_WRITE(sc, 1, 0xFF95); 471 PHY_WRITE(sc, 0, 0xBF00); 472 PHY_SETBIT(sc, 4, 0x0800); 473 PHY_CLRBIT(sc, 4, 0x0800); 474 PHY_WRITE(sc, 31, 0x0000); 475 476 DELAY(40); 477 } 478 479 void 480 rgephy_reset(struct mii_softc *sc) 481 { 482 mii_phy_reset(sc); 483 DELAY(1000); 484 rgephy_load_dspcode(sc); 485 } 486