1 /* $OpenBSD: atphy.c,v 1.2 2009/03/23 05:26:47 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for the Attansic F1 10/100/1000 PHY. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/device.h> 38 #include <sys/socket.h> 39 40 #include <net/if.h> 41 #include <net/if_media.h> 42 43 #include <dev/mii/mii.h> 44 #include <dev/mii/miivar.h> 45 #include <dev/mii/miidevs.h> 46 47 /* Special Control Register */ 48 #define ATPHY_SCR 0x10 49 #define ATPHY_SCR_JABBER_DISABLE 0x0001 50 #define ATPHY_SCR_POLARITY_REVERSAL 0x0002 51 #define ATPHY_SCR_SQE_TEST 0x0004 52 #define ATPHY_SCR_MAC_PDOWN 0x0008 53 #define ATPHY_SCR_CLK125_DISABLE 0x0010 54 #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000 55 #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020 56 #define ATPHY_SCR_AUTO_X_1000T 0x0040 57 #define ATPHY_SCR_AUTO_X_MODE 0x0060 58 #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080 59 #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100 60 #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200 61 #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400 62 #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800 63 64 /* Special Status Register. */ 65 #define ATPHY_SSR 0x11 66 #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800 67 #define ATPHY_SSR_DUPLEX 0x2000 68 #define ATPHY_SSR_SPEED_MASK 0xC000 69 #define ATPHY_SSR_10MBS 0x0000 70 #define ATPHY_SSR_100MBS 0x4000 71 #define ATPHY_SSR_1000MBS 0x8000 72 73 int atphy_service(struct mii_softc *, struct mii_data *, int); 74 void atphy_attach(struct device *, struct device *, void *); 75 int atphy_match(struct device *, void *, void *); 76 void atphy_reset(struct mii_softc *); 77 void atphy_status(struct mii_softc *); 78 int atphy_mii_phy_auto(struct mii_softc *); 79 80 const struct mii_phy_funcs atphy_funcs = { 81 atphy_service, atphy_status, atphy_reset, 82 }; 83 84 static const struct mii_phydesc etphys[] = { 85 { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1, 86 MII_STR_ATHEROS_F1 }, 87 { 0, 0, 88 NULL }, 89 }; 90 91 struct cfattach atphy_ca = { 92 sizeof (struct mii_softc), atphy_match, atphy_attach, 93 mii_phy_detach, mii_phy_activate 94 }; 95 96 struct cfdriver atphy_cd = { 97 NULL, "atphy", DV_DULL 98 }; 99 100 int 101 atphy_match(struct device *parent, void *match, void *aux) 102 { 103 struct mii_attach_args *ma = aux; 104 105 if (mii_phy_match(ma, etphys) != NULL) 106 return (10); 107 108 return (0); 109 } 110 111 void 112 atphy_attach(struct device *parent, struct device *self, void *aux) 113 { 114 struct mii_softc *sc = (struct mii_softc *)self; 115 struct mii_attach_args *ma = aux; 116 struct mii_data *mii = ma->mii_data; 117 const struct mii_phydesc *mpd; 118 119 mpd = mii_phy_match(ma, etphys); 120 printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 121 122 sc->mii_inst = mii->mii_instance; 123 sc->mii_phy = ma->mii_phyno; 124 sc->mii_funcs = &atphy_funcs; 125 sc->mii_pdata = mii; 126 sc->mii_flags = ma->mii_flags; 127 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 128 129 sc->mii_flags |= MIIF_NOLOOP; 130 131 PHY_RESET(sc); 132 133 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 134 if (sc->mii_capabilities & BMSR_EXTSTAT) 135 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 136 137 mii_phy_add_media(sc); 138 } 139 140 int 141 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 142 { 143 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 144 uint16_t anar, bmcr, bmsr; 145 146 switch (cmd) { 147 case MII_POLLSTAT: 148 /* 149 * If we're not polling our PHY instance, just return. 150 */ 151 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 152 return (0); 153 break; 154 155 case MII_MEDIACHG: 156 /* 157 * If the media indicates a different PHY instance, 158 * isolate ourselves. 159 */ 160 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 161 bmcr = PHY_READ(sc, MII_BMCR); 162 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 163 return (0); 164 } 165 166 /* 167 * If the interface is not up, don't do anything. 168 */ 169 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 170 break; 171 172 bmcr = 0; 173 switch (IFM_SUBTYPE(ife->ifm_media)) { 174 case IFM_AUTO: 175 case IFM_1000_T: 176 atphy_mii_phy_auto(sc); 177 goto done; 178 case IFM_100_TX: 179 bmcr = BMCR_S100; 180 break; 181 case IFM_10_T: 182 bmcr = BMCR_S10; 183 break; 184 case IFM_NONE: 185 bmcr = PHY_READ(sc, MII_BMCR); 186 /* 187 * XXX 188 * Due to an unknown reason powering down PHY resulted 189 * in unexpected results such as inaccessbility of 190 * hardware of freshly rebooted system. Disable 191 * powering down PHY until I got more information for 192 * Attansic/Atheros PHY hardwares. 193 */ 194 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 195 goto done; 196 default: 197 return (EINVAL); 198 } 199 200 anar = mii_anar(ife->ifm_media); 201 if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) { 202 bmcr |= BMCR_FDX; 203 /* Enable pause. */ 204 if (sc->mii_flags & MIIF_DOPAUSE) 205 anar |= (3 << 10); 206 } 207 208 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 209 EXTSR_1000THDX)) != 0) 210 PHY_WRITE(sc, MII_100T2CR, 0); 211 PHY_WRITE(sc, MII_ANAR, anar); 212 213 /* 214 * Reset the PHY so all changes take effect. 215 */ 216 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN | 217 BMCR_STARTNEG); 218 done: 219 break; 220 221 case MII_TICK: 222 /* 223 * If we're not currently selected, just return. 224 */ 225 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 226 return (0); 227 228 /* 229 * Is the interface even up? 230 */ 231 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 232 return (0); 233 234 /* 235 * Only used for autonegotiation. 236 */ 237 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 238 sc->mii_ticks = 0; 239 break; 240 } 241 242 /* 243 * Check for link. 244 * Read the status register twice; BMSR_LINK is latch-low. 245 */ 246 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 247 if (bmsr & BMSR_LINK) { 248 sc->mii_ticks = 0; 249 break; 250 } 251 252 /* Announce link loss right after it happens. */ 253 if (sc->mii_ticks++ == 0) 254 break; 255 256 /* 257 * Only retry autonegotiation every mii_anegticks seconds. 258 */ 259 if (sc->mii_ticks <= sc->mii_anegticks) 260 break; 261 262 sc->mii_ticks = 0; 263 atphy_mii_phy_auto(sc); 264 break; 265 } 266 267 /* Update the media status. */ 268 mii_phy_status(sc); 269 270 /* Callback if something changed. */ 271 mii_phy_update(sc, cmd); 272 return (0); 273 } 274 275 void 276 atphy_status(struct mii_softc *sc) 277 { 278 struct mii_data *mii = sc->mii_pdata; 279 uint32_t bmsr, bmcr, gsr, ssr; 280 281 mii->mii_media_status = IFM_AVALID; 282 mii->mii_media_active = IFM_ETHER; 283 284 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 285 if (bmsr & BMSR_LINK) 286 mii->mii_media_status |= IFM_ACTIVE; 287 288 bmcr = PHY_READ(sc, MII_BMCR); 289 if (bmcr & BMCR_ISO) { 290 mii->mii_media_active |= IFM_NONE; 291 mii->mii_media_status = 0; 292 return; 293 } 294 295 if (bmcr & BMCR_LOOP) 296 mii->mii_media_active |= IFM_LOOP; 297 298 ssr = PHY_READ(sc, ATPHY_SSR); 299 if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) { 300 /* Erg, still trying, I guess... */ 301 mii->mii_media_active |= IFM_NONE; 302 return; 303 } 304 305 switch (ssr & ATPHY_SSR_SPEED_MASK) { 306 case ATPHY_SSR_1000MBS: 307 mii->mii_media_active |= IFM_1000_T; 308 /* 309 * atphy(4) has a valid link so reset mii_ticks. 310 * Resetting mii_ticks is needed in order to 311 * detect link loss after auto-negotiation. 312 */ 313 sc->mii_ticks = 0; 314 break; 315 case ATPHY_SSR_100MBS: 316 mii->mii_media_active |= IFM_100_TX; 317 sc->mii_ticks = 0; 318 break; 319 case ATPHY_SSR_10MBS: 320 mii->mii_media_active |= IFM_10_T; 321 sc->mii_ticks = 0; 322 break; 323 default: 324 mii->mii_media_active |= IFM_NONE; 325 return; 326 } 327 328 if (ssr & ATPHY_SSR_DUPLEX) 329 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 330 else 331 mii->mii_media_active |= IFM_HDX; 332 333 gsr = PHY_READ(sc, MII_100T2SR); 334 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 335 gsr & GTSR_MS_RES) 336 mii->mii_media_active |= IFM_ETH_MASTER; 337 } 338 339 void 340 atphy_reset(struct mii_softc *sc) 341 { 342 uint32_t reg; 343 int i; 344 345 /* Take PHY out of power down mode. */ 346 PHY_WRITE(sc, 29, 0x29); 347 PHY_WRITE(sc, 30, 0); 348 349 reg = PHY_READ(sc, ATPHY_SCR); 350 /* Enable automatic crossover. */ 351 reg |= ATPHY_SCR_AUTO_X_MODE; 352 /* Disable power down. */ 353 reg &= ~ATPHY_SCR_MAC_PDOWN; 354 /* Enable CRS on Tx. */ 355 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 356 /* Auto correction for reversed cable polarity. */ 357 reg |= ATPHY_SCR_POLARITY_REVERSAL; 358 PHY_WRITE(sc, ATPHY_SCR, reg); 359 360 /* Workaround F1 bug to reset phy. */ 361 atphy_mii_phy_auto(sc); 362 363 for (i = 0; i < 1000; i++) { 364 DELAY(1); 365 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) 366 break; 367 } 368 } 369 370 int 371 atphy_mii_phy_auto(struct mii_softc *sc) 372 { 373 uint16_t anar; 374 375 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 376 if (sc->mii_flags & MIIF_DOPAUSE) 377 anar |= (3 << 10); 378 PHY_WRITE(sc, MII_ANAR, anar); 379 if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) 380 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 381 GTCR_ADV_1000THDX); 382 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 383 384 return (EJUSTRETURN); 385 } 386