1 /* $OpenBSD: addcom_isa.c,v 1.4 2001/07/21 04:24:13 jason Exp $ */ 2 /* $NetBSD: addcom_isa.c,v 1.2 2000/04/21 20:13:41 explorer Exp $ */ 3 4 /* 5 * Copyright (c) 2000 Michael Graff. All rights reserved. 6 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1995 Charles M. Hannum. All rights reserved. 8 * 9 * This code is derived from public-domain software written by 10 * Roland McGrath, and information provided by David Muir Sharnoff. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Charles M. Hannum. 23 * 4. The name of the author may not be used to endorse or promote products 24 * derived from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * This code was written and tested with the Addonics FlexPort 8S. 40 * It has 8 ports, using 16650-compatible chips, sharing a single 41 * interrupt. 42 * 43 * An interrupt status register exists at 0x240, according to the 44 * skimpy documentation supplied. It doesn't change depending on 45 * io base address, so only one of these cards can ever be used at 46 * a time. 47 * 48 * NOTE: the status register does not appear to work as advertised, 49 * so instead we depend on the slave devices being intelligent enough 50 * to determine whether they interrupted or not. 51 * 52 * This card is different from the boca or other cards in that ports 53 * 0..5 are from addresses 0x108..0x137, and 6..7 are from 0x200..0x20f, 54 * making a gap that the other cards do not have. 55 * 56 * The addresses which are documented are 0x108, 0x1108, 0x1d08, and 57 * 0x8508, for the base (port 0) address. 58 * 59 * --Michael <explorer@netbsd.org> -- April 21, 2000 60 */ 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/termios.h> 66 67 #include <machine/bus.h> 68 #include <machine/intr.h> 69 70 #include <dev/ic/comreg.h> 71 #include <dev/ic/comvar.h> 72 73 #include <dev/isa/isavar.h> 74 75 #define NSLAVES 8 76 77 /* 78 * Grr. This card always uses 0x420 for the status register, regardless 79 * of io base address. 80 */ 81 #define STATUS_IOADDR 0x420 82 #define STATUS_SIZE 8 /* May be bogus... */ 83 84 struct addcom_softc { 85 struct device sc_dev; 86 void *sc_ih; 87 88 bus_space_tag_t sc_iot; 89 int sc_iobase; 90 91 int sc_alive; /* mask of slave units attached */ 92 void *sc_slaves[NSLAVES]; /* com device unit numbers */ 93 bus_space_handle_t sc_slaveioh[NSLAVES]; 94 bus_space_handle_t sc_statusioh; 95 }; 96 97 #define SLAVE_IOBASE_OFFSET 0x108 98 static int slave_iobases[8] = { 99 0x108, /* port 0, base port */ 100 0x110, 101 0x118, 102 0x120, 103 0x128, 104 0x130, 105 0x200, /* port 7, note address skip... */ 106 0x208 107 }; 108 109 int addcomprobe __P((struct device *, void *, void *)); 110 void addcomattach __P((struct device *, struct device *, void *)); 111 int addcomintr __P((void *)); 112 int addcomprint __P((void *, const char *)); 113 114 struct cfattach addcom_isa_ca = { 115 sizeof(struct addcom_softc), addcomprobe, addcomattach, 116 }; 117 118 struct cfdriver addcom_cd = { 119 NULL, "addcom", DV_TTY 120 }; 121 122 int 123 addcomprobe(parent, self, aux) 124 struct device *parent; 125 void *self, *aux; 126 { 127 struct isa_attach_args *ia = aux; 128 int iobase = ia->ia_iobase; 129 bus_space_tag_t iot = ia->ia_iot; 130 bus_space_handle_t ioh; 131 int i, rv = 1; 132 133 /* 134 * Do the normal com probe for the first UART and assume 135 * its presence, and the ability to map the other UARTS, 136 * means there is a multiport board there. 137 * XXX Needs more robustness. 138 */ 139 140 /* Disallow wildcard interrupt. */ 141 if (ia->ia_irq == IRQUNK) 142 return (0); 143 144 /* Disallow wildcarded i/o address. */ 145 if (ia->ia_iobase == -1 /* ISACF_PORT_DEFAULT */) 146 return (0); 147 148 /* if the first port is in use as console, then it. */ 149 if (iobase == comconsaddr && !comconsattached) 150 goto checkmappings; 151 152 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) { 153 rv = 0; 154 goto out; 155 } 156 rv = comprobe1(iot, ioh); 157 bus_space_unmap(iot, ioh, COM_NPORTS); 158 if (rv == 0) 159 goto out; 160 161 checkmappings: 162 for (i = 1; i < NSLAVES; i++) { 163 iobase += slave_iobases[i] - slave_iobases[i - 1]; 164 165 if (iobase == comconsaddr && !comconsattached) 166 continue; 167 168 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) { 169 rv = 0; 170 goto out; 171 } 172 bus_space_unmap(iot, ioh, COM_NPORTS); 173 } 174 175 out: 176 if (rv) 177 ia->ia_iosize = NSLAVES * COM_NPORTS; 178 return (rv); 179 } 180 181 int 182 addcomprint(aux, pnp) 183 void *aux; 184 const char *pnp; 185 { 186 struct commulti_attach_args *ca = aux; 187 188 if (pnp) 189 printf("com at %s", pnp); 190 printf(" slave %d", ca->ca_slave); 191 return (UNCONF); 192 } 193 194 void 195 addcomattach(parent, self, aux) 196 struct device *parent, *self; 197 void *aux; 198 { 199 struct addcom_softc *sc = (void *)self; 200 struct isa_attach_args *ia = aux; 201 struct commulti_attach_args ca; 202 bus_space_tag_t iot = ia->ia_iot; 203 bus_addr_t iobase; 204 int i; 205 206 sc->sc_iot = ia->ia_iot; 207 sc->sc_iobase = ia->ia_iobase; 208 209 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, 210 IPL_TTY, addcomintr, sc, sc->sc_dev.dv_xname); 211 if (sc->sc_ih == NULL) { 212 printf(": can't establish interrupt\n"); 213 return; 214 } 215 216 if (bus_space_map(iot, STATUS_IOADDR, STATUS_SIZE, 217 0, &sc->sc_statusioh)) { 218 printf(": can't map status space\n"); 219 return; 220 } 221 222 for (i = 0; i < NSLAVES; i++) { 223 iobase = sc->sc_iobase 224 + slave_iobases[i] 225 - SLAVE_IOBASE_OFFSET; 226 227 if ((!(iobase == comconsaddr && !comconsattached)) && 228 bus_space_map(iot, iobase, COM_NPORTS, 0, 229 &sc->sc_slaveioh[i])) { 230 printf(": can't map i/o space for slave %d\n", i); 231 return; 232 } 233 } 234 235 printf("\n"); 236 237 for (i = 0; i < NSLAVES; i++) { 238 ca.ca_slave = i; 239 ca.ca_iot = sc->sc_iot; 240 ca.ca_ioh = sc->sc_slaveioh[i]; 241 ca.ca_iobase = sc->sc_iobase 242 + slave_iobases[i] 243 - SLAVE_IOBASE_OFFSET; 244 ca.ca_noien = 0; 245 246 sc->sc_slaves[i] = config_found(self, &ca, addcomprint); 247 if (sc->sc_slaves[i] != NULL) 248 sc->sc_alive |= 1 << i; 249 } 250 251 } 252 253 int 254 addcomintr(arg) 255 void *arg; 256 { 257 struct addcom_softc *sc = arg; 258 int intrd, r = 0, i; 259 260 do { 261 intrd = 0; 262 for (i = 0; i < NSLAVES; i++) { 263 if (sc->sc_alive & (1 << i) && 264 comintr(sc->sc_slaves[i])) { 265 r = 1; 266 intrd = 1; 267 } 268 } 269 } while (intrd); 270 271 return (r); 272 } 273