1 /* $OpenBSD: ad1848.c,v 1.21 2001/04/12 07:51:56 csapuntz Exp $ */ 2 /* $NetBSD: ad1848.c,v 1.45 1998/01/30 02:02:38 augustss Exp $ */ 3 4 /* 5 * Copyright (c) 1994 John Brezak 6 * Copyright (c) 1991-1993 Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the Computer Systems 20 * Engineering Group at Lawrence Berkeley Laboratory. 21 * 4. Neither the name of the University nor of the Laboratory may be used 22 * to endorse or promote products derived from this software without 23 * specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 /* 40 * Copyright by Hannu Savolainen 1994 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions are 44 * met: 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 2. 46 * Redistributions in binary form must reproduce the above copyright notice, 47 * this list of conditions and the following disclaimer in the documentation 48 * and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 51 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 52 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 53 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 54 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 55 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 56 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 57 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 58 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 59 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 60 * SUCH DAMAGE. 61 * 62 */ 63 /* 64 * Portions of this code are from the VOXware support for the ad1848 65 * by Hannu Savolainen <hannu@voxware.pp.fi> 66 * 67 * Portions also supplied from the SoundBlaster driver for NetBSD. 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/errno.h> 73 #include <sys/ioctl.h> 74 #include <sys/syslog.h> 75 #include <sys/device.h> 76 #include <sys/proc.h> 77 #include <sys/buf.h> 78 79 #include <machine/cpu.h> 80 #include <machine/bus.h> 81 82 #include <sys/audioio.h> 83 #include <vm/vm.h> 84 85 #include <dev/audio_if.h> 86 #include <dev/auconv.h> 87 88 #include <dev/isa/isavar.h> 89 #include <dev/isa/isadmavar.h> 90 91 #include <dev/ic/ad1848reg.h> 92 #include <dev/ic/cs4231reg.h> 93 #include <dev/isa/ad1848var.h> 94 #include <dev/isa/cs4231var.h> 95 96 #ifdef AUDIO_DEBUG 97 #define DPRINTF(x) if (ad1848debug) printf x 98 int ad1848debug = 0; 99 #else 100 #define DPRINTF(x) 101 #endif 102 103 /* 104 * Initial values for the indirect registers of CS4248/AD1848. 105 */ 106 static int ad1848_init_values[] = { 107 /* Left Input Control */ 108 GAIN_12|INPUT_MIC_GAIN_ENABLE, 109 /* Right Input Control */ 110 GAIN_12|INPUT_MIC_GAIN_ENABLE, 111 ATTEN_12, /* Left Aux #1 Input Control */ 112 ATTEN_12, /* Right Aux #1 Input Control */ 113 ATTEN_12, /* Left Aux #2 Input Control */ 114 ATTEN_12, /* Right Aux #2 Input Control */ 115 /* bits 5-0 are attenuation select */ 116 ATTEN_12, /* Left DAC output Control */ 117 ATTEN_12, /* Right DAC output Control */ 118 /* Clock and Data Format */ 119 CLOCK_XTAL1|FMT_PCM8, 120 /* Interface Config */ 121 SINGLE_DMA|AUTO_CAL_ENABLE, 122 INTERRUPT_ENABLE, /* Pin control */ 123 0x00, /* Test and Init */ 124 MODE2, /* Misc control */ 125 ATTEN_0<<2, /* Digital Mix Control */ 126 0, /* Upper base Count */ 127 0, /* Lower base Count */ 128 129 /* These are for CS4231 &c. only (additional registers): */ 130 0, /* Alt feature 1 */ 131 0, /* Alt feature 2 */ 132 ATTEN_12, /* Left line in */ 133 ATTEN_12, /* Right line in */ 134 0, /* Timer low */ 135 0, /* Timer high */ 136 0, /* unused */ 137 0, /* unused */ 138 0, /* IRQ status */ 139 0, /* unused */ 140 /* Mono input (a.k.a speaker) (mic) Control */ 141 MONO_INPUT_MUTE|ATTEN_6, /* mute speaker by default */ 142 0, /* unused */ 143 0, /* record format */ 144 0, /* Crystal Clock Select */ 145 0, /* upper record count */ 146 0 /* lower record count */ 147 }; 148 149 void ad1848_reset __P((struct ad1848_softc *)); 150 int ad1848_set_speed __P((struct ad1848_softc *, u_long *)); 151 void ad1848_mute_monitor __P((void *, int)); 152 153 static int ad_read __P((struct ad1848_softc *, int)); 154 static void ad_write __P((struct ad1848_softc *, int, int)); 155 static void ad_set_MCE __P((struct ad1848_softc *, int)); 156 static void wait_for_calibration __P((struct ad1848_softc *)); 157 158 #define ADREAD(sc, addr) bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (sc)->sc_iooffs+(addr)) 159 #define ADWRITE(sc, addr, data) bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (sc)->sc_iooffs+(addr), (data)) 160 161 static int 162 ad_read(sc, reg) 163 struct ad1848_softc *sc; 164 int reg; 165 { 166 int x, s; 167 168 s = splaudio(); 169 ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit); 170 x = ADREAD(sc, AD1848_IDATA); 171 splx(s); 172 /* printf("(%02x<-%02x) ", reg|sc->MCE_bit, x); */ 173 174 return x; 175 } 176 177 static void 178 ad_write(sc, reg, data) 179 struct ad1848_softc *sc; 180 int reg; 181 int data; 182 { 183 int s = splaudio(); 184 ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit); 185 ADWRITE(sc, AD1848_IDATA, data & 0xff); 186 splx(s); 187 /* printf("(%02x->%02x) ", reg|sc->MCE_bit, data); */ 188 } 189 190 static void 191 ad_set_MCE(sc, state) 192 struct ad1848_softc *sc; 193 int state; 194 { 195 if (state) 196 sc->MCE_bit = MODE_CHANGE_ENABLE; 197 else 198 sc->MCE_bit = 0; 199 200 ADWRITE(sc, AD1848_IADDR, sc->MCE_bit); 201 } 202 203 static void 204 wait_for_calibration(sc) 205 struct ad1848_softc *sc; 206 { 207 int timeout; 208 209 DPRINTF(("ad1848: Auto calibration started.\n")); 210 /* 211 * Wait until the auto calibration process has finished. 212 * 213 * 1) Wait until the chip becomes ready (reads don't return 0x80). 214 * 2) Wait until the ACI bit of I11 gets on and then off. 215 */ 216 timeout = 100000; 217 while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 218 timeout--; 219 220 if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 221 DPRINTF(("ad1848: Auto calibration timed out(1).\n")); 222 223 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 224 timeout = 100000; 225 while (timeout > 0 && ADREAD(sc, AD1848_IADDR) != SP_TEST_AND_INIT) 226 timeout--; 227 228 if (ADREAD(sc, AD1848_IADDR) == SP_TEST_AND_INIT) 229 DPRINTF(("ad1848: Auto calibration timed out(1.5).\n")); 230 231 if (!(ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG)) { 232 timeout = 100000; 233 while (timeout > 0 && !(ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG)) 234 timeout--; 235 236 if (!(ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG)) 237 DPRINTF(("ad1848: Auto calibration timed out(2).\n")); 238 } 239 240 timeout = 100000; 241 while (timeout > 0 && ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG) 242 timeout--; 243 if (ad_read(sc, SP_TEST_AND_INIT) & AUTO_CAL_IN_PROG) 244 DPRINTF(("ad1848: Auto calibration timed out(3).\n")); 245 } 246 247 #ifdef AUDIO_DEBUG 248 void ad1848_dump_regs __P((struct ad1848_softc *)); 249 250 void 251 ad1848_dump_regs(sc) 252 struct ad1848_softc *sc; 253 { 254 int i; 255 u_char r; 256 257 printf("ad1848 status=%02x", ADREAD(sc, AD1848_STATUS)); 258 printf(" regs: "); 259 for (i = 0; i < 16; i++) { 260 r = ad_read(sc, i); 261 printf("%02x ", r); 262 } 263 if (sc->mode == 2) { 264 for (i = 16; i < 32; i++) { 265 r = ad_read(sc, i); 266 printf("%02x ", r); 267 } 268 } 269 printf("\n"); 270 } 271 #endif 272 273 /* 274 * Map and probe for the ad1848 chip 275 */ 276 int 277 ad1848_mapprobe(sc, iobase) 278 struct ad1848_softc *sc; 279 int iobase; 280 { 281 if (!AD1848_BASE_VALID(iobase)) { 282 #ifdef AUDIO_DEBUG 283 printf("ad1848: configured iobase %04x invalid\n", iobase); 284 #endif 285 return 0; 286 } 287 288 sc->sc_iooffs = 0; 289 /* Map the AD1848 ports */ 290 if (bus_space_map(sc->sc_iot, iobase, AD1848_NPORT, 0, &sc->sc_ioh)) 291 return 0; 292 293 if (!ad1848_probe(sc)) { 294 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 295 return 0; 296 } else 297 return 1; 298 } 299 300 /* 301 * Probe for the ad1848 chip 302 */ 303 int 304 ad1848_probe(sc) 305 struct ad1848_softc *sc; 306 { 307 u_char tmp, tmp1 = 0xff, tmp2 = 0xff; 308 #if 0 309 int i; 310 #endif 311 312 /* Is there an ad1848 chip ? */ 313 sc->MCE_bit = MODE_CHANGE_ENABLE; 314 sc->mode = 1; /* MODE 1 = original ad1848/ad1846/cs4248 */ 315 316 /* 317 * Check that the I/O address is in use. 318 * 319 * The SP_IN_INIT bit of the base I/O port is known to be 0 after the 320 * chip has performed its power-on initialization. Just assume 321 * this has happened before the OS is starting. 322 * 323 * If the I/O address is unused, inb() typically returns 0xff. 324 */ 325 tmp = ADREAD(sc, AD1848_IADDR); 326 if (tmp & SP_IN_INIT) { /* Not a AD1848 */ 327 #if 0 328 DPRINTF(("ad_detect_A %x\n", tmp)); 329 #endif 330 goto bad; 331 } 332 333 /* 334 * Test if it's possible to change contents of the indirect registers. 335 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only 336 * so try to avoid using it. 337 */ 338 ad_write(sc, 0, 0xaa); 339 ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ 340 341 if ((tmp1 = ad_read(sc, 0)) != 0xaa || 342 (tmp2 = ad_read(sc, 1)) != 0x45) { 343 DPRINTF(("ad_detect_B (%x/%x)\n", tmp1, tmp2)); 344 goto bad; 345 } 346 347 ad_write(sc, 0, 0x45); 348 ad_write(sc, 1, 0xaa); 349 350 if ((tmp1 = ad_read(sc, 0)) != 0x45 || 351 (tmp2 = ad_read(sc, 1)) != 0xaa) { 352 DPRINTF(("ad_detect_C (%x/%x)\n", tmp1, tmp2)); 353 goto bad; 354 } 355 356 /* 357 * The indirect register I12 has some read only bits. Lets 358 * try to change them. 359 */ 360 tmp = ad_read(sc, SP_MISC_INFO); 361 ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); 362 363 if ((tmp & 0x0f) != ((tmp1 = ad_read(sc, SP_MISC_INFO)) & 0x0f)) { 364 DPRINTF(("ad_detect_D (%x)\n", tmp1)); 365 goto bad; 366 } 367 368 /* 369 * MSB and 4 LSBs of the reg I12 tell the chip revision. 370 * 371 * A preliminary version of the AD1846 data sheet stated that it 372 * used an ID field of 0x0B. The current version, however, 373 * states that the AD1846 uses ID 0x0A, just like the AD1848K. 374 * 375 * this switch statement will need updating as newer clones arrive.... 376 */ 377 switch (tmp1 & 0x8f) { 378 case 0x09: 379 sc->chip_name = "AD1848J"; 380 break; 381 case 0x0A: 382 sc->chip_name = "AD1848K"; 383 break; 384 #if 0 /* See above */ 385 case 0x0B: 386 sc->chip_name = "AD1846"; 387 break; 388 #endif 389 case 0x81: 390 sc->chip_name = "CS4248revB"; /* or CS4231 rev B; see below */ 391 break; 392 case 0x89: 393 sc->chip_name = "CS4248"; 394 break; 395 case 0x8A: 396 sc->chip_name = "broken"; /* CS4231/AD1845; see below */ 397 break; 398 default: 399 sc->chip_name = "unknown"; 400 DPRINTF(("ad1848: unknown codec version %#02X\n", (tmp1 & 0x8f))); 401 } 402 403 #if 0 404 /* 405 * XXX I don't know why, but this probe fails on an otherwise well-working 406 * AW35/pro card, so I'll just take it out for now. [niklas@openbsd.org] 407 */ 408 409 /* 410 * The original AD1848/CS4248 has just 16 indirect registers. This means 411 * that I0 and I16 should return the same value (etc.). 412 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails 413 * with CS4231, AD1845, etc. 414 */ 415 ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ 416 417 for (i = 0; i < 16; i++) 418 if ((tmp1 = ad_read(sc, i)) != (tmp2 = ad_read(sc, i + 16))) { 419 if (i != SP_TEST_AND_INIT) { 420 DPRINTF(("ad_detect_F(%d/%x/%x)\n", i, tmp1, tmp2)); 421 goto bad; 422 } 423 } 424 #endif 425 426 /* 427 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 428 * The bit 0x80 is always 1 in CS4248, CS4231, and AD1845. 429 */ 430 ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ 431 432 tmp1 = ad_read(sc, SP_MISC_INFO); 433 if ((tmp1 & 0xc0) == (0x80 | MODE2)) { 434 /* 435 * CS4231 or AD1845 detected - is it? 436 * 437 * Verify that setting I2 doesn't change I18. 438 */ 439 ad_write(sc, 18, 0x88); /* Set I18 to known value */ 440 441 ad_write(sc, 2, 0x45); 442 if ((tmp2 = ad_read(sc, 18)) != 0x45) { /* No change -> CS4231? */ 443 ad_write(sc, 2, 0xaa); 444 if ((tmp2 = ad_read(sc, 18)) == 0xaa) { /* Rotten bits? */ 445 DPRINTF(("ad_detect_H(%x)\n", tmp2)); 446 goto bad; 447 } 448 449 /* 450 * It's a CS4231, or another clone with 32 registers. 451 * Let's find out which by checking I25. 452 */ 453 if ((tmp1 & 0x8f) == 0x8a) { 454 tmp1 = ad_read(sc, CS_VERSION_ID); 455 switch (tmp1 & 0xe7) { 456 case 0xA0: 457 sc->chip_name = "CS4231A"; 458 break; 459 case 0x80: 460 /* XXX I25 no good, AD1845 same as CS4231 */ 461 sc->chip_name = "CS4231 or AD1845"; 462 break; 463 case 0x82: 464 case 0xa2: 465 sc->chip_name = "CS4232"; 466 break; 467 case 0x03: 468 sc->chip_name = "CS4236/CS4236B"; 469 break; 470 } 471 } 472 sc->mode = 2; 473 } 474 } 475 476 /* Wait for 1848 to init */ 477 while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) 478 ; 479 480 /* Wait for 1848 to autocal */ 481 ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT); 482 while(ADREAD(sc, AD1848_IDATA) & AUTO_CAL_IN_PROG) 483 ; 484 485 return 1; 486 bad: 487 return 0; 488 } 489 490 /* Unmap the I/O ports */ 491 void 492 ad1848_unmap(sc) 493 struct ad1848_softc *sc; 494 { 495 bus_space_unmap(sc->sc_iot, sc->sc_ioh, AD1848_NPORT); 496 } 497 498 /* 499 * Attach hardware to driver, attach hardware driver to audio 500 * pseudo-device driver . 501 */ 502 void 503 ad1848_attach(sc) 504 struct ad1848_softc *sc; 505 { 506 int i; 507 struct ad1848_volume vol_mid = {220, 220}; 508 struct ad1848_volume vol_0 = {0, 0}; 509 struct audio_params pparams, rparams; 510 int timeout; 511 512 sc->sc_locked = 0; 513 sc->sc_playrun = NOTRUNNING; 514 sc->sc_recrun = NOTRUNNING; 515 516 if (sc->sc_drq != -1) { 517 if (isa_dmamap_create(sc->sc_isa, sc->sc_drq, MAX_ISADMA, 518 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 519 printf("ad1848_attach: can't create map for drq %d\n", 520 sc->sc_drq); 521 return; 522 } 523 } 524 if (sc->sc_recdrq != -1 && sc->sc_recdrq != sc->sc_drq) { 525 if (isa_dmamap_create(sc->sc_isa, sc->sc_recdrq, MAX_ISADMA, 526 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { 527 printf("ad1848_attach: can't creape map for drq %d\n", 528 sc->sc_recdrq); 529 return; 530 } 531 } 532 533 /* Initialize the ad1848... */ 534 for (i = 0; i < 0x10; i++) { 535 ad_write(sc, i, ad1848_init_values[i]); 536 timeout = 100000; 537 while (timeout > 0 && ad_read(sc, AD1848_IADDR) & SP_IN_INIT) 538 timeout--; 539 } 540 /* ...and additional CS4231 stuff too */ 541 if (sc->mode == 2) { 542 ad_write(sc, SP_INTERFACE_CONFIG, 0); /* disable SINGLE_DMA */ 543 for (i = 0x10; i < 0x20; i++) 544 if (ad1848_init_values[i] != 0) { 545 ad_write(sc, i, ad1848_init_values[i]); 546 timeout = 100000; 547 while (timeout > 0 && 548 ad_read(sc, AD1848_IADDR) & SP_IN_INIT) 549 timeout--; 550 } 551 } 552 ad1848_reset(sc); 553 554 pparams = audio_default; 555 rparams = audio_default; 556 (void) ad1848_set_params(sc, AUMODE_RECORD|AUMODE_PLAY, 0, &pparams, &rparams); 557 558 /* Set default gains */ 559 (void) ad1848_set_rec_gain(sc, &vol_mid); 560 (void) ad1848_set_channel_gain(sc, AD1848_DAC_CHANNEL, &vol_mid); 561 (void) ad1848_set_channel_gain(sc, AD1848_MONITOR_CHANNEL, &vol_0); 562 (void) ad1848_set_channel_gain(sc, AD1848_AUX1_CHANNEL, &vol_mid); /* CD volume */ 563 if (sc->mode == 2) { 564 (void) ad1848_set_channel_gain(sc, AD1848_AUX2_CHANNEL, &vol_mid); /* CD volume */ 565 (void) ad1848_set_channel_gain(sc, AD1848_LINE_CHANNEL, &vol_mid); 566 (void) ad1848_set_channel_gain(sc, AD1848_MONO_CHANNEL, &vol_0); 567 sc->mute[AD1848_MONO_CHANNEL] = MUTE_ALL; 568 } else 569 (void) ad1848_set_channel_gain(sc, AD1848_AUX2_CHANNEL, &vol_0); 570 571 /* Set default port */ 572 (void) ad1848_set_rec_port(sc, MIC_IN_PORT); 573 574 if (sc->chip_name) 575 printf(": %s", sc->chip_name); 576 #undef WAITREADY 577 } 578 579 /* 580 * Various routines to interface to higher level audio driver 581 */ 582 struct ad1848_mixerinfo { 583 int left_reg; 584 int right_reg; 585 int atten_bits; 586 int atten_mask; 587 } mixer_channel_info[] = 588 { { SP_LEFT_AUX2_CONTROL, SP_RIGHT_AUX2_CONTROL, AUX_INPUT_ATTEN_BITS, 589 AUX_INPUT_ATTEN_MASK }, 590 { SP_LEFT_AUX1_CONTROL, SP_RIGHT_AUX1_CONTROL, AUX_INPUT_ATTEN_BITS, 591 AUX_INPUT_ATTEN_MASK }, 592 { SP_LEFT_OUTPUT_CONTROL, SP_RIGHT_OUTPUT_CONTROL, 593 OUTPUT_ATTEN_BITS, OUTPUT_ATTEN_MASK }, 594 { CS_LEFT_LINE_CONTROL, CS_RIGHT_LINE_CONTROL, LINE_INPUT_ATTEN_BITS, 595 LINE_INPUT_ATTEN_MASK }, 596 { CS_MONO_IO_CONTROL, 0, MONO_INPUT_ATTEN_BITS, MONO_INPUT_ATTEN_MASK }, 597 { SP_DIGITAL_MIX, 0, OUTPUT_ATTEN_BITS, MIX_ATTEN_MASK } 598 }; 599 600 /* 601 * This function doesn't set the mute flags but does use them. 602 * The mute flags reflect the mutes that have been applied by the user. 603 * However, the driver occasionally wants to mute devices (e.g. when chaing 604 * sampling rate). These operations should not affect the mute flags. 605 */ 606 607 void 608 ad1848_mute_channel(sc, device, mute) 609 struct ad1848_softc *sc; 610 int device; 611 int mute; 612 { 613 u_char reg; 614 615 reg = ad_read(sc, mixer_channel_info[device].left_reg); 616 617 if (mute & MUTE_LEFT) { 618 if (device == AD1848_MONITOR_CHANNEL) 619 ad_write(sc, mixer_channel_info[device].left_reg, reg & 0xFE); 620 else 621 ad_write(sc, mixer_channel_info[device].left_reg, reg | 0x80); 622 } else if (!(sc->mute[device] & MUTE_LEFT)) { 623 if (device == AD1848_MONITOR_CHANNEL) 624 ad_write(sc, mixer_channel_info[device].left_reg, reg | 0x01); 625 else 626 ad_write(sc, mixer_channel_info[device].left_reg, reg & ~0x80); 627 } 628 629 if (!mixer_channel_info[device].right_reg) { 630 return; 631 } 632 633 reg = ad_read(sc, mixer_channel_info[device].right_reg); 634 635 if (mute & MUTE_RIGHT) 636 ad_write(sc, mixer_channel_info[device].right_reg, reg | 0x80); 637 else if (!(sc->mute[device] & MUTE_RIGHT)) { 638 ad_write(sc, mixer_channel_info[device].right_reg, reg & ~0x80); 639 } 640 } 641 642 643 int 644 ad1848_set_channel_gain(sc, device, gp) 645 struct ad1848_softc *sc; 646 int device; 647 struct ad1848_volume *gp; 648 { 649 struct ad1848_mixerinfo *info = &mixer_channel_info[device]; 650 u_char reg; 651 u_int atten; 652 653 sc->gains[device] = *gp; 654 655 atten = ((AUDIO_MAX_GAIN - gp->left) * info->atten_bits)/AUDIO_MAX_GAIN; 656 657 reg = ad_read(sc, info->left_reg) & (info->atten_mask); 658 if (device == AD1848_MONITOR_CHANNEL) 659 reg |= ((atten & info->atten_bits) << 2); 660 else 661 reg |= ((atten & info->atten_bits)); 662 663 ad_write(sc, info->left_reg, reg); 664 665 if (!info->right_reg) 666 return (0); 667 668 atten = ((AUDIO_MAX_GAIN - gp->right) * info->atten_bits)/AUDIO_MAX_GAIN; 669 reg = ad_read(sc, info->right_reg); 670 reg &= (info->atten_mask); 671 ad_write(sc, info->right_reg, (atten& info->atten_bits)|reg); 672 673 return(0); 674 } 675 676 677 int 678 ad1848_get_device_gain(sc, device, gp) 679 struct ad1848_softc *sc; 680 int device; 681 struct ad1848_volume *gp; 682 { 683 *gp = sc->gains[device]; 684 return(0); 685 } 686 687 int 688 ad1848_get_rec_gain(sc, gp) 689 struct ad1848_softc *sc; 690 struct ad1848_volume *gp; 691 { 692 *gp = sc->rec_gain; 693 return(0); 694 } 695 696 int 697 ad1848_set_rec_gain(sc, gp) 698 struct ad1848_softc *sc; 699 struct ad1848_volume *gp; 700 { 701 u_char reg, gain; 702 703 DPRINTF(("ad1848_set_rec_gain: %d:%d\n", gp->left, gp->right)); 704 705 sc->rec_gain = *gp; 706 707 gain = (gp->left * GAIN_22_5)/AUDIO_MAX_GAIN; 708 reg = ad_read(sc, SP_LEFT_INPUT_CONTROL); 709 reg &= INPUT_GAIN_MASK; 710 ad_write(sc, SP_LEFT_INPUT_CONTROL, (gain&0x0f)|reg); 711 712 gain = (gp->right * GAIN_22_5)/AUDIO_MAX_GAIN; 713 reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL); 714 reg &= INPUT_GAIN_MASK; 715 ad_write(sc, SP_RIGHT_INPUT_CONTROL, (gain&0x0f)|reg); 716 717 return(0); 718 } 719 720 721 void 722 ad1848_mute_monitor(addr, mute) 723 void *addr; 724 int mute; 725 { 726 struct ad1848_softc *sc = addr; 727 728 DPRINTF(("ad1848_mute_monitor: %smuting\n", mute ? "" : "un")); 729 if (sc->mode == 2) { 730 ad1848_mute_channel(sc, AD1848_DAC_CHANNEL, mute ? MUTE_ALL : 0); 731 ad1848_mute_channel(sc, AD1848_MONO_CHANNEL, mute ? MUTE_MONO : 0); 732 ad1848_mute_channel(sc, AD1848_LINE_CHANNEL, mute ? MUTE_ALL : 0); 733 } 734 735 ad1848_mute_channel(sc, AD1848_AUX2_CHANNEL, mute ? MUTE_ALL : 0); 736 ad1848_mute_channel(sc, AD1848_AUX1_CHANNEL, mute ? MUTE_ALL : 0); 737 } 738 739 int 740 ad1848_set_mic_gain(sc, gp) 741 struct ad1848_softc *sc; 742 struct ad1848_volume *gp; 743 { 744 u_char reg; 745 746 DPRINTF(("cs4231_set_mic_gain: %d\n", gp->left)); 747 748 if (gp->left > AUDIO_MAX_GAIN/2) { 749 sc->mic_gain_on = 1; 750 reg = ad_read(sc, SP_LEFT_INPUT_CONTROL); 751 ad_write(sc, SP_LEFT_INPUT_CONTROL, reg | INPUT_MIC_GAIN_ENABLE); 752 } else { 753 sc->mic_gain_on = 0; 754 reg = ad_read(sc, SP_LEFT_INPUT_CONTROL); 755 ad_write(sc, SP_LEFT_INPUT_CONTROL, reg & ~INPUT_MIC_GAIN_ENABLE); 756 } 757 758 return(0); 759 } 760 761 int 762 ad1848_get_mic_gain(sc, gp) 763 struct ad1848_softc *sc; 764 struct ad1848_volume *gp; 765 { 766 if (sc->mic_gain_on) 767 gp->left = gp->right = AUDIO_MAX_GAIN; 768 else 769 gp->left = gp->right = AUDIO_MIN_GAIN; 770 return(0); 771 } 772 773 774 static ad1848_devmap_t *ad1848_mixer_find_dev __P((ad1848_devmap_t *, int, mixer_ctrl_t *)); 775 776 static ad1848_devmap_t * 777 ad1848_mixer_find_dev(map, cnt, cp) 778 ad1848_devmap_t *map; 779 int cnt; 780 mixer_ctrl_t *cp; 781 782 { 783 int idx; 784 785 for (idx = 0; idx < cnt; idx++) { 786 if (map[idx].id == cp->dev) { 787 return (&map[idx]); 788 } 789 } 790 return (NULL); 791 } 792 793 int 794 ad1848_mixer_get_port(ac, map, cnt, cp) 795 struct ad1848_softc *ac; 796 struct ad1848_devmap *map; 797 int cnt; 798 mixer_ctrl_t *cp; 799 { 800 ad1848_devmap_t *entry; 801 struct ad1848_volume vol; 802 int error = EINVAL; 803 int dev; 804 805 if (!(entry = ad1848_mixer_find_dev(map, cnt, cp))) 806 return (ENXIO); 807 808 dev = entry->dev; 809 810 switch (entry->kind) { 811 case AD1848_KIND_LVL: 812 if (cp->type != AUDIO_MIXER_VALUE) 813 break; 814 815 if (dev < AD1848_AUX2_CHANNEL || 816 dev > AD1848_MONITOR_CHANNEL) 817 break; 818 819 if (cp->un.value.num_channels != 1 && 820 mixer_channel_info[dev].right_reg == 0) 821 break; 822 823 error = ad1848_get_device_gain(ac, dev, &vol); 824 if (!error) 825 ad1848_from_vol(cp, &vol); 826 827 break; 828 829 case AD1848_KIND_MUTE: 830 if (cp->type != AUDIO_MIXER_ENUM) break; 831 832 cp->un.ord = ac->mute[dev] ? 1 : 0; 833 error = 0; 834 break; 835 836 case AD1848_KIND_RECORDGAIN: 837 if (cp->type != AUDIO_MIXER_VALUE) break; 838 839 error = ad1848_get_rec_gain(ac, &vol); 840 if (!error) 841 ad1848_from_vol(cp, &vol); 842 843 break; 844 845 case AD1848_KIND_MICGAIN: 846 if (cp->type != AUDIO_MIXER_VALUE) break; 847 848 error = ad1848_get_mic_gain(ac, &vol); 849 if (!error) 850 ad1848_from_vol(cp, &vol); 851 852 break; 853 854 case AD1848_KIND_RECORDSOURCE: 855 if (cp->type != AUDIO_MIXER_ENUM) break; 856 cp->un.ord = ad1848_get_rec_port(ac); 857 error = 0; 858 break; 859 default: 860 printf ("Invalid kind\n"); 861 break; 862 } 863 864 return (error); 865 } 866 867 int 868 ad1848_mixer_set_port(ac, map, cnt, cp) 869 struct ad1848_softc *ac; 870 struct ad1848_devmap *map; 871 int cnt; 872 mixer_ctrl_t *cp; 873 { 874 ad1848_devmap_t *entry; 875 struct ad1848_volume vol; 876 int error = EINVAL; 877 int dev; 878 879 if (!(entry = ad1848_mixer_find_dev(map, cnt, cp))) 880 return (ENXIO); 881 882 dev = entry->dev; 883 884 switch (entry->kind) { 885 case AD1848_KIND_LVL: 886 if (cp->type != AUDIO_MIXER_VALUE) 887 break; 888 889 if (dev < AD1848_AUX2_CHANNEL || 890 dev > AD1848_MONITOR_CHANNEL) 891 break; 892 893 if (cp->un.value.num_channels != 1 && 894 mixer_channel_info[dev].right_reg == 0) 895 break; 896 897 ad1848_to_vol(cp, &vol); 898 error = ad1848_set_channel_gain(ac, dev, &vol); 899 break; 900 901 case AD1848_KIND_MUTE: 902 if (cp->type != AUDIO_MIXER_ENUM) break; 903 904 ac->mute[dev] = (cp->un.ord ? MUTE_ALL : 0); 905 ad1848_mute_channel(ac, dev, ac->mute[dev]); 906 error = 0; 907 break; 908 909 case AD1848_KIND_RECORDGAIN: 910 if (cp->type != AUDIO_MIXER_VALUE) break; 911 912 ad1848_to_vol(cp, &vol); 913 error = ad1848_set_rec_gain(ac, &vol); 914 break; 915 916 case AD1848_KIND_MICGAIN: 917 if (cp->type != AUDIO_MIXER_VALUE) break; 918 919 ad1848_to_vol(cp, &vol); 920 error = ad1848_set_mic_gain(ac, &vol); 921 break; 922 923 case AD1848_KIND_RECORDSOURCE: 924 if (cp->type != AUDIO_MIXER_ENUM) break; 925 926 error = ad1848_set_rec_port(ac, cp->un.ord); 927 break; 928 default: 929 printf ("Invalid kind\n"); 930 break; 931 } 932 933 return (error); 934 } 935 936 937 int 938 ad1848_query_encoding(addr, fp) 939 void *addr; 940 struct audio_encoding *fp; 941 { 942 struct ad1848_softc *sc = addr; 943 944 switch (fp->index) { 945 case 0: 946 strcpy(fp->name, AudioEmulaw); 947 fp->encoding = AUDIO_ENCODING_ULAW; 948 fp->precision = 8; 949 fp->flags = 0; 950 break; 951 case 1: 952 strcpy(fp->name, AudioEalaw); 953 fp->encoding = AUDIO_ENCODING_ALAW; 954 fp->precision = 8; 955 fp->flags = 0; 956 break; 957 case 2: 958 strcpy(fp->name, AudioEslinear_le); 959 fp->encoding = AUDIO_ENCODING_SLINEAR_LE; 960 fp->precision = 16; 961 fp->flags = 0; 962 break; 963 case 3: 964 strcpy(fp->name, AudioEulinear); 965 fp->encoding = AUDIO_ENCODING_ULINEAR; 966 fp->precision = 8; 967 fp->flags = 0; 968 break; 969 970 case 4: /* only on CS4231 */ 971 strcpy(fp->name, AudioEslinear_be); 972 fp->encoding = AUDIO_ENCODING_SLINEAR_BE; 973 fp->precision = 16; 974 fp->flags = sc->mode == 1 ? AUDIO_ENCODINGFLAG_EMULATED : 0; 975 break; 976 977 /* emulate some modes */ 978 case 5: 979 strcpy(fp->name, AudioEslinear); 980 fp->encoding = AUDIO_ENCODING_SLINEAR; 981 fp->precision = 8; 982 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 983 break; 984 case 6: 985 strcpy(fp->name, AudioEulinear_le); 986 fp->encoding = AUDIO_ENCODING_ULINEAR_LE; 987 fp->precision = 16; 988 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 989 break; 990 case 7: 991 strcpy(fp->name, AudioEulinear_be); 992 fp->encoding = AUDIO_ENCODING_ULINEAR_BE; 993 fp->precision = 16; 994 fp->flags = AUDIO_ENCODINGFLAG_EMULATED; 995 break; 996 997 case 8: /* only on CS4231 */ 998 if (sc->mode == 1) 999 return EINVAL; 1000 strcpy(fp->name, AudioEadpcm); 1001 fp->encoding = AUDIO_ENCODING_ADPCM; 1002 fp->precision = 8; 1003 fp->flags = 0; 1004 break; 1005 default: 1006 return EINVAL; 1007 /*NOTREACHED*/ 1008 } 1009 return (0); 1010 } 1011 1012 int 1013 ad1848_set_params(addr, setmode, usemode, p, r) 1014 void *addr; 1015 int setmode, usemode; 1016 struct audio_params *p, *r; 1017 { 1018 struct ad1848_softc *sc = addr; 1019 int error, bits, enc; 1020 void (*pswcode) __P((void *, u_char *buf, int cnt)); 1021 void (*rswcode) __P((void *, u_char *buf, int cnt)); 1022 1023 DPRINTF(("ad1848_set_params: %d %d %d %ld\n", 1024 p->encoding, p->precision, p->channels, p->sample_rate)); 1025 1026 enc = p->encoding; 1027 pswcode = rswcode = 0; 1028 switch (enc) { 1029 case AUDIO_ENCODING_SLINEAR_LE: 1030 if (p->precision == 8) { 1031 enc = AUDIO_ENCODING_ULINEAR_LE; 1032 pswcode = rswcode = change_sign8; 1033 } 1034 break; 1035 case AUDIO_ENCODING_SLINEAR_BE: 1036 if (p->precision == 16 && sc->mode == 1) { 1037 enc = AUDIO_ENCODING_SLINEAR_LE; 1038 pswcode = rswcode = swap_bytes; 1039 } 1040 break; 1041 case AUDIO_ENCODING_ULINEAR_LE: 1042 if (p->precision == 16) { 1043 enc = AUDIO_ENCODING_SLINEAR_LE; 1044 pswcode = rswcode = change_sign16; 1045 } 1046 break; 1047 case AUDIO_ENCODING_ULINEAR_BE: 1048 if (p->precision == 16) { 1049 enc = AUDIO_ENCODING_SLINEAR_LE; 1050 pswcode = swap_bytes_change_sign16; 1051 rswcode = change_sign16_swap_bytes; 1052 } 1053 break; 1054 } 1055 switch (enc) { 1056 case AUDIO_ENCODING_ULAW: 1057 bits = FMT_ULAW >> 5; 1058 break; 1059 case AUDIO_ENCODING_ALAW: 1060 bits = FMT_ALAW >> 5; 1061 break; 1062 case AUDIO_ENCODING_ADPCM: 1063 bits = FMT_ADPCM >> 5; 1064 break; 1065 case AUDIO_ENCODING_SLINEAR_LE: 1066 if (p->precision == 16) 1067 bits = FMT_TWOS_COMP >> 5; 1068 else 1069 return EINVAL; 1070 break; 1071 case AUDIO_ENCODING_SLINEAR_BE: 1072 if (p->precision == 16) 1073 bits = FMT_TWOS_COMP_BE >> 5; 1074 else 1075 return EINVAL; 1076 break; 1077 case AUDIO_ENCODING_ULINEAR_LE: 1078 if (p->precision == 8) 1079 bits = FMT_PCM8 >> 5; 1080 else 1081 return EINVAL; 1082 break; 1083 default: 1084 return EINVAL; 1085 } 1086 1087 if (p->channels < 1 || p->channels > 2) 1088 return EINVAL; 1089 1090 error = ad1848_set_speed(sc, &p->sample_rate); 1091 if (error) 1092 return error; 1093 1094 p->sw_code = pswcode; 1095 r->sw_code = rswcode; 1096 1097 sc->format_bits = bits; 1098 sc->channels = p->channels; 1099 sc->precision = p->precision; 1100 sc->need_commit = 1; 1101 1102 DPRINTF(("ad1848_set_params succeeded, bits=%x\n", bits)); 1103 return (0); 1104 } 1105 1106 int 1107 ad1848_set_rec_port(sc, port) 1108 struct ad1848_softc *sc; 1109 int port; 1110 { 1111 u_char inp, reg; 1112 1113 DPRINTF(("ad1848_set_rec_port: 0x%x\n", port)); 1114 1115 if (port == MIC_IN_PORT) { 1116 inp = MIC_INPUT; 1117 } 1118 else if (port == LINE_IN_PORT) { 1119 inp = LINE_INPUT; 1120 } 1121 else if (port == DAC_IN_PORT) { 1122 inp = MIXED_DAC_INPUT; 1123 } 1124 else if (sc->mode == 2 && port == AUX1_IN_PORT) { 1125 inp = AUX_INPUT; 1126 } 1127 else 1128 return(EINVAL); 1129 1130 reg = ad_read(sc, SP_LEFT_INPUT_CONTROL); 1131 reg &= INPUT_SOURCE_MASK; 1132 ad_write(sc, SP_LEFT_INPUT_CONTROL, (inp|reg)); 1133 1134 reg = ad_read(sc, SP_RIGHT_INPUT_CONTROL); 1135 reg &= INPUT_SOURCE_MASK; 1136 ad_write(sc, SP_RIGHT_INPUT_CONTROL, (inp|reg)); 1137 1138 sc->rec_port = port; 1139 1140 return(0); 1141 } 1142 1143 int 1144 ad1848_get_rec_port(sc) 1145 struct ad1848_softc *sc; 1146 { 1147 return(sc->rec_port); 1148 } 1149 1150 int 1151 ad1848_round_blocksize(addr, blk) 1152 void *addr; 1153 int blk; 1154 { 1155 struct ad1848_softc *sc = addr; 1156 1157 sc->sc_lastcc = -1; 1158 1159 /* Round to a multiple of the biggest sample size. */ 1160 blk &= -4; 1161 1162 return (blk); 1163 } 1164 1165 int 1166 ad1848_open(addr, flags) 1167 void *addr; 1168 int flags; 1169 { 1170 struct ad1848_softc *sc = addr; 1171 1172 DPRINTF(("ad1848_open: sc=%p\n", sc)); 1173 1174 sc->sc_intr = 0; 1175 sc->sc_lastcc = -1; 1176 sc->sc_locked = 0; 1177 1178 /* Enable interrupts */ 1179 DPRINTF(("ad1848_open: enable intrs\n")); 1180 ad_write(sc, SP_PIN_CONTROL, INTERRUPT_ENABLE|ad_read(sc, SP_PIN_CONTROL)); 1181 1182 #ifdef AUDIO_DEBUG 1183 if (ad1848debug) 1184 ad1848_dump_regs(sc); 1185 #endif 1186 1187 return 0; 1188 } 1189 1190 /* 1191 * Close function is called at splaudio(). 1192 */ 1193 void 1194 ad1848_close(addr) 1195 void *addr; 1196 { 1197 struct ad1848_softc *sc = addr; 1198 u_char r; 1199 1200 sc->sc_intr = 0; 1201 1202 DPRINTF(("ad1848_close: stop DMA\n")); 1203 if (sc->sc_playrun != NOTRUNNING) { 1204 isa_dmaabort(sc->sc_isa, sc->sc_drq); 1205 sc->sc_playrun = NOTRUNNING; 1206 } 1207 if (sc->sc_recrun != NOTRUNNING) { 1208 isa_dmaabort(sc->sc_isa, sc->sc_recdrq); 1209 sc->sc_recrun = NOTRUNNING; 1210 } 1211 ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)0); 1212 ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)0); 1213 1214 /* Disable interrupts */ 1215 DPRINTF(("ad1848_close: disable intrs\n")); 1216 ad_write(sc, SP_PIN_CONTROL, 1217 ad_read(sc, SP_PIN_CONTROL) & ~INTERRUPT_ENABLE); 1218 1219 DPRINTF(("ad1848_close: disable capture and playback\n")); 1220 r = ad_read(sc, SP_INTERFACE_CONFIG); 1221 r &= ~(CAPTURE_ENABLE|PLAYBACK_ENABLE); 1222 ad_write(sc, SP_INTERFACE_CONFIG, r); 1223 1224 #ifdef AUDIO_DEBUG 1225 if (ad1848debug) 1226 ad1848_dump_regs(sc); 1227 #endif 1228 } 1229 1230 /* 1231 * Lower-level routines 1232 */ 1233 int 1234 ad1848_commit_settings(addr) 1235 void *addr; 1236 { 1237 struct ad1848_softc *sc = addr; 1238 int timeout; 1239 u_char fs; 1240 int s; 1241 1242 if (!sc->need_commit) 1243 return 0; 1244 1245 s = splaudio(); 1246 1247 ad1848_mute_monitor(sc, 1); 1248 1249 ad_set_MCE(sc, 1); /* Enables changes to the format select reg */ 1250 1251 fs = sc->speed_bits | (sc->format_bits << 5); 1252 1253 if (sc->channels == 2) 1254 fs |= FMT_STEREO; 1255 1256 ad_write(sc, SP_CLOCK_DATA_FORMAT, fs); 1257 1258 /* 1259 * If mode == 2 (CS4231), set I28 also. It's the capture format register. 1260 */ 1261 if (sc->mode == 2) { 1262 /* Gravis Ultrasound MAX SDK sources says something about errata 1263 * sheets, with the implication that these inb()s are necessary. 1264 */ 1265 (void)ADREAD(sc, AD1848_IDATA); 1266 (void)ADREAD(sc, AD1848_IDATA); 1267 /* 1268 * Write to I8 starts resyncronization. Wait until it completes. 1269 */ 1270 timeout = 100000; 1271 while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 1272 timeout--; 1273 1274 ad_write(sc, CS_REC_FORMAT, fs); 1275 /* Gravis Ultrasound MAX SDK sources says something about errata 1276 * sheets, with the implication that these inb()s are necessary. 1277 */ 1278 (void)ADREAD(sc, AD1848_IDATA); 1279 (void)ADREAD(sc, AD1848_IDATA); 1280 /* Now wait for resync for capture side of the house */ 1281 } 1282 /* 1283 * Write to I8 starts resyncronization. Wait until it completes. 1284 */ 1285 timeout = 100000; 1286 while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 1287 timeout--; 1288 1289 if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT) 1290 printf("ad1848_commit: Auto calibration timed out\n"); 1291 1292 /* 1293 * Starts the calibration process and 1294 * enters playback mode after it. 1295 */ 1296 ad_set_MCE(sc, 0); 1297 wait_for_calibration(sc); 1298 1299 ad1848_mute_monitor(sc, 0); 1300 1301 sc->sc_lastcc = -1; 1302 1303 splx(s); 1304 1305 sc->need_commit = 0; 1306 return 0; 1307 } 1308 1309 void 1310 ad1848_reset(sc) 1311 struct ad1848_softc *sc; 1312 { 1313 u_char r; 1314 1315 DPRINTF(("ad1848_reset\n")); 1316 1317 /* Clear the PEN and CEN bits */ 1318 r = ad_read(sc, SP_INTERFACE_CONFIG); 1319 r &= ~(CAPTURE_ENABLE|PLAYBACK_ENABLE); 1320 ad_write(sc, SP_INTERFACE_CONFIG, r); 1321 1322 if (sc->mode == 2) { 1323 ADWRITE(sc, AD1848_IADDR, CS_IRQ_STATUS); 1324 ADWRITE(sc, AD1848_IDATA, 0); 1325 } 1326 /* Clear interrupt status */ 1327 ADWRITE(sc, AD1848_STATUS, 0); 1328 #ifdef AUDIO_DEBUG 1329 if (ad1848debug) 1330 ad1848_dump_regs(sc); 1331 #endif 1332 } 1333 1334 int 1335 ad1848_set_speed(sc, argp) 1336 struct ad1848_softc *sc; 1337 u_long *argp; 1338 { 1339 /* 1340 * The sampling speed is encoded in the least significant nible of I8. The 1341 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other 1342 * three bits select the divisor (indirectly): 1343 * 1344 * The available speeds are in the following table. Keep the speeds in 1345 * the increasing order. 1346 */ 1347 typedef struct { 1348 int speed; 1349 u_char bits; 1350 } speed_struct; 1351 u_long arg = *argp; 1352 1353 static speed_struct speed_table[] = { 1354 {5510, (0 << 1) | 1}, 1355 {5510, (0 << 1) | 1}, 1356 {6620, (7 << 1) | 1}, 1357 {8000, (0 << 1) | 0}, 1358 {9600, (7 << 1) | 0}, 1359 {11025, (1 << 1) | 1}, 1360 {16000, (1 << 1) | 0}, 1361 {18900, (2 << 1) | 1}, 1362 {22050, (3 << 1) | 1}, 1363 {27420, (2 << 1) | 0}, 1364 {32000, (3 << 1) | 0}, 1365 {33075, (6 << 1) | 1}, 1366 {37800, (4 << 1) | 1}, 1367 {44100, (5 << 1) | 1}, 1368 {48000, (6 << 1) | 0} 1369 }; 1370 1371 int i, n, selected = -1; 1372 1373 n = sizeof(speed_table) / sizeof(speed_struct); 1374 1375 if (arg < speed_table[0].speed) 1376 selected = 0; 1377 if (arg > speed_table[n - 1].speed) 1378 selected = n - 1; 1379 1380 for (i = 1 /*really*/ ; selected == -1 && i < n; i++) 1381 if (speed_table[i].speed == arg) 1382 selected = i; 1383 else if (speed_table[i].speed > arg) { 1384 int diff1, diff2; 1385 1386 diff1 = arg - speed_table[i - 1].speed; 1387 diff2 = speed_table[i].speed - arg; 1388 1389 if (diff1 < diff2) 1390 selected = i - 1; 1391 else 1392 selected = i; 1393 } 1394 1395 if (selected == -1) { 1396 printf("ad1848: Can't find speed???\n"); 1397 selected = 3; 1398 } 1399 1400 sc->speed_bits = speed_table[selected].bits; 1401 sc->need_commit = 1; 1402 *argp = speed_table[selected].speed; 1403 1404 return (0); 1405 } 1406 1407 /* 1408 * Halt a DMA in progress. 1409 */ 1410 int 1411 ad1848_halt_out_dma(addr) 1412 void *addr; 1413 { 1414 struct ad1848_softc *sc = addr; 1415 u_char reg; 1416 1417 DPRINTF(("ad1848: ad1848_halt_out_dma\n")); 1418 1419 reg = ad_read(sc, SP_INTERFACE_CONFIG); 1420 ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~PLAYBACK_ENABLE)); 1421 sc->sc_locked = 0; 1422 1423 return(0); 1424 } 1425 1426 int 1427 ad1848_halt_in_dma(addr) 1428 void *addr; 1429 { 1430 struct ad1848_softc *sc = addr; 1431 u_char reg; 1432 1433 DPRINTF(("ad1848: ad1848_halt_in_dma\n")); 1434 1435 reg = ad_read(sc, SP_INTERFACE_CONFIG); 1436 ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~CAPTURE_ENABLE)); 1437 sc->sc_locked = 0; 1438 1439 return(0); 1440 } 1441 1442 int 1443 ad1848_dma_init_input(addr, buf, cc) 1444 void *addr; 1445 void *buf; 1446 int cc; 1447 { 1448 struct ad1848_softc *sc = addr; 1449 1450 sc->sc_recrun = DMARUNNING; 1451 sc->sc_dma_flags = DMAMODE_READ | DMAMODE_LOOP; 1452 sc->sc_dma_bp = buf; 1453 sc->sc_dma_cnt = cc; 1454 isa_dmastart(sc->sc_isa, sc->sc_recdrq, buf, cc, NULL, 1455 sc->sc_dma_flags, BUS_DMA_NOWAIT); 1456 DPRINTF(("ad1848_dma_init_input: %p %d\n", buf, cc)); 1457 return 0; 1458 } 1459 1460 /* 1461 * DMA input/output are called at splaudio(). 1462 */ 1463 int 1464 ad1848_dma_input(addr, p, cc, intr, arg) 1465 void *addr; 1466 void *p; 1467 int cc; 1468 void (*intr) __P((void *)); 1469 void *arg; 1470 { 1471 struct ad1848_softc *sc = addr; 1472 u_char reg; 1473 1474 if (sc->sc_locked) { 1475 DPRINTF(("ad1848_dma_input: locked\n")); 1476 return 0; 1477 } 1478 1479 #ifdef AUDIO_DEBUG 1480 if (ad1848debug > 1) 1481 printf("ad1848_dma_input: cc=%d %p (%p)\n", cc, intr, arg); 1482 #endif 1483 sc->sc_locked = 1; 1484 sc->sc_intr = intr; 1485 sc->sc_arg = arg; 1486 1487 switch (sc->sc_recrun) { 1488 case NOTRUNNING: 1489 sc->sc_dma_flags = DMAMODE_READ; 1490 sc->sc_dma_bp = p; 1491 sc->sc_dma_cnt = cc; 1492 isa_dmastart(sc->sc_isa, sc->sc_recdrq, p, cc, NULL, 1493 DMAMODE_READ, BUS_DMA_NOWAIT); 1494 goto startpcm; 1495 case DMARUNNING: 1496 sc->sc_recrun = PCMRUNNING; 1497 startpcm: 1498 if (sc->precision == 16) 1499 cc >>= 1; 1500 if (sc->channels == 2) 1501 cc >>= 1; 1502 cc--; 1503 1504 if (sc->sc_lastcc != cc || sc->sc_mode != AUMODE_RECORD) { 1505 ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)(cc & 0xff)); 1506 ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)((cc >> 8) & 0xff)); 1507 1508 if (sc->mode == 2) { 1509 ad_write(sc, CS_LOWER_REC_CNT, (u_char)(cc & 0xff)); 1510 ad_write(sc, CS_UPPER_REC_CNT, (u_char)((cc >> 8) & 0xff)); 1511 } 1512 1513 reg = ad_read(sc, SP_INTERFACE_CONFIG); 1514 ad_write(sc, SP_INTERFACE_CONFIG, (CAPTURE_ENABLE|reg)); 1515 1516 sc->sc_lastcc = cc; 1517 sc->sc_mode = AUMODE_RECORD; 1518 #ifdef AUDIO_DEBUG 1519 if (ad1848debug > 1) 1520 printf("ad1848_dma_input: started capture\n"); 1521 #endif 1522 } 1523 case PCMRUNNING: 1524 break; 1525 } 1526 1527 return 0; 1528 } 1529 1530 int 1531 ad1848_dma_init_output(addr, buf, cc) 1532 void *addr; 1533 void *buf; 1534 int cc; 1535 { 1536 struct ad1848_softc *sc = addr; 1537 1538 sc->sc_playrun = DMARUNNING; 1539 sc->sc_dma_flags = DMAMODE_WRITE | DMAMODE_LOOP; 1540 sc->sc_dma_bp = buf; 1541 sc->sc_dma_cnt = cc; 1542 isa_dmastart(sc->sc_isa, sc->sc_drq, buf, cc, NULL, 1543 sc->sc_dma_flags, BUS_DMA_NOWAIT); 1544 DPRINTF(("ad1848_dma_init_output: %p %d\n", buf, cc)); 1545 return 0; 1546 } 1547 1548 int 1549 ad1848_dma_output(addr, p, cc, intr, arg) 1550 void *addr; 1551 void *p; 1552 int cc; 1553 void (*intr) __P((void *)); 1554 void *arg; 1555 { 1556 struct ad1848_softc *sc = addr; 1557 u_char reg; 1558 1559 if (sc->sc_locked) { 1560 DPRINTF(("ad1848_dma_output: locked\n")); 1561 return 0; 1562 } 1563 1564 #ifdef AUDIO_DEBUG 1565 if (ad1848debug > 0) 1566 printf("ad1848_dma_output: cc=%d at %p 0x%p (0x%p)\n", cc, p, intr, arg); 1567 #endif 1568 sc->sc_locked = 1; 1569 sc->sc_intr = intr; 1570 sc->sc_arg = arg; 1571 1572 switch (sc->sc_playrun) { 1573 case NOTRUNNING: 1574 sc->sc_dma_flags = DMAMODE_WRITE; 1575 sc->sc_dma_bp = p; 1576 sc->sc_dma_cnt = cc; 1577 isa_dmastart(sc->sc_isa, sc->sc_drq, p, cc, NULL, 1578 DMAMODE_WRITE, BUS_DMA_NOWAIT); 1579 goto startpcm; 1580 case DMARUNNING: 1581 sc->sc_playrun = PCMRUNNING; 1582 startpcm: 1583 if (sc->precision == 16) 1584 cc >>= 1; 1585 if (sc->channels == 2) 1586 cc >>= 1; 1587 cc--; 1588 1589 if (sc->sc_lastcc != cc || sc->sc_mode != AUMODE_PLAY) { 1590 ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)(cc & 0xff)); 1591 ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)((cc >> 8) & 0xff)); 1592 1593 reg = ad_read(sc, SP_INTERFACE_CONFIG); 1594 ad_write(sc, SP_INTERFACE_CONFIG, (PLAYBACK_ENABLE|reg)); 1595 1596 sc->sc_lastcc = cc; 1597 sc->sc_mode = AUMODE_PLAY; 1598 } 1599 break; 1600 case PCMRUNNING: 1601 break; 1602 } 1603 1604 return 0; 1605 } 1606 1607 int 1608 ad1848_intr(arg) 1609 void *arg; 1610 { 1611 struct ad1848_softc *sc = arg; 1612 int retval = 0; 1613 u_char status; 1614 1615 /* Get intr status */ 1616 status = ADREAD(sc, AD1848_STATUS); 1617 1618 #ifdef AUDIO_DEBUG 1619 if (ad1848debug > 1) 1620 printf("ad1848_intr: intr=%p status=%x\n", sc->sc_intr, status); 1621 #endif 1622 sc->sc_locked = 0; 1623 sc->sc_interrupts++; 1624 1625 /* Handle interrupt */ 1626 if (sc->sc_intr && (status & INTERRUPT_STATUS)) { 1627 /* ACK DMA read because it may be in a bounce buffer */ 1628 /* XXX Do write to mask DMA ? */ 1629 if ((sc->sc_dma_flags & DMAMODE_READ) && sc->sc_recrun == NOTRUNNING) 1630 isa_dmadone(sc->sc_isa, sc->sc_recdrq); 1631 (*sc->sc_intr)(sc->sc_arg); 1632 retval = 1; 1633 } 1634 1635 /* clear interrupt */ 1636 if (status & INTERRUPT_STATUS) 1637 ADWRITE(sc, AD1848_STATUS, 0); 1638 1639 return(retval); 1640 } 1641 1642 void * 1643 ad1848_malloc(addr, size, pool, flags) 1644 void *addr; 1645 unsigned long size; 1646 int pool; 1647 int flags; 1648 { 1649 struct ad1848_softc *sc = addr; 1650 1651 return isa_malloc(sc->sc_isa, 1, size, pool, flags); 1652 } 1653 1654 void 1655 ad1848_free(addr, ptr, pool) 1656 void *addr; 1657 void *ptr; 1658 int pool; 1659 { 1660 isa_free(ptr, pool); 1661 } 1662 1663 unsigned long 1664 ad1848_round(addr, size) 1665 void *addr; 1666 unsigned long size; 1667 { 1668 if (size > MAX_ISADMA) 1669 size = MAX_ISADMA; 1670 return size; 1671 } 1672 1673 int 1674 ad1848_mappage(addr, mem, off, prot) 1675 void *addr; 1676 void *mem; 1677 int off; 1678 int prot; 1679 { 1680 return isa_mappage(mem, off, prot); 1681 } 1682 1683 int 1684 ad1848_get_props(addr) 1685 void *addr; 1686 { 1687 struct ad1848_softc *sc = addr; 1688 1689 return AUDIO_PROP_MMAP | 1690 (sc->sc_drq != sc->sc_recdrq ? AUDIO_PROP_FULLDUPLEX : 0); 1691 } 1692