1 /* $OpenBSD: wdc.c,v 1.131 2016/09/15 02:00:17 dlg Exp $ */ 2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */ 3 /* 4 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/conf.h> 60 #include <sys/buf.h> 61 #include <sys/device.h> 62 #include <sys/malloc.h> 63 #include <sys/syslog.h> 64 #include <sys/disk.h> 65 #include <sys/pool.h> 66 67 #include <machine/intr.h> 68 #include <machine/bus.h> 69 70 #include <dev/ata/atavar.h> 71 #include <dev/ata/atareg.h> 72 #include <dev/ic/wdcreg.h> 73 #include <dev/ic/wdcvar.h> 74 #include <dev/ic/wdcevent.h> 75 76 #include <scsi/scsi_all.h> 77 #include <scsi/scsiconf.h> 78 79 #define WDCDELAY 100 /* 100 microseconds */ 80 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 81 #if 0 82 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 83 #define WDCNDELAY_DEBUG 50 84 #endif /* 0 */ 85 86 struct pool wdc_xfer_pool; 87 struct scsi_iopool wdc_xfer_iopool; 88 89 void * wdc_xfer_get(void *); 90 void wdc_xfer_put(void *, void *); 91 92 void __wdcerror(struct channel_softc *, char *); 93 int __wdcwait_reset(struct channel_softc *, int); 94 void __wdccommand_done(struct channel_softc *, struct wdc_xfer *); 95 void __wdccommand_start(struct channel_softc *, struct wdc_xfer *); 96 int __wdccommand_intr(struct channel_softc *, struct wdc_xfer *, int); 97 int wdprint(void *, const char *); 98 void wdc_kill_pending(struct channel_softc *); 99 100 #define DEBUG_INTR 0x01 101 #define DEBUG_XFERS 0x02 102 #define DEBUG_STATUS 0x04 103 #define DEBUG_FUNCS 0x08 104 #define DEBUG_PROBE 0x10 105 #define DEBUG_STATUSX 0x20 106 #define DEBUG_SDRIVE 0x40 107 #define DEBUG_DETACH 0x80 108 109 #ifdef WDCDEBUG 110 #ifndef WDCDEBUG_MASK 111 #define WDCDEBUG_MASK 0x00 112 #endif 113 int wdcdebug_mask = WDCDEBUG_MASK; 114 int wdc_nxfer = 0; 115 #define WDCDEBUG_PRINT(args, level) do { \ 116 if ((wdcdebug_mask & (level)) != 0) \ 117 printf args; \ 118 } while (0) 119 #else 120 #define WDCDEBUG_PRINT(args, level) 121 #endif /* WDCDEBUG */ 122 123 int at_poll = AT_POLL; 124 125 int wdc_floating_bus(struct channel_softc *, int); 126 int wdc_preata_drive(struct channel_softc *, int); 127 int wdc_ata_present(struct channel_softc *, int); 128 129 struct cfdriver wdc_cd = { 130 NULL, "wdc", DV_DULL 131 }; 132 133 struct channel_softc_vtbl wdc_default_vtbl = { 134 wdc_default_read_reg, 135 wdc_default_write_reg, 136 wdc_default_lba48_write_reg, 137 wdc_default_read_raw_multi_2, 138 wdc_default_write_raw_multi_2, 139 wdc_default_read_raw_multi_4, 140 wdc_default_write_raw_multi_4 141 }; 142 143 #ifdef WDCDEBUG 144 static char *wdc_log_buf = NULL; 145 static unsigned int wdc_tail = 0; 146 static unsigned int wdc_head = 0; 147 static unsigned int wdc_log_cap = 16 * 1024; 148 static int chp_idx = 1; 149 150 void 151 wdc_log(struct channel_softc *chp, enum wdcevent_type type, 152 unsigned int size, char val[]) 153 { 154 unsigned int request_size; 155 char *ptr; 156 int log_size; 157 unsigned int head = wdc_head; 158 unsigned int tail = wdc_tail; 159 160 #ifdef DIAGNOSTIC 161 if (head < 0 || head > wdc_log_cap || 162 tail < 0 || tail > wdc_log_cap) { 163 printf ("wdc_log: head %x wdc_tail %x\n", head, 164 tail); 165 return; 166 } 167 168 if (size > wdc_log_cap / 2) { 169 printf ("wdc_log: type %d size %x\n", type, size); 170 return; 171 } 172 #endif 173 174 if (wdc_log_buf == NULL) { 175 wdc_log_buf = malloc(wdc_log_cap, M_DEVBUF, M_NOWAIT); 176 if (wdc_log_buf == NULL) 177 return; 178 } 179 if (chp->ch_log_idx == 0) 180 chp->ch_log_idx = chp_idx++; 181 182 request_size = size + 2; 183 184 /* Check how many bytes are left */ 185 log_size = head - tail; 186 if (log_size < 0) log_size += wdc_log_cap; 187 188 if (log_size + request_size >= wdc_log_cap) { 189 int nb = 0; 190 int rec_size; 191 192 while (nb <= (request_size * 2)) { 193 if (wdc_log_buf[tail] == 0) 194 rec_size = 1; 195 else 196 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2; 197 tail = (tail + rec_size) % wdc_log_cap; 198 nb += rec_size; 199 } 200 } 201 202 /* Avoid wrapping in the middle of a request */ 203 if (head + request_size >= wdc_log_cap) { 204 memset(&wdc_log_buf[head], 0, wdc_log_cap - head); 205 head = 0; 206 } 207 208 ptr = &wdc_log_buf[head]; 209 *ptr++ = type & 0xff; 210 *ptr++ = ((chp->ch_log_idx & 0x7) << 5) | (size & 0x1f); 211 memcpy(ptr, val, size); 212 213 wdc_head = (head + request_size) % wdc_log_cap; 214 wdc_tail = tail; 215 } 216 217 char *wdc_get_log(unsigned int *, unsigned int *); 218 219 char * 220 wdc_get_log(unsigned int * size, unsigned int *left) 221 { 222 int log_size; 223 char *retbuf = NULL; 224 int nb, tocopy; 225 int s; 226 unsigned int head = wdc_head; 227 unsigned int tail = wdc_tail; 228 229 s = splbio(); 230 231 log_size = (head - tail); 232 if (left != NULL) 233 *left = 0; 234 235 if (log_size < 0) 236 log_size += wdc_log_cap; 237 238 tocopy = log_size; 239 if ((u_int)tocopy > *size) 240 tocopy = *size; 241 242 if (wdc_log_buf == NULL) { 243 *size = 0; 244 *left = 0; 245 goto out; 246 } 247 248 #ifdef DIAGNOSTIC 249 if (head < 0 || head > wdc_log_cap || 250 tail < 0 || tail > wdc_log_cap) { 251 printf ("wdc_log: head %x tail %x\n", head, 252 tail); 253 *size = 0; 254 *left = 0; 255 goto out; 256 } 257 #endif 258 259 retbuf = malloc(tocopy, M_TEMP, M_NOWAIT); 260 if (retbuf == NULL) { 261 *size = 0; 262 *left = log_size; 263 goto out; 264 } 265 266 nb = 0; 267 for (;;) { 268 int rec_size; 269 270 if (wdc_log_buf[tail] == 0) 271 rec_size = 1; 272 else 273 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2; 274 275 if ((nb + rec_size) >= tocopy) 276 break; 277 278 memcpy(&retbuf[nb], &wdc_log_buf[tail], rec_size); 279 tail = (tail + rec_size) % wdc_log_cap; 280 nb += rec_size; 281 } 282 283 wdc_tail = tail; 284 *size = nb; 285 *left = log_size - nb; 286 287 out: 288 splx(s); 289 return (retbuf); 290 } 291 #endif /* WDCDEBUG */ 292 293 u_int8_t 294 wdc_default_read_reg(struct channel_softc *chp, enum wdc_regs reg) 295 { 296 #ifdef DIAGNOSTIC 297 if (reg & _WDC_WRONLY) { 298 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg); 299 } 300 #endif /* DIAGNOSTIC */ 301 302 if (reg & _WDC_AUX) 303 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh, 304 reg & _WDC_REGMASK)); 305 else 306 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 307 reg & _WDC_REGMASK)); 308 } 309 310 void 311 wdc_default_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) 312 { 313 #ifdef DIAGNOSTIC 314 if (reg & _WDC_RDONLY) { 315 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg); 316 } 317 #endif /* DIAGNOSTIC */ 318 319 if (reg & _WDC_AUX) 320 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, 321 reg & _WDC_REGMASK, val); 322 else 323 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 324 reg & _WDC_REGMASK, val); 325 } 326 327 void 328 wdc_default_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, 329 u_int16_t val) 330 { 331 /* All registers are two byte deep FIFOs. */ 332 CHP_WRITE_REG(chp, reg, val >> 8); 333 CHP_WRITE_REG(chp, reg, val); 334 } 335 336 void 337 wdc_default_read_raw_multi_2(struct channel_softc *chp, void *data, 338 unsigned int nbytes) 339 { 340 if (data == NULL) { 341 unsigned int i; 342 343 for (i = 0; i < nbytes; i += 2) { 344 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0); 345 } 346 347 return; 348 } 349 350 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 351 data, nbytes); 352 } 353 354 355 void 356 wdc_default_write_raw_multi_2(struct channel_softc *chp, void *data, 357 unsigned int nbytes) 358 { 359 if (data == NULL) { 360 unsigned int i; 361 362 for (i = 0; i < nbytes; i += 2) { 363 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0); 364 } 365 366 return; 367 } 368 369 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0, 370 data, nbytes); 371 } 372 373 374 void 375 wdc_default_write_raw_multi_4(struct channel_softc *chp, void *data, 376 unsigned int nbytes) 377 { 378 if (data == NULL) { 379 unsigned int i; 380 381 for (i = 0; i < nbytes; i += 4) { 382 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0); 383 } 384 385 return; 386 } 387 388 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 389 data, nbytes); 390 } 391 392 393 void 394 wdc_default_read_raw_multi_4(struct channel_softc *chp, void *data, 395 unsigned int nbytes) 396 { 397 if (data == NULL) { 398 unsigned int i; 399 400 for (i = 0; i < nbytes; i += 4) { 401 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0); 402 } 403 404 return; 405 } 406 407 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0, 408 data, nbytes); 409 } 410 411 int 412 wdprint(void *aux, const char *pnp) 413 { 414 struct ata_atapi_attach *aa_link = aux; 415 if (pnp) 416 printf("drive at %s", pnp); 417 printf(" channel %d drive %d", aa_link->aa_channel, 418 aa_link->aa_drv_data->drive); 419 return (UNCONF); 420 } 421 422 void 423 wdc_disable_intr(struct channel_softc *chp) 424 { 425 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS); 426 } 427 428 void 429 wdc_enable_intr(struct channel_softc *chp) 430 { 431 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 432 } 433 434 void 435 wdc_set_drive(struct channel_softc *chp, int drive) 436 { 437 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_IBM); 438 WDC_LOG_SET_DRIVE(chp, drive); 439 } 440 441 int 442 wdc_floating_bus(struct channel_softc *chp, int drive) 443 { 444 u_int8_t cumulative_status, status; 445 int iter; 446 447 wdc_set_drive(chp, drive); 448 delay(10); 449 450 /* Stolen from Phoenix BIOS Drive Autotyping document */ 451 cumulative_status = 0; 452 for (iter = 0; iter < 100; iter++) { 453 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f); 454 delay (1); 455 456 status = CHP_READ_REG(chp, wdr_status); 457 458 /* The other bits are meaningless if BSY is set */ 459 if (status & WDCS_BSY) 460 continue; 461 462 cumulative_status |= status; 463 464 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR) 465 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO) 466 return 1; 467 } 468 469 470 return 0; 471 } 472 473 int 474 wdc_preata_drive(struct channel_softc *chp, int drive) 475 { 476 if (wdc_floating_bus(chp, drive)) { 477 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n", 478 chp->wdc->sc_dev.dv_xname, 479 chp->channel, drive), DEBUG_PROBE); 480 return 0; 481 } 482 483 wdc_set_drive(chp, drive); 484 delay(100); 485 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 486 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 487 chp->wdc->sc_dev.dv_xname, 488 chp->channel, drive), DEBUG_PROBE); 489 return 0; 490 } 491 492 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL); 493 WDC_LOG_ATA_CMDSHORT(chp, WDCC_RECAL); 494 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) { 495 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 496 chp->wdc->sc_dev.dv_xname, 497 chp->channel, drive), DEBUG_PROBE); 498 return 0; 499 } 500 501 return 1; 502 } 503 504 int 505 wdc_ata_present(struct channel_softc *chp, int drive) 506 { 507 int time_to_done; 508 int retry_cnt = 0; 509 510 wdc_set_drive(chp, drive); 511 delay(10); 512 513 retry: 514 /* 515 You're actually supposed to wait up to 10 seconds 516 for DRDY. However, as a practical matter, most 517 drives assert DRDY very quickly after dropping BSY. 518 519 The 10 seconds wait is sub-optimal because, according 520 to the ATA standard, the master should reply with 00 521 for any reads to a non-existent slave. 522 */ 523 time_to_done = wdc_wait_for_status(chp, 524 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ), 525 (WDCS_DRDY | WDCS_DSC), 1000); 526 if (time_to_done == -1) { 527 if (retry_cnt == 0 && chp->ch_status == 0x00) { 528 /* At least one flash card needs to be kicked */ 529 wdccommandshort(chp, drive, WDCC_CHECK_PWR); 530 retry_cnt++; 531 goto retry; 532 } 533 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status" 534 " %02x\n", 535 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 536 chp->channel, drive, chp->ch_status), 537 DEBUG_PROBE); 538 return 0; 539 } 540 541 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) { 542 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with" 543 " %02x\n", 544 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 545 chp->channel, drive, chp->ch_status), 546 DEBUG_PROBE); 547 548 return 0; 549 } 550 551 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n", 552 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 553 chp->channel, drive, time_to_done), DEBUG_PROBE); 554 555 /* 556 * Test register writability 557 */ 558 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa); 559 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55); 560 CHP_WRITE_REG(chp, wdr_seccnt, 0xff); 561 DELAY(10); 562 563 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa && 564 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) { 565 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n", 566 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 567 chp->channel, drive), DEBUG_PROBE); 568 return 0; 569 } 570 571 return 1; 572 } 573 574 575 /* 576 * Test to see controller with at least one attached drive is there. 577 * Returns a bit for each possible drive found (0x01 for drive 0, 578 * 0x02 for drive 1). 579 * Logic: 580 * - If a status register is at 0x7f or 0xff, assume there is no drive here 581 * (ISA has pull-up resistors). Similarly if the status register has 582 * the value we last wrote to the bus (for IDE interfaces without pullups). 583 * If no drive at all -> return. 584 * - reset the controller, wait for it to complete (may take up to 31s !). 585 * If timeout -> return. 586 * - test ATA/ATAPI signatures. If at last one drive found -> return. 587 * - try an ATA command on the master. 588 */ 589 590 int 591 wdcprobe(struct channel_softc *chp) 592 { 593 u_int8_t st0, st1, sc, sn, cl, ch; 594 u_int8_t ret_value = 0x03; 595 u_int8_t drive; 596 #ifdef WDCDEBUG 597 int savedmask = wdcdebug_mask; 598 #endif 599 600 if (chp->_vtbl == 0) { 601 int s = splbio(); 602 chp->_vtbl = &wdc_default_vtbl; 603 splx(s); 604 } 605 606 #ifdef WDCDEBUG 607 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) || 608 (chp->wdc && 609 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE))) 610 wdcdebug_mask |= DEBUG_PROBE; 611 #endif /* WDCDEBUG */ 612 613 if (chp->wdc == NULL || 614 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 615 /* Sample the statuses of drive 0 and 1 into st0 and st1 */ 616 wdc_set_drive(chp, 0); 617 delay(10); 618 st0 = CHP_READ_REG(chp, wdr_status); 619 WDC_LOG_STATUS(chp, st0); 620 wdc_set_drive(chp, 1); 621 delay(10); 622 st1 = CHP_READ_REG(chp, wdr_status); 623 WDC_LOG_STATUS(chp, st1); 624 625 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%b, st1=0x%b\n", 626 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 627 chp->channel, st0, WDCS_BITS, st1, WDCS_BITS), 628 DEBUG_PROBE); 629 630 if (st0 == 0xff || st0 == WDSD_IBM) 631 ret_value &= ~0x01; 632 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 633 ret_value &= ~0x02; 634 if (ret_value == 0) 635 return 0; 636 } 637 638 /* reset the channel */ 639 wdc_do_reset(chp); 640 641 ret_value = __wdcwait_reset(chp, ret_value); 642 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 643 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 644 ret_value), DEBUG_PROBE); 645 646 if (ret_value == 0) 647 return 0; 648 649 /* 650 * Use signatures to find potential ATAPI drives 651 */ 652 for (drive = 0; drive < 2; drive++) { 653 if ((ret_value & (0x01 << drive)) == 0) 654 continue; 655 wdc_set_drive(chp, drive); 656 delay(10); 657 /* Save registers contents */ 658 st0 = CHP_READ_REG(chp, wdr_status); 659 sc = CHP_READ_REG(chp, wdr_seccnt); 660 sn = CHP_READ_REG(chp, wdr_sector); 661 cl = CHP_READ_REG(chp, wdr_cyl_lo); 662 ch = CHP_READ_REG(chp, wdr_cyl_hi); 663 WDC_LOG_REG(chp, wdr_cyl_lo, (ch << 8) | cl); 664 665 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%b, sc=0x%x" 666 " sn=0x%x cl=0x%x ch=0x%x\n", 667 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 668 chp->channel, drive, st0, WDCS_BITS, sc, sn, cl, ch), 669 DEBUG_PROBE); 670 /* 671 * This is a simplification of the test in the ATAPI 672 * spec since not all drives seem to set the other regs 673 * correctly. 674 */ 675 if (cl == 0x14 && ch == 0xeb) 676 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 677 } 678 679 /* 680 * Detect ATA drives by poking around the registers 681 */ 682 for (drive = 0; drive < 2; drive++) { 683 if ((ret_value & (0x01 << drive)) == 0) 684 continue; 685 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI) 686 continue; 687 688 wdc_disable_intr(chp); 689 /* ATA detect */ 690 if (wdc_ata_present(chp, drive)) { 691 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 692 if (chp->wdc == NULL || 693 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 694 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 695 } else { 696 ret_value &= ~(1 << drive); 697 } 698 wdc_enable_intr(chp); 699 } 700 701 #ifdef WDCDEBUG 702 wdcdebug_mask = savedmask; 703 #endif 704 return (ret_value); 705 } 706 707 struct channel_queue * 708 wdc_alloc_queue(void) 709 { 710 static int inited = 0; 711 struct channel_queue *queue; 712 713 /* Initialize global data. */ 714 if (inited == 0) { 715 /* Initialize the wdc_xfer pool. */ 716 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, IPL_BIO, 717 0, "wdcxfer", NULL); 718 scsi_iopool_init(&wdc_xfer_iopool, NULL, 719 wdc_xfer_get, wdc_xfer_put); 720 inited = 1; 721 } 722 723 queue = malloc(sizeof(*queue), M_DEVBUF, M_NOWAIT); 724 if (queue != NULL) { 725 TAILQ_INIT(&queue->sc_xfer); 726 } 727 return (queue); 728 } 729 730 void 731 wdc_free_queue(struct channel_queue *queue) 732 { 733 free(queue, M_DEVBUF, sizeof(*queue)); 734 } 735 736 void 737 wdcattach(struct channel_softc *chp) 738 { 739 int i; 740 struct ata_atapi_attach aa_link; 741 #ifdef WDCDEBUG 742 int savedmask = wdcdebug_mask; 743 #endif 744 745 if (!cold) 746 at_poll = AT_WAIT; 747 748 if (chp->wdc->reset == NULL) 749 chp->wdc->reset = wdc_do_reset; 750 751 timeout_set(&chp->ch_timo, wdctimeout, chp); 752 753 if (!chp->_vtbl) 754 chp->_vtbl = &wdc_default_vtbl; 755 756 for (i = 0; i < 2; i++) { 757 chp->ch_drive[i].chnl_softc = chp; 758 chp->ch_drive[i].drive = i; 759 } 760 761 if (chp->wdc->drv_probe != NULL) { 762 chp->wdc->drv_probe(chp); 763 } else { 764 if (wdcprobe(chp) == 0) 765 /* If no drives, abort attach here. */ 766 return; 767 } 768 769 /* ATAPI drives need settling time. Give them 250ms */ 770 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 771 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 772 delay(250 * 1000); 773 } 774 775 #ifdef WDCDEBUG 776 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE) 777 wdcdebug_mask |= DEBUG_PROBE; 778 779 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 780 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 781 wdcdebug_mask = DEBUG_PROBE; 782 } 783 #endif /* WDCDEBUG */ 784 785 for (i = 0; i < 2; i++) { 786 struct ata_drive_datas *drvp = &chp->ch_drive[i]; 787 788 /* If controller can't do 16bit flag the drives as 32bit */ 789 if ((chp->wdc->cap & 790 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 791 WDC_CAPABILITY_DATA32) 792 drvp->drive_flags |= DRIVE_CAP32; 793 794 if ((drvp->drive_flags & DRIVE) == 0) 795 continue; 796 797 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0)) 798 chp->ch_flags |= WDCF_ONESLAVE; 799 /* 800 * Wait a bit, some devices are weird just after a reset. 801 * Then issue a IDENTIFY command, to try to detect slave ghost. 802 */ 803 delay(5000); 804 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) == 805 CMD_OK) { 806 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 807 drvp->drive_flags &= ~DRIVE_OLD; 808 } else { 809 bzero(&drvp->id, sizeof(struct ataparams)); 810 drvp->drive_flags &= 811 ~(DRIVE_ATA | DRIVE_ATAPI); 812 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n", 813 chp->wdc->sc_dev.dv_xname, 814 chp->channel, i), DEBUG_PROBE); 815 816 if ((drvp->drive_flags & DRIVE_OLD) && 817 !wdc_preata_drive(chp, i)) 818 drvp->drive_flags &= ~DRIVE_OLD; 819 } 820 } 821 822 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 823 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 824 DEBUG_PROBE); 825 826 /* If no drives, abort here */ 827 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 828 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 829 goto exit; 830 831 for (i = 0; i < 2; i++) { 832 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) { 833 continue; 834 } 835 bzero(&aa_link, sizeof(struct ata_atapi_attach)); 836 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) 837 aa_link.aa_type = T_ATAPI; 838 else 839 aa_link.aa_type = T_ATA; 840 aa_link.aa_channel = chp->channel; 841 aa_link.aa_openings = 1; 842 aa_link.aa_drv_data = &chp->ch_drive[i]; 843 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint); 844 } 845 846 /* 847 * reset drive_flags for unattached devices, reset state for attached 848 * ones 849 */ 850 for (i = 0; i < 2; i++) { 851 if (chp->ch_drive[i].drive_name[0] == 0) 852 chp->ch_drive[i].drive_flags = 0; 853 } 854 855 exit: 856 #ifdef WDCDEBUG 857 wdcdebug_mask = savedmask; 858 #endif 859 return; /* for the ``exit'' label above */ 860 } 861 862 /* 863 * Start I/O on a controller, for the given channel. 864 * The first xfer may be not for our channel if the channel queues 865 * are shared. 866 */ 867 void 868 wdcstart(struct channel_softc *chp) 869 { 870 struct wdc_xfer *xfer; 871 872 splassert(IPL_BIO); 873 874 /* is there a xfer ? */ 875 if ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) == NULL) { 876 return; 877 } 878 879 /* adjust chp, in case we have a shared queue */ 880 chp = xfer->chp; 881 882 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 883 return; /* channel already active */ 884 } 885 #ifdef DIAGNOSTIC 886 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 887 panic("wdcstart: channel waiting for irq"); 888 #endif /* DIAGNOSTIC */ 889 890 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 891 chp->channel, xfer->drive), DEBUG_XFERS); 892 chp->ch_flags |= WDCF_ACTIVE; 893 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 894 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 895 chp->ch_drive[xfer->drive].state = 0; 896 } 897 xfer->c_start(chp, xfer); 898 } 899 900 int 901 wdcdetach(struct channel_softc *chp, int flags) 902 { 903 int s, rv; 904 905 s = splbio(); 906 chp->dying = 1; 907 908 wdc_kill_pending(chp); 909 timeout_del(&chp->ch_timo); 910 911 rv = config_detach_children((struct device *)chp->wdc, flags); 912 splx(s); 913 914 return (rv); 915 } 916 917 /* 918 * Interrupt routine for the controller. Acknowledge the interrupt, check for 919 * errors on the current operation, mark it done if necessary, and start the 920 * next request. Also check for a partially done transfer, and continue with 921 * the next chunk if so. 922 */ 923 int 924 wdcintr(void *arg) 925 { 926 struct channel_softc *chp = arg; 927 struct wdc_xfer *xfer; 928 u_int8_t st = 0; 929 int ret = 0; 930 931 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 932 /* Acknowledge interrupt by reading status */ 933 if (chp->_vtbl == 0) 934 st = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 935 wdr_status & _WDC_REGMASK); 936 else 937 st = CHP_READ_REG(chp, wdr_status); 938 if (st == 0xff) 939 return (-1); 940 941 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 942 return ret; 943 } 944 945 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 946 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 947 if (chp->ch_flags & WDCF_DMA_WAIT) { 948 chp->wdc->dma_status = 949 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 950 xfer->drive, 0); 951 if (chp->wdc->dma_status == 0xff) 952 return (-1); 953 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 954 /* IRQ not for us, not detected by DMA engine */ 955 return 0; 956 } 957 chp->ch_flags &= ~WDCF_DMA_WAIT; 958 } 959 960 chp->ch_flags &= ~WDCF_IRQ_WAIT; 961 ret = xfer->c_intr(chp, xfer, 1); 962 if (ret == 0) /* irq was not for us, still waiting for irq */ 963 chp->ch_flags |= WDCF_IRQ_WAIT; 964 return (ret); 965 } 966 967 /* Put all disk in RESET state */ 968 void 969 wdc_reset_channel(struct ata_drive_datas *drvp, int nowait) 970 { 971 struct channel_softc *chp = drvp->chnl_softc; 972 int drive; 973 974 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 975 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 976 DEBUG_FUNCS); 977 (void) wdcreset(chp, nowait ? NOWAIT : VERBOSE); 978 for (drive = 0; drive < 2; drive++) { 979 chp->ch_drive[drive].state = 0; 980 } 981 } 982 983 int 984 wdcreset(struct channel_softc *chp, int flags) 985 { 986 int drv_mask1, drv_mask2; 987 988 if (!chp->_vtbl) 989 chp->_vtbl = &wdc_default_vtbl; 990 991 chp->wdc->reset(chp); 992 993 if (flags & NOWAIT) 994 return 0; 995 996 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 997 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 998 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 999 1000 if ((flags & VERBOSE) && drv_mask2 != drv_mask1) { 1001 printf("%s channel %d: reset failed for", 1002 chp->wdc->sc_dev.dv_xname, chp->channel); 1003 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1004 printf(" drive 0"); 1005 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1006 printf(" drive 1"); 1007 printf("\n"); 1008 } 1009 1010 return (drv_mask1 != drv_mask2) ? 1 : 0; 1011 } 1012 1013 void 1014 wdc_do_reset(struct channel_softc *chp) 1015 { 1016 wdc_set_drive(chp, 0); 1017 DELAY(10); 1018 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT | WDCTL_RST); 1019 delay(10000); 1020 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT); 1021 delay(10000); 1022 } 1023 1024 int 1025 __wdcwait_reset(struct channel_softc *chp, int drv_mask) 1026 { 1027 int timeout; 1028 u_int8_t st0, er0, st1, er1; 1029 1030 /* wait for BSY to deassert */ 1031 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 1032 wdc_set_drive(chp, 0); 1033 delay(10); 1034 st0 = CHP_READ_REG(chp, wdr_status); 1035 er0 = CHP_READ_REG(chp, wdr_error); 1036 wdc_set_drive(chp, 1); 1037 delay(10); 1038 st1 = CHP_READ_REG(chp, wdr_status); 1039 er1 = CHP_READ_REG(chp, wdr_error); 1040 1041 if ((drv_mask & 0x01) == 0) { 1042 /* no master */ 1043 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1044 /* No master, slave is ready, it's done */ 1045 goto end; 1046 } 1047 } else if ((drv_mask & 0x02) == 0) { 1048 /* no slave */ 1049 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1050 /* No slave, master is ready, it's done */ 1051 goto end; 1052 } 1053 } else { 1054 /* Wait for both master and slave to be ready */ 1055 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1056 goto end; 1057 } 1058 } 1059 delay(WDCDELAY); 1060 } 1061 /* Reset timed out. Maybe it's because drv_mask was not right */ 1062 if (st0 & WDCS_BSY) 1063 drv_mask &= ~0x01; 1064 if (st1 & WDCS_BSY) 1065 drv_mask &= ~0x02; 1066 end: 1067 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%b, er0=0x%x, " 1068 "st1=0x%b, er1=0x%x, reset time=%d msec\n", 1069 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 1070 st0, WDCS_BITS, er0, st1, WDCS_BITS, er1, 1071 timeout * WDCDELAY / 1000), DEBUG_PROBE); 1072 1073 return drv_mask; 1074 } 1075 1076 /* 1077 * Wait for a drive to be !BSY, and have mask in its status register. 1078 * return -1 for a timeout after "timeout" ms. 1079 */ 1080 int 1081 wdc_wait_for_status(struct channel_softc *chp, int mask, int bits, int timeout) 1082 { 1083 u_char status; 1084 int time = 0; 1085 1086 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 1087 :"none", chp->channel), DEBUG_STATUS); 1088 chp->ch_error = 0; 1089 1090 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1091 1092 for (;;) { 1093 chp->ch_status = status = CHP_READ_REG(chp, wdr_status); 1094 WDC_LOG_STATUS(chp, chp->ch_status); 1095 1096 if (status == 0xff) { 1097 if ((chp->ch_flags & WDCF_ONESLAVE)) { 1098 wdc_set_drive(chp, 1); 1099 chp->ch_status = status = 1100 CHP_READ_REG(chp, wdr_status); 1101 WDC_LOG_STATUS(chp, chp->ch_status); 1102 } 1103 } 1104 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 1105 break; 1106 if (++time > timeout) { 1107 WDCDEBUG_PRINT(("wdcwait: timeout, status 0x%b " 1108 "error 0x%x\n", status, WDCS_BITS, 1109 CHP_READ_REG(chp, wdr_error)), 1110 DEBUG_STATUSX | DEBUG_STATUS); 1111 return -1; 1112 } 1113 delay(WDCDELAY); 1114 } 1115 if (status & WDCS_ERR) { 1116 chp->ch_error = CHP_READ_REG(chp, wdr_error); 1117 WDC_LOG_ERROR(chp, chp->ch_error); 1118 1119 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error), 1120 DEBUG_STATUSX | DEBUG_STATUS); 1121 } 1122 1123 #ifdef WDCNDELAY_DEBUG 1124 /* After autoconfig, there should be no long delays. */ 1125 if (!cold && time > WDCNDELAY_DEBUG) { 1126 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1127 if (xfer == NULL) 1128 printf("%s channel %d: warning: busy-wait took %dus\n", 1129 chp->wdc->sc_dev.dv_xname, chp->channel, 1130 WDCDELAY * time); 1131 else 1132 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1133 chp->wdc->sc_dev.dv_xname, chp->channel, 1134 xfer->drive, 1135 WDCDELAY * time); 1136 } 1137 #endif /* WDCNDELAY_DEBUG */ 1138 return time; 1139 } 1140 1141 /* 1142 * Busy-wait for DMA to complete 1143 */ 1144 int 1145 wdc_dmawait(struct channel_softc *chp, struct wdc_xfer *xfer, int timeout) 1146 { 1147 int time; 1148 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1149 chp->wdc->dma_status = 1150 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1151 chp->channel, xfer->drive, 0); 1152 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1153 return 0; 1154 if (chp->wdc->dma_status == 0xff) { 1155 chp->dying = 1; 1156 return -1; 1157 } 1158 delay(WDCDELAY); 1159 } 1160 /* timeout, force a DMA halt */ 1161 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1162 chp->channel, xfer->drive, 1); 1163 return 1; 1164 } 1165 1166 void 1167 wdctimeout(void *arg) 1168 { 1169 struct channel_softc *chp = (struct channel_softc *)arg; 1170 struct wdc_xfer *xfer; 1171 int s; 1172 1173 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1174 1175 s = splbio(); 1176 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 1177 1178 /* Did we lose a race with the interrupt? */ 1179 if (xfer == NULL || 1180 !timeout_triggered(&chp->ch_timo)) { 1181 splx(s); 1182 return; 1183 } 1184 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1185 __wdcerror(chp, "timeout"); 1186 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ? 1187 "atapi":"ata"); 1188 printf("\tc_bcount: %d\n", xfer->c_bcount); 1189 printf("\tc_skip: %d\n", xfer->c_skip); 1190 if (chp->ch_flags & WDCF_DMA_WAIT) { 1191 chp->wdc->dma_status = 1192 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 1193 chp->channel, xfer->drive, 1); 1194 chp->ch_flags &= ~WDCF_DMA_WAIT; 1195 } 1196 /* 1197 * Call the interrupt routine. If we just missed and interrupt, 1198 * it will do what's needed. Else, it will take the needed 1199 * action (reset the device). 1200 */ 1201 xfer->c_flags |= C_TIMEOU; 1202 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1203 xfer->c_intr(chp, xfer, 1); 1204 } else 1205 __wdcerror(chp, "missing untimeout"); 1206 splx(s); 1207 } 1208 1209 /* 1210 * Probe drive's capabilities, for use by the controller later. 1211 * Assumes drvp points to an existing drive. 1212 * XXX this should be a controller-indep function 1213 */ 1214 void 1215 wdc_probe_caps(struct ata_drive_datas *drvp, struct ataparams *params) 1216 { 1217 struct channel_softc *chp = drvp->chnl_softc; 1218 struct wdc_softc *wdc = chp->wdc; 1219 int i, valid_mode_found; 1220 int cf_flags = drvp->cf_flags; 1221 1222 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1223 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1224 struct ataparams params2; 1225 1226 /* 1227 * Controller claims 16 and 32 bit transfers. 1228 * Re-do an IDENTIFY with 32-bit transfers, 1229 * and compare results. 1230 */ 1231 drvp->drive_flags |= DRIVE_CAP32; 1232 ata_get_params(drvp, at_poll, ¶ms2); 1233 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) { 1234 /* Not good. fall back to 16bits */ 1235 drvp->drive_flags &= ~DRIVE_CAP32; 1236 } 1237 } 1238 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1239 if (params->atap_ata_major > 0x01 && 1240 params->atap_ata_major != 0xffff) { 1241 for (i = 14; i > 0; i--) { 1242 if (params->atap_ata_major & (1 << i)) { 1243 printf("%sATA version %d\n", sep, i); 1244 drvp->ata_vers = i; 1245 break; 1246 } 1247 } 1248 } else 1249 #endif /* 0 */ 1250 /* Use PIO mode 3 as a default value for ATAPI devices */ 1251 if (drvp->drive_flags & DRIVE_ATAPI) 1252 drvp->PIO_mode = 3; 1253 1254 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap 0x%x cf_flags 0x%x\n", 1255 wdc->cap, cf_flags), DEBUG_PROBE); 1256 1257 valid_mode_found = 0; 1258 1259 WDCDEBUG_PRINT(("%s: atap_oldpiotiming=%d\n", __func__, 1260 params->atap_oldpiotiming), DEBUG_PROBE); 1261 /* 1262 * ATA-4 compliant devices contain PIO mode 1263 * number in atap_oldpiotiming. 1264 */ 1265 if (params->atap_oldpiotiming <= 2) { 1266 drvp->PIO_cap = params->atap_oldpiotiming; 1267 valid_mode_found = 1; 1268 drvp->drive_flags |= DRIVE_MODE; 1269 } else if (params->atap_oldpiotiming > 180) { 1270 /* 1271 * ATA-2 compliant devices contain cycle 1272 * time in atap_oldpiotiming. 1273 * A device with a cycle time of 180ns 1274 * or less is at least PIO mode 3 and 1275 * should be reporting that in 1276 * atap_piomode_supp, so ignore it here. 1277 */ 1278 if (params->atap_oldpiotiming <= 240) { 1279 drvp->PIO_cap = 2; 1280 } else { 1281 drvp->PIO_cap = 1; 1282 } 1283 valid_mode_found = 1; 1284 drvp->drive_flags |= DRIVE_MODE; 1285 } 1286 if (valid_mode_found) 1287 drvp->PIO_mode = drvp->PIO_cap; 1288 1289 WDCDEBUG_PRINT(("%s: atap_extensions=0x%x, atap_piomode_supp=0x%x, " 1290 "atap_dmamode_supp=0x%x, atap_udmamode_supp=0x%x\n", 1291 __func__, params->atap_extensions, params->atap_piomode_supp, 1292 params->atap_dmamode_supp, params->atap_udmamode_supp), 1293 DEBUG_PROBE); 1294 1295 /* 1296 * It's not in the specs, but it seems that some drive 1297 * returns 0xffff in atap_extensions when this field is invalid 1298 */ 1299 if (params->atap_extensions != 0xffff && 1300 (params->atap_extensions & WDC_EXT_MODES)) { 1301 /* 1302 * XXX some drives report something wrong here (they claim to 1303 * support PIO mode 8 !). As mode is coded on 3 bits in 1304 * SET FEATURE, limit it to 7 (so limit i to 4). 1305 * If higher mode than 7 is found, abort. 1306 */ 1307 for (i = 7; i >= 0; i--) { 1308 if ((params->atap_piomode_supp & (1 << i)) == 0) 1309 continue; 1310 if (i > 4) 1311 return; 1312 1313 valid_mode_found = 1; 1314 1315 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) { 1316 drvp->PIO_cap = i + 3; 1317 continue; 1318 } 1319 1320 /* 1321 * See if mode is accepted. 1322 * If the controller can't set its PIO mode, 1323 * assume the BIOS set it up correctly 1324 */ 1325 if (ata_set_mode(drvp, 0x08 | (i + 3), 1326 at_poll) != CMD_OK) 1327 continue; 1328 1329 /* 1330 * If controller's driver can't set its PIO mode, 1331 * set the highest one the controller supports 1332 */ 1333 if (wdc->PIO_cap >= i + 3) { 1334 drvp->PIO_mode = i + 3; 1335 drvp->PIO_cap = i + 3; 1336 break; 1337 } 1338 } 1339 if (!valid_mode_found) { 1340 /* 1341 * We didn't find a valid PIO mode. 1342 * Assume the values returned for DMA are buggy too 1343 */ 1344 return; 1345 } 1346 drvp->drive_flags |= DRIVE_MODE; 1347 1348 /* Some controllers don't support ATAPI DMA */ 1349 if ((drvp->drive_flags & DRIVE_ATAPI) && 1350 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA)) 1351 return; 1352 1353 valid_mode_found = 0; 1354 for (i = 7; i >= 0; i--) { 1355 if ((params->atap_dmamode_supp & (1 << i)) == 0) 1356 continue; 1357 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1358 (wdc->cap & WDC_CAPABILITY_MODE)) 1359 if (ata_set_mode(drvp, 0x20 | i, at_poll) 1360 != CMD_OK) 1361 continue; 1362 1363 valid_mode_found = 1; 1364 1365 if (wdc->cap & WDC_CAPABILITY_DMA) { 1366 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1367 wdc->DMA_cap < i) 1368 continue; 1369 drvp->DMA_mode = i; 1370 drvp->DMA_cap = i; 1371 drvp->drive_flags |= DRIVE_DMA; 1372 } 1373 break; 1374 } 1375 if (params->atap_extensions & WDC_EXT_UDMA_MODES) { 1376 for (i = 7; i >= 0; i--) { 1377 if ((params->atap_udmamode_supp & (1 << i)) 1378 == 0) 1379 continue; 1380 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1381 (wdc->cap & WDC_CAPABILITY_UDMA)) 1382 if (ata_set_mode(drvp, 0x40 | i, 1383 at_poll) != CMD_OK) 1384 continue; 1385 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1386 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1387 wdc->UDMA_cap < i) 1388 continue; 1389 drvp->UDMA_mode = i; 1390 drvp->UDMA_cap = i; 1391 drvp->drive_flags |= DRIVE_UDMA; 1392 } 1393 break; 1394 } 1395 } 1396 } 1397 1398 /* Try to guess ATA version here, if it didn't get reported */ 1399 if (drvp->ata_vers == 0) { 1400 if (drvp->drive_flags & DRIVE_UDMA) 1401 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1402 else if (drvp->PIO_cap > 2) 1403 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1404 } 1405 if (cf_flags & ATA_CONFIG_PIO_SET) { 1406 drvp->PIO_mode = 1407 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1408 drvp->drive_flags |= DRIVE_MODE; 1409 } 1410 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1411 /* don't care about DMA modes */ 1412 return; 1413 } 1414 if (cf_flags & ATA_CONFIG_DMA_SET) { 1415 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1416 ATA_CONFIG_DMA_DISABLE) { 1417 drvp->drive_flags &= ~DRIVE_DMA; 1418 } else { 1419 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1420 ATA_CONFIG_DMA_OFF; 1421 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1422 } 1423 } 1424 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1425 /* don't care about UDMA modes */ 1426 return; 1427 } 1428 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1429 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1430 ATA_CONFIG_UDMA_DISABLE) { 1431 drvp->drive_flags &= ~DRIVE_UDMA; 1432 } else { 1433 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1434 ATA_CONFIG_UDMA_OFF; 1435 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1436 } 1437 } 1438 } 1439 1440 void 1441 wdc_output_bytes(struct ata_drive_datas *drvp, void *bytes, unsigned int buflen) 1442 { 1443 struct channel_softc *chp = drvp->chnl_softc; 1444 unsigned int off = 0; 1445 unsigned int len = buflen, roundlen; 1446 1447 if (drvp->drive_flags & DRIVE_CAP32) { 1448 roundlen = len & ~3; 1449 1450 CHP_WRITE_RAW_MULTI_4(chp, 1451 (void *)((u_int8_t *)bytes + off), roundlen); 1452 1453 off += roundlen; 1454 len -= roundlen; 1455 } 1456 1457 if (len > 0) { 1458 roundlen = (len + 1) & ~0x1; 1459 1460 CHP_WRITE_RAW_MULTI_2(chp, 1461 (void *)((u_int8_t *)bytes + off), roundlen); 1462 } 1463 } 1464 1465 void 1466 wdc_input_bytes(struct ata_drive_datas *drvp, void *bytes, unsigned int buflen) 1467 { 1468 struct channel_softc *chp = drvp->chnl_softc; 1469 unsigned int off = 0; 1470 unsigned int len = buflen, roundlen; 1471 1472 if (drvp->drive_flags & DRIVE_CAP32) { 1473 roundlen = len & ~3; 1474 1475 CHP_READ_RAW_MULTI_4(chp, 1476 (void *)((u_int8_t *)bytes + off), roundlen); 1477 1478 off += roundlen; 1479 len -= roundlen; 1480 } 1481 1482 if (len > 0) { 1483 roundlen = (len + 1) & ~0x1; 1484 1485 CHP_READ_RAW_MULTI_2(chp, 1486 (void *)((u_int8_t *)bytes + off), roundlen); 1487 } 1488 } 1489 1490 void 1491 wdc_print_caps(struct ata_drive_datas *drvp) 1492 { 1493 /* This is actually a lie until we fix the _probe_caps 1494 algorithm. Don't print out lies */ 1495 #if 0 1496 printf("%s: can use ", drvp->drive_name); 1497 1498 if (drvp->drive_flags & DRIVE_CAP32) { 1499 printf("32-bit"); 1500 } else 1501 printf("16-bit"); 1502 1503 printf(", PIO mode %d", drvp->PIO_cap); 1504 1505 if (drvp->drive_flags & DRIVE_DMA) { 1506 printf(", DMA mode %d", drvp->DMA_cap); 1507 } 1508 1509 if (drvp->drive_flags & DRIVE_UDMA) { 1510 printf(", Ultra-DMA mode %d", drvp->UDMA_cap); 1511 } 1512 1513 printf("\n"); 1514 #endif /* 0 */ 1515 } 1516 1517 void 1518 wdc_print_current_modes(struct channel_softc *chp) 1519 { 1520 int drive; 1521 struct ata_drive_datas *drvp; 1522 1523 for (drive = 0; drive < 2; drive++) { 1524 drvp = &chp->ch_drive[drive]; 1525 if ((drvp->drive_flags & DRIVE) == 0) 1526 continue; 1527 1528 printf("%s(%s:%d:%d):", 1529 drvp->drive_name, 1530 chp->wdc->sc_dev.dv_xname, chp->channel, drive); 1531 1532 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 && 1533 !(drvp->cf_flags & ATA_CONFIG_PIO_SET)) 1534 printf(" using BIOS timings"); 1535 else 1536 printf(" using PIO mode %d", drvp->PIO_mode); 1537 if (drvp->drive_flags & DRIVE_DMA) 1538 printf(", DMA mode %d", drvp->DMA_mode); 1539 if (drvp->drive_flags & DRIVE_UDMA) 1540 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1541 printf("\n"); 1542 } 1543 } 1544 1545 /* 1546 * downgrade the transfer mode of a drive after an error. return 1 if 1547 * downgrade was possible, 0 otherwise. 1548 */ 1549 int 1550 wdc_downgrade_mode(struct ata_drive_datas *drvp) 1551 { 1552 struct channel_softc *chp = drvp->chnl_softc; 1553 struct wdc_softc *wdc = chp->wdc; 1554 int cf_flags = drvp->cf_flags; 1555 1556 /* if drive or controller don't know its mode, we can't do much */ 1557 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1558 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1559 return 0; 1560 /* current drive mode was set by a config flag, let it this way */ 1561 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1562 (cf_flags & ATA_CONFIG_DMA_SET) || 1563 (cf_flags & ATA_CONFIG_UDMA_SET)) 1564 return 0; 1565 1566 /* 1567 * We'd ideally like to use an Ultra DMA mode since they have the 1568 * protection of a CRC. So we try each Ultra DMA mode and see if 1569 * we can find any working combo 1570 */ 1571 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) { 1572 drvp->UDMA_mode = drvp->UDMA_mode - 1; 1573 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1574 drvp->drive_name, drvp->UDMA_mode); 1575 } else if ((drvp->drive_flags & DRIVE_UDMA) && 1576 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1577 /* 1578 * If we were using ultra-DMA, don't downgrade to 1579 * multiword DMA if we noticed a CRC error. It has 1580 * been noticed that CRC errors in ultra-DMA lead to 1581 * silent data corruption in multiword DMA. Data 1582 * corruption is less likely to occur in PIO mode. 1583 */ 1584 drvp->drive_flags &= ~DRIVE_UDMA; 1585 drvp->drive_flags |= DRIVE_DMA; 1586 drvp->DMA_mode = drvp->DMA_cap; 1587 printf("%s: transfer error, downgrading to DMA mode %d\n", 1588 drvp->drive_name, drvp->DMA_mode); 1589 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1590 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1591 drvp->PIO_mode = drvp->PIO_cap; 1592 printf("%s: transfer error, downgrading to PIO mode %d\n", 1593 drvp->drive_name, drvp->PIO_mode); 1594 } else /* already using PIO, can't downgrade */ 1595 return 0; 1596 1597 wdc->set_modes(chp); 1598 /* reset the channel, which will schedule all drives for setup */ 1599 wdc_reset_channel(drvp, 0); 1600 return 1; 1601 } 1602 1603 int 1604 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1605 { 1606 struct channel_softc *chp = drvp->chnl_softc; 1607 struct wdc_xfer *xfer; 1608 int s, ret; 1609 1610 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1611 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1612 DEBUG_FUNCS); 1613 1614 /* set up an xfer and queue. Wait for completion */ 1615 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1616 WDC_NOSLEEP); 1617 if (xfer == NULL) { 1618 return WDC_TRY_AGAIN; 1619 } 1620 1621 if (wdc_c->flags & AT_POLL) 1622 xfer->c_flags |= C_POLL; 1623 xfer->drive = drvp->drive; 1624 xfer->databuf = wdc_c->data; 1625 xfer->c_bcount = wdc_c->bcount; 1626 xfer->cmd = wdc_c; 1627 xfer->c_start = __wdccommand_start; 1628 xfer->c_intr = __wdccommand_intr; 1629 xfer->c_kill_xfer = __wdccommand_done; 1630 1631 s = splbio(); 1632 wdc_exec_xfer(chp, xfer); 1633 #ifdef DIAGNOSTIC 1634 if ((wdc_c->flags & AT_POLL) != 0 && 1635 (wdc_c->flags & AT_DONE) == 0) 1636 panic("wdc_exec_command: polled command not done"); 1637 #endif /* DIAGNOSTIC */ 1638 if (wdc_c->flags & AT_DONE) { 1639 ret = WDC_COMPLETE; 1640 } else { 1641 if (wdc_c->flags & AT_WAIT) { 1642 WDCDEBUG_PRINT(("wdc_exec_command sleeping\n"), 1643 DEBUG_FUNCS); 1644 1645 while ((wdc_c->flags & AT_DONE) == 0) { 1646 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1647 } 1648 ret = WDC_COMPLETE; 1649 } else { 1650 ret = WDC_QUEUED; 1651 } 1652 } 1653 splx(s); 1654 return ret; 1655 } 1656 1657 void 1658 __wdccommand_start(struct channel_softc *chp, struct wdc_xfer *xfer) 1659 { 1660 int drive = xfer->drive; 1661 struct wdc_command *wdc_c = xfer->cmd; 1662 1663 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1664 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1665 DEBUG_FUNCS); 1666 1667 /* 1668 * Disable interrupts if we're polling 1669 */ 1670 if (xfer->c_flags & C_POLL) { 1671 wdc_disable_intr(chp); 1672 } 1673 1674 wdc_set_drive(chp, drive); 1675 DELAY(1); 1676 1677 /* 1678 * For resets, we don't really care to make sure that 1679 * the bus is free 1680 */ 1681 if (wdc_c->r_command != ATAPI_SOFT_RESET) { 1682 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1683 wdc_c->r_st_bmask, wdc_c->timeout) != 0) { 1684 goto timeout; 1685 } 1686 } else 1687 DELAY(10); 1688 1689 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1690 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_features); 1691 1692 if ((wdc_c->flags & AT_WRITE) == AT_WRITE) { 1693 /* wait at least 400ns before reading status register */ 1694 DELAY(10); 1695 if (wait_for_unbusy(chp, wdc_c->timeout) != 0) 1696 goto timeout; 1697 1698 if ((chp->ch_status & (WDCS_DRQ | WDCS_ERR)) == WDCS_ERR) { 1699 __wdccommand_done(chp, xfer); 1700 return; 1701 } 1702 1703 if (wait_for_drq(chp, wdc_c->timeout) != 0) 1704 goto timeout; 1705 1706 wdc_output_bytes(&chp->ch_drive[drive], 1707 wdc_c->data, wdc_c->bcount); 1708 } 1709 1710 if ((wdc_c->flags & AT_POLL) == 0) { 1711 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1712 timeout_add_msec(&chp->ch_timo, wdc_c->timeout); 1713 return; 1714 } 1715 1716 /* 1717 * Polled command. Wait for drive ready or drq. Done in intr(). 1718 * Wait for at last 400ns for status bit to be valid. 1719 */ 1720 delay(10); 1721 __wdccommand_intr(chp, xfer, 0); 1722 return; 1723 1724 timeout: 1725 wdc_c->flags |= AT_TIMEOU; 1726 __wdccommand_done(chp, xfer); 1727 } 1728 1729 int 1730 __wdccommand_intr(struct channel_softc *chp, struct wdc_xfer *xfer, int irq) 1731 { 1732 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive]; 1733 struct wdc_command *wdc_c = xfer->cmd; 1734 int bcount = wdc_c->bcount; 1735 char *data = wdc_c->data; 1736 1737 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1738 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1739 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1740 (irq == 0) ? wdc_c->timeout : 0)) { 1741 if (chp->dying) { 1742 __wdccommand_done(chp, xfer); 1743 return -1; 1744 } 1745 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1746 return 0; /* IRQ was not for us */ 1747 wdc_c->flags |= AT_TIMEOU; 1748 goto out; 1749 } 1750 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1751 chp->wdc->irqack(chp); 1752 if (wdc_c->flags & AT_READ) { 1753 if ((chp->ch_status & WDCS_DRQ) == 0) { 1754 wdc_c->flags |= AT_TIMEOU; 1755 goto out; 1756 } 1757 wdc_input_bytes(drvp, data, bcount); 1758 /* Should we wait for device to indicate idle? */ 1759 } 1760 out: 1761 __wdccommand_done(chp, xfer); 1762 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR); 1763 return 1; 1764 } 1765 1766 void 1767 __wdccommand_done(struct channel_softc *chp, struct wdc_xfer *xfer) 1768 { 1769 struct wdc_command *wdc_c = xfer->cmd; 1770 1771 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n", 1772 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive, 1773 chp->ch_status), DEBUG_FUNCS); 1774 if (chp->dying) 1775 goto killit; 1776 if (chp->ch_status & WDCS_DWF) 1777 wdc_c->flags |= AT_DF; 1778 if (chp->ch_status & WDCS_ERR) { 1779 wdc_c->flags |= AT_ERROR; 1780 wdc_c->r_error = chp->ch_error; 1781 } 1782 wdc_c->flags |= AT_DONE; 1783 if ((wdc_c->flags & AT_READREG) != 0 && 1784 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1785 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh); 1786 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8; 1787 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo); 1788 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector); 1789 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt); 1790 wdc_c->r_error = CHP_READ_REG(chp, wdr_error); 1791 wdc_c->r_features = wdc_c->r_error; 1792 } 1793 1794 killit: 1795 if (xfer->c_flags & C_POLL) { 1796 wdc_enable_intr(chp); 1797 } else 1798 timeout_del(&chp->ch_timo); 1799 1800 wdc_free_xfer(chp, xfer); 1801 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR); 1802 1803 if (chp->dying) 1804 return; 1805 1806 if (wdc_c->flags & AT_WAIT) 1807 wakeup(wdc_c); 1808 else 1809 if (wdc_c->callback) 1810 wdc_c->callback(wdc_c->callback_arg); 1811 wdcstart(chp); 1812 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR); 1813 } 1814 1815 /* 1816 * Send a command. The drive should be ready. 1817 * Assumes interrupts are blocked. 1818 */ 1819 void 1820 wdccommand(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1821 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1822 u_int8_t features) 1823 { 1824 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1825 "sector=%d count=%d features=%d\n", chp->wdc->sc_dev.dv_xname, 1826 chp->channel, drive, command, cylin, head, sector, count, features), 1827 DEBUG_FUNCS); 1828 WDC_LOG_ATA_CMDLONG(chp, head, features, cylin, cylin >> 8, sector, 1829 count, command); 1830 1831 /* Select drive, head, and addressing mode. */ 1832 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head); 1833 1834 /* Load parameters. */ 1835 CHP_WRITE_REG(chp, wdr_features, features); 1836 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin); 1837 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8); 1838 CHP_WRITE_REG(chp, wdr_sector, sector); 1839 CHP_WRITE_REG(chp, wdr_seccnt, count); 1840 1841 /* Send command. */ 1842 CHP_WRITE_REG(chp, wdr_command, command); 1843 } 1844 1845 /* 1846 * Send a 48-bit addressing command. The drive should be ready. 1847 * Assumes interrupts are blocked. 1848 */ 1849 void 1850 wdccommandext(struct channel_softc *chp, u_int8_t drive, u_int8_t command, 1851 u_int64_t blkno, u_int16_t count) 1852 { 1853 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%llu " 1854 "count=%d\n", chp->wdc->sc_dev.dv_xname, 1855 chp->channel, drive, command, blkno, count), 1856 DEBUG_FUNCS); 1857 WDC_LOG_ATA_CMDEXT(chp, blkno >> 40, blkno >> 16, blkno >> 32, 1858 blkno >> 8, blkno >> 24, blkno, count >> 8, count, command); 1859 1860 /* Select drive and LBA mode. */ 1861 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_LBA); 1862 1863 /* Load parameters. */ 1864 CHP_LBA48_WRITE_REG(chp, wdr_lba_hi, 1865 ((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0xff)); 1866 CHP_LBA48_WRITE_REG(chp, wdr_lba_mi, 1867 ((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0xff)); 1868 CHP_LBA48_WRITE_REG(chp, wdr_lba_lo, 1869 ((blkno >> 16) & 0xff00) | (blkno & 0xff)); 1870 CHP_LBA48_WRITE_REG(chp, wdr_seccnt, count); 1871 1872 /* Send command. */ 1873 CHP_WRITE_REG(chp, wdr_command, command); 1874 } 1875 1876 /* 1877 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1878 * tested by the caller. 1879 */ 1880 void 1881 wdccommandshort(struct channel_softc *chp, int drive, int command) 1882 { 1883 1884 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1885 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1886 DEBUG_FUNCS); 1887 WDC_LOG_ATA_CMDSHORT(chp, command); 1888 1889 /* Select drive. */ 1890 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4)); 1891 CHP_WRITE_REG(chp, wdr_command, command); 1892 } 1893 1894 /* Add a command to the queue and start controller. Must be called at splbio */ 1895 1896 void 1897 wdc_exec_xfer(struct channel_softc *chp, struct wdc_xfer *xfer) 1898 { 1899 WDCDEBUG_PRINT(("wdc_exec_xfer %p flags 0x%x channel %d drive %d\n", 1900 xfer, xfer->c_flags, chp->channel, xfer->drive), DEBUG_XFERS); 1901 1902 /* complete xfer setup */ 1903 xfer->chp = chp; 1904 1905 /* 1906 * If we are a polled command, and the list is not empty, 1907 * we are doing a dump. Drop the list to allow the polled command 1908 * to complete, we're going to reboot soon anyway. 1909 */ 1910 if ((xfer->c_flags & C_POLL) != 0 && 1911 !TAILQ_EMPTY(&chp->ch_queue->sc_xfer)) { 1912 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1913 } 1914 /* insert at the end of command list */ 1915 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1916 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1917 chp->ch_flags), DEBUG_XFERS); 1918 wdcstart(chp); 1919 } 1920 1921 void * 1922 wdc_xfer_get(void *null) 1923 { 1924 return (pool_get(&wdc_xfer_pool, PR_NOWAIT | PR_ZERO)); 1925 } 1926 1927 void 1928 wdc_scrub_xfer(struct wdc_xfer *xfer) 1929 { 1930 memset(xfer, 0, sizeof(*xfer)); 1931 xfer->c_flags = C_SCSIXFER; 1932 } 1933 1934 void 1935 wdc_xfer_put(void *null, void *xxfer) 1936 { 1937 struct wdc_xfer *xfer = xxfer; 1938 int put = 0; 1939 int s; 1940 1941 s = splbio(); 1942 if (ISSET(xfer->c_flags, C_SCSIXFER)) 1943 CLR(xfer->c_flags, C_SCSIXFER); 1944 else 1945 put = 1; 1946 splx(s); 1947 1948 if (put) 1949 pool_put(&wdc_xfer_pool, xfer); 1950 } 1951 1952 struct wdc_xfer * 1953 wdc_get_xfer(int flags) 1954 { 1955 return (scsi_io_get(&wdc_xfer_iopool, 1956 ISSET(flags, WDC_NOSLEEP) ? SCSI_NOSLEEP : 0)); 1957 } 1958 1959 void 1960 wdc_free_xfer(struct channel_softc *chp, struct wdc_xfer *xfer) 1961 { 1962 int put = 0; 1963 int s; 1964 1965 if (xfer->c_flags & C_PRIVATEXFER) { 1966 chp->ch_flags &= ~WDCF_ACTIVE; 1967 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1968 return; 1969 } 1970 1971 s = splbio(); 1972 chp->ch_flags &= ~WDCF_ACTIVE; 1973 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1974 if (ISSET(xfer->c_flags, C_SCSIXFER)) 1975 CLR(xfer->c_flags, C_SCSIXFER); 1976 else 1977 put = 1; 1978 splx(s); 1979 1980 if (put) 1981 scsi_io_put(&wdc_xfer_iopool, xfer); 1982 } 1983 1984 1985 /* 1986 * Kill off all pending xfers for a channel_softc. 1987 * 1988 * Must be called at splbio(). 1989 */ 1990 void 1991 wdc_kill_pending(struct channel_softc *chp) 1992 { 1993 struct wdc_xfer *xfer; 1994 1995 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1996 chp = xfer->chp; 1997 (*xfer->c_kill_xfer)(chp, xfer); 1998 } 1999 } 2000 2001 void 2002 __wdcerror(struct channel_softc *chp, char *msg) 2003 { 2004 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer); 2005 if (xfer == NULL) 2006 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 2007 msg); 2008 else 2009 printf("%s(%s:%d:%d): %s\n", 2010 chp->ch_drive[xfer->drive].drive_name, 2011 chp->wdc->sc_dev.dv_xname, 2012 chp->channel, xfer->drive, msg); 2013 } 2014 2015 /* 2016 * the bit bucket 2017 */ 2018 void 2019 wdcbit_bucket(struct channel_softc *chp, int size) 2020 { 2021 CHP_READ_RAW_MULTI_2(chp, NULL, size); 2022 } 2023 2024 2025 #include <sys/ataio.h> 2026 #include <sys/file.h> 2027 2028 int wdc_ioc_ata_cmd(struct ata_drive_datas *, atareq_t *); 2029 2030 int 2031 wdc_ioc_ata_cmd(struct ata_drive_datas *drvp, atareq_t *atareq) 2032 { 2033 struct wdc_command wdc_c; 2034 int err = 0; 2035 2036 /* 2037 * Make sure a timeout was supplied in the ioctl request 2038 */ 2039 if (atareq->timeout == 0) 2040 return (EINVAL); 2041 2042 if (atareq->datalen > MAXPHYS) 2043 return (EINVAL); 2044 2045 bzero(&wdc_c, sizeof(wdc_c)); 2046 2047 if (atareq->datalen > 0) { 2048 wdc_c.data = dma_alloc(atareq->datalen, PR_NOWAIT | PR_ZERO); 2049 if (wdc_c.data == NULL) { 2050 err = ENOMEM; 2051 goto err; 2052 } 2053 wdc_c.bcount = atareq->datalen; 2054 } 2055 2056 wdc_c.flags = AT_WAIT; 2057 if (atareq->flags & ATACMD_READ) 2058 wdc_c.flags |= AT_READ; 2059 if (atareq->flags & ATACMD_WRITE) { 2060 if (atareq->datalen > 0) { 2061 err = copyin(atareq->databuf, wdc_c.data, 2062 atareq->datalen); 2063 if (err != 0) 2064 goto err; 2065 } 2066 wdc_c.flags |= AT_WRITE; 2067 } 2068 if (atareq->flags & ATACMD_READREG) 2069 wdc_c.flags |= AT_READREG; 2070 2071 wdc_c.timeout = atareq->timeout; 2072 wdc_c.r_command = atareq->command; 2073 wdc_c.r_head = atareq->head & 0x0f; 2074 wdc_c.r_cyl = atareq->cylinder; 2075 wdc_c.r_sector = atareq->sec_num; 2076 wdc_c.r_count = atareq->sec_count; 2077 wdc_c.r_features = atareq->features; 2078 if (drvp->drive_flags & DRIVE_ATAPI) { 2079 if (wdc_c.r_command == WDCC_IDENTIFY) 2080 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE; 2081 } else { 2082 wdc_c.r_st_bmask = WDCS_DRDY; 2083 wdc_c.r_st_pmask = WDCS_DRDY; 2084 } 2085 2086 if (wdc_exec_command(drvp, &wdc_c) != WDC_COMPLETE) { 2087 atareq->retsts = ATACMD_ERROR; 2088 goto copyout; 2089 } 2090 2091 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) { 2092 if (wdc_c.flags & AT_ERROR) { 2093 atareq->retsts = ATACMD_ERROR; 2094 atareq->error = wdc_c.r_error; 2095 } else if (wdc_c.flags & AT_DF) 2096 atareq->retsts = ATACMD_DF; 2097 else 2098 atareq->retsts = ATACMD_TIMEOUT; 2099 } else { 2100 atareq->retsts = ATACMD_OK; 2101 if (atareq->flags & ATACMD_READREG) { 2102 atareq->head = wdc_c.r_head; 2103 atareq->cylinder = wdc_c.r_cyl; 2104 atareq->sec_num = wdc_c.r_sector; 2105 atareq->sec_count = wdc_c.r_count; 2106 atareq->features = wdc_c.r_features; 2107 atareq->error = wdc_c.r_error; 2108 } 2109 } 2110 2111 copyout: 2112 if (atareq->datalen > 0 && atareq->flags & ATACMD_READ) { 2113 err = copyout(wdc_c.data, atareq->databuf, atareq->datalen); 2114 if (err != 0) 2115 goto err; 2116 } 2117 2118 err: 2119 if (wdc_c.data) 2120 dma_free(wdc_c.data, atareq->datalen); 2121 return (err); 2122 } 2123 2124 int 2125 wdc_ioctl(struct ata_drive_datas *drvp, u_long xfer, caddr_t addr, int flag, 2126 struct proc *p) 2127 { 2128 int error = 0; 2129 2130 switch (xfer) { 2131 #ifdef WDCDEBUG 2132 case ATAIOGETTRACE: { 2133 atagettrace_t *agt = (atagettrace_t *)addr; 2134 unsigned int size = 0; 2135 char *log_to_copy; 2136 2137 size = agt->buf_size; 2138 if (size > 65536) { 2139 size = 65536; 2140 } 2141 2142 log_to_copy = wdc_get_log(&size, &agt->bytes_left); 2143 2144 if (log_to_copy != NULL) { 2145 error = copyout(log_to_copy, agt->buf, size); 2146 free(log_to_copy, M_TEMP, 0); 2147 } 2148 2149 agt->bytes_copied = size; 2150 break; 2151 } 2152 #endif /* WDCDEBUG */ 2153 2154 case ATAIOCCOMMAND: { 2155 atareq_t *atareq = (atareq_t *)addr; 2156 2157 /* 2158 * Make sure this command is (relatively) safe first 2159 */ 2160 if ((flag & FWRITE) == 0 && atareq->flags & ATACMD_WRITE) 2161 error = EPERM; 2162 else 2163 error = wdc_ioc_ata_cmd(drvp, atareq); 2164 break; 2165 } 2166 2167 default: 2168 error = ENOTTY; 2169 goto exit; 2170 } 2171 2172 exit: 2173 return (error); 2174 } 2175